[RESEND PATCH 0/8] ARM64: Update support for FSL's LS2085A SoC

[RESEND PATCH 0/8] ARM64: Update support for FSL's LS2085A SoC

[Bhupesh Sharma]

This patchset updates the support for FSL's LS2085A SoC which is based on
ARMv8 architecture:

  - Updates the support of various peripherals (PMU, Watchdog, SMMU,
    SPI, etc.) present on FSL LS2085a SoC in the SoC DTSI.

  - Updates the DTS LS2085a simulator platform to reflect the new
    peripherals added in the DTSI.

  - Adds new DTS files for LS2085a based QDS and RDB boards.

Rebased against arm-soc git tree, branch: next/dt

Further details of the LS2085a based platforms can be seen here:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=LS2085A

Note:
-----
I get a checkpatch warning for the amba-bus compatible string
being missing from Documentation/devicetree/bindings/ . I am not aware
if some patch is already being worked on, to solve the same:
	compatible = "arm,amba-bus";

If not, I can try to send a patch, with the re-spin of this patchset.

Bhupesh Sharma (7):
  Documentation: DT: Add entry for FSL LS2085A QDS and RDB boards
  doc/bindings: Update PCIe devicetree binding documentation for
    LS2085A
  doc/bindings: Update clk-qoriq bindings for FSL's chassis-3.0 SoCs
  dts/ls2085a: Update DTSI to add support of various peripherals
  dts/ls2085a: Update Simulator DTS to add support of various
    peripherals
  dts/ls2085a: Add DTS support for LS2085a QDS & RDB boards
  dts/Makefile: Add build support for LS2085a QDS & RDB board DTS

Wang Dongsheng (1):
  layerscape/ftm: Add compatible string for FTM0 be used as alarm
    timer.

 Documentation/devicetree/bindings/arm/fsl.txt      |    8 +
 .../devicetree/bindings/clock/qoriq-clock.txt      |   14 +-
 .../devicetree/bindings/pci/layerscape-pci.txt     |    3 +-
 .../devicetree/bindings/timer/fsl,ftm-timer.txt    |   46 +-
 arch/arm64/boot/dts/freescale/Makefile             |    2 +-
 .../{fsl-ls2085a-simu.dts => fsl-ls2085a-qds.dts}  |  140 +++++-
 .../{fsl-ls2085a-simu.dts => fsl-ls2085a-rdb.dts}  |   76 ++-
 arch/arm64/boot/dts/freescale/fsl-ls2085a-simu.dts |   40 ++
 arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi     |  523 +++++++++++++++++++-
 9 files changed, 812 insertions(+), 40 deletions(-)
 copy arch/arm64/boot/dts/freescale/{fsl-ls2085a-simu.dts => fsl-ls2085a-qds.dts} (51%)
 copy arch/arm64/boot/dts/freescale/{fsl-ls2085a-simu.dts => fsl-ls2085a-rdb.dts} (69%)

-- 
1.7.9.5

[RESEND PATCH 1/8] Documentation: DT: Add entry for FSL LS2085A QDS and RDB boards

[Bhupesh Sharma]

This patch adds a devicetree binding documentation for FSL's
LS2085A QDS and RDB boards.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
 Documentation/devicetree/bindings/arm/fsl.txt |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index a5462b6..29b53a7 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -132,3 +132,11 @@ LS2085A ARMv8 based Simulator model
 Required root node properties:
     - compatible = "fsl,ls2085a-simu", "fsl,ls2085a";
 
+LS2085A ARMv8 based QDS Board
+Required root node properties:
+    - compatible = "fsl,ls2085a-qds", "fsl,ls2085a";
+
+LS2085A ARMv8 based RDB Board
+Required root node properties:
+    - compatible = "fsl,ls2085a-rdb", "fsl,ls2085a";
+
-- 
1.7.9.5

[RESEND PATCH 2/8] doc/bindings: Update PCIe devicetree binding documentation for LS2085A

[Bhupesh Sharma]

Add the documentation for compatible string "fsl,ls2085a-pcie"
for LS2085A platform.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
 .../devicetree/bindings/pci/layerscape-pci.txt     |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 6286f04..0654809 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -4,7 +4,8 @@ This PCIe host controller is based on the Synopsis Designware PCIe IP
 and thus inherits all the common properties defined in designware-pcie.txt.
 
 Required properties:
-- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie"
+- compatible: should contain the platform identifier such as "fsl,ls1021a-pcie",
+  "fsl,ls2085a-pcie".
 - reg: base addresses and lengths of the PCIe controller
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
-- 
1.7.9.5

[RESEND PATCH 3/8] doc/bindings: Update clk-qoriq bindings for FSL's chassis-3.0 SoCs

[Bhupesh Sharma]

This patch updates the 'clk-qoriq' device-tree bindings for
chassis-3.0 compliant SoCs from FSL, for e.g. LS2085A

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
 .../devicetree/bindings/clock/qoriq-clock.txt      |   14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index df4a259..60d758e 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -14,6 +14,7 @@ Chassis Version		Example Chips
 ---------------		-------------
 1.0			p4080, p5020, p5040
 2.0			t4240, b4860, t1040
+3.0			ls2085a
 
 1. Clock Block Binding
 
@@ -30,9 +31,11 @@ Required properties:
 	* "fsl,b4420-clockgen"
 	* "fsl,b4860-clockgen"
 	* "fsl,ls1021a-clockgen"
+	* "fsl,ls2085a-clockgen"
 	Chassis clock strings include:
 	* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
 	* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
+	* "fsl,qoriq-clockgen-3.0": for chassis 3.0 clocks
 - reg: Describes the address of the device's resources within the
 	address space defined by its parent bus, and resource zero
 	represents the clock register set
@@ -57,18 +60,23 @@ Required properties:
 - compatible : Should include one of the following:
 	* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
 	* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
+	* "fsl,qoriq-core-pll-3.0" for core PLL clocks (v3.0)
 	* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0)
 	* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0)
+	* "fsl,qoriq-core-mux-3.0" for core mux clocks (v3.0)
 	* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0).
 		It takes parent's clock-frequency as its clock.
 	* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
 		It takes parent's clock-frequency as its clock.
+	* "fsl,qoriq-sysclk-3.0": for input system clock (v3.0).
+		It takes parent's clock-frequency as its clock.
 	* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
 	* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
+	* "fsl,qoriq-platform-pll-3.0" for the platform PLL clock (v3.0)
 - #clock-cells: From common clock binding. The number of cells in a
-	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
-	clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
-	For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
+	clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2,3].0"
+	clocks, or <1> for "fsl,qoriq-core-pll-[1,2,3].0" clocks.
+	For "fsl,qoriq-core-pll-[1,2,3].0" clocks, the single
 	clock-specifier cell may take the following values:
 	* 0 - equal to the PLL frequency
 	* 1 - equal to the PLL frequency divided by 2
-- 
1.7.9.5

[RESEND PATCH 4/8] layerscape/ftm: Add compatible string for FTM0 be used as alarm timer.

[Bhupesh Sharma]

From: Wang Dongsheng <dongsheng.wang@freescale.com>

Only FTM0 can be used as an alarm timer, so add a "fsl,ftm-alarm"
compatible string to describe FTM0 alarm mode.

Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
 .../devicetree/bindings/timer/fsl,ftm-timer.txt    |   46 ++++++++++++++------
 1 file changed, 32 insertions(+), 14 deletions(-)

diff --git a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
index aa8c402..a372ed7 100644
--- a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
+++ b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
@@ -2,12 +2,18 @@ Freescale FlexTimer Module (FTM) Timer
 
 Required properties:
 
-- compatible : should be "fsl,ftm-timer"
+- compatible : should be "fsl,ftm-timer" & "fsl,ftm-alarm".
+  (a) "fsl,ftm-timer", for FlexTimer compatible as normal timer.
+  (b) "fsl,ftm-alarm", for FlexTimer compatible when FTM0 as an ALARM timer.
+
 - reg : Specifies base physical address and size of the register sets for the
   clock event device and clock source device.
+
 - interrupts : Should be the clock event device interrupt.
+
 - clocks : The clocks provided by the SoC to drive the timer, must contain an
   entry for each entry in clock-names.
+
 - clock-names : Must include the following entries:
   o "ftm-evt"
   o "ftm-src"
@@ -16,16 +22,28 @@ Required properties:
 - big-endian: One boolean property, the big endian mode will be in use if it is
   present, or the little endian mode will be in use for all the device registers.
 
-Example:
-ftm: ftm at 400b8000 {
-	compatible = "fsl,ftm-timer";
-	reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
-	interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
-	clock-names = "ftm-evt", "ftm-src",
-		"ftm-evt-counter-en", "ftm-src-counter-en";
-	clocks = <&clks VF610_CLK_FTM2>,
-		<&clks VF610_CLK_FTM3>,
-		<&clks VF610_CLK_FTM2_EXT_FIX_EN>,
-		<&clks VF610_CLK_FTM3_EXT_FIX_EN>;
-	big-endian;
-};
+Example 1: In this example, The FlexTimer module (FTM) is a two-to-eight,
+	   channel timer that supports input capture, output compare, and
+	   the generation of PWM signals to control electric motor and power
+	   management applications.
+
+	ftm: ftm at 400b8000 {
+		compatible = "fsl,ftm-timer";
+		reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
+		interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "ftm-evt", "ftm-src",
+			"ftm-evt-counter-en", "ftm-src-counter-en";
+		clocks = <&clks VF610_CLK_FTM2>,
+			<&clks VF610_CLK_FTM3>,
+			<&clks VF610_CLK_FTM2_EXT_FIX_EN>,
+			<&clks VF610_CLK_FTM3_EXT_FIX_EN>;
+		big-endian;
+	};
+
+Example 2: In this example, FTM0 only be used as an alarm timer.
+
+	ftm0: ftm0 at 2800000 {
+		compatible = "fsl,ftm-alarm";
+		reg = <0x0 0x2800000 0x0 0x10000>;
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+	};
-- 
1.7.9.5

[RESEND PATCH 5/8] dts/ls2085a: Update DTSI to add support of various peripherals

[Bhupesh Sharma]

This patch updates the LS2085a DTSI (DTS Include) file to add
support for various peripherals supported by FSL LS2085a SoC, for e.g.:
	- USB 3.0 Host
	- PMU
	- Watchdog
	- SPI
	- etc.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Haikun Wang <b53464@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi |  523 +++++++++++++++++++++++-
 1 file changed, 520 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi
index e281ceb..2c2418f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi
@@ -1,7 +1,7 @@
 /*
  * Device Tree Include file for Freescale Layerscape-2085A family SoC.
  *
- * Copyright (C) 2014, Freescale Semiconductor
+ * Copyright (C) 2014-15, Freescale Semiconductor
  *
  * Bhupesh Sharma <bhupesh.sharma@freescale.com>
  *
@@ -122,13 +122,129 @@
 		      /* DRAM space - 1, size : 2 GB DRAM */
 	};
 
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
+	};
+
 	gic: interrupt-controller at 6000000 {
 		compatible = "arm,gic-v3";
 		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
 		      <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
 		#interrupt-cells = <3>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
 		interrupt-controller;
 		interrupts = <1 9 0x4>;
+
+		its: gic-its at 6020000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			reg = <0x0 0x6020000 0 0x20000>;
+		};
+	};
+
+	clockgen: clocking at 1300000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x1300000 0xa0000>;
+
+		sysclk: sysclk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+			clock-output-names = "sysclk";
+		};
+
+		cga_pll1: pll at 80 {
+			compatible = "fsl,qoriq-core-pll-3.0";
+			#clock-cells = <1>;
+			reg = <0x80 0x10>;
+			clocks = <&sysclk>;
+			clock-output-names = "cga-pll1", "cga-pll1-div2",
+					     "cga-pll1-div3", "cga-pll1-div4";
+		};
+
+		cga_pll2: pll at a00 {
+			compatible = "fsl,qoriq-core-pll-3.0";
+			#clock-cells = <1>;
+			reg = <0xa0 0x10>;
+			clocks = <&sysclk>;
+			clock-output-names = "cga-pll2", "cga-pll2-div2",
+					     "cga-pll2-div3", "cga-pll2-div4";
+		};
+
+		cgb_pll1: pll at 10080 {
+			compatible = "fsl,qoriq-core-pll-3.0";
+			#clock-cells = <1>;
+			reg = <0x10080 0x10>;
+			clocks = <&sysclk>;
+			clock-output-names = "cgb-pll1", "cgb-pll1-div2",
+					     "cgb-pll1-div3", "cgb-pll1-div4";
+		};
+
+		cgb_pll2: pll at 100a0 {
+			compatible = "fsl,qoriq-core-pll-3.0";
+			#clock-cells = <1>;
+			reg = <0x100a0 0x10>;
+			clocks = <&sysclk>;
+			clock-output-names = "cgb-pll2", "cgb-pll2-div2",
+					     "cgb-pll2-div3", "cgb-pll2-div4";
+		};
+
+		platform_clk: pll at 60080 {
+			compatible = "fsl,qoriq-core-pll-3.0";
+			#clock-cells = <1>;
+			reg = <0x60080 0x10>;
+			clocks = <&sysclk>;
+			clock-output-names = "platform-clk",
+					     "platform-clk-div2";
+		};
+
+		cluster1_clk: clk0c0 at 70000 {
+			compatible = "fsl,qoriq-core-mux-3.0";
+			#clock-cells = <0>;
+			reg = <0x70000 0x10>;
+			clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4",
+				      "pll2cga", "pll2cga-div2", "pll2cga-div4";
+			clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>,
+				 <&cga_pll2 0>, <&cga_pll2 1>, <&cga_pll2 2>;
+			clock-output-names = "cluster1-clk";
+		};
+
+		cluster2_clk: clk0c0 at 70020 {
+			compatible = "fsl,qoriq-core-mux-3.0";
+			#clock-cells = <0>;
+			reg = <0x70020 0x10>;
+			clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4",
+				      "pll2cga", "pll2cga-div2", "pll2cga-div4";
+			clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>,
+				 <&cga_pll2 0>, <&cga_pll2 1>, <&cga_pll2 2>;
+			clock-output-names = "cluster2-clk";
+		};
+
+		cluster3_clk: clk0c0 at 70040 {
+			compatible = "fsl,qoriq-core-mux-3.0";
+			#clock-cells = <0>;
+			reg = <0x70040 0x10>;
+			clock-names = "pll1cgb", "pll1cgb-div2", "pll1cgb-div4",
+				      "pll2cgb", "pll2cgb-div2", "pll2cgb-div4";
+			clocks = <&cgb_pll1 0>, <&cgb_pll1 1>, <&cgb_pll1 2>,
+				 <&cgb_pll2 0>, <&cgb_pll2 1>, <&cgb_pll2 2>;
+			clock-output-names = "cluster3-clk";
+		};
+
+		cluster4_clk: clk0c0 at 70060 {
+			compatible = "fsl,qoriq-core-mux-3.0";
+			#clock-cells = <0>;
+			reg = <0x70060 0x10>;
+			clock-names = "pll1cgb", "pll1cgb-div2", "pll1cgb-div4",
+				      "pll2cgb", "pll2cgb-div2", "pll2cgb-div4";
+			clocks = <&cgb_pll1 0>, <&cgb_pll1 1>, <&cgb_pll1 2>,
+				 <&cgb_pll2 0>, <&cgb_pll2 1>, <&cgb_pll2 2>;
+			clock-output-names = "cluster4-clk";
+		};
 	};
 
 	timer {
@@ -139,12 +255,83 @@
 			     <1 10 0x8>; /* Hypervisor PPI, active-low */
 	};
 
+	amba {
+		compatible = "arm,amba-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cluster1_core0_watchdog: wdt at c000000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0xc000000 0x0 0x1000>;
+			interrupts = <1 12 0x8>; /* PPI, Level low type */
+			clocks = <&platform_clk 1>;
+			clock-names = "apb_pclk";
+		};
+
+		cluster1_core1_watchdog: wdt at c010000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0xc010000 0x0 0x1000>;
+			interrupts = <1 12 0x8>; /* PPI, Level low type */
+			clocks = <&platform_clk 1>;
+			clock-names = "apb_pclk";
+		};
+
+		cluster2_core0_watchdog: wdt at c100000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0xc100000 0x0 0x1000>;
+			interrupts = <1 12 0x8>; /* PPI, Level low type */
+			clocks = <&platform_clk 1>;
+			clock-names = "apb_pclk";
+		};
+
+		cluster2_core1_watchdog: wdt at c110000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0xc110000 0x0 0x1000>;
+			interrupts = <1 12 0x8>; /* PPI, Level low type */
+			clocks = <&platform_clk 1>;
+			clock-names = "apb_pclk";
+		};
+
+		cluster3_core0_watchdog: wdt at c200000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0xc200000 0x0 0x1000>;
+			interrupts = <1 12 0x8>; /* PPI, Level low type */
+			clocks = <&platform_clk 1>;
+			clock-names = "apb_pclk";
+		};
+
+		cluster3_core1_watchdog: wdt at c210000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0xc210000 0x0 0x1000>;
+			interrupts = <1 12 0x8>; /* PPI, Level low type */
+			clocks = <&platform_clk 1>;
+			clock-names = "apb_pclk";
+		};
+
+		cluster4_core0_watchdog: wdt at c300000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0xc300000 0x0 0x1000>;
+			interrupts = <1 12 0x8>; /* PPI, Level low type */
+			clocks = <&platform_clk 1>;
+			clock-names = "apb_pclk";
+		};
+
+		cluster4_core1_watchdog: wdt at c310000 {
+			compatible = "arm,primecell";
+			reg = <0x0 0xc310000 0x0 0x1000>;
+			interrupts = <1 12 0x8>; /* PPI, Level low type */
+			clocks = <&platform_clk 1>;
+			clock-names = "apb_pclk";
+		};
+	};
+
 	serial0: serial at 21c0500 {
 		device_type = "serial";
 		compatible = "fsl,ns16550", "ns16550a";
 		reg = <0x0 0x21c0500 0x0 0x100>;
 		clock-frequency = <0>;	/* Updated by bootloader */
-		interrupts = <0 32 0x1>; /* edge triggered */
+		interrupts = <0 32 0x4>; /* Level high type */
 	};
 
 	serial1: serial at 21c0600 {
@@ -152,12 +339,342 @@
 		compatible = "fsl,ns16550", "ns16550a";
 		reg = <0x0 0x21c0600 0x0 0x100>;
 		clock-frequency = <0>; 	/* Updated by bootloader */
-		interrupts = <0 32 0x1>; /* edge triggered */
+		interrupts = <0 32 0x4>; /* Level high type */
 	};
 
 	fsl_mc: fsl-mc at 80c000000 {
 		compatible = "fsl,qoriq-mc";
+		#stream-id-cells = <2>;
 		reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
 		      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
+		lpi-parent = <&its>;
+	};
+
+	smmu: iommu at 5000000 {
+		compatible = "arm,mmu-500";
+		reg = <0 0x5000000 0 0x800000>;
+		#global-interrupts = <12>;
+		interrupts = <0 13 4>, /* global secure fault */
+			     <0 14 4>, /* combined secure interrupt */
+			     <0 15 4>, /* global non-secure fault */
+			     <0 16 4>, /* combined non-secure interrupt */
+			/* performance counter interrupts 0-7 */
+			     <0 211 4>,
+			     <0 212 4>,
+			     <0 213 4>,
+			     <0 214 4>,
+			     <0 215 4>,
+			     <0 216 4>,
+			     <0 217 4>,
+			     <0 218 4>,
+			/* per context interrupt, 64 interrupts */
+			     <0 146 4>,
+			     <0 147 4>,
+			     <0 148 4>,
+			     <0 149 4>,
+			     <0 150 4>,
+			     <0 151 4>,
+			     <0 152 4>,
+			     <0 153 4>,
+			     <0 154 4>,
+			     <0 155 4>,
+			     <0 156 4>,
+			     <0 157 4>,
+			     <0 158 4>,
+			     <0 159 4>,
+			     <0 160 4>,
+			     <0 161 4>,
+			     <0 162 4>,
+			     <0 163 4>,
+			     <0 164 4>,
+			     <0 165 4>,
+			     <0 166 4>,
+			     <0 167 4>,
+			     <0 168 4>,
+			     <0 169 4>,
+			     <0 170 4>,
+			     <0 171 4>,
+			     <0 172 4>,
+			     <0 173 4>,
+			     <0 174 4>,
+			     <0 175 4>,
+			     <0 176 4>,
+			     <0 177 4>,
+			     <0 178 4>,
+			     <0 179 4>,
+			     <0 180 4>,
+			     <0 181 4>,
+			     <0 182 4>,
+			     <0 183 4>,
+			     <0 184 4>,
+			     <0 185 4>,
+			     <0 186 4>,
+			     <0 187 4>,
+			     <0 188 4>,
+			     <0 189 4>,
+			     <0 190 4>,
+			     <0 191 4>,
+			     <0 192 4>,
+			     <0 193 4>,
+			     <0 194 4>,
+			     <0 195 4>,
+			     <0 196 4>,
+			     <0 197 4>,
+			     <0 198 4>,
+			     <0 199 4>,
+			     <0 200 4>,
+			     <0 201 4>,
+			     <0 202 4>,
+			     <0 203 4>,
+			     <0 204 4>,
+			     <0 205 4>,
+			     <0 206 4>,
+			     <0 207 4>,
+			     <0 208 4>,
+			     <0 209 4>;
+		mmu-masters = <&fsl_mc 0x300 0>;
+	};
+
+	dspi: dspi at 2100000 {
+		compatible = "fsl,vf610-dspi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2100000 0x0 0x10000>;
+		interrupts = <0 26 0x4>; /* Level high type */
+		tcfq-mode;
+		clocks = <&platform_clk 1>;
+		clock-names = "dspi";
+		spi-num-chipselects = <5>;
+		bus-num = <0>;
+		spi-cpol;
+		spi-cpha;
+	};
+
+	esdhc: esdhc at 2140000 {
+		compatible = "fsl,ls2085a-esdhc", "fsl,esdhc";
+		reg = <0x0 0x2140000 0x0 0x10000>;
+		interrupts = <0 28 0x4>; /* Level high type */
+		clock-frequency = <0>;
+		voltage-ranges = <1800 1800 3300 3300>;
+		sdhci,auto-cmd12;
+		little-endian;
+		bus-width = <4>;
+	};
+
+	ftm0: ftm0 at 2800000 {
+		compatible = "fsl,ftm-alarm";
+		reg = <0x0 0x2800000 0x0 0x10000>;
+		interrupts = <0 44 4>;
+	};
+
+	gpio0: gpio at 2300000 {
+		compatible = "fsl,ls2085a-gpio";
+		reg = <0x0 0x2300000 0x0 0x10000>;
+		interrupts = <0 36 0x4>; /* Level high type */
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio1: gpio at 2310000 {
+		compatible = "fsl,ls2085a-gpio";
+		reg = <0x0 0x2310000 0x0 0x10000>;
+		interrupts = <0 36 0x4>; /* Level high type */
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio2: gpio at 2320000 {
+		compatible = "fsl,ls2085a-gpio";
+		reg = <0x0 0x2320000 0x0 0x10000>;
+		interrupts = <0 37 0x4>; /* Level high type */
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	gpio3: gpio at 2330000 {
+		compatible = "fsl,ls2085a-gpio";
+		reg = <0x0 0x2330000 0x0 0x10000>;
+		interrupts = <0 37 0x4>; /* Level high type */
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
+	i2c0: i2c at 2000000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2000000 0x0 0x10000>;
+		interrupts = <0 34 0x4>; /* Level high type */
+		clock-names = "i2c";
+		clocks = <&platform_clk 1>;
+	};
+
+	i2c1: i2c at 2010000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2010000 0x0 0x10000>;
+		interrupts = <0 34 0x4>; /* Level high type */
+		clock-names = "i2c";
+		clocks = <&platform_clk 1>;
+	};
+
+	i2c2: i2c at 2020000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2020000 0x0 0x10000>;
+		interrupts = <0 35 0x4>; /* Level high type */
+		clock-names = "i2c";
+		clocks = <&platform_clk 1>;
+	};
+
+	i2c3: i2c at 2030000 {
+		compatible = "fsl,vf610-i2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x2030000 0x0 0x10000>;
+		interrupts = <0 35 0x4>; /* Level high type */
+		clock-names = "i2c";
+		clocks = <&platform_clk 1>;
+	};
+
+	ifc: ifc at 2240000 {
+		compatible = "fsl,ifc", "simple-bus";
+		reg = <0x0 0x2240000 0x0 0x20000>;
+		interrupts = <0 21 0x4>; /* Level high type */
+		little-endian;
+		#address-cells = <2>;
+		#size-cells = <1>;
+
+		ranges = <0 0 0x5 0x80000000 0x08000000
+			  2 0 0x5 0x30000000 0x00010000
+			  3 0 0x5 0x20000000 0x00010000>;
+	};
+
+	qspi: quadspi at 20c0000 {
+		compatible = "fsl,vf610-qspi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x0 0x20c0000 0x0 0x10000>,
+		      <0x0 0x20000000 0x0 0x10000000>;
+		reg-names = "QuadSPI", "QuadSPI-memory";
+		interrupts = <0 25 0x4>; /* Level high type */
+		clocks = <&platform_clk 1>, <&platform_clk 1>;
+		clock-names = "qspi_en", "qspi";
+	};
+
+	pcie at 3400000 {
+		compatible = "fsl,ls2085a-pcie", "snps,dw-pcie";
+		reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
+		       0x10 0x00000000 0x0 0x00002000>; /* configuration space */
+		reg-names = "regs", "config";
+		interrupts = <0 108 0x4>; /* Level high type */
+		interrupt-names = "intr";
+		num-atus = <6>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		num-lanes = <4>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
+				<0000 0 0 2 &gic 0 0 0 110 4>,
+				<0000 0 0 3 &gic 0 0 0 111 4>,
+				<0000 0 0 4 &gic 0 0 0 112 4>;
+	};
+
+	pcie at 3500000 {
+		compatible = "fsl,ls2085a-pcie", "snps,dw-pcie";
+		reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
+		       0x12 0x00000000 0x0 0x00002000>; /* configuration space */
+		reg-names = "regs", "config";
+		interrupts = <0 113 0x4>; /* Level high type */
+		interrupt-names = "intr";
+		num-atus = <6>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		num-lanes = <2>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
+				<0000 0 0 2 &gic 0 0 0 115 4>,
+				<0000 0 0 3 &gic 0 0 0 116 4>,
+				<0000 0 0 4 &gic 0 0 0 117 4>;
+	};
+
+	pcie at 3600000 {
+		compatible = "fsl,ls2085a-pcie", "snps,dw-pcie";
+		reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
+		       0x14 0x00000000 0x0 0x00002000>; /* configuration space */
+		reg-names = "regs", "config";
+		interrupts = <0 118 0x4>; /* Level high type */
+		interrupt-names = "intr";
+		num-atus = <6>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		num-lanes = <4>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
+				<0000 0 0 2 &gic 0 0 0 120 4>,
+				<0000 0 0 3 &gic 0 0 0 121 4>,
+				<0000 0 0 4 &gic 0 0 0 122 4>;
+	};
+
+	pcie at 3700000 {
+		compatible = "fsl,ls2085a-pcie", "snps,dw-pcie";
+		reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
+		       0x16 0x00000000 0x0 0x00002000>; /* configuration space */
+		reg-names = "regs", "config";
+		interrupts = <0 123 0x4>; /* Level high type */
+		interrupt-names = "intr";
+		num-atus = <6>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		num-lanes = <2>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
+				<0000 0 0 2 &gic 0 0 0 125 4>,
+				<0000 0 0 3 &gic 0 0 0 126 4>,
+				<0000 0 0 4 &gic 0 0 0 127 4>;
+	};
+
+	usb0: usb3 at 3100000 {
+		compatible = "snps,dwc3";
+		reg = <0x0 0x3100000 0x0 0x10000>;
+		interrupts = <0 80 0x4>; /* Level high type */
+		dr_mode = "host";
+	};
+
+	usb1: usb3 at 3110000 {
+		compatible = "snps,dwc3";
+		reg = <0x0 0x3110000 0x0 0x10000>;
+		interrupts = <0 81 0x4>; /* Level high type */
+		dr_mode = "host";
 	};
 };
-- 
1.7.9.5

[RESEND PATCH 6/8] dts/ls2085a: Update Simulator DTS to add support of various peripherals

[Bhupesh Sharma]

This patch updates the LS2085a simulator DTS to add support of various
peripherals which are supported on the simulator platform and explicitly
disables those which are yet not supported on the platform.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls2085a-simu.dts |   40 ++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2085a-simu.dts b/arch/arm64/boot/dts/freescale/fsl-ls2085a-simu.dts
index 82e2a6f..8cd4a4d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2085a-simu.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2085a-simu.dts
@@ -63,3 +63,43 @@
 		interrupts = <0 58 0x1>;
 	};
 };
+
+&esdhc {
+	status = "disabled";
+};
+
+&ifc {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "disabled";
+};
+
+&i2c1 {
+	status = "disabled";
+};
+
+&i2c2 {
+	status = "disabled";
+};
+
+&i2c3 {
+	status = "disabled";
+};
+
+&dspi {
+	status = "disabled";
+};
+
+&qspi {
+	status = "disabled";
+};
+
+&usb0 {
+	status = "disabled";
+};
+
+&usb1 {
+	status = "disabled";
+};
-- 
1.7.9.5

[RESEND PATCH 7/8] dts/ls2085a: Add DTS support for LS2085a QDS & RDB boards

[Bhupesh Sharma]

This patch adds the LS2085a DTS files for QDS and RDB boards
which support the LS2085a SoC.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
 arch/arm64/boot/dts/freescale/fsl-ls2085a-qds.dts |  187 +++++++++++++++++++++
 arch/arm64/boot/dts/freescale/fsl-ls2085a-rdb.dts |  123 ++++++++++++++
 2 files changed, 310 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2085a-qds.dts
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2085a-rdb.dts

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2085a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2085a-qds.dts
new file mode 100644
index 0000000..38b62d7
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2085a-qds.dts
@@ -0,0 +1,187 @@
+/*
+ * Device Tree file for Freescale LS2085a QDS Board.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * Bhupesh Sharma <bhupesh.sharma@freescale.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+/include/ "fsl-ls2085a.dtsi"
+
+/ {
+	model = "Freescale Layerscape 2085a QDS Board";
+	compatible = "fsl,ls2085a-qds", "fsl,ls2085a";
+};
+
+&esdhc {
+	status = "okay";
+};
+
+&ifc {
+	status = "okay";
+	#address-cells = <2>;
+	#size-cells = <1>;
+	ranges = <0x0 0x0 0x5 0x80000000 0x08000000>;
+
+	nor at 0,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "cfi-flash";
+		reg = <0x0 0x0 0x8000000>;
+		bank-width = <2>;
+		device-width = <1>;
+	};
+};
+
+&ftm0 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	pca9547 at 77 {
+		compatible = "nxp,pca9547";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		i2c at 0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x00>;
+			rtc at 68 {
+				compatible = "dallas,ds3232";
+				reg = <0x68>;
+			};
+		};
+
+		i2c at 2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x02>;
+
+			ina220 at 40 {
+				compatible = "ti,ina220";
+				reg = <0x40>;
+				shunt-resistor = <500>;
+			};
+
+			ina220 at 41 {
+				compatible = "ti,ina220";
+				reg = <0x41>;
+				shunt-resistor = <1000>;
+			};
+		};
+
+		i2c at 3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+
+			adt7481 at 4c {
+				compatible = "adi,adt7461";
+				reg = <0x4c>;
+			};
+		};
+	};
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&dspi {
+	status = "okay";
+	dflash0: n25q128a {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p80";
+		spi-max-frequency = <3000000>;
+		reg = <0>;
+	};
+	dflash1: sst25wf040b {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p80";
+		spi-max-frequency = <3000000>;
+		reg = <1>;
+	};
+	dflash2: en25s64 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p80";
+		spi-max-frequency = <3000000>;
+		reg = <2>;
+	};
+};
+
+&qspi {
+	status = "okay";
+	qflash0: s25fl008k {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p80";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2085a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2085a-rdb.dts
new file mode 100644
index 0000000..43eef18
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2085a-rdb.dts
@@ -0,0 +1,123 @@
+/*
+ * Device Tree file for Freescale LS2085a RDB Board.
+ *
+ * Copyright (C) 2015, Freescale Semiconductor
+ *
+ * Bhupesh Sharma <bhupesh.sharma@freescale.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+/include/ "fsl-ls2085a.dtsi"
+
+/ {
+	model = "Freescale Layerscape 2085a RDB Board";
+	compatible = "fsl,ls2085a-rdb", "fsl,ls2085a";
+};
+
+&esdhc {
+	status = "okay";
+};
+
+&ifc {
+	status = "okay";
+	#address-cells = <2>;
+	#size-cells = <1>;
+	ranges = <0x0 0x0 0x5 0x80000000 0x08000000>;
+
+	nor at 0,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "cfi-flash";
+		reg = <0x0 0x0 0x8000000>;
+		bank-width = <2>;
+		device-width = <1>;
+	};
+
+};
+
+&ftm0 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&dspi {
+	status = "okay";
+	dflash0: n25q512a {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p80";
+		spi-max-frequency = <3000000>;
+		reg = <0>;
+	};
+};
+
+&qspi {
+	status = "disabled";
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
-- 
1.7.9.5

[RESEND PATCH 8/8] dts/Makefile: Add build support for LS2085a QDS & RDB board DTS

[Bhupesh Sharma]

This patch adds build support for LS2085a QDS & RDB board DTS files
in the arm64 DTS Makefile.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
 arch/arm64/boot/dts/freescale/Makefile |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 4f2de3e7..a4fb84b 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -1,4 +1,4 @@
-dtb-$(CONFIG_ARCH_FSL_LS2085A) += fsl-ls2085a-simu.dtb
+dtb-$(CONFIG_ARCH_FSL_LS2085A) += fsl-ls2085a-qds.dtb fsl-ls2085a-rdb.dtb fsl-ls2085a-simu.dtb
  
 always		:= $(dtb-y)
 subdir-y	:= $(dts-dirs)
-- 
1.7.9.5

[RESEND PATCH 4/8] layerscape/ftm: Add compatible string for FTM0 be used as alarm timer.

[Mark Rutland]

On Wed, Apr 01, 2015 at 12:47:34PM +0100, Bhupesh Sharma wrote:
> From: Wang Dongsheng <dongsheng.wang@freescale.com>
> 
> Only FTM0 can be used as an alarm timer, so add a "fsl,ftm-alarm"
> compatible string to describe FTM0 alarm mode.
> 
> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
> Reviewed-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> ---
>  .../devicetree/bindings/timer/fsl,ftm-timer.txt    |   46 ++++++++++++++------
>  1 file changed, 32 insertions(+), 14 deletions(-)

Shouldn't there be a corresponding driver update?

There wasn't one in this series.

> 
> diff --git a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
> index aa8c402..a372ed7 100644
> --- a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
> +++ b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
> @@ -2,12 +2,18 @@ Freescale FlexTimer Module (FTM) Timer
>  
>  Required properties:
>  
> -- compatible : should be "fsl,ftm-timer"
> +- compatible : should be "fsl,ftm-timer" & "fsl,ftm-alarm".
> +  (a) "fsl,ftm-timer", for FlexTimer compatible as normal timer.
> +  (b) "fsl,ftm-alarm", for FlexTimer compatible when FTM0 as an ALARM timer.


Lets not be redundant here. This would be better as:

- compatible: should contain one of:
  * "fsl,ftm-timer" for a FlexTimer usable as a normal timer.
  * "fsl,ftm-alarm" for a FlexTimer usable as an ALARM timer.

I don't think FTM0 is useful to mention here; it sounds like that's just
the name of an instance on a particular design.

What exactly is the difference between a "normal" timer and an "alarm"
timer?

> +
>  - reg : Specifies base physical address and size of the register sets for the
>    clock event device and clock source device.
> +
>  - interrupts : Should be the clock event device interrupt.
> +
>  - clocks : The clocks provided by the SoC to drive the timer, must contain an
>    entry for each entry in clock-names.
> +
>  - clock-names : Must include the following entries:
>    o "ftm-evt"
>    o "ftm-src"
> @@ -16,16 +22,28 @@ Required properties:
>  - big-endian: One boolean property, the big endian mode will be in use if it is
>    present, or the little endian mode will be in use for all the device registers.
>  
> -Example:
> -ftm: ftm at 400b8000 {
> -	compatible = "fsl,ftm-timer";
> -	reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
> -	interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
> -	clock-names = "ftm-evt", "ftm-src",
> -		"ftm-evt-counter-en", "ftm-src-counter-en";
> -	clocks = <&clks VF610_CLK_FTM2>,
> -		<&clks VF610_CLK_FTM3>,
> -		<&clks VF610_CLK_FTM2_EXT_FIX_EN>,
> -		<&clks VF610_CLK_FTM3_EXT_FIX_EN>;
> -	big-endian;
> -};
> +Example 1: In this example, The FlexTimer module (FTM) is a two-to-eight,
> +	   channel timer that supports input capture, output compare, and
> +	   the generation of PWM signals to control electric motor and power
> +	   management applications.
> +
> +	ftm: ftm at 400b8000 {
> +		compatible = "fsl,ftm-timer";
> +		reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
> +		interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
> +		clock-names = "ftm-evt", "ftm-src",
> +			"ftm-evt-counter-en", "ftm-src-counter-en";
> +		clocks = <&clks VF610_CLK_FTM2>,
> +			<&clks VF610_CLK_FTM3>,
> +			<&clks VF610_CLK_FTM2_EXT_FIX_EN>,
> +			<&clks VF610_CLK_FTM3_EXT_FIX_EN>;
> +		big-endian;
> +	};
> +
> +Example 2: In this example, FTM0 only be used as an alarm timer.

Do you mean that FTM0 is the only instance usable as an alarm timer, or
that the FTM0 instance can only be used as an alarm timer?

> +
> +	ftm0: ftm0 at 2800000 {
> +		compatible = "fsl,ftm-alarm";
> +		reg = <0x0 0x2800000 0x0 0x10000>;
> +		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> +	};

Missing properties?

Mark.

[RESEND PATCH 4/8] layerscape/ftm: Add compatible string for FTM0 be used as alarm timer.

[Dongsheng.Wang at freescale.com]

> -----Original Message-----
> From: Mark Rutland [mailto:mark.rutland at arm.com]
> Sent: Wednesday, April 01, 2015 9:24 PM
> To: Sharma Bhupesh-B45370
> Cc: arnd at arndb.de; linux-arm-kernel at lists.infradead.org; Marc Zyngier;
> bhupesh.linux at gmail.com; Catalin Marinas; Yoder Stuart-B08248; olof at lixom.net;
> Will Deacon; Wang Dongsheng-B40534
> Subject: Re: [RESEND PATCH 4/8] layerscape/ftm: Add compatible string for FTM0
> be used as alarm timer.
> 
> On Wed, Apr 01, 2015 at 12:47:34PM +0100, Bhupesh Sharma wrote:
> > From: Wang Dongsheng <dongsheng.wang@freescale.com>
> >
> > Only FTM0 can be used as an alarm timer, so add a "fsl,ftm-alarm"
> > compatible string to describe FTM0 alarm mode.
> >
> > Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
> > Reviewed-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
> > ---
> >  .../devicetree/bindings/timer/fsl,ftm-timer.txt    |   46 ++++++++++++++-----
> -
> >  1 file changed, 32 insertions(+), 14 deletions(-)
> 
> Shouldn't there be a corresponding driver update?
> 
> There wasn't one in this series.
> 

Hi Bhupesh, would you paste the driver link to here? Thanks very much.

> >
> > diff --git a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
> > b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
> > index aa8c402..a372ed7 100644
> > --- a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
> > +++ b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.txt
> > @@ -2,12 +2,18 @@ Freescale FlexTimer Module (FTM) Timer
> >
> >  Required properties:
> >
> > -- compatible : should be "fsl,ftm-timer"
> > +- compatible : should be "fsl,ftm-timer" & "fsl,ftm-alarm".
> > +  (a) "fsl,ftm-timer", for FlexTimer compatible as normal timer.
> > +  (b) "fsl,ftm-alarm", for FlexTimer compatible when FTM0 as an ALARM timer.
> 
> 
> Lets not be redundant here. This would be better as:
> 
> - compatible: should contain one of:
>   * "fsl,ftm-timer" for a FlexTimer usable as a normal timer.
>   * "fsl,ftm-alarm" for a FlexTimer usable as an ALARM timer.
> 

Looks better, thanks.

> I don't think FTM0 is useful to mention here; it sounds like that's just the
> name of an instance on a particular design.
> 
> What exactly is the difference between a "normal" timer and an "alarm"
> timer?
>

Only FTM0 can be used as alarm timer.
 
> > +
> >  - reg : Specifies base physical address and size of the register sets for the
> >    clock event device and clock source device.
> > +
> >  - interrupts : Should be the clock event device interrupt.
> > +
> >  - clocks : The clocks provided by the SoC to drive the timer, must contain an
> >    entry for each entry in clock-names.
> > +
> >  - clock-names : Must include the following entries:
> >    o "ftm-evt"
> >    o "ftm-src"
> > @@ -16,16 +22,28 @@ Required properties:
> >  - big-endian: One boolean property, the big endian mode will be in use if it
> is
> >    present, or the little endian mode will be in use for all the device
> registers.
> >
> > -Example:
> > -ftm: ftm at 400b8000 {
> > -	compatible = "fsl,ftm-timer";
> > -	reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
> > -	interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
> > -	clock-names = "ftm-evt", "ftm-src",
> > -		"ftm-evt-counter-en", "ftm-src-counter-en";
> > -	clocks = <&clks VF610_CLK_FTM2>,
> > -		<&clks VF610_CLK_FTM3>,
> > -		<&clks VF610_CLK_FTM2_EXT_FIX_EN>,
> > -		<&clks VF610_CLK_FTM3_EXT_FIX_EN>;
> > -	big-endian;
> > -};
> > +Example 1: In this example, The FlexTimer module (FTM) is a two-to-eight,
> > +	   channel timer that supports input capture, output compare, and
> > +	   the generation of PWM signals to control electric motor and power
> > +	   management applications.
> > +
> > +	ftm: ftm at 400b8000 {
> > +		compatible = "fsl,ftm-timer";
> > +		reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
> > +		interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
> > +		clock-names = "ftm-evt", "ftm-src",
> > +			"ftm-evt-counter-en", "ftm-src-counter-en";
> > +		clocks = <&clks VF610_CLK_FTM2>,
> > +			<&clks VF610_CLK_FTM3>,
> > +			<&clks VF610_CLK_FTM2_EXT_FIX_EN>,
> > +			<&clks VF610_CLK_FTM3_EXT_FIX_EN>;
> > +		big-endian;
> > +	};
> > +
> > +Example 2: In this example, FTM0 only be used as an alarm timer.
> 
> Do you mean that FTM0 is the only instance usable as an alarm timer, or that the
> FTM0 instance can only be used as an alarm timer?
> 

Ditto.

> > +
> > +	ftm0: ftm0 at 2800000 {
> > +		compatible = "fsl,ftm-alarm";
> > +		reg = <0x0 0x2800000 0x0 0x10000>;
> > +		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> > +	};
> 
> Missing properties?
> 

The FTM0 alarm timer only need "compatible", "reg" and "interrupts" properties.
I miss something about the properties?

Regards,
-Dongsheng

[RESEND PATCH 4/8] layerscape/ftm: Add compatible string for FTM0 be used as alarm timer.

[Mark Rutland]

> > > +	ftm0: ftm0 at 2800000 {
> > > +		compatible = "fsl,ftm-alarm";
> > > +		reg = <0x0 0x2800000 0x0 0x10000>;
> > > +		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> > > +	};
> > 
> > Missing properties?
> > 
> 
> The FTM0 alarm timer only need "compatible", "reg" and "interrupts" properties.
> I miss something about the properties?

As far as I could tell from the original patch, clocks were also listed
as required properties regardless.

Mark.

[RESEND PATCH 4/8] layerscape/ftm: Add compatible string for FTM0 be used as alarm timer.

[Dongsheng.Wang at freescale.com]

> -----Original Message-----
> From: Mark Rutland [mailto:mark.rutland at arm.com]
> Sent: Tuesday, April 21, 2015 6:42 PM
> To: Wang Dongsheng-B40534
> Cc: Sharma Bhupesh-B45370; arnd at arndb.de; linux-arm-kernel at lists.infradead.org;
> Marc Zyngier; bhupesh.linux at gmail.com; Catalin Marinas; Yoder Stuart-B08248;
> olof at lixom.net; Will Deacon
> Subject: Re: [RESEND PATCH 4/8] layerscape/ftm: Add compatible string for FTM0
> be used as alarm timer.
> 
> > > > +	ftm0: ftm0 at 2800000 {
> > > > +		compatible = "fsl,ftm-alarm";
> > > > +		reg = <0x0 0x2800000 0x0 0x10000>;
> > > > +		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> > > > +	};
> > >
> > > Missing properties?
> > >
> >
> > The FTM0 alarm timer only need "compatible", "reg" and "interrupts" properties.
> > I miss something about the properties?
> 
> As far as I could tell from the original patch, clocks were also listed as
> required properties regardless.
> 

Yes, But only one clock can be used for FTM0 as alarm timer. So this node not need to
"clock" properties. :)

Regards,
-Dongsheng

[RESEND PATCH 4/8] layerscape/ftm: Add compatible string for FTM0 be used as alarm timer.

[Mark Rutland]

On Tue, Apr 21, 2015 at 12:01:06PM +0100, Dongsheng.Wang at freescale.com wrote:
> 
> 
> > -----Original Message-----
> > From: Mark Rutland [mailto:mark.rutland at arm.com]
> > Sent: Tuesday, April 21, 2015 6:42 PM
> > To: Wang Dongsheng-B40534
> > Cc: Sharma Bhupesh-B45370; arnd at arndb.de; linux-arm-kernel at lists.infradead.org;
> > Marc Zyngier; bhupesh.linux at gmail.com; Catalin Marinas; Yoder Stuart-B08248;
> > olof at lixom.net; Will Deacon
> > Subject: Re: [RESEND PATCH 4/8] layerscape/ftm: Add compatible string for FTM0
> > be used as alarm timer.
> > 
> > > > > +	ftm0: ftm0 at 2800000 {
> > > > > +		compatible = "fsl,ftm-alarm";
> > > > > +		reg = <0x0 0x2800000 0x0 0x10000>;
> > > > > +		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> > > > > +	};
> > > >
> > > > Missing properties?
> > > >
> > >
> > > The FTM0 alarm timer only need "compatible", "reg" and "interrupts" properties.
> > > I miss something about the properties?
> > 
> > As far as I could tell from the original patch, clocks were also listed as
> > required properties regardless.
> > 
> 
> Yes, But only one clock can be used for FTM0 as alarm timer. So this node not need to
> "clock" properties. :)

If the clock property is not necessary in some cases, please add those
caveats in the clock property description.

I'm not sure I follow why you don't need a clock in this case. Is there
a clock internal to the unit? Or is it simply that there is only one
possible external clock? For the latter it should still be described
explicitly.

Mark.