* [PATCH 1/4] drm/i915: Split SSEU init into functions by platform
2015-04-04 1:13 [PATCH 0/4 v2] BXT basic slice/subslice/EU stuff jeff.mcgee
@ 2015-04-04 1:13 ` jeff.mcgee
2015-04-04 1:13 ` [PATCH 2/4] drm/i915/bxt: Determine BXT slice/subslice/EU info jeff.mcgee
` (2 subsequent siblings)
3 siblings, 0 replies; 8+ messages in thread
From: jeff.mcgee @ 2015-04-04 1:13 UTC (permalink / raw)
To: intel-gfx
From: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
---
drivers/gpu/drm/i915/i915_dma.c | 234 +++++++++++++++++++++-------------------
1 file changed, 125 insertions(+), 109 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index ec661fe..9691f0f 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -564,6 +564,127 @@ static void i915_dump_device_info(struct drm_i915_private *dev_priv)
#undef SEP_COMMA
}
+static void cherryview_sseu_info_init(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_device_info *info;
+ u32 fuse, eu_dis;
+
+ info = (struct intel_device_info *)&dev_priv->info;
+ fuse = I915_READ(CHV_FUSE_GT);
+
+ info->slice_total = 1;
+
+ if (!(fuse & CHV_FGT_DISABLE_SS0)) {
+ info->subslice_per_slice++;
+ eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
+ CHV_FGT_EU_DIS_SS0_R1_MASK);
+ info->eu_total += 8 - hweight32(eu_dis);
+ }
+
+ if (!(fuse & CHV_FGT_DISABLE_SS1)) {
+ info->subslice_per_slice++;
+ eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
+ CHV_FGT_EU_DIS_SS1_R1_MASK);
+ info->eu_total += 8 - hweight32(eu_dis);
+ }
+
+ info->subslice_total = info->subslice_per_slice;
+ /*
+ * CHV expected to always have a uniform distribution of EU
+ * across subslices.
+ */
+ info->eu_per_subslice = info->subslice_total ?
+ info->eu_total / info->subslice_total :
+ 0;
+ /*
+ * CHV supports subslice power gating on devices with more than
+ * one subslice, and supports EU power gating on devices with
+ * more than one EU pair per subslice.
+ */
+ info->has_slice_pg = 0;
+ info->has_subslice_pg = (info->subslice_total > 1);
+ info->has_eu_pg = (info->eu_per_subslice > 2);
+}
+
+static void gen9_sseu_info_init(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_device_info *info;
+ const int s_max = 3, ss_max = 4, eu_max = 8;
+ int s, ss;
+ u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
+
+ info = (struct intel_device_info *)&dev_priv->info;
+ fuse2 = I915_READ(GEN8_FUSE2);
+ s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
+ GEN8_F2_S_ENA_SHIFT;
+ ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
+ GEN9_F2_SS_DIS_SHIFT;
+
+ eu_disable[0] = I915_READ(GEN8_EU_DISABLE0);
+ eu_disable[1] = I915_READ(GEN8_EU_DISABLE1);
+ eu_disable[2] = I915_READ(GEN8_EU_DISABLE2);
+
+ info->slice_total = hweight32(s_enable);
+ /*
+ * The subslice disable field is global, i.e. it applies
+ * to each of the enabled slices.
+ */
+ info->subslice_per_slice = ss_max - hweight32(ss_disable);
+ info->subslice_total = info->slice_total *
+ info->subslice_per_slice;
+
+ /*
+ * Iterate through enabled slices and subslices to
+ * count the total enabled EU.
+ */
+ for (s = 0; s < s_max; s++) {
+ if (!(s_enable & (0x1 << s)))
+ /* skip disabled slice */
+ continue;
+
+ for (ss = 0; ss < ss_max; ss++) {
+ u32 n_disabled;
+
+ if (ss_disable & (0x1 << ss))
+ /* skip disabled subslice */
+ continue;
+
+ n_disabled = hweight8(eu_disable[s] >>
+ (ss * eu_max));
+
+ /*
+ * Record which subslice(s) has(have) 7 EUs. we
+ * can tune the hash used to spread work among
+ * subslices if they are unbalanced.
+ */
+ if (eu_max - n_disabled == 7)
+ info->subslice_7eu[s] |= 1 << ss;
+
+ info->eu_total += eu_max - n_disabled;
+ }
+ }
+
+ /*
+ * SKL is expected to always have a uniform distribution
+ * of EU across subslices with the exception that any one
+ * EU in any one subslice may be fused off for die
+ * recovery.
+ */
+ info->eu_per_subslice = info->subslice_total ?
+ DIV_ROUND_UP(info->eu_total,
+ info->subslice_total) : 0;
+ /*
+ * SKL supports slice power gating on devices with more than
+ * one slice, and supports EU power gating on devices with
+ * more than one EU pair per subslice.
+ */
+ info->has_slice_pg = (info->slice_total > 1) ? 1 : 0;
+ info->has_subslice_pg = 0;
+ info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0;
+}
+
/*
* Determine various intel_device_info fields at runtime.
*
@@ -624,116 +745,11 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
}
/* Initialize slice/subslice/EU info */
- if (IS_CHERRYVIEW(dev)) {
- u32 fuse, eu_dis;
-
- fuse = I915_READ(CHV_FUSE_GT);
+ if (IS_CHERRYVIEW(dev))
+ cherryview_sseu_info_init(dev);
+ else if (IS_SKYLAKE(dev))
+ gen9_sseu_info_init(dev);
- info->slice_total = 1;
-
- if (!(fuse & CHV_FGT_DISABLE_SS0)) {
- info->subslice_per_slice++;
- eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
- CHV_FGT_EU_DIS_SS0_R1_MASK);
- info->eu_total += 8 - hweight32(eu_dis);
- }
-
- if (!(fuse & CHV_FGT_DISABLE_SS1)) {
- info->subslice_per_slice++;
- eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
- CHV_FGT_EU_DIS_SS1_R1_MASK);
- info->eu_total += 8 - hweight32(eu_dis);
- }
-
- info->subslice_total = info->subslice_per_slice;
- /*
- * CHV expected to always have a uniform distribution of EU
- * across subslices.
- */
- info->eu_per_subslice = info->subslice_total ?
- info->eu_total / info->subslice_total :
- 0;
- /*
- * CHV supports subslice power gating on devices with more than
- * one subslice, and supports EU power gating on devices with
- * more than one EU pair per subslice.
- */
- info->has_slice_pg = 0;
- info->has_subslice_pg = (info->subslice_total > 1);
- info->has_eu_pg = (info->eu_per_subslice > 2);
- } else if (IS_SKYLAKE(dev)) {
- const int s_max = 3, ss_max = 4, eu_max = 8;
- int s, ss;
- u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
-
- fuse2 = I915_READ(GEN8_FUSE2);
- s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
- GEN8_F2_S_ENA_SHIFT;
- ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
- GEN9_F2_SS_DIS_SHIFT;
-
- eu_disable[0] = I915_READ(GEN8_EU_DISABLE0);
- eu_disable[1] = I915_READ(GEN8_EU_DISABLE1);
- eu_disable[2] = I915_READ(GEN8_EU_DISABLE2);
-
- info->slice_total = hweight32(s_enable);
- /*
- * The subslice disable field is global, i.e. it applies
- * to each of the enabled slices.
- */
- info->subslice_per_slice = ss_max - hweight32(ss_disable);
- info->subslice_total = info->slice_total *
- info->subslice_per_slice;
-
- /*
- * Iterate through enabled slices and subslices to
- * count the total enabled EU.
- */
- for (s = 0; s < s_max; s++) {
- if (!(s_enable & (0x1 << s)))
- /* skip disabled slice */
- continue;
-
- for (ss = 0; ss < ss_max; ss++) {
- u32 n_disabled;
-
- if (ss_disable & (0x1 << ss))
- /* skip disabled subslice */
- continue;
-
- n_disabled = hweight8(eu_disable[s] >>
- (ss * eu_max));
-
- /*
- * Record which subslice(s) has(have) 7 EUs. we
- * can tune the hash used to spread work among
- * subslices if they are unbalanced.
- */
- if (eu_max - n_disabled == 7)
- info->subslice_7eu[s] |= 1 << ss;
-
- info->eu_total += eu_max - n_disabled;
- }
- }
-
- /*
- * SKL is expected to always have a uniform distribution
- * of EU across subslices with the exception that any one
- * EU in any one subslice may be fused off for die
- * recovery.
- */
- info->eu_per_subslice = info->subslice_total ?
- DIV_ROUND_UP(info->eu_total,
- info->subslice_total) : 0;
- /*
- * SKL supports slice power gating on devices with more than
- * one slice, and supports EU power gating on devices with
- * more than one EU pair per subslice.
- */
- info->has_slice_pg = (info->slice_total > 1) ? 1 : 0;
- info->has_subslice_pg = 0;
- info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0;
- }
DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
--
2.3.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/4] drm/i915/bxt: Determine BXT slice/subslice/EU info
2015-04-04 1:13 [PATCH 0/4 v2] BXT basic slice/subslice/EU stuff jeff.mcgee
2015-04-04 1:13 ` [PATCH 1/4] drm/i915: Split SSEU init into functions by platform jeff.mcgee
@ 2015-04-04 1:13 ` jeff.mcgee
2015-04-09 13:26 ` Imre Deak
2015-04-04 1:13 ` [PATCH 3/4] drm/i915: Split-up SSEU device status by platform jeff.mcgee
2015-04-04 1:13 ` [PATCH 4/4] drm/i915/bxt: Support BXT in SSEU device status dump jeff.mcgee
3 siblings, 1 reply; 8+ messages in thread
From: jeff.mcgee @ 2015-04-04 1:13 UTC (permalink / raw)
To: intel-gfx
From: Jeff McGee <jeff.mcgee@intel.com>
Modify the Gen9 SSEU info initialization logic to support
Broxton. Broxton reuses the SKL fuse registers but has at most
1 slice and 6 EU per subslice.
Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
---
drivers/gpu/drm/i915/i915_dma.c | 47 ++++++++++++++++++++++++++---------------
drivers/gpu/drm/i915/i915_reg.h | 4 +---
2 files changed, 31 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 9691f0f..a9b7770 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -611,9 +611,21 @@ static void gen9_sseu_info_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_device_info *info;
- const int s_max = 3, ss_max = 4, eu_max = 8;
+ int s_max = 3, ss_max = 4, eu_max = 8;
int s, ss;
- u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
+ u32 fuse2, s_enable, ss_disable, eu_disable;
+ u8 eu_mask = 0xff;
+
+ /*
+ * BXT has a single slice. BXT also has at most 6 EU per subslice,
+ * and therefore only the lowest 6 bits of the 8-bit EU disable
+ * fields are valid.
+ */
+ if (IS_BROXTON(dev)) {
+ s_max = 1;
+ eu_max = 6;
+ eu_mask = 0x3f;
+ }
info = (struct intel_device_info *)&dev_priv->info;
fuse2 = I915_READ(GEN8_FUSE2);
@@ -622,10 +634,6 @@ static void gen9_sseu_info_init(struct drm_device *dev)
ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
GEN9_F2_SS_DIS_SHIFT;
- eu_disable[0] = I915_READ(GEN8_EU_DISABLE0);
- eu_disable[1] = I915_READ(GEN8_EU_DISABLE1);
- eu_disable[2] = I915_READ(GEN8_EU_DISABLE2);
-
info->slice_total = hweight32(s_enable);
/*
* The subslice disable field is global, i.e. it applies
@@ -644,25 +652,26 @@ static void gen9_sseu_info_init(struct drm_device *dev)
/* skip disabled slice */
continue;
+ eu_disable = I915_READ(GEN9_EU_DISABLE(s));
for (ss = 0; ss < ss_max; ss++) {
- u32 n_disabled;
+ int eu_per_ss;
if (ss_disable & (0x1 << ss))
/* skip disabled subslice */
continue;
- n_disabled = hweight8(eu_disable[s] >>
- (ss * eu_max));
+ eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
+ eu_mask);
/*
* Record which subslice(s) has(have) 7 EUs. we
* can tune the hash used to spread work among
* subslices if they are unbalanced.
*/
- if (eu_max - n_disabled == 7)
+ if (eu_per_ss == 7)
info->subslice_7eu[s] |= 1 << ss;
- info->eu_total += eu_max - n_disabled;
+ info->eu_total += eu_per_ss;
}
}
@@ -670,7 +679,8 @@ static void gen9_sseu_info_init(struct drm_device *dev)
* SKL is expected to always have a uniform distribution
* of EU across subslices with the exception that any one
* EU in any one subslice may be fused off for die
- * recovery.
+ * recovery. BXT is expected to be perfectly uniform in EU
+ * distribution.
*/
info->eu_per_subslice = info->subslice_total ?
DIV_ROUND_UP(info->eu_total,
@@ -678,11 +688,14 @@ static void gen9_sseu_info_init(struct drm_device *dev)
/*
* SKL supports slice power gating on devices with more than
* one slice, and supports EU power gating on devices with
- * more than one EU pair per subslice.
+ * more than one EU pair per subslice. BXT supports subslice
+ * power gating on devices with more than one subslice, and
+ * supports EU power gating on devices with more than one EU
+ * pair per subslice.
*/
- info->has_slice_pg = (info->slice_total > 1) ? 1 : 0;
- info->has_subslice_pg = 0;
- info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0;
+ info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1));
+ info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
+ info->has_eu_pg = (info->eu_per_subslice > 2);
}
/*
@@ -747,7 +760,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
/* Initialize slice/subslice/EU info */
if (IS_CHERRYVIEW(dev))
cherryview_sseu_info_init(dev);
- else if (IS_SKYLAKE(dev))
+ else if (INTEL_INFO(dev)->gen >= 9)
gen9_sseu_info_init(dev);
DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b134fa3..69d3689 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1554,9 +1554,7 @@ enum skl_disp_power_wells {
#define GEN9_F2_SS_DIS_SHIFT 20
#define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
-#define GEN8_EU_DISABLE0 0x9134
-#define GEN8_EU_DISABLE1 0x9138
-#define GEN8_EU_DISABLE2 0x913c
+#define GEN9_EU_DISABLE(slice) (0x9134 + (slice)*0x4)
#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
--
2.3.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 2/4] drm/i915/bxt: Determine BXT slice/subslice/EU info
2015-04-04 1:13 ` [PATCH 2/4] drm/i915/bxt: Determine BXT slice/subslice/EU info jeff.mcgee
@ 2015-04-09 13:26 ` Imre Deak
2015-04-09 13:59 ` Daniel Vetter
0 siblings, 1 reply; 8+ messages in thread
From: Imre Deak @ 2015-04-09 13:26 UTC (permalink / raw)
To: jeff.mcgee; +Cc: intel-gfx
On Fri, 2015-04-03 at 18:13 -0700, jeff.mcgee@intel.com wrote:
> From: Jeff McGee <jeff.mcgee@intel.com>
>
> Modify the Gen9 SSEU info initialization logic to support
> Broxton. Broxton reuses the SKL fuse registers but has at most
> 1 slice and 6 EU per subslice.
>
> Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
> ---
> drivers/gpu/drm/i915/i915_dma.c | 47 ++++++++++++++++++++++++++---------------
> drivers/gpu/drm/i915/i915_reg.h | 4 +---
> 2 files changed, 31 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 9691f0f..a9b7770 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -611,9 +611,21 @@ static void gen9_sseu_info_init(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_device_info *info;
> - const int s_max = 3, ss_max = 4, eu_max = 8;
> + int s_max = 3, ss_max = 4, eu_max = 8;
> int s, ss;
> - u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
> + u32 fuse2, s_enable, ss_disable, eu_disable;
> + u8 eu_mask = 0xff;
> +
> + /*
> + * BXT has a single slice. BXT also has at most 6 EU per subslice,
> + * and therefore only the lowest 6 bits of the 8-bit EU disable
> + * fields are valid.
> + */
> + if (IS_BROXTON(dev)) {
> + s_max = 1;
> + eu_max = 6;
> + eu_mask = 0x3f;
> + }
>
> info = (struct intel_device_info *)&dev_priv->info;
> fuse2 = I915_READ(GEN8_FUSE2);
> @@ -622,10 +634,6 @@ static void gen9_sseu_info_init(struct drm_device *dev)
> ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
> GEN9_F2_SS_DIS_SHIFT;
>
> - eu_disable[0] = I915_READ(GEN8_EU_DISABLE0);
> - eu_disable[1] = I915_READ(GEN8_EU_DISABLE1);
> - eu_disable[2] = I915_READ(GEN8_EU_DISABLE2);
> -
> info->slice_total = hweight32(s_enable);
> /*
> * The subslice disable field is global, i.e. it applies
> @@ -644,25 +652,26 @@ static void gen9_sseu_info_init(struct drm_device *dev)
> /* skip disabled slice */
> continue;
>
> + eu_disable = I915_READ(GEN9_EU_DISABLE(s));
> for (ss = 0; ss < ss_max; ss++) {
> - u32 n_disabled;
> + int eu_per_ss;
>
> if (ss_disable & (0x1 << ss))
> /* skip disabled subslice */
> continue;
>
> - n_disabled = hweight8(eu_disable[s] >>
> - (ss * eu_max));
> + eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
> + eu_mask);
>
> /*
> * Record which subslice(s) has(have) 7 EUs. we
> * can tune the hash used to spread work among
> * subslices if they are unbalanced.
> */
> - if (eu_max - n_disabled == 7)
> + if (eu_per_ss == 7)
> info->subslice_7eu[s] |= 1 << ss;
>
> - info->eu_total += eu_max - n_disabled;
> + info->eu_total += eu_per_ss;
> }
> }
>
> @@ -670,7 +679,8 @@ static void gen9_sseu_info_init(struct drm_device *dev)
> * SKL is expected to always have a uniform distribution
> * of EU across subslices with the exception that any one
> * EU in any one subslice may be fused off for die
> - * recovery.
> + * recovery. BXT is expected to be perfectly uniform in EU
> + * distribution.
Nitpick: I would have added here an assertion for BXT about the above.
The patchset looks otherwise ok to me, so on 1-4:
Reviewed-by: Imre Deak <imre.deak@intel.com>
> */
> info->eu_per_subslice = info->subslice_total ?
> DIV_ROUND_UP(info->eu_total,
> @@ -678,11 +688,14 @@ static void gen9_sseu_info_init(struct drm_device *dev)
> /*
> * SKL supports slice power gating on devices with more than
> * one slice, and supports EU power gating on devices with
> - * more than one EU pair per subslice.
> + * more than one EU pair per subslice. BXT supports subslice
> + * power gating on devices with more than one subslice, and
> + * supports EU power gating on devices with more than one EU
> + * pair per subslice.
> */
> - info->has_slice_pg = (info->slice_total > 1) ? 1 : 0;
> - info->has_subslice_pg = 0;
> - info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0;
> + info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1));
> + info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
> + info->has_eu_pg = (info->eu_per_subslice > 2);
> }
>
> /*
> @@ -747,7 +760,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> /* Initialize slice/subslice/EU info */
> if (IS_CHERRYVIEW(dev))
> cherryview_sseu_info_init(dev);
> - else if (IS_SKYLAKE(dev))
> + else if (INTEL_INFO(dev)->gen >= 9)
> gen9_sseu_info_init(dev);
>
> DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b134fa3..69d3689 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1554,9 +1554,7 @@ enum skl_disp_power_wells {
> #define GEN9_F2_SS_DIS_SHIFT 20
> #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
>
> -#define GEN8_EU_DISABLE0 0x9134
> -#define GEN8_EU_DISABLE1 0x9138
> -#define GEN8_EU_DISABLE2 0x913c
> +#define GEN9_EU_DISABLE(slice) (0x9134 + (slice)*0x4)
>
> #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
> #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 2/4] drm/i915/bxt: Determine BXT slice/subslice/EU info
2015-04-09 13:26 ` Imre Deak
@ 2015-04-09 13:59 ` Daniel Vetter
0 siblings, 0 replies; 8+ messages in thread
From: Daniel Vetter @ 2015-04-09 13:59 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Apr 09, 2015 at 04:26:19PM +0300, Imre Deak wrote:
> On Fri, 2015-04-03 at 18:13 -0700, jeff.mcgee@intel.com wrote:
> > From: Jeff McGee <jeff.mcgee@intel.com>
> >
> > Modify the Gen9 SSEU info initialization logic to support
> > Broxton. Broxton reuses the SKL fuse registers but has at most
> > 1 slice and 6 EU per subslice.
> >
> > Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_dma.c | 47 ++++++++++++++++++++++++++---------------
> > drivers/gpu/drm/i915/i915_reg.h | 4 +---
> > 2 files changed, 31 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> > index 9691f0f..a9b7770 100644
> > --- a/drivers/gpu/drm/i915/i915_dma.c
> > +++ b/drivers/gpu/drm/i915/i915_dma.c
> > @@ -611,9 +611,21 @@ static void gen9_sseu_info_init(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > struct intel_device_info *info;
> > - const int s_max = 3, ss_max = 4, eu_max = 8;
> > + int s_max = 3, ss_max = 4, eu_max = 8;
> > int s, ss;
> > - u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
> > + u32 fuse2, s_enable, ss_disable, eu_disable;
> > + u8 eu_mask = 0xff;
> > +
> > + /*
> > + * BXT has a single slice. BXT also has at most 6 EU per subslice,
> > + * and therefore only the lowest 6 bits of the 8-bit EU disable
> > + * fields are valid.
> > + */
> > + if (IS_BROXTON(dev)) {
> > + s_max = 1;
> > + eu_max = 6;
> > + eu_mask = 0x3f;
> > + }
> >
> > info = (struct intel_device_info *)&dev_priv->info;
> > fuse2 = I915_READ(GEN8_FUSE2);
> > @@ -622,10 +634,6 @@ static void gen9_sseu_info_init(struct drm_device *dev)
> > ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
> > GEN9_F2_SS_DIS_SHIFT;
> >
> > - eu_disable[0] = I915_READ(GEN8_EU_DISABLE0);
> > - eu_disable[1] = I915_READ(GEN8_EU_DISABLE1);
> > - eu_disable[2] = I915_READ(GEN8_EU_DISABLE2);
> > -
> > info->slice_total = hweight32(s_enable);
> > /*
> > * The subslice disable field is global, i.e. it applies
> > @@ -644,25 +652,26 @@ static void gen9_sseu_info_init(struct drm_device *dev)
> > /* skip disabled slice */
> > continue;
> >
> > + eu_disable = I915_READ(GEN9_EU_DISABLE(s));
> > for (ss = 0; ss < ss_max; ss++) {
> > - u32 n_disabled;
> > + int eu_per_ss;
> >
> > if (ss_disable & (0x1 << ss))
> > /* skip disabled subslice */
> > continue;
> >
> > - n_disabled = hweight8(eu_disable[s] >>
> > - (ss * eu_max));
> > + eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
> > + eu_mask);
> >
> > /*
> > * Record which subslice(s) has(have) 7 EUs. we
> > * can tune the hash used to spread work among
> > * subslices if they are unbalanced.
> > */
> > - if (eu_max - n_disabled == 7)
> > + if (eu_per_ss == 7)
> > info->subslice_7eu[s] |= 1 << ss;
> >
> > - info->eu_total += eu_max - n_disabled;
> > + info->eu_total += eu_per_ss;
> > }
> > }
> >
> > @@ -670,7 +679,8 @@ static void gen9_sseu_info_init(struct drm_device *dev)
> > * SKL is expected to always have a uniform distribution
> > * of EU across subslices with the exception that any one
> > * EU in any one subslice may be fused off for die
> > - * recovery.
> > + * recovery. BXT is expected to be perfectly uniform in EU
> > + * distribution.
>
> Nitpick: I would have added here an assertion for BXT about the above.
> The patchset looks otherwise ok to me, so on 1-4:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
Applied to topic/bxt-stage1, thanks.
-Daniel
>
> > */
> > info->eu_per_subslice = info->subslice_total ?
> > DIV_ROUND_UP(info->eu_total,
> > @@ -678,11 +688,14 @@ static void gen9_sseu_info_init(struct drm_device *dev)
> > /*
> > * SKL supports slice power gating on devices with more than
> > * one slice, and supports EU power gating on devices with
> > - * more than one EU pair per subslice.
> > + * more than one EU pair per subslice. BXT supports subslice
> > + * power gating on devices with more than one subslice, and
> > + * supports EU power gating on devices with more than one EU
> > + * pair per subslice.
> > */
> > - info->has_slice_pg = (info->slice_total > 1) ? 1 : 0;
> > - info->has_subslice_pg = 0;
> > - info->has_eu_pg = (info->eu_per_subslice > 2) ? 1 : 0;
> > + info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1));
> > + info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
> > + info->has_eu_pg = (info->eu_per_subslice > 2);
> > }
> >
> > /*
> > @@ -747,7 +760,7 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
> > /* Initialize slice/subslice/EU info */
> > if (IS_CHERRYVIEW(dev))
> > cherryview_sseu_info_init(dev);
> > - else if (IS_SKYLAKE(dev))
> > + else if (INTEL_INFO(dev)->gen >= 9)
> > gen9_sseu_info_init(dev);
> >
> > DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index b134fa3..69d3689 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1554,9 +1554,7 @@ enum skl_disp_power_wells {
> > #define GEN9_F2_SS_DIS_SHIFT 20
> > #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT)
> >
> > -#define GEN8_EU_DISABLE0 0x9134
> > -#define GEN8_EU_DISABLE1 0x9138
> > -#define GEN8_EU_DISABLE2 0x913c
> > +#define GEN9_EU_DISABLE(slice) (0x9134 + (slice)*0x4)
> >
> > #define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
> > #define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
>
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/4] drm/i915: Split-up SSEU device status by platform
2015-04-04 1:13 [PATCH 0/4 v2] BXT basic slice/subslice/EU stuff jeff.mcgee
2015-04-04 1:13 ` [PATCH 1/4] drm/i915: Split SSEU init into functions by platform jeff.mcgee
2015-04-04 1:13 ` [PATCH 2/4] drm/i915/bxt: Determine BXT slice/subslice/EU info jeff.mcgee
@ 2015-04-04 1:13 ` jeff.mcgee
2015-04-04 1:13 ` [PATCH 4/4] drm/i915/bxt: Support BXT in SSEU device status dump jeff.mcgee
3 siblings, 0 replies; 8+ messages in thread
From: jeff.mcgee @ 2015-04-04 1:13 UTC (permalink / raw)
To: intel-gfx
From: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 172 +++++++++++++++++++++---------------
1 file changed, 100 insertions(+), 72 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 91c945b..c5746ef 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4483,12 +4483,97 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
i915_cache_sharing_get, i915_cache_sharing_set,
"%llu\n");
+struct sseu_dev_status {
+ unsigned int slice_total;
+ unsigned int subslice_total;
+ unsigned int subslice_per_slice;
+ unsigned int eu_total;
+ unsigned int eu_per_subslice;
+};
+
+static void cherryview_sseu_device_status(struct drm_device *dev,
+ struct sseu_dev_status *stat)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ const int ss_max = 2;
+ int ss;
+ u32 sig1[ss_max], sig2[ss_max];
+
+ sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
+ sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
+ sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
+ sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
+
+ for (ss = 0; ss < ss_max; ss++) {
+ unsigned int eu_cnt;
+
+ if (sig1[ss] & CHV_SS_PG_ENABLE)
+ /* skip disabled subslice */
+ continue;
+
+ stat->slice_total = 1;
+ stat->subslice_per_slice++;
+ eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
+ ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
+ ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
+ ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
+ stat->eu_total += eu_cnt;
+ stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
+ }
+ stat->subslice_total = stat->subslice_per_slice;
+}
+
+static void gen9_sseu_device_status(struct drm_device *dev,
+ struct sseu_dev_status *stat)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ const int s_max = 3, ss_max = 4;
+ int s, ss;
+ u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
+
+ s_reg[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK);
+ s_reg[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK);
+ s_reg[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK);
+ eu_reg[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK);
+ eu_reg[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK);
+ eu_reg[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK);
+ eu_reg[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK);
+ eu_reg[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK);
+ eu_reg[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK);
+ eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
+ GEN9_PGCTL_SSA_EU19_ACK |
+ GEN9_PGCTL_SSA_EU210_ACK |
+ GEN9_PGCTL_SSA_EU311_ACK;
+ eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
+ GEN9_PGCTL_SSB_EU19_ACK |
+ GEN9_PGCTL_SSB_EU210_ACK |
+ GEN9_PGCTL_SSB_EU311_ACK;
+
+ for (s = 0; s < s_max; s++) {
+ if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
+ /* skip disabled slice */
+ continue;
+
+ stat->slice_total++;
+ stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
+ stat->subslice_total += stat->subslice_per_slice;
+ for (ss = 0; ss < ss_max; ss++) {
+ unsigned int eu_cnt;
+
+ eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
+ eu_mask[ss%2]);
+ stat->eu_total += eu_cnt;
+ stat->eu_per_subslice = max(stat->eu_per_subslice,
+ eu_cnt);
+ }
+ }
+}
+
static int i915_sseu_status(struct seq_file *m, void *unused)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- unsigned int s_tot = 0, ss_tot = 0, ss_per = 0, eu_tot = 0, eu_per = 0;
+ struct sseu_dev_status stat;
if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
return -ENODEV;
@@ -4512,79 +4597,22 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
yesno(INTEL_INFO(dev)->has_eu_pg));
seq_puts(m, "SSEU Device Status\n");
+ memset(&stat, 0, sizeof(stat));
if (IS_CHERRYVIEW(dev)) {
- const int ss_max = 2;
- int ss;
- u32 sig1[ss_max], sig2[ss_max];
-
- sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
- sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
- sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
- sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
-
- for (ss = 0; ss < ss_max; ss++) {
- unsigned int eu_cnt;
-
- if (sig1[ss] & CHV_SS_PG_ENABLE)
- /* skip disabled subslice */
- continue;
-
- s_tot = 1;
- ss_per++;
- eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
- ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
- ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
- ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
- eu_tot += eu_cnt;
- eu_per = max(eu_per, eu_cnt);
- }
- ss_tot = ss_per;
+ cherryview_sseu_device_status(dev, &stat);
} else if (IS_SKYLAKE(dev)) {
- const int s_max = 3, ss_max = 4;
- int s, ss;
- u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
-
- s_reg[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK);
- s_reg[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK);
- s_reg[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK);
- eu_reg[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK);
- eu_reg[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK);
- eu_reg[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK);
- eu_reg[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK);
- eu_reg[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK);
- eu_reg[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK);
- eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
- GEN9_PGCTL_SSA_EU19_ACK |
- GEN9_PGCTL_SSA_EU210_ACK |
- GEN9_PGCTL_SSA_EU311_ACK;
- eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
- GEN9_PGCTL_SSB_EU19_ACK |
- GEN9_PGCTL_SSB_EU210_ACK |
- GEN9_PGCTL_SSB_EU311_ACK;
-
- for (s = 0; s < s_max; s++) {
- if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
- /* skip disabled slice */
- continue;
-
- s_tot++;
- ss_per = INTEL_INFO(dev)->subslice_per_slice;
- ss_tot += ss_per;
- for (ss = 0; ss < ss_max; ss++) {
- unsigned int eu_cnt;
-
- eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
- eu_mask[ss%2]);
- eu_tot += eu_cnt;
- eu_per = max(eu_per, eu_cnt);
- }
- }
+ gen9_sseu_device_status(dev, &stat);
}
- seq_printf(m, " Enabled Slice Total: %u\n", s_tot);
- seq_printf(m, " Enabled Subslice Total: %u\n", ss_tot);
- seq_printf(m, " Enabled Subslice Per Slice: %u\n", ss_per);
- seq_printf(m, " Enabled EU Total: %u\n", eu_tot);
- seq_printf(m, " Enabled EU Per Subslice: %u\n", eu_per);
+ seq_printf(m, " Enabled Slice Total: %u\n",
+ stat.slice_total);
+ seq_printf(m, " Enabled Subslice Total: %u\n",
+ stat.subslice_total);
+ seq_printf(m, " Enabled Subslice Per Slice: %u\n",
+ stat.subslice_per_slice);
+ seq_printf(m, " Enabled EU Total: %u\n",
+ stat.eu_total);
+ seq_printf(m, " Enabled EU Per Subslice: %u\n",
+ stat.eu_per_subslice);
return 0;
}
--
2.3.3
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 4/4] drm/i915/bxt: Support BXT in SSEU device status dump
2015-04-04 1:13 [PATCH 0/4 v2] BXT basic slice/subslice/EU stuff jeff.mcgee
` (2 preceding siblings ...)
2015-04-04 1:13 ` [PATCH 3/4] drm/i915: Split-up SSEU device status by platform jeff.mcgee
@ 2015-04-04 1:13 ` jeff.mcgee
2015-04-09 16:21 ` shuang.he
3 siblings, 1 reply; 8+ messages in thread
From: jeff.mcgee @ 2015-04-04 1:13 UTC (permalink / raw)
To: intel-gfx
From: Jeff McGee <jeff.mcgee@intel.com>
Modify the Gen9 SSEU device status logic to support Broxton.
Broxton reuses the Skylake power gate acknowledgment registers but
has at most 1 slice and 3 subslices. Broxton supports subslice
power gating within its single slice.
Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 45 ++++++++++++++++++++++++++-----------
drivers/gpu/drm/i915/i915_reg.h | 13 ++++-------
2 files changed, 36 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index c5746ef..266e4e4 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4527,19 +4527,22 @@ static void gen9_sseu_device_status(struct drm_device *dev,
struct sseu_dev_status *stat)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- const int s_max = 3, ss_max = 4;
+ int s_max = 3, ss_max = 4;
int s, ss;
u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
- s_reg[0] = I915_READ(GEN9_SLICE0_PGCTL_ACK);
- s_reg[1] = I915_READ(GEN9_SLICE1_PGCTL_ACK);
- s_reg[2] = I915_READ(GEN9_SLICE2_PGCTL_ACK);
- eu_reg[0] = I915_READ(GEN9_SLICE0_SS01_EU_PGCTL_ACK);
- eu_reg[1] = I915_READ(GEN9_SLICE0_SS23_EU_PGCTL_ACK);
- eu_reg[2] = I915_READ(GEN9_SLICE1_SS01_EU_PGCTL_ACK);
- eu_reg[3] = I915_READ(GEN9_SLICE1_SS23_EU_PGCTL_ACK);
- eu_reg[4] = I915_READ(GEN9_SLICE2_SS01_EU_PGCTL_ACK);
- eu_reg[5] = I915_READ(GEN9_SLICE2_SS23_EU_PGCTL_ACK);
+ /* BXT has a single slice and at most 3 subslices. */
+ if (IS_BROXTON(dev)) {
+ s_max = 1;
+ ss_max = 3;
+ }
+
+ for (s = 0; s < s_max; s++) {
+ s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
+ eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
+ eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
+ }
+
eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
GEN9_PGCTL_SSA_EU19_ACK |
GEN9_PGCTL_SSA_EU210_ACK |
@@ -4550,22 +4553,38 @@ static void gen9_sseu_device_status(struct drm_device *dev,
GEN9_PGCTL_SSB_EU311_ACK;
for (s = 0; s < s_max; s++) {
+ unsigned int ss_cnt = 0;
+
if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
/* skip disabled slice */
continue;
stat->slice_total++;
- stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
- stat->subslice_total += stat->subslice_per_slice;
+
+ if (IS_SKYLAKE(dev))
+ ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
+
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
+ if (IS_BROXTON(dev) &&
+ !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
+ /* skip disabled subslice */
+ continue;
+
+ if (IS_BROXTON(dev))
+ ss_cnt++;
+
eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
eu_mask[ss%2]);
stat->eu_total += eu_cnt;
stat->eu_per_subslice = max(stat->eu_per_subslice,
eu_cnt);
}
+
+ stat->subslice_total += ss_cnt;
+ stat->subslice_per_slice = max(stat->subslice_per_slice,
+ ss_cnt);
}
}
@@ -4600,7 +4619,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
memset(&stat, 0, sizeof(stat));
if (IS_CHERRYVIEW(dev)) {
cherryview_sseu_device_status(dev, &stat);
- } else if (IS_SKYLAKE(dev)) {
+ } else if (INTEL_INFO(dev)->gen >= 9) {
gen9_sseu_device_status(dev, &stat);
}
seq_printf(m, " Enabled Slice Total: %u\n",
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 69d3689..34b6290 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6269,17 +6269,12 @@ enum skl_disp_power_wells {
#define CHV_POWER_SS1_SIG2 0xa72c
#define CHV_EU311_PG_ENABLE (1<<1)
-#define GEN9_SLICE0_PGCTL_ACK 0x804c
-#define GEN9_SLICE1_PGCTL_ACK 0x8050
-#define GEN9_SLICE2_PGCTL_ACK 0x8054
+#define GEN9_SLICE_PGCTL_ACK(slice) (0x804c + (slice)*0x4)
#define GEN9_PGCTL_SLICE_ACK (1 << 0)
+#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice)*2))
-#define GEN9_SLICE0_SS01_EU_PGCTL_ACK 0x805c
-#define GEN9_SLICE0_SS23_EU_PGCTL_ACK 0x8060
-#define GEN9_SLICE1_SS01_EU_PGCTL_ACK 0x8064
-#define GEN9_SLICE1_SS23_EU_PGCTL_ACK 0x8068
-#define GEN9_SLICE2_SS01_EU_PGCTL_ACK 0x806c
-#define GEN9_SLICE2_SS23_EU_PGCTL_ACK 0x8070
+#define GEN9_SS01_EU_PGCTL_ACK(slice) (0x805c + (slice)*0x8)
+#define GEN9_SS23_EU_PGCTL_ACK(slice) (0x8060 + (slice)*0x8)
#define GEN9_PGCTL_SSA_EU08_ACK (1 << 0)
#define GEN9_PGCTL_SSA_EU19_ACK (1 << 2)
#define GEN9_PGCTL_SSA_EU210_ACK (1 << 4)
--
2.3.3
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^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 4/4] drm/i915/bxt: Support BXT in SSEU device status dump
2015-04-04 1:13 ` [PATCH 4/4] drm/i915/bxt: Support BXT in SSEU device status dump jeff.mcgee
@ 2015-04-09 16:21 ` shuang.he
0 siblings, 0 replies; 8+ messages in thread
From: shuang.he @ 2015-04-09 16:21 UTC (permalink / raw)
To: shuang.he, ethan.gao, intel-gfx, jeff.mcgee
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6131
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 276/276 276/276
ILK 302/302 302/302
SNB 313/313 313/313
IVB 337/337 337/337
BYT 286/286 286/286
HSW 395/395 395/395
BDW 321/321 321/321
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
Note: You need to pay more attention to line start with '*'
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^ permalink raw reply [flat|nested] 8+ messages in thread