All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH 1/2] drm/i915: Add psr_ready on pipe_config
@ 2015-04-15 16:38 Rodrigo Vivi
  2015-04-15 16:38 ` [PATCH 2/2] drm/i915: Only enabled DRRS if PRS won't be enabled on this pipe Rodrigo Vivi
  2015-04-15 20:21 ` [PATCH] drm/i915: Add psr_ready on pipe_config Rodrigo Vivi
  0 siblings, 2 replies; 10+ messages in thread
From: Rodrigo Vivi @ 2015-04-15 16:38 UTC (permalink / raw)
  To: intel-gfx; +Cc: Rodrigo Vivi

Let's know beforehand if PSR is ready and will be enabled so we can
prevent DRRS to get enabled.

v2: Removing is_edp_psr func that is not used after this patch.
    Rename match_conditions and document it since it is now external.
    Moving to a propper place as pointed out by Sivakumar.
    Use a better name as pointed out by Ram.

v3: Don't dereferrence drm_encoder->crtc and intel_crtc->config on psr_ready check.
    Fix a opps caused with previous versions.

Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel@ffwll.ch>
Reviewed-by: Ramalingam C <ramalingam.c@intel.com> (v2)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |  1 +
 drivers/gpu/drm/i915/intel_dp.c      |  2 ++
 drivers/gpu/drm/i915/intel_drv.h     |  3 ++
 drivers/gpu/drm/i915/intel_psr.c     | 57 ++++++++++++++++++++----------------
 4 files changed, 38 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 75afa6e..50f2db7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10895,6 +10895,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
 		      pipe_config->pch_pfit.pos,
 		      pipe_config->pch_pfit.size,
 		      pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
+	DRM_DEBUG_KMS("psr ready: %i\n", pipe_config->psr_ready);
 	DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
 	DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
 
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 14cdd00..94bbdf4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1394,6 +1394,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 		 */
 		min_lane_count = max_lane_count;
 		min_clock = max_clock;
+
+		pipe_config->psr_ready = intel_psr_ready(intel_dp, pipe_config);
 	}
 
 	for (; bpp >= 6*3; bpp -= 2*3) {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 082be71..9895772 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -448,6 +448,7 @@ struct intel_crtc_state {
 	int fdi_lanes;
 	struct intel_link_m_n fdi_m_n;
 
+	bool psr_ready;
 	bool ips_enabled;
 
 	bool double_wide;
@@ -1287,6 +1288,8 @@ void intel_backlight_unregister(struct drm_device *dev);
 
 
 /* intel_psr.c */
+bool intel_psr_ready(struct intel_dp *intel_dp,
+		     struct intel_crtc_state *pipe_config);
 void intel_psr_enable(struct intel_dp *intel_dp);
 void intel_psr_disable(struct intel_dp *intel_dp);
 void intel_psr_invalidate(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 5ee0fa5..61d582b 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -56,11 +56,6 @@
 #include "intel_drv.h"
 #include "i915_drv.h"
 
-static bool is_edp_psr(struct intel_dp *intel_dp)
-{
-	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
-}
-
 static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -282,19 +277,32 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
 				EDP_SU_TRACK_ENABLE | EDP_PSR2_TP2_TIME_100);
 }
 
-static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
+/**
+ * intel_psr_ready - PSR ready
+ * @intel_dp: Intel DP
+ * @pipe_config: Pipe Config
+ *
+ * This function Checks if PSR is supported by Hardware/Source and
+ * Panel/Sink and if all conditions to be enabled are fulfilled.
+ *
+ * It is used to know beforehand if PSR is going to be enabled.
+ *
+ * Returns:
+ * True when PSR is ready to be enabled, false otherwise.
+ */
+bool intel_psr_ready(struct intel_dp *intel_dp,
+		     struct intel_crtc_state *pipe_config)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_device *dev = dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct drm_crtc *crtc = dig_port->base.base.crtc;
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
-	lockdep_assert_held(&dev_priv->psr.lock);
-	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
-	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
+	if (!HAS_PSR(dev)) {
+		DRM_DEBUG_KMS("PSR not supported on this platform\n");
+		return false;
+	}
 
-	dev_priv->psr.source_ok = false;
+	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
 
 	if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
 		DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
@@ -307,14 +315,14 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
 	}
 
 	if (IS_HASWELL(dev) &&
-	    I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
+	    I915_READ(HSW_STEREO_3D_CTL(pipe_config->cpu_transcoder)) &
 		      S3D_ENABLE) {
 		DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
 		return false;
 	}
 
 	if (IS_HASWELL(dev) &&
-	    intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+	    pipe_config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
 		DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
 		return false;
 	}
@@ -325,10 +333,19 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
 		return false;
 	}
 
+	/* At this point we can tell HW/Source supports PSR */
 	dev_priv->psr.source_ok = true;
+
+	/* Now check if Panel/Sink supports it */
+	if (!dev_priv->psr.sink_support) {
+		DRM_DEBUG_KMS("PSR not supported by this panel\n");
+		return false;
+	}
+
 	return true;
 }
 
+
 static void intel_psr_activate(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
@@ -365,15 +382,8 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
 
-	if (!HAS_PSR(dev)) {
-		DRM_DEBUG_KMS("PSR not supported on this platform\n");
-		return;
-	}
-
-	if (!is_edp_psr(intel_dp)) {
-		DRM_DEBUG_KMS("PSR not supported by this panel\n");
+	if (!crtc->config->psr_ready)
 		return;
-	}
 
 	mutex_lock(&dev_priv->psr.lock);
 	if (dev_priv->psr.enabled) {
@@ -381,9 +391,6 @@ void intel_psr_enable(struct intel_dp *intel_dp)
 		goto unlock;
 	}
 
-	if (!intel_psr_match_conditions(intel_dp))
-		goto unlock;
-
 	dev_priv->psr.busy_frontbuffer_bits = 0;
 
 	if (HAS_DDI(dev)) {
-- 
2.1.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/i915: Add psr_enabled on pipe_config
@ 2015-03-26 14:50 Ramalingam C
  2015-03-26 19:20 ` [PATCH 1/2] drm/i915: Add psr_ready " Rodrigo Vivi
  0 siblings, 1 reply; 10+ messages in thread
From: Ramalingam C @ 2015-03-26 14:50 UTC (permalink / raw)
  To: Rodrigo Vivi, intel-gfx


On Wednesday 25 March 2015 12:42 AM, Rodrigo Vivi wrote:
> Let's pre-compute it on pipe_config compute to let it exported there but also
> to use to see if we can enable DRRS.
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_display.c | 35 +++++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/intel_drv.h     |  2 ++
>   drivers/gpu/drm/i915/intel_psr.c     | 19 +++++--------------
>   3 files changed, 42 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 35cdb48..91dd7bf 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5750,6 +5750,38 @@ retry:
>   	return setup_ok ? 0 : -EINVAL;
>   }
>   
> +static void intel_compute_psr_config(struct intel_crtc *crtc,
> +				     struct intel_crtc_state *pipe_config)
> +{
> +	struct drm_device *dev = crtc->base.dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_encoder *intel_encoder;
> +	struct intel_digital_port *dig_port;
> +
> +	pipe_config->psr_enabled = false;
> +
> +	if (!HAS_PSR(dev)) {
> +		DRM_DEBUG_KMS("PSR not supported on this platform\n");
> +		return;
> +	}
> +
> +	for_each_encoder_on_crtc(dev, &crtc->base, intel_encoder)
> +		if (intel_encoder->type == INTEL_OUTPUT_EDP)
> +			break;
> +
> +	if (intel_encoder->type != INTEL_OUTPUT_EDP)
> +		return;
> +
> +	if (!dev_priv->psr.sink_support) {
> +		DRM_DEBUG_KMS("PSR not supported by this panel\n");
> +		return;
> +	}
> +
> +	dig_port = enc_to_dig_port(&intel_encoder->base);
> +
> +	pipe_config->psr_enabled = intel_psr_match_conditions(dig_port);
> +}
> +
>   static void hsw_compute_ips_config(struct intel_crtc *crtc,
>   				   struct intel_crtc_state *pipe_config)
>   {
> @@ -5812,6 +5844,8 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
>   		pipe_config->pipe_bpp = 8*3;
>   	}
>   
> +	intel_compute_psr_config(crtc, pipe_config);
> +
>   	if (HAS_IPS(dev))
>   		hsw_compute_ips_config(crtc, pipe_config);
>   
> @@ -10367,6 +10401,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
>   		      pipe_config->pch_pfit.pos,
>   		      pipe_config->pch_pfit.size,
>   		      pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
> +	DRM_DEBUG_KMS("psr: %i\n", pipe_config->psr_enabled);
>   	DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
>   	DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
>   }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index c0fa1cb..d79852f 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -384,6 +384,7 @@ struct intel_crtc_state {
>   	int fdi_lanes;
>   	struct intel_link_m_n fdi_m_n;
>   
> +	bool psr_enabled;
flag is indicating the status of the PSR capability of PSR source and 
sink, not the status of PSR enabling.
Naming is misleading?
>   	bool ips_enabled;
>   
>   	bool double_wide;
> @@ -1206,6 +1207,7 @@ void intel_backlight_unregister(struct drm_device *dev);
>   
>   
>   /* intel_psr.c */
> +bool intel_psr_match_conditions(struct intel_digital_port *dig_port);
>   void intel_psr_enable(struct intel_dp *intel_dp);
>   void intel_psr_disable(struct intel_dp *intel_dp);
>   void intel_psr_invalidate(struct drm_device *dev,
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index c1ca923..34854af 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -249,15 +249,13 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp)
>   		   EDP_PSR_ENABLE);
>   }
>   
> -static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
> +bool intel_psr_match_conditions(struct intel_digital_port *dig_port)
>   {
> -	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>   	struct drm_device *dev = dig_port->base.base.dev;
>   	struct drm_i915_private *dev_priv = dev->dev_private;
>   	struct drm_crtc *crtc = dig_port->base.base.crtc;
>   	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>   
> -	lockdep_assert_held(&dev_priv->psr.lock);
>   	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
>   	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
>   
> @@ -296,6 +294,7 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
>   	return true;
>   }
>   
> +
>   static void intel_psr_activate(struct intel_dp *intel_dp)
>   {
>   	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> @@ -330,16 +329,11 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>   	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>   	struct drm_device *dev = intel_dig_port->base.base.dev;
>   	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_crtc *intel_crtc =
> +		to_intel_crtc(intel_dig_port->base.base.crtc);
>   
> -	if (!HAS_PSR(dev)) {
> -		DRM_DEBUG_KMS("PSR not supported on this platform\n");
> -		return;
> -	}
> -
> -	if (!is_edp_psr(intel_dp)) {
> -		DRM_DEBUG_KMS("PSR not supported by this panel\n");
> +	if (!intel_crtc->config->psr_enabled)
>   		return;
> -	}
>   
>   	mutex_lock(&dev_priv->psr.lock);
>   	if (dev_priv->psr.enabled) {
> @@ -347,9 +341,6 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>   		goto unlock;
>   	}
>   
> -	if (!intel_psr_match_conditions(intel_dp))
> -		goto unlock;
> -
>   	dev_priv->psr.busy_frontbuffer_bits = 0;
>   
>   	if (HAS_DDI(dev)) {

-- 
Ram

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 10+ messages in thread
end of thread, other threads:[~2015-04-17  6:56 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-04-15 16:38 [PATCH 1/2] drm/i915: Add psr_ready on pipe_config Rodrigo Vivi
2015-04-15 16:38 ` [PATCH 2/2] drm/i915: Only enabled DRRS if PRS won't be enabled on this pipe Rodrigo Vivi
2015-04-16 11:49   ` shuang.he
2015-04-15 20:21 ` [PATCH] drm/i915: Add psr_ready on pipe_config Rodrigo Vivi
2015-04-17  6:56   ` shuang.he
  -- strict thread matches above, loose matches on Subject: below --
2015-03-26 14:50 [PATCH 1/2] drm/i915: Add psr_enabled " Ramalingam C
2015-03-26 19:20 ` [PATCH 1/2] drm/i915: Add psr_ready " Rodrigo Vivi
2015-03-27  6:07   ` Sivakumar Thulasimani
2015-03-27  8:32     ` Daniel Vetter
2015-03-27  9:00       ` Sivakumar Thulasimani
2015-03-30  9:50   ` Ramalingam C

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.