[U-Boot] [PATCH 1/4] x86: Implement reset_cpu() correctly for modern CPUs

[U-Boot] [PATCH 1/4] x86: Implement reset_cpu() correctly for modern CPUs

[Simon Glass]

The existing code is pretty ancient and is unreliable on modern hardware.
Generally it will hang.

We can use port 0xcf9 to initiate reset on more modern hardware (say in the
last 10 years). Update the reset_cpu() function to do this, and add a new
'full reset' function to perform a full power cycle.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/cpu.c               | 22 +++++++++-------------
 arch/x86/include/asm/processor.h | 11 +++++++++++
 2 files changed, 20 insertions(+), 13 deletions(-)

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index c9614f1..13b3baa 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -380,21 +380,17 @@ void  flush_cache(unsigned long dummy1, unsigned long dummy2)
 	asm("wbinvd\n");
 }
 
-void __attribute__ ((regparm(0))) generate_gpf(void);
-
-/* segment 0x70 is an arbitrary segment which does not exist */
-asm(".globl generate_gpf\n"
-	".hidden generate_gpf\n"
-	".type generate_gpf, @function\n"
-	"generate_gpf:\n"
-	"ljmp   $0x70, $0x47114711\n");
-
 __weak void reset_cpu(ulong addr)
 {
-	printf("Resetting using x86 Triple Fault\n");
-	set_vector(13, generate_gpf);	/* general protection fault handler */
-	set_vector(8, generate_gpf);	/* double fault handler */
-	generate_gpf();			/* start the show */
+	/* Do a hard reset through the chipset's reset control register */
+	outb(SYS_RST | RST_CPU, PORT_RESET);
+	for (;;)
+		cpu_hlt();
+}
+
+void x86_full_reset(void)
+{
+	outb(FULL_RST, PORT_RESET);
 }
 
 int dcache_status(void)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 3e26202..a24028d 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -27,6 +27,17 @@
 
 #define PORT_RESET		0xcf9
 
+enum {
+	SYS_RST		= 1 << 1,	/* clear for soft reset, set for hard */
+	RST_CPU		= 1 << 2,	/* initiate reset */
+	FULL_RST	= 1 << 3,	/* full power cycle */
+};
+
+/**
+ * x86_full_reset() - reset everything: perform a full power cycle
+ */
+void x86_full_reset(void);
+
 static inline __attribute__((always_inline)) void cpu_hlt(void)
 {
 	asm("hlt");
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 2/4] x86: ivybridge: Use reset_cpu()

[Simon Glass]

Now that reset_cpu() functions correctly, use it instead of directly
accessing the port.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/ivybridge/cpu.c      | 5 ++---
 arch/x86/cpu/ivybridge/early_me.c | 7 +++----
 arch/x86/cpu/ivybridge/sdram.c    | 3 +--
 3 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 37f3731..a62b30e 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -92,7 +92,7 @@ static int set_flex_ratio_to_tdp_nominal(void)
 
 	/* Issue warm reset, will be "CPU only" due to soft reset data */
 	outb(0x0, PORT_RESET);
-	outb(0x6, PORT_RESET);
+	outb(SYS_RST | RST_CPU, PORT_RESET);
 	cpu_hlt();
 
 	/* Not reached */
@@ -286,8 +286,7 @@ int print_cpuinfo(void)
 
 		/* System is not happy after keyboard reset... */
 		debug("Issuing CF9 warm reset\n");
-		outb(0x6, 0xcf9);
-		cpu_hlt();
+		reset_cpu();
 	}
 
 	/* Early chipset init required before RAM init can work */
diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c
index 356bbb4..0347197 100644
--- a/arch/x86/cpu/ivybridge/early_me.c
+++ b/arch/x86/cpu/ivybridge/early_me.c
@@ -183,9 +183,8 @@ int intel_early_me_init_done(u8 status)
 	}
 
 	/* Perform the requested reset */
-	if (reset) {
-		outb(reset, 0xcf9);
-		cpu_hlt();
-	}
+	if (reset)
+		reset_cpu();
+
 	return -1;
 }
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 9a6da37..42e1e60 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -393,8 +393,7 @@ int sdram_initialise(struct pei_data *pei_data)
 	/* If MRC data is not found we cannot continue S3 resume. */
 	if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
 		debug("Giving up in sdram_initialize: No MRC data\n");
-		outb(0x6, PORT_RESET);
-		cpu_hlt();
+		reset_cpu();
 	}
 
 	/* Pass console handler in pei_data */
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 3/4] x86: quark: Use reset_cpu()

[Simon Glass]

Now that reset_cpu() functions correctly, use it instead of directly
accessing the port.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/quark/quark.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index e4b19c2..a5aa014 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -110,7 +110,7 @@ int print_cpuinfo(void)
 void reset_cpu(ulong addr)
 {
 	/* cold reset */
-	outb(0x08, PORT_RESET);
+	x86_full_reset();
 }
 
 int cpu_mmc_init(bd_t *bis)
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 4/4] x86: fsp: Use reset_cpu()

[Simon Glass]

Now that reset_cpu() functions correctly, use it instead of directly
accessing the port on boards that use a Firmware Support Package (FSP).

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/lib/fsp/fsp_common.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
index f668259..001494d 100644
--- a/arch/x86/lib/fsp/fsp_common.c
+++ b/arch/x86/lib/fsp/fsp_common.c
@@ -17,13 +17,6 @@ int print_cpuinfo(void)
 	return default_print_cpuinfo();
 }
 
-void reset_cpu(ulong addr)
-{
-	/* cold reset */
-	outb(0x06, PORT_RESET);
-}
-
-
 int board_pci_post_scan(struct pci_controller *hose)
 {
 	u32 status;
-- 
2.2.0.rc0.207.ga3a616c

[U-Boot] [PATCH 1/4] x86: Implement reset_cpu() correctly for modern CPUs

[Bin Meng]

Hi Simon,

On Sat, Apr 25, 2015 at 11:04 PM, Simon Glass <sjg@chromium.org> wrote:
> The existing code is pretty ancient and is unreliable on modern hardware.
> Generally it will hang.
>
> We can use port 0xcf9 to initiate reset on more modern hardware (say in the
> last 10 years). Update the reset_cpu() function to do this, and add a new
> 'full reset' function to perform a full power cycle.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/cpu/cpu.c               | 22 +++++++++-------------
>  arch/x86/include/asm/processor.h | 11 +++++++++++
>  2 files changed, 20 insertions(+), 13 deletions(-)
>
> diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
> index c9614f1..13b3baa 100644
> --- a/arch/x86/cpu/cpu.c
> +++ b/arch/x86/cpu/cpu.c
> @@ -380,21 +380,17 @@ void  flush_cache(unsigned long dummy1, unsigned long dummy2)
>         asm("wbinvd\n");
>  }
>
> -void __attribute__ ((regparm(0))) generate_gpf(void);
> -
> -/* segment 0x70 is an arbitrary segment which does not exist */
> -asm(".globl generate_gpf\n"
> -       ".hidden generate_gpf\n"
> -       ".type generate_gpf, @function\n"
> -       "generate_gpf:\n"
> -       "ljmp   $0x70, $0x47114711\n");
> -
>  __weak void reset_cpu(ulong addr)
>  {
> -       printf("Resetting using x86 Triple Fault\n");
> -       set_vector(13, generate_gpf);   /* general protection fault handler */
> -       set_vector(8, generate_gpf);    /* double fault handler */
> -       generate_gpf();                 /* start the show */
> +       /* Do a hard reset through the chipset's reset control register */
> +       outb(SYS_RST | RST_CPU, PORT_RESET);
> +       for (;;)
> +               cpu_hlt();
> +}
> +
> +void x86_full_reset(void)
> +{
> +       outb(FULL_RST, PORT_RESET);
>  }
>
>  int dcache_status(void)
> diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
> index 3e26202..a24028d 100644
> --- a/arch/x86/include/asm/processor.h
> +++ b/arch/x86/include/asm/processor.h
> @@ -27,6 +27,17 @@
>
>  #define PORT_RESET             0xcf9
>
> +enum {
> +       SYS_RST         = 1 << 1,       /* clear for soft reset, set for hard */

The comment looks confusing. What does 'clear for soft reset' mean?

> +       RST_CPU         = 1 << 2,       /* initiate reset */

CPU_RST? to follow the same convention as SYS_RST and FULL_RST?

> +       FULL_RST        = 1 << 3,       /* full power cycle */
> +};
> +
> +/**
> + * x86_full_reset() - reset everything: perform a full power cycle
> + */
> +void x86_full_reset(void);
> +
>  static inline __attribute__((always_inline)) void cpu_hlt(void)
>  {
>         asm("hlt");
> --

Regards,
Bin

[U-Boot] [PATCH 2/4] x86: ivybridge: Use reset_cpu()

[Bin Meng]

Hi Simon,

On Sat, Apr 25, 2015 at 11:04 PM, Simon Glass <sjg@chromium.org> wrote:
> Now that reset_cpu() functions correctly, use it instead of directly
> accessing the port.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/cpu/ivybridge/cpu.c      | 5 ++---
>  arch/x86/cpu/ivybridge/early_me.c | 7 +++----
>  arch/x86/cpu/ivybridge/sdram.c    | 3 +--
>  3 files changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
> index 37f3731..a62b30e 100644
> --- a/arch/x86/cpu/ivybridge/cpu.c
> +++ b/arch/x86/cpu/ivybridge/cpu.c
> @@ -92,7 +92,7 @@ static int set_flex_ratio_to_tdp_nominal(void)
>
>         /* Issue warm reset, will be "CPU only" due to soft reset data */
>         outb(0x0, PORT_RESET);
> -       outb(0x6, PORT_RESET);
> +       outb(SYS_RST | RST_CPU, PORT_RESET);
>         cpu_hlt();
>
>         /* Not reached */
> @@ -286,8 +286,7 @@ int print_cpuinfo(void)
>
>                 /* System is not happy after keyboard reset... */
>                 debug("Issuing CF9 warm reset\n");
> -               outb(0x6, 0xcf9);
> -               cpu_hlt();
> +               reset_cpu();
>         }
>
>         /* Early chipset init required before RAM init can work */
> diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c
> index 356bbb4..0347197 100644
> --- a/arch/x86/cpu/ivybridge/early_me.c
> +++ b/arch/x86/cpu/ivybridge/early_me.c
> @@ -183,9 +183,8 @@ int intel_early_me_init_done(u8 status)
>         }
>
>         /* Perform the requested reset */
> -       if (reset) {
> -               outb(reset, 0xcf9);
> -               cpu_hlt();
> -       }
> +       if (reset)
> +               reset_cpu();
> +

I think the following codes before this code block need to be updated
to use the reset bit enum to assign to the reset variable.

        reset = 0;
        switch (hfs.ack_data) {
        case ME_HFS_ACK_CONTINUE:
                /* Continue to boot */
                return 0;
        case ME_HFS_ACK_RESET:
                /* Non-power cycle reset */
                set_global_reset(0);
                reset = 0x06;
                break;
        case ME_HFS_ACK_PWR_CYCLE:
                /* Power cycle reset */
                set_global_reset(0);
                reset = 0x0e;
                break;
        case ME_HFS_ACK_GBL_RESET:
                /* Global reset */
                set_global_reset(1);
                reset = 0x0e;
                break;

>         return -1;
>  }
> diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
> index 9a6da37..42e1e60 100644
> --- a/arch/x86/cpu/ivybridge/sdram.c
> +++ b/arch/x86/cpu/ivybridge/sdram.c
> @@ -393,8 +393,7 @@ int sdram_initialise(struct pei_data *pei_data)
>         /* If MRC data is not found we cannot continue S3 resume. */
>         if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
>                 debug("Giving up in sdram_initialize: No MRC data\n");
> -               outb(0x6, PORT_RESET);
> -               cpu_hlt();
> +               reset_cpu();
>         }
>
>         /* Pass console handler in pei_data */
> --

Regards,
Bin

[U-Boot] [PATCH 3/4] x86: quark: Use reset_cpu()

[Bin Meng]

On Sat, Apr 25, 2015 at 11:04 PM, Simon Glass <sjg@chromium.org> wrote:
> Now that reset_cpu() functions correctly, use it instead of directly
> accessing the port.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/cpu/quark/quark.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
> index e4b19c2..a5aa014 100644
> --- a/arch/x86/cpu/quark/quark.c
> +++ b/arch/x86/cpu/quark/quark.c
> @@ -110,7 +110,7 @@ int print_cpuinfo(void)
>  void reset_cpu(ulong addr)
>  {
>         /* cold reset */
> -       outb(0x08, PORT_RESET);
> +       x86_full_reset();
>  }
>
>  int cpu_mmc_init(bd_t *bis)
> --

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 4/4] x86: fsp: Use reset_cpu()

[Bin Meng]

On Sat, Apr 25, 2015 at 11:04 PM, Simon Glass <sjg@chromium.org> wrote:
> Now that reset_cpu() functions correctly, use it instead of directly
> accessing the port on boards that use a Firmware Support Package (FSP).
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/lib/fsp/fsp_common.c | 7 -------
>  1 file changed, 7 deletions(-)
>
> diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c
> index f668259..001494d 100644
> --- a/arch/x86/lib/fsp/fsp_common.c
> +++ b/arch/x86/lib/fsp/fsp_common.c
> @@ -17,13 +17,6 @@ int print_cpuinfo(void)
>         return default_print_cpuinfo();
>  }
>
> -void reset_cpu(ulong addr)
> -{
> -       /* cold reset */
> -       outb(0x06, PORT_RESET);
> -}
> -
> -
>  int board_pci_post_scan(struct pci_controller *hose)
>  {
>         u32 status;
> --

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

[U-Boot] [PATCH 1/4] x86: Implement reset_cpu() correctly for modern CPUs

[Simon Glass]

Hi Bin,

On 26 April 2015 at 22:56, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Sat, Apr 25, 2015 at 11:04 PM, Simon Glass <sjg@chromium.org> wrote:
>> The existing code is pretty ancient and is unreliable on modern hardware.
>> Generally it will hang.
>>
>> We can use port 0xcf9 to initiate reset on more modern hardware (say in the
>> last 10 years). Update the reset_cpu() function to do this, and add a new
>> 'full reset' function to perform a full power cycle.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>>  arch/x86/cpu/cpu.c               | 22 +++++++++-------------
>>  arch/x86/include/asm/processor.h | 11 +++++++++++
>>  2 files changed, 20 insertions(+), 13 deletions(-)
>>
>> diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
>> index c9614f1..13b3baa 100644
>> --- a/arch/x86/cpu/cpu.c
>> +++ b/arch/x86/cpu/cpu.c
>> @@ -380,21 +380,17 @@ void  flush_cache(unsigned long dummy1, unsigned long dummy2)
>>         asm("wbinvd\n");
>>  }
>>
>> -void __attribute__ ((regparm(0))) generate_gpf(void);
>> -
>> -/* segment 0x70 is an arbitrary segment which does not exist */
>> -asm(".globl generate_gpf\n"
>> -       ".hidden generate_gpf\n"
>> -       ".type generate_gpf, @function\n"
>> -       "generate_gpf:\n"
>> -       "ljmp   $0x70, $0x47114711\n");
>> -
>>  __weak void reset_cpu(ulong addr)
>>  {
>> -       printf("Resetting using x86 Triple Fault\n");
>> -       set_vector(13, generate_gpf);   /* general protection fault handler */
>> -       set_vector(8, generate_gpf);    /* double fault handler */
>> -       generate_gpf();                 /* start the show */
>> +       /* Do a hard reset through the chipset's reset control register */
>> +       outb(SYS_RST | RST_CPU, PORT_RESET);
>> +       for (;;)
>> +               cpu_hlt();
>> +}
>> +
>> +void x86_full_reset(void)
>> +{
>> +       outb(FULL_RST, PORT_RESET);
>>  }
>>
>>  int dcache_status(void)
>> diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
>> index 3e26202..a24028d 100644
>> --- a/arch/x86/include/asm/processor.h
>> +++ b/arch/x86/include/asm/processor.h
>> @@ -27,6 +27,17 @@
>>
>>  #define PORT_RESET             0xcf9
>>
>> +enum {
>> +       SYS_RST         = 1 << 1,       /* clear for soft reset, set for hard */
>
> The comment looks confusing. What does 'clear for soft reset' mean?
>
>> +       RST_CPU         = 1 << 2,       /* initiate reset */
>
> CPU_RST? to follow the same convention as SYS_RST and FULL_RST?

It should do, but I want to follow Intel's register naming. I'll add a
bit more detail of where this came from.

>
>> +       FULL_RST        = 1 << 3,       /* full power cycle */
>> +};
>> +
>> +/**
>> + * x86_full_reset() - reset everything: perform a full power cycle
>> + */
>> +void x86_full_reset(void);
>> +
>>  static inline __attribute__((always_inline)) void cpu_hlt(void)
>>  {
>>         asm("hlt");
>> --
>

Regards,
Simon

[U-Boot] [PATCH 2/4] x86: ivybridge: Use reset_cpu()

[Simon Glass]

Hi Bin,

On 26 April 2015 at 22:58, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Simon,
>
> On Sat, Apr 25, 2015 at 11:04 PM, Simon Glass <sjg@chromium.org> wrote:
>> Now that reset_cpu() functions correctly, use it instead of directly
>> accessing the port.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>>  arch/x86/cpu/ivybridge/cpu.c      | 5 ++---
>>  arch/x86/cpu/ivybridge/early_me.c | 7 +++----
>>  arch/x86/cpu/ivybridge/sdram.c    | 3 +--
>>  3 files changed, 6 insertions(+), 9 deletions(-)
>>
>> diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
>> index 37f3731..a62b30e 100644
>> --- a/arch/x86/cpu/ivybridge/cpu.c
>> +++ b/arch/x86/cpu/ivybridge/cpu.c
>> @@ -92,7 +92,7 @@ static int set_flex_ratio_to_tdp_nominal(void)
>>
>>         /* Issue warm reset, will be "CPU only" due to soft reset data */
>>         outb(0x0, PORT_RESET);
>> -       outb(0x6, PORT_RESET);
>> +       outb(SYS_RST | RST_CPU, PORT_RESET);
>>         cpu_hlt();
>>
>>         /* Not reached */
>> @@ -286,8 +286,7 @@ int print_cpuinfo(void)
>>
>>                 /* System is not happy after keyboard reset... */
>>                 debug("Issuing CF9 warm reset\n");
>> -               outb(0x6, 0xcf9);
>> -               cpu_hlt();
>> +               reset_cpu();
>>         }
>>
>>         /* Early chipset init required before RAM init can work */
>> diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c
>> index 356bbb4..0347197 100644
>> --- a/arch/x86/cpu/ivybridge/early_me.c
>> +++ b/arch/x86/cpu/ivybridge/early_me.c
>> @@ -183,9 +183,8 @@ int intel_early_me_init_done(u8 status)
>>         }
>>
>>         /* Perform the requested reset */
>> -       if (reset) {
>> -               outb(reset, 0xcf9);
>> -               cpu_hlt();
>> -       }
>> +       if (reset)
>> +               reset_cpu();
>> +
>
> I think the following codes before this code block need to be updated
> to use the reset bit enum to assign to the reset variable.

Ah yes, I didn't look very hard. I'll fix this.

>
>         reset = 0;
>         switch (hfs.ack_data) {
>         case ME_HFS_ACK_CONTINUE:
>                 /* Continue to boot */
>                 return 0;
>         case ME_HFS_ACK_RESET:
>                 /* Non-power cycle reset */
>                 set_global_reset(0);
>                 reset = 0x06;
>                 break;
>         case ME_HFS_ACK_PWR_CYCLE:
>                 /* Power cycle reset */
>                 set_global_reset(0);
>                 reset = 0x0e;
>                 break;
>         case ME_HFS_ACK_GBL_RESET:
>                 /* Global reset */
>                 set_global_reset(1);
>                 reset = 0x0e;
>                 break;
>
>>         return -1;
>>  }
>> diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
>> index 9a6da37..42e1e60 100644
>> --- a/arch/x86/cpu/ivybridge/sdram.c
>> +++ b/arch/x86/cpu/ivybridge/sdram.c
>> @@ -393,8 +393,7 @@ int sdram_initialise(struct pei_data *pei_data)
>>         /* If MRC data is not found we cannot continue S3 resume. */
>>         if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
>>                 debug("Giving up in sdram_initialize: No MRC data\n");
>> -               outb(0x6, PORT_RESET);
>> -               cpu_hlt();
>> +               reset_cpu();
>>         }
>>
>>         /* Pass console handler in pei_data */
>> --

Regards,
Simon