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From: Tiejun Chen <tiejun.chen@intel.com>
To: yang.z.zhang@intel.com, kevin.tian@intel.com, jbeulich@suse.com,
	jinsong.liu@alibaba-inc.com, keir@xen.org,
	andrew.cooper3@citrix.com
Cc: xen-devel@lists.xen.org
Subject: [PATCH 1/3] xen/vt-d: need barriers to workaround CLFLUSH
Date: Mon,  4 May 2015 10:16:09 +0800	[thread overview]
Message-ID: <1430705771-6744-1-git-send-email-tiejun.chen@intel.com> (raw)

clflush is a light weight but not serializing instruction, so
hence memory fence is necessary to make sure all load/store
visible before flush cache line.

Signed-off-by: Tiejun Chen <tiejun.chen@intel.com>
---
 xen/drivers/passthrough/vtd/x86/vtd.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/xen/drivers/passthrough/vtd/x86/vtd.c b/xen/drivers/passthrough/vtd/x86/vtd.c
index 109234e..fd2ff04 100644
--- a/xen/drivers/passthrough/vtd/x86/vtd.c
+++ b/xen/drivers/passthrough/vtd/x86/vtd.c
@@ -56,7 +56,9 @@ unsigned int get_cache_line_size(void)
 
 void cacheline_flush(char * addr)
 {
+    mb();
     clflush(addr);
+    mb();
 }
 
 void flush_all_cache()
-- 
1.9.1

             reply	other threads:[~2015-05-04  2:16 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-04  2:16 Tiejun Chen [this message]
2015-05-04  2:16 ` [PATCH 2/3] xen/vt-d: mask interrupt message generation Tiejun Chen
2015-05-04  4:07   ` Zhang, Yang Z
2015-05-04  5:08     ` Chen, Tiejun
2015-05-04  6:41       ` Zhang, Yang Z
2015-05-04  8:57       ` Jan Beulich
2015-05-04 11:21         ` Chen, Tiejun
2015-05-04  2:16 ` [PATCH 3/3] xen/iommu: disable IOMMU engine completely before enter S5 Tiejun Chen
2015-05-04  9:00   ` Jan Beulich
2015-05-04  4:07 ` [PATCH 1/3] xen/vt-d: need barriers to workaround CLFLUSH Zhang, Yang Z
2015-05-04  8:52 ` Jan Beulich
2015-05-04  9:14   ` Andrew Cooper
2015-05-04  9:24     ` Jan Beulich
2015-05-05  1:13       ` Zhang, Yang Z
2015-05-05 15:46     ` Boris Ostrovsky
2015-05-05 15:58       ` Jan Beulich
2015-05-05 16:11         ` Boris Ostrovsky
2015-05-06  7:12           ` Jan Beulich
2015-05-06  7:26             ` Chen, Tiejun
2015-05-06  7:33               ` Jan Beulich
2015-05-06 15:11             ` Boris Ostrovsky
2015-05-06  7:09       ` Chen, Tiejun
2015-05-04 10:39   ` Chen, Tiejun
2015-05-04 10:43     ` Jan Beulich
2015-05-04 10:52       ` Tian, Kevin
2015-05-04 11:26         ` Chen, Tiejun
2015-05-05  1:13           ` Tian, Kevin
2015-05-05  2:45       ` Chen, Tiejun
2015-05-05  9:24         ` Jan Beulich
2015-05-06  6:47           ` Chen, Tiejun
2015-05-06  7:14             ` Jan Beulich
2015-05-04 15:22     ` Konrad Rzeszutek Wilk
2015-05-04 15:33       ` Andrew Cooper

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