[PATCH v3 0/6] ARM: l2c / shmobile: r8a7740 : Shared Override

[PATCH v3 0/6] ARM: l2c / shmobile: r8a7740 : Shared Override

[Geert Uytterhoeven]

	Hi all,

This patch series migrates the shmobile DT-based generic r8a7740 and
armadillo legacy platforms from calling l2x0_of_init() to the generic
l2c OF initialization.

It was sent before as "[PATCH v2 0/5] ARM: shmobile: r8a7740/armadillo:
Migrate to generic l2c OF". Major changes in v3 are the introduction of
the "arm,shared-override" property in DT, and only setting the Shared
Override bit if CMA is not available. Note that not setting this bit may
lead to memory corruption in the presence of other bus masters.

For shmobile, this conversion should be done on sh73a0, r8a7778, and
r8a7779, too.

Several other ARM platforms (berlin, cns3xxx, nomadik, omap, realview,
sti, tegra, vexpress) currently set the Shared Override bit in various
ways. As soon as the first patch in this series is accepted, they can
start specifying the "arm,shared-override" property in their DTSes, and
remove the corresponding board code.

Changes in v3:
  - Add DT support for Shared Override,
  - Setting Shared Override is done only if CMA is not available (as
    Russell claims it's not needed if CMA is available),
  - Use 0/~0 in machine_desc.l2c_aux_{val,mask}, as DT now supports
    "arm,shared-override".

Changes in v2:
  - Fix interrupt reference in DT,
  - Describe L2 better in DT,
  - Keep only {,~}L2C_AUX_CTRL_SHARED_OVERRIDE in
    machine_desc.l2c_aux_{val,mask}, as there's no DT property for
    this.
  - Add L1 cache to DT.

Dependencies:
  - Although there are separate patches for ARM code, dtsi, SoC code, and
    board code, there are dependencies among the individual patches:
      - patches 3 and 4 depend on patches 1 and 2,
      - patch 5 depends on patches 3 and 4,
      - patch 6 depends on patch 2.

This was tested on armadillo-legacy and armadillo-multiplatform.

Thanks!

Geert Uytterhoeven (6):
  ARM: l2c: Add DT support for Shared Override
  ARM: shmobile: r8a7740 dtsi: Add L2 cache-controller node
  ARM: shmobile: r8a7740: Migrate to generic l2c OF initialization
  ARM: shmobile: armadillo legacy: Migrate to generic l2c OF
    initialization
  ARM: shmobile: r8a7740: Remove mapping of L2 cache controller
    registers
  ARM: shmobile: r8a7740 dtsi: Add L1 cache information to CPU node

 Documentation/devicetree/bindings/arm/l2cc.txt |  6 ++++++
 arch/arm/boot/dts/r8a7740.dtsi                 | 25 +++++++++++++++++++++++++
 arch/arm/mach-shmobile/board-armadillo800eva.c |  8 ++------
 arch/arm/mach-shmobile/setup-r8a7740.c         | 18 ++----------------
 arch/arm/mm/cache-l2x0.c                       | 10 ++++++++++
 5 files changed, 45 insertions(+), 22 deletions(-)

-- 
1.9.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH v3 0/6] ARM: l2c / shmobile: r8a7740 : Shared Override

[Geert Uytterhoeven]

	Hi all,

This patch series migrates the shmobile DT-based generic r8a7740 and
armadillo legacy platforms from calling l2x0_of_init() to the generic
l2c OF initialization.

It was sent before as "[PATCH v2 0/5] ARM: shmobile: r8a7740/armadillo:
Migrate to generic l2c OF". Major changes in v3 are the introduction of
the "arm,shared-override" property in DT, and only setting the Shared
Override bit if CMA is not available. Note that not setting this bit may
lead to memory corruption in the presence of other bus masters.

For shmobile, this conversion should be done on sh73a0, r8a7778, and
r8a7779, too.

Several other ARM platforms (berlin, cns3xxx, nomadik, omap, realview,
sti, tegra, vexpress) currently set the Shared Override bit in various
ways. As soon as the first patch in this series is accepted, they can
start specifying the "arm,shared-override" property in their DTSes, and
remove the corresponding board code.

Changes in v3:
  - Add DT support for Shared Override,
  - Setting Shared Override is done only if CMA is not available (as
    Russell claims it's not needed if CMA is available),
  - Use 0/~0 in machine_desc.l2c_aux_{val,mask}, as DT now supports
    "arm,shared-override".

Changes in v2:
  - Fix interrupt reference in DT,
  - Describe L2 better in DT,
  - Keep only {,~}L2C_AUX_CTRL_SHARED_OVERRIDE in
    machine_desc.l2c_aux_{val,mask}, as there's no DT property for
    this.
  - Add L1 cache to DT.

Dependencies:
  - Although there are separate patches for ARM code, dtsi, SoC code, and
    board code, there are dependencies among the individual patches:
      - patches 3 and 4 depend on patches 1 and 2,
      - patch 5 depends on patches 3 and 4,
      - patch 6 depends on patch 2.

This was tested on armadillo-legacy and armadillo-multiplatform.

Thanks!

Geert Uytterhoeven (6):
  ARM: l2c: Add DT support for Shared Override
  ARM: shmobile: r8a7740 dtsi: Add L2 cache-controller node
  ARM: shmobile: r8a7740: Migrate to generic l2c OF initialization
  ARM: shmobile: armadillo legacy: Migrate to generic l2c OF
    initialization
  ARM: shmobile: r8a7740: Remove mapping of L2 cache controller
    registers
  ARM: shmobile: r8a7740 dtsi: Add L1 cache information to CPU node

 Documentation/devicetree/bindings/arm/l2cc.txt |  6 ++++++
 arch/arm/boot/dts/r8a7740.dtsi                 | 25 +++++++++++++++++++++++++
 arch/arm/mach-shmobile/board-armadillo800eva.c |  8 ++------
 arch/arm/mach-shmobile/setup-r8a7740.c         | 18 ++----------------
 arch/arm/mm/cache-l2x0.c                       | 10 ++++++++++
 5 files changed, 45 insertions(+), 22 deletions(-)

-- 
1.9.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH v3 0/6] ARM: l2c / shmobile: r8a7740 : Shared Override

[Geert Uytterhoeven]

	Hi all,

This patch series migrates the shmobile DT-based generic r8a7740 and
armadillo legacy platforms from calling l2x0_of_init() to the generic
l2c OF initialization.

It was sent before as "[PATCH v2 0/5] ARM: shmobile: r8a7740/armadillo:
Migrate to generic l2c OF". Major changes in v3 are the introduction of
the "arm,shared-override" property in DT, and only setting the Shared
Override bit if CMA is not available. Note that not setting this bit may
lead to memory corruption in the presence of other bus masters.

For shmobile, this conversion should be done on sh73a0, r8a7778, and
r8a7779, too.

Several other ARM platforms (berlin, cns3xxx, nomadik, omap, realview,
sti, tegra, vexpress) currently set the Shared Override bit in various
ways. As soon as the first patch in this series is accepted, they can
start specifying the "arm,shared-override" property in their DTSes, and
remove the corresponding board code.

Changes in v3:
  - Add DT support for Shared Override,
  - Setting Shared Override is done only if CMA is not available (as
    Russell claims it's not needed if CMA is available),
  - Use 0/~0 in machine_desc.l2c_aux_{val,mask}, as DT now supports
    "arm,shared-override".

Changes in v2:
  - Fix interrupt reference in DT,
  - Describe L2 better in DT,
  - Keep only {,~}L2C_AUX_CTRL_SHARED_OVERRIDE in
    machine_desc.l2c_aux_{val,mask}, as there's no DT property for
    this.
  - Add L1 cache to DT.

Dependencies:
  - Although there are separate patches for ARM code, dtsi, SoC code, and
    board code, there are dependencies among the individual patches:
      - patches 3 and 4 depend on patches 1 and 2,
      - patch 5 depends on patches 3 and 4,
      - patch 6 depends on patch 2.

This was tested on armadillo-legacy and armadillo-multiplatform.

Thanks!

Geert Uytterhoeven (6):
  ARM: l2c: Add DT support for Shared Override
  ARM: shmobile: r8a7740 dtsi: Add L2 cache-controller node
  ARM: shmobile: r8a7740: Migrate to generic l2c OF initialization
  ARM: shmobile: armadillo legacy: Migrate to generic l2c OF
    initialization
  ARM: shmobile: r8a7740: Remove mapping of L2 cache controller
    registers
  ARM: shmobile: r8a7740 dtsi: Add L1 cache information to CPU node

 Documentation/devicetree/bindings/arm/l2cc.txt |  6 ++++++
 arch/arm/boot/dts/r8a7740.dtsi                 | 25 +++++++++++++++++++++++++
 arch/arm/mach-shmobile/board-armadillo800eva.c |  8 ++------
 arch/arm/mach-shmobile/setup-r8a7740.c         | 18 ++----------------
 arch/arm/mm/cache-l2x0.c                       | 10 ++++++++++
 5 files changed, 45 insertions(+), 22 deletions(-)

-- 
1.9.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Geert Uytterhoeven]

"CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2
Shareable attribute" states:

    "The default behavior of the cache controller with respect to the
     shareable attribute is to transform Normal Memory Non-cacheable
     transactions into:
        - cacheable no allocate for reads
        - write through no write allocate for writes."

Depending on the system architecture, this may cause memory corruption
in the presence of bus mastering devices (e.g. OHCI). To avoid such
corruption, the default behavior can be disabled by setting the Shared
Override bit in the Auxiliary Control register.

Currently the Shared Override bit can be set only using C code:
  - by calling l2x0_init() directly, which is deprecated,
  - by setting/clearing the bit in the machine_desc.l2c_aux_val/mask
    fields, but using values differing from 0/~0 is also deprecated.

Hence add support for an "arm,shared-override" device tree property for
the l2c device node. By specifying this property, affected systems can
indicate that non-cacheable transactions must not be transformed.

If specified, the actual behavior of the kernel depends on whether CMA
is available or not:
  - If CMA is available, nothing needs to be done, as there won't be a
    kernel linear mappings and cacheable aliases for the DMA buffers,
  - If CMA is not available, the "shared attribute override enable" bit
    will be set.

See also commit 1a8e41cd672f894b ("ARM: 6395/1: VExpress: Set bit 22 in
the PL310 (cache controller) AuxCtlr register"):

    "Clearing bit 22 in the PL310 Auxiliary Control register (shared
     attribute override enable) has the side effect of transforming
     Normal Shared Non-cacheable reads into Cacheable no-allocate reads.

     Coherent DMA buffers in Linux always have a Cacheable alias via the
     kernel linear mapping and the processor can speculatively load
     cache lines into the PL310 controller. With bit 22 cleared,
     Non-cacheable reads would unexpectedly hit such cache lines leading
     to buffer corruption."

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - New.
---
 Documentation/devicetree/bindings/arm/l2cc.txt |  6 ++++++
 arch/arm/mm/cache-l2x0.c                       | 10 ++++++++++
 2 files changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index 0dbabe9a6b0abb91..f6f81b263a9cf56d 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -67,6 +67,12 @@ Optional properties:
   disable if zero.
 - arm,prefetch-offset : Override prefetch offset value. Valid values are
   0-7, 15, 23, and 31.
+- arm,shared-override : As of r2p0, the default behavior of the pl310 cache
+  controller with respect to the shareable attribute is to transform "normal
+  memory non-cacheable transactions" into "cacheable no allocate" (for reads)
+  or "write through no write allocate" (for writes).
+  On systems where this may cause DMA buffer corruption, this property must be
+  specified to indicate that such transforms are precluded.
 
 Example:
 
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index e309c8f35af5af61..535b575ac3d7a52f 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -17,6 +17,7 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  */
 #include <linux/cpu.h>
+#include <linux/dma-contiguous.h>
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/smp.h>
@@ -1149,6 +1150,15 @@ static void __init l2c310_of_parse(const struct device_node *np,
 		}
 	}
 
+	if (of_property_read_bool(np, "arm,shared-override")) {
+		if (dev_get_cma_area(NULL)) {
+			pr_info("L2C-310 ignoring arm,shared-override when CMA is enabled\n");
+		} else {
+			*aux_val |= L2C_AUX_CTRL_SHARED_OVERRIDE;
+			*aux_mask &= ~L2C_AUX_CTRL_SHARED_OVERRIDE;
+		}
+	}
+
 	prefetch = l2x0_saved_regs.prefetch_ctrl;
 
 	ret = of_property_read_u32(np, "arm,double-linefill", &val);
-- 
1.9.1

[PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Geert Uytterhoeven]

"CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2
Shareable attribute" states:

    "The default behavior of the cache controller with respect to the
     shareable attribute is to transform Normal Memory Non-cacheable
     transactions into:
        - cacheable no allocate for reads
        - write through no write allocate for writes."

Depending on the system architecture, this may cause memory corruption
in the presence of bus mastering devices (e.g. OHCI). To avoid such
corruption, the default behavior can be disabled by setting the Shared
Override bit in the Auxiliary Control register.

Currently the Shared Override bit can be set only using C code:
  - by calling l2x0_init() directly, which is deprecated,
  - by setting/clearing the bit in the machine_desc.l2c_aux_val/mask
    fields, but using values differing from 0/~0 is also deprecated.

Hence add support for an "arm,shared-override" device tree property for
the l2c device node. By specifying this property, affected systems can
indicate that non-cacheable transactions must not be transformed.

If specified, the actual behavior of the kernel depends on whether CMA
is available or not:
  - If CMA is available, nothing needs to be done, as there won't be a
    kernel linear mappings and cacheable aliases for the DMA buffers,
  - If CMA is not available, the "shared attribute override enable" bit
    will be set.

See also commit 1a8e41cd672f894b ("ARM: 6395/1: VExpress: Set bit 22 in
the PL310 (cache controller) AuxCtlr register"):

    "Clearing bit 22 in the PL310 Auxiliary Control register (shared
     attribute override enable) has the side effect of transforming
     Normal Shared Non-cacheable reads into Cacheable no-allocate reads.

     Coherent DMA buffers in Linux always have a Cacheable alias via the
     kernel linear mapping and the processor can speculatively load
     cache lines into the PL310 controller. With bit 22 cleared,
     Non-cacheable reads would unexpectedly hit such cache lines leading
     to buffer corruption."

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - New.
---
 Documentation/devicetree/bindings/arm/l2cc.txt |  6 ++++++
 arch/arm/mm/cache-l2x0.c                       | 10 ++++++++++
 2 files changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index 0dbabe9a6b0abb91..f6f81b263a9cf56d 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -67,6 +67,12 @@ Optional properties:
   disable if zero.
 - arm,prefetch-offset : Override prefetch offset value. Valid values are
   0-7, 15, 23, and 31.
+- arm,shared-override : As of r2p0, the default behavior of the pl310 cache
+  controller with respect to the shareable attribute is to transform "normal
+  memory non-cacheable transactions" into "cacheable no allocate" (for reads)
+  or "write through no write allocate" (for writes).
+  On systems where this may cause DMA buffer corruption, this property must be
+  specified to indicate that such transforms are precluded.
 
 Example:
 
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index e309c8f35af5af61..535b575ac3d7a52f 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -17,6 +17,7 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  */
 #include <linux/cpu.h>
+#include <linux/dma-contiguous.h>
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/smp.h>
@@ -1149,6 +1150,15 @@ static void __init l2c310_of_parse(const struct device_node *np,
 		}
 	}
 
+	if (of_property_read_bool(np, "arm,shared-override")) {
+		if (dev_get_cma_area(NULL)) {
+			pr_info("L2C-310 ignoring arm,shared-override when CMA is enabled\n");
+		} else {
+			*aux_val |= L2C_AUX_CTRL_SHARED_OVERRIDE;
+			*aux_mask &= ~L2C_AUX_CTRL_SHARED_OVERRIDE;
+		}
+	}
+
 	prefetch = l2x0_saved_regs.prefetch_ctrl;
 
 	ret = of_property_read_u32(np, "arm,double-linefill", &val);
-- 
1.9.1

[PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Geert Uytterhoeven]

"CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2
Shareable attribute" states:

    "The default behavior of the cache controller with respect to the
     shareable attribute is to transform Normal Memory Non-cacheable
     transactions into:
        - cacheable no allocate for reads
        - write through no write allocate for writes."

Depending on the system architecture, this may cause memory corruption
in the presence of bus mastering devices (e.g. OHCI). To avoid such
corruption, the default behavior can be disabled by setting the Shared
Override bit in the Auxiliary Control register.

Currently the Shared Override bit can be set only using C code:
  - by calling l2x0_init() directly, which is deprecated,
  - by setting/clearing the bit in the machine_desc.l2c_aux_val/mask
    fields, but using values differing from 0/~0 is also deprecated.

Hence add support for an "arm,shared-override" device tree property for
the l2c device node. By specifying this property, affected systems can
indicate that non-cacheable transactions must not be transformed.

If specified, the actual behavior of the kernel depends on whether CMA
is available or not:
  - If CMA is available, nothing needs to be done, as there won't be a
    kernel linear mappings and cacheable aliases for the DMA buffers,
  - If CMA is not available, the "shared attribute override enable" bit
    will be set.

See also commit 1a8e41cd672f894b ("ARM: 6395/1: VExpress: Set bit 22 in
the PL310 (cache controller) AuxCtlr register"):

    "Clearing bit 22 in the PL310 Auxiliary Control register (shared
     attribute override enable) has the side effect of transforming
     Normal Shared Non-cacheable reads into Cacheable no-allocate reads.

     Coherent DMA buffers in Linux always have a Cacheable alias via the
     kernel linear mapping and the processor can speculatively load
     cache lines into the PL310 controller. With bit 22 cleared,
     Non-cacheable reads would unexpectedly hit such cache lines leading
     to buffer corruption."

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - New.
---
 Documentation/devicetree/bindings/arm/l2cc.txt |  6 ++++++
 arch/arm/mm/cache-l2x0.c                       | 10 ++++++++++
 2 files changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/l2cc.txt b/Documentation/devicetree/bindings/arm/l2cc.txt
index 0dbabe9a6b0abb91..f6f81b263a9cf56d 100644
--- a/Documentation/devicetree/bindings/arm/l2cc.txt
+++ b/Documentation/devicetree/bindings/arm/l2cc.txt
@@ -67,6 +67,12 @@ Optional properties:
   disable if zero.
 - arm,prefetch-offset : Override prefetch offset value. Valid values are
   0-7, 15, 23, and 31.
+- arm,shared-override : As of r2p0, the default behavior of the pl310 cache
+  controller with respect to the shareable attribute is to transform "normal
+  memory non-cacheable transactions" into "cacheable no allocate" (for reads)
+  or "write through no write allocate" (for writes).
+  On systems where this may cause DMA buffer corruption, this property must be
+  specified to indicate that such transforms are precluded.
 
 Example:
 
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index e309c8f35af5af61..535b575ac3d7a52f 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -17,6 +17,7 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  */
 #include <linux/cpu.h>
+#include <linux/dma-contiguous.h>
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/smp.h>
@@ -1149,6 +1150,15 @@ static void __init l2c310_of_parse(const struct device_node *np,
 		}
 	}
 
+	if (of_property_read_bool(np, "arm,shared-override")) {
+		if (dev_get_cma_area(NULL)) {
+			pr_info("L2C-310 ignoring arm,shared-override when CMA is enabled\n");
+		} else {
+			*aux_val |= L2C_AUX_CTRL_SHARED_OVERRIDE;
+			*aux_mask &= ~L2C_AUX_CTRL_SHARED_OVERRIDE;
+		}
+	}
+
 	prefetch = l2x0_saved_regs.prefetch_ctrl;
 
 	ret = of_property_read_u32(np, "arm,double-linefill", &val);
-- 
1.9.1

[PATCH v3 2/6] ARM: shmobile: r8a7740 dtsi: Add L2 cache-controller node

[Geert Uytterhoeven]

Add the missing L2 cache-controller node. This will allow migration to
the generic l2c OF initialization.

The L2 cache is an ARM L2C-310 (r3p1-150rel0), of size 256 KiB (32 KiB x
8 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Add "arm,shared-override",

v2:
  - Fix interrupt (should be 3 cells, not 1),
  - Describe cache better.
---
 arch/arm/boot/dts/r8a7740.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index d84714468cce18df..ddef5b1c68fa06b3 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -37,6 +37,22 @@
 		      <0xc2000000 0x1000>;
 	};
 
+	L2: cache-controller {
+		compatible = "arm,pl310-cache";
+		reg = <0xf0100000 0x1000>;
+		interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&pd_a3sm>;
+		arm,data-latency = <3 3 3>;
+		arm,tag-latency = <2 2 2>;
+		arm,shared-override;
+		cache-unified;
+		cache-level = <2>;
+		cache-size = <0x40000>;
+		cache-sets = <1024>;
+		cache-block-size = <32>;
+		cache-line-size = <32>;
+	};
+
 	dbsc3: memory-controller@fe400000 {
 		compatible = "renesas,dbsc3-r8a7740";
 		reg = <0xfe400000 0x400>;
-- 
1.9.1

[PATCH v3 2/6] ARM: shmobile: r8a7740 dtsi: Add L2 cache-controller node

[Geert Uytterhoeven]

Add the missing L2 cache-controller node. This will allow migration to
the generic l2c OF initialization.

The L2 cache is an ARM L2C-310 (r3p1-150rel0), of size 256 KiB (32 KiB x
8 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Add "arm,shared-override",

v2:
  - Fix interrupt (should be 3 cells, not 1),
  - Describe cache better.
---
 arch/arm/boot/dts/r8a7740.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index d84714468cce18df..ddef5b1c68fa06b3 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -37,6 +37,22 @@
 		      <0xc2000000 0x1000>;
 	};
 
+	L2: cache-controller {
+		compatible = "arm,pl310-cache";
+		reg = <0xf0100000 0x1000>;
+		interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&pd_a3sm>;
+		arm,data-latency = <3 3 3>;
+		arm,tag-latency = <2 2 2>;
+		arm,shared-override;
+		cache-unified;
+		cache-level = <2>;
+		cache-size = <0x40000>;
+		cache-sets = <1024>;
+		cache-block-size = <32>;
+		cache-line-size = <32>;
+	};
+
 	dbsc3: memory-controller@fe400000 {
 		compatible = "renesas,dbsc3-r8a7740";
 		reg = <0xfe400000 0x400>;
-- 
1.9.1

[PATCH v3 2/6] ARM: shmobile: r8a7740 dtsi: Add L2 cache-controller node

[Geert Uytterhoeven]

Add the missing L2 cache-controller node. This will allow migration to
the generic l2c OF initialization.

The L2 cache is an ARM L2C-310 (r3p1-150rel0), of size 256 KiB (32 KiB x
8 ways).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Add "arm,shared-override",

v2:
  - Fix interrupt (should be 3 cells, not 1),
  - Describe cache better.
---
 arch/arm/boot/dts/r8a7740.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index d84714468cce18df..ddef5b1c68fa06b3 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -37,6 +37,22 @@
 		      <0xc2000000 0x1000>;
 	};
 
+	L2: cache-controller {
+		compatible = "arm,pl310-cache";
+		reg = <0xf0100000 0x1000>;
+		interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&pd_a3sm>;
+		arm,data-latency = <3 3 3>;
+		arm,tag-latency = <2 2 2>;
+		arm,shared-override;
+		cache-unified;
+		cache-level = <2>;
+		cache-size = <0x40000>;
+		cache-sets = <1024>;
+		cache-block-size = <32>;
+		cache-line-size = <32>;
+	};
+
 	dbsc3: memory-controller at fe400000 {
 		compatible = "renesas,dbsc3-r8a7740";
 		reg = <0xfe400000 0x400>;
-- 
1.9.1

[PATCH v3 3/6] ARM: shmobile: r8a7740: Migrate to generic l2c OF initialization

[Geert Uytterhoeven]

Migrate the generic r8a7740 platform from calling l2x0_of_init() to the
generic l2c OF initialization.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Use 0/~0 now DT supports "arm,shared-override",

v2:
  - Keep only {,~}L2C_AUX_CTRL_SHARED_OVERRIDE.
---
 arch/arm/mach-shmobile/setup-r8a7740.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 9832e48396a40a92..5dbb40d5c56b6495 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -835,10 +835,6 @@ static void __init r8a7740_generic_init(void)
 {
 	r8a7740_meram_workaround();
 
-#ifdef CONFIG_CACHE_L2X0
-	/* Shared attribute override enable, 32K*8way */
-	l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
-#endif
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
@@ -848,6 +844,8 @@ static const char *r8a7740_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
 	.map_io		= r8a7740_map_io,
 	.init_early	= shmobile_init_delay,
 	.init_irq	= r8a7740_init_irq_of,
-- 
1.9.1

[PATCH v3 3/6] ARM: shmobile: r8a7740: Migrate to generic l2c OF initialization

[Geert Uytterhoeven]

Migrate the generic r8a7740 platform from calling l2x0_of_init() to the
generic l2c OF initialization.

Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
v3:
  - Use 0/~0 now DT supports "arm,shared-override",

v2:
  - Keep only {,~}L2C_AUX_CTRL_SHARED_OVERRIDE.
---
 arch/arm/mach-shmobile/setup-r8a7740.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 9832e48396a40a92..5dbb40d5c56b6495 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -835,10 +835,6 @@ static void __init r8a7740_generic_init(void)
 {
 	r8a7740_meram_workaround();
 
-#ifdef CONFIG_CACHE_L2X0
-	/* Shared attribute override enable, 32K*8way */
-	l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
-#endif
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
@@ -848,6 +844,8 @@ static const char *r8a7740_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
 	.map_io		= r8a7740_map_io,
 	.init_early	= shmobile_init_delay,
 	.init_irq	= r8a7740_init_irq_of,
-- 
1.9.1

--
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[PATCH v3 3/6] ARM: shmobile: r8a7740: Migrate to generic l2c OF initialization

[Geert Uytterhoeven]

Migrate the generic r8a7740 platform from calling l2x0_of_init() to the
generic l2c OF initialization.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Use 0/~0 now DT supports "arm,shared-override",

v2:
  - Keep only {,~}L2C_AUX_CTRL_SHARED_OVERRIDE.
---
 arch/arm/mach-shmobile/setup-r8a7740.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 9832e48396a40a92..5dbb40d5c56b6495 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -835,10 +835,6 @@ static void __init r8a7740_generic_init(void)
 {
 	r8a7740_meram_workaround();
 
-#ifdef CONFIG_CACHE_L2X0
-	/* Shared attribute override enable, 32K*8way */
-	l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
-#endif
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
@@ -848,6 +844,8 @@ static const char *r8a7740_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
 	.map_io		= r8a7740_map_io,
 	.init_early	= shmobile_init_delay,
 	.init_irq	= r8a7740_init_irq_of,
-- 
1.9.1

[PATCH v3 4/6] ARM: shmobile: armadillo legacy: Migrate to generic l2c OF initialization

[Geert Uytterhoeven]

Migrate the generic r8a7740 platform from calling l2x0_of_init() to the
generic l2c OF initialization.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Use 0/~0 now DT supports "arm,shared-override",

v2:
  - Keep only {,~}L2C_AUX_CTRL_SHARED_OVERRIDE.
---
 arch/arm/mach-shmobile/board-armadillo800eva.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index bf37e3c532f661a6..e77fe29db4658357 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -1308,12 +1308,6 @@ static void __init eva_init(void)
 		sdhi1 = &sdhi1_device;
 	}
 
-
-#ifdef CONFIG_CACHE_L2X0
-	/* Shared attribute override enable, 32K*8way */
-	l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
-#endif
-
 	i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
 	i2c_register_board_info(2, i2c2_devices, ARRAY_SIZE(i2c2_devices));
 
@@ -1354,6 +1348,8 @@ static const char *eva_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
 	.map_io		= r8a7740_map_io,
 	.init_early	= r8a7740_add_early_devices,
 	.init_irq	= r8a7740_init_irq_of,
-- 
1.9.1

[PATCH v3 4/6] ARM: shmobile: armadillo legacy: Migrate to generic l2c OF initialization

[Geert Uytterhoeven]

Migrate the generic r8a7740 platform from calling l2x0_of_init() to the
generic l2c OF initialization.

Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
v3:
  - Use 0/~0 now DT supports "arm,shared-override",

v2:
  - Keep only {,~}L2C_AUX_CTRL_SHARED_OVERRIDE.
---
 arch/arm/mach-shmobile/board-armadillo800eva.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index bf37e3c532f661a6..e77fe29db4658357 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -1308,12 +1308,6 @@ static void __init eva_init(void)
 		sdhi1 = &sdhi1_device;
 	}
 
-
-#ifdef CONFIG_CACHE_L2X0
-	/* Shared attribute override enable, 32K*8way */
-	l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
-#endif
-
 	i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
 	i2c_register_board_info(2, i2c2_devices, ARRAY_SIZE(i2c2_devices));
 
@@ -1354,6 +1348,8 @@ static const char *eva_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
 	.map_io		= r8a7740_map_io,
 	.init_early	= r8a7740_add_early_devices,
 	.init_irq	= r8a7740_init_irq_of,
-- 
1.9.1

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH v3 4/6] ARM: shmobile: armadillo legacy: Migrate to generic l2c OF initialization

[Geert Uytterhoeven]

Migrate the generic r8a7740 platform from calling l2x0_of_init() to the
generic l2c OF initialization.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - Use 0/~0 now DT supports "arm,shared-override",

v2:
  - Keep only {,~}L2C_AUX_CTRL_SHARED_OVERRIDE.
---
 arch/arm/mach-shmobile/board-armadillo800eva.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index bf37e3c532f661a6..e77fe29db4658357 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -1308,12 +1308,6 @@ static void __init eva_init(void)
 		sdhi1 = &sdhi1_device;
 	}
 
-
-#ifdef CONFIG_CACHE_L2X0
-	/* Shared attribute override enable, 32K*8way */
-	l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
-#endif
-
 	i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
 	i2c_register_board_info(2, i2c2_devices, ARRAY_SIZE(i2c2_devices));
 
@@ -1354,6 +1348,8 @@ static const char *eva_boards_compat_dt[] __initdata = {
 };
 
 DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
 	.map_io		= r8a7740_map_io,
 	.init_early	= r8a7740_add_early_devices,
 	.init_irq	= r8a7740_init_irq_of,
-- 
1.9.1

[PATCH v3 5/6] ARM: shmobile: r8a7740: Remove mapping of L2 cache controller registers

[Geert Uytterhoeven]

Now all r8a7740-based platforms have been migrated to the generic l2c OF
initialization, it's no longer needed to map the L2 cache controller
registers from .map_io().

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - No changes,

v2:
  - No changes.
---
 arch/arm/mach-shmobile/setup-r8a7740.c | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 5dbb40d5c56b6495..3d8a8cfee9a62c6c 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -51,18 +51,6 @@ static struct map_desc r8a7740_io_desc[] __initdata = {
 		.length		= 160 << 20,
 		.type		= MT_DEVICE_NONSHARED
 	},
-#ifdef CONFIG_CACHE_L2X0
-	/*
-	 * for l2x0_init()
-	 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
-	 */
-	{
-		.virtual	= 0xf0002000,
-		.pfn		= __phys_to_pfn(0xf0100000),
-		.length		= PAGE_SIZE,
-		.type		= MT_DEVICE_NONSHARED
-	},
-#endif
 };
 
 void __init r8a7740_map_io(void)
-- 
1.9.1

[PATCH v3 5/6] ARM: shmobile: r8a7740: Remove mapping of L2 cache controller registers

[Geert Uytterhoeven]

Now all r8a7740-based platforms have been migrated to the generic l2c OF
initialization, it's no longer needed to map the L2 cache controller
registers from .map_io().

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - No changes,

v2:
  - No changes.
---
 arch/arm/mach-shmobile/setup-r8a7740.c | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 5dbb40d5c56b6495..3d8a8cfee9a62c6c 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -51,18 +51,6 @@ static struct map_desc r8a7740_io_desc[] __initdata = {
 		.length		= 160 << 20,
 		.type		= MT_DEVICE_NONSHARED
 	},
-#ifdef CONFIG_CACHE_L2X0
-	/*
-	 * for l2x0_init()
-	 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
-	 */
-	{
-		.virtual	= 0xf0002000,
-		.pfn		= __phys_to_pfn(0xf0100000),
-		.length		= PAGE_SIZE,
-		.type		= MT_DEVICE_NONSHARED
-	},
-#endif
 };
 
 void __init r8a7740_map_io(void)
-- 
1.9.1

[PATCH v3 5/6] ARM: shmobile: r8a7740: Remove mapping of L2 cache controller registers

[Geert Uytterhoeven]

Now all r8a7740-based platforms have been migrated to the generic l2c OF
initialization, it's no longer needed to map the L2 cache controller
registers from .map_io().

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - No changes,

v2:
  - No changes.
---
 arch/arm/mach-shmobile/setup-r8a7740.c | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 5dbb40d5c56b6495..3d8a8cfee9a62c6c 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -51,18 +51,6 @@ static struct map_desc r8a7740_io_desc[] __initdata = {
 		.length		= 160 << 20,
 		.type		= MT_DEVICE_NONSHARED
 	},
-#ifdef CONFIG_CACHE_L2X0
-	/*
-	 * for l2x0_init()
-	 * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
-	 */
-	{
-		.virtual	= 0xf0002000,
-		.pfn		= __phys_to_pfn(0xf0100000),
-		.length		= PAGE_SIZE,
-		.type		= MT_DEVICE_NONSHARED
-	},
-#endif
 };
 
 void __init r8a7740_map_io(void)
-- 
1.9.1

[PATCH v3 6/6] ARM: shmobile: r8a7740 dtsi: Add L1 cache information to CPU node

[Geert Uytterhoeven]

Describe the L1 cache in the CPU node:
  - L1 instruction cache: 32 KiB (8 KiB x 4 ways),
  - L1 data cache: 32 KiB (8 KiB x 4 ways).

Add a link to the L2 cache.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - No changes,

v2:
  - New.
---
 arch/arm/boot/dts/r8a7740.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index ddef5b1c68fa06b3..3aaab195132bfc2c 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -26,6 +26,15 @@
 			reg = <0x0>;
 			clock-frequency = <800000000>;
 			power-domains = <&pd_a3sm>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <256>;
+			i-cache-block-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <256>;
+			d-cache-block-size = <32>;
+			d-cache-line-size = <32>;
+			next-level-cache = <&L2>;
 		};
 	};
 
-- 
1.9.1

[PATCH v3 6/6] ARM: shmobile: r8a7740 dtsi: Add L1 cache information to CPU node

[Geert Uytterhoeven]

Describe the L1 cache in the CPU node:
  - L1 instruction cache: 32 KiB (8 KiB x 4 ways),
  - L1 data cache: 32 KiB (8 KiB x 4 ways).

Add a link to the L2 cache.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - No changes,

v2:
  - New.
---
 arch/arm/boot/dts/r8a7740.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index ddef5b1c68fa06b3..3aaab195132bfc2c 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -26,6 +26,15 @@
 			reg = <0x0>;
 			clock-frequency = <800000000>;
 			power-domains = <&pd_a3sm>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <256>;
+			i-cache-block-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <256>;
+			d-cache-block-size = <32>;
+			d-cache-line-size = <32>;
+			next-level-cache = <&L2>;
 		};
 	};
 
-- 
1.9.1

[PATCH v3 6/6] ARM: shmobile: r8a7740 dtsi: Add L1 cache information to CPU node

[Geert Uytterhoeven]

Describe the L1 cache in the CPU node:
  - L1 instruction cache: 32 KiB (8 KiB x 4 ways),
  - L1 data cache: 32 KiB (8 KiB x 4 ways).

Add a link to the L2 cache.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v3:
  - No changes,

v2:
  - New.
---
 arch/arm/boot/dts/r8a7740.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index ddef5b1c68fa06b3..3aaab195132bfc2c 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -26,6 +26,15 @@
 			reg = <0x0>;
 			clock-frequency = <800000000>;
 			power-domains = <&pd_a3sm>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <256>;
+			i-cache-block-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <256>;
+			d-cache-block-size = <32>;
+			d-cache-line-size = <32>;
+			next-level-cache = <&L2>;
 		};
 	};
 
-- 
1.9.1

Re: [PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Catalin Marinas]

On Mon, May 04, 2015 at 05:24:27PM +0200, Geert Uytterhoeven wrote:
> "CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2
> Shareable attribute" states:
> 
>     "The default behavior of the cache controller with respect to the
>      shareable attribute is to transform Normal Memory Non-cacheable
>      transactions into:
>         - cacheable no allocate for reads
>         - write through no write allocate for writes."
> 
> Depending on the system architecture, this may cause memory corruption
> in the presence of bus mastering devices (e.g. OHCI). To avoid such
> corruption, the default behavior can be disabled by setting the Shared
> Override bit in the Auxiliary Control register.
> 
> Currently the Shared Override bit can be set only using C code:
>   - by calling l2x0_init() directly, which is deprecated,
>   - by setting/clearing the bit in the machine_desc.l2c_aux_val/mask
>     fields, but using values differing from 0/~0 is also deprecated.

Or you can set it in firmware/boot-loader before Linux starts.

> Hence add support for an "arm,shared-override" device tree property for
> the l2c device node. By specifying this property, affected systems can
> indicate that non-cacheable transactions must not be transformed.
> 
> If specified, the actual behavior of the kernel depends on whether CMA
> is available or not:
>   - If CMA is available, nothing needs to be done, as there won't be a
>     kernel linear mappings and cacheable aliases for the DMA buffers,

I don't think this is true. See this thread:

http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/329492.html

>   - If CMA is not available, the "shared attribute override enable" bit
>     will be set.

IMO, this should always be done, independent of any DT or kernel
configuration. I stated it several times already that I don't see why we
would ever need such bit cleared:

http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/330573.html

Personally I don't think this configuration belongs to the DT,
especially as it may depend on how the OS is configured. But since
Russell has refused to take patches setting this bit by default (I have
yet to see a valid argument), it's still better than nothing.

-- 
Catalin

Re: [PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Catalin Marinas]

On Mon, May 04, 2015 at 05:24:27PM +0200, Geert Uytterhoeven wrote:
> "CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2
> Shareable attribute" states:
> 
>     "The default behavior of the cache controller with respect to the
>      shareable attribute is to transform Normal Memory Non-cacheable
>      transactions into:
>         - cacheable no allocate for reads
>         - write through no write allocate for writes."
> 
> Depending on the system architecture, this may cause memory corruption
> in the presence of bus mastering devices (e.g. OHCI). To avoid such
> corruption, the default behavior can be disabled by setting the Shared
> Override bit in the Auxiliary Control register.
> 
> Currently the Shared Override bit can be set only using C code:
>   - by calling l2x0_init() directly, which is deprecated,
>   - by setting/clearing the bit in the machine_desc.l2c_aux_val/mask
>     fields, but using values differing from 0/~0 is also deprecated.

Or you can set it in firmware/boot-loader before Linux starts.

> Hence add support for an "arm,shared-override" device tree property for
> the l2c device node. By specifying this property, affected systems can
> indicate that non-cacheable transactions must not be transformed.
> 
> If specified, the actual behavior of the kernel depends on whether CMA
> is available or not:
>   - If CMA is available, nothing needs to be done, as there won't be a
>     kernel linear mappings and cacheable aliases for the DMA buffers,

I don't think this is true. See this thread:

http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/329492.html

>   - If CMA is not available, the "shared attribute override enable" bit
>     will be set.

IMO, this should always be done, independent of any DT or kernel
configuration. I stated it several times already that I don't see why we
would ever need such bit cleared:

http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/330573.html

Personally I don't think this configuration belongs to the DT,
especially as it may depend on how the OS is configured. But since
Russell has refused to take patches setting this bit by default (I have
yet to see a valid argument), it's still better than nothing.

-- 
Catalin

[PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Catalin Marinas]

On Mon, May 04, 2015 at 05:24:27PM +0200, Geert Uytterhoeven wrote:
> "CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2
> Shareable attribute" states:
> 
>     "The default behavior of the cache controller with respect to the
>      shareable attribute is to transform Normal Memory Non-cacheable
>      transactions into:
>         - cacheable no allocate for reads
>         - write through no write allocate for writes."
> 
> Depending on the system architecture, this may cause memory corruption
> in the presence of bus mastering devices (e.g. OHCI). To avoid such
> corruption, the default behavior can be disabled by setting the Shared
> Override bit in the Auxiliary Control register.
> 
> Currently the Shared Override bit can be set only using C code:
>   - by calling l2x0_init() directly, which is deprecated,
>   - by setting/clearing the bit in the machine_desc.l2c_aux_val/mask
>     fields, but using values differing from 0/~0 is also deprecated.

Or you can set it in firmware/boot-loader before Linux starts.

> Hence add support for an "arm,shared-override" device tree property for
> the l2c device node. By specifying this property, affected systems can
> indicate that non-cacheable transactions must not be transformed.
> 
> If specified, the actual behavior of the kernel depends on whether CMA
> is available or not:
>   - If CMA is available, nothing needs to be done, as there won't be a
>     kernel linear mappings and cacheable aliases for the DMA buffers,

I don't think this is true. See this thread:

http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/329492.html

>   - If CMA is not available, the "shared attribute override enable" bit
>     will be set.

IMO, this should always be done, independent of any DT or kernel
configuration. I stated it several times already that I don't see why we
would ever need such bit cleared:

http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/330573.html

Personally I don't think this configuration belongs to the DT,
especially as it may depend on how the OS is configured. But since
Russell has refused to take patches setting this bit by default (I have
yet to see a valid argument), it's still better than nothing.

-- 
Catalin

Re: [PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Geert Uytterhoeven]

Hi Catalin,

On Tue, May 5, 2015 at 1:21 PM, Catalin Marinas <catalin.marinas@arm.com> wrote:
> On Mon, May 04, 2015 at 05:24:27PM +0200, Geert Uytterhoeven wrote:
>> "CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2
>> Shareable attribute" states:
>>
>>     "The default behavior of the cache controller with respect to the
>>      shareable attribute is to transform Normal Memory Non-cacheable
>>      transactions into:
>>         - cacheable no allocate for reads
>>         - write through no write allocate for writes."
>>
>> Depending on the system architecture, this may cause memory corruption
>> in the presence of bus mastering devices (e.g. OHCI). To avoid such
>> corruption, the default behavior can be disabled by setting the Shared
>> Override bit in the Auxiliary Control register.
>>
>> Currently the Shared Override bit can be set only using C code:
>>   - by calling l2x0_init() directly, which is deprecated,
>>   - by setting/clearing the bit in the machine_desc.l2c_aux_val/mask
>>     fields, but using values differing from 0/~0 is also deprecated.
>
> Or you can set it in firmware/boot-loader before Linux starts.

... together with all other additional settings cache-l2x0.c does?

I'm afraid this is not going to happen...

>> Hence add support for an "arm,shared-override" device tree property for
>> the l2c device node. By specifying this property, affected systems can
>> indicate that non-cacheable transactions must not be transformed.
>>
>> If specified, the actual behavior of the kernel depends on whether CMA
>> is available or not:
>>   - If CMA is available, nothing needs to be done, as there won't be a
>>     kernel linear mappings and cacheable aliases for the DMA buffers,
>
> I don't think this is true. See this thread:
>
> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/329492.html

Doh, and I had hoped to please Russell...

To bad, will drop this.

>>   - If CMA is not available, the "shared attribute override enable" bit
>>     will be set.
>
> IMO, this should always be done, independent of any DT or kernel
> configuration. I stated it several times already that I don't see why we
> would ever need such bit cleared:
>
> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/330573.html
>
> Personally I don't think this configuration belongs to the DT,
> especially as it may depend on how the OS is configured. But since

That's why I worded the bindings like "[...] this property must be specified to
indicate that such transforms are precluded.", not "[...] this property must be
specified if the Shared Override bit must be set by the OS.".
It's still up to the OS to decide (e.g. if CMA will get fixed).

> Russell has refused to take patches setting this bit by default (I have
> yet to see a valid argument), it's still better than nothing.

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Geert Uytterhoeven]

Hi Catalin,

On Tue, May 5, 2015 at 1:21 PM, Catalin Marinas <catalin.marinas@arm.com> wrote:
> On Mon, May 04, 2015 at 05:24:27PM +0200, Geert Uytterhoeven wrote:
>> "CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2
>> Shareable attribute" states:
>>
>>     "The default behavior of the cache controller with respect to the
>>      shareable attribute is to transform Normal Memory Non-cacheable
>>      transactions into:
>>         - cacheable no allocate for reads
>>         - write through no write allocate for writes."
>>
>> Depending on the system architecture, this may cause memory corruption
>> in the presence of bus mastering devices (e.g. OHCI). To avoid such
>> corruption, the default behavior can be disabled by setting the Shared
>> Override bit in the Auxiliary Control register.
>>
>> Currently the Shared Override bit can be set only using C code:
>>   - by calling l2x0_init() directly, which is deprecated,
>>   - by setting/clearing the bit in the machine_desc.l2c_aux_val/mask
>>     fields, but using values differing from 0/~0 is also deprecated.
>
> Or you can set it in firmware/boot-loader before Linux starts.

... together with all other additional settings cache-l2x0.c does?

I'm afraid this is not going to happen...

>> Hence add support for an "arm,shared-override" device tree property for
>> the l2c device node. By specifying this property, affected systems can
>> indicate that non-cacheable transactions must not be transformed.
>>
>> If specified, the actual behavior of the kernel depends on whether CMA
>> is available or not:
>>   - If CMA is available, nothing needs to be done, as there won't be a
>>     kernel linear mappings and cacheable aliases for the DMA buffers,
>
> I don't think this is true. See this thread:
>
> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/329492.html

Doh, and I had hoped to please Russell...

To bad, will drop this.

>>   - If CMA is not available, the "shared attribute override enable" bit
>>     will be set.
>
> IMO, this should always be done, independent of any DT or kernel
> configuration. I stated it several times already that I don't see why we
> would ever need such bit cleared:
>
> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/330573.html
>
> Personally I don't think this configuration belongs to the DT,
> especially as it may depend on how the OS is configured. But since

That's why I worded the bindings like "[...] this property must be specified to
indicate that such transforms are precluded.", not "[...] this property must be
specified if the Shared Override bit must be set by the OS.".
It's still up to the OS to decide (e.g. if CMA will get fixed).

> Russell has refused to take patches setting this bit by default (I have
> yet to see a valid argument), it's still better than nothing.

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Geert Uytterhoeven]

Hi Catalin,

On Tue, May 5, 2015 at 1:21 PM, Catalin Marinas <catalin.marinas@arm.com> wrote:
> On Mon, May 04, 2015 at 05:24:27PM +0200, Geert Uytterhoeven wrote:
>> "CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2
>> Shareable attribute" states:
>>
>>     "The default behavior of the cache controller with respect to the
>>      shareable attribute is to transform Normal Memory Non-cacheable
>>      transactions into:
>>         - cacheable no allocate for reads
>>         - write through no write allocate for writes."
>>
>> Depending on the system architecture, this may cause memory corruption
>> in the presence of bus mastering devices (e.g. OHCI). To avoid such
>> corruption, the default behavior can be disabled by setting the Shared
>> Override bit in the Auxiliary Control register.
>>
>> Currently the Shared Override bit can be set only using C code:
>>   - by calling l2x0_init() directly, which is deprecated,
>>   - by setting/clearing the bit in the machine_desc.l2c_aux_val/mask
>>     fields, but using values differing from 0/~0 is also deprecated.
>
> Or you can set it in firmware/boot-loader before Linux starts.

... together with all other additional settings cache-l2x0.c does?

I'm afraid this is not going to happen...

>> Hence add support for an "arm,shared-override" device tree property for
>> the l2c device node. By specifying this property, affected systems can
>> indicate that non-cacheable transactions must not be transformed.
>>
>> If specified, the actual behavior of the kernel depends on whether CMA
>> is available or not:
>>   - If CMA is available, nothing needs to be done, as there won't be a
>>     kernel linear mappings and cacheable aliases for the DMA buffers,
>
> I don't think this is true. See this thread:
>
> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/329492.html

Doh, and I had hoped to please Russell...

To bad, will drop this.

>>   - If CMA is not available, the "shared attribute override enable" bit
>>     will be set.
>
> IMO, this should always be done, independent of any DT or kernel
> configuration. I stated it several times already that I don't see why we
> would ever need such bit cleared:
>
> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/330573.html
>
> Personally I don't think this configuration belongs to the DT,
> especially as it may depend on how the OS is configured. But since

That's why I worded the bindings like "[...] this property must be specified to
indicate that such transforms are precluded.", not "[...] this property must be
specified if the Shared Override bit must be set by the OS.".
It's still up to the OS to decide (e.g. if CMA will get fixed).

> Russell has refused to take patches setting this bit by default (I have
> yet to see a valid argument), it's still better than nothing.

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Catalin Marinas]

On Tue, May 05, 2015 at 01:42:21PM +0200, Geert Uytterhoeven wrote:
> On Tue, May 5, 2015 at 1:21 PM, Catalin Marinas <catalin.marinas@arm.com> wrote:
> > On Mon, May 04, 2015 at 05:24:27PM +0200, Geert Uytterhoeven wrote:
> >> "CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2
> >> Shareable attribute" states:
> >>
> >>     "The default behavior of the cache controller with respect to the
> >>      shareable attribute is to transform Normal Memory Non-cacheable
> >>      transactions into:
> >>         - cacheable no allocate for reads
> >>         - write through no write allocate for writes."
> >>
> >> Depending on the system architecture, this may cause memory corruption
> >> in the presence of bus mastering devices (e.g. OHCI). To avoid such
> >> corruption, the default behavior can be disabled by setting the Shared
> >> Override bit in the Auxiliary Control register.
> >>
> >> Currently the Shared Override bit can be set only using C code:
> >>   - by calling l2x0_init() directly, which is deprecated,
> >>   - by setting/clearing the bit in the machine_desc.l2c_aux_val/mask
> >>     fields, but using values differing from 0/~0 is also deprecated.
> >
> > Or you can set it in firmware/boot-loader before Linux starts.
> 
> ... together with all other additional settings cache-l2x0.c does?
> 
> I'm afraid this is not going to happen...

It's not that bad but, well, it requires changes elsewhere (U-Boot
already does this for some SoCs).

> >> Hence add support for an "arm,shared-override" device tree property for
> >> the l2c device node. By specifying this property, affected systems can
> >> indicate that non-cacheable transactions must not be transformed.
> >>
> >> If specified, the actual behavior of the kernel depends on whether CMA
> >> is available or not:
> >>   - If CMA is available, nothing needs to be done, as there won't be a
> >>     kernel linear mappings and cacheable aliases for the DMA buffers,
> >
> > I don't think this is true. See this thread:
> >
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/329492.html
> 
> Doh, and I had hoped to please Russell...
> 
> To bad, will drop this.

You should only drop the "if (dev_get_cma_area(NULL))" check.

> >>   - If CMA is not available, the "shared attribute override enable" bit
> >>     will be set.
> >
> > IMO, this should always be done, independent of any DT or kernel
> > configuration. I stated it several times already that I don't see why we
> > would ever need such bit cleared:
> >
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/330573.html
> >
> > Personally I don't think this configuration belongs to the DT,
> > especially as it may depend on how the OS is configured. But since
> 
> That's why I worded the bindings like "[...] this property must be specified to
> indicate that such transforms are precluded.", not "[...] this property must be
> specified if the Shared Override bit must be set by the OS.".
> It's still up to the OS to decide (e.g. if CMA will get fixed).

We are kind of stretching this definition if the CMA check is removed.
The check could added back if DMA allocations are ever fixed to avoid
memory attributes aliases (right now they still exist, even though
temporarily). A situation where this bit probably does not need to be
set (though it's harmless) is I/O coherent systems ("arm,io-coherent").

My view is that we should always set this bit without any additional DT
properties but if it's easier to get it accepted this way, I'm fine as
well.

BTW, your patch mentions r2p0. My reading of the PL310 TRM shows this
bit as default from r0p0.

-- 
Catalin

Re: [PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Catalin Marinas]

On Tue, May 05, 2015 at 01:42:21PM +0200, Geert Uytterhoeven wrote:
> On Tue, May 5, 2015 at 1:21 PM, Catalin Marinas <catalin.marinas@arm.com> wrote:
> > On Mon, May 04, 2015 at 05:24:27PM +0200, Geert Uytterhoeven wrote:
> >> "CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2
> >> Shareable attribute" states:
> >>
> >>     "The default behavior of the cache controller with respect to the
> >>      shareable attribute is to transform Normal Memory Non-cacheable
> >>      transactions into:
> >>         - cacheable no allocate for reads
> >>         - write through no write allocate for writes."
> >>
> >> Depending on the system architecture, this may cause memory corruption
> >> in the presence of bus mastering devices (e.g. OHCI). To avoid such
> >> corruption, the default behavior can be disabled by setting the Shared
> >> Override bit in the Auxiliary Control register.
> >>
> >> Currently the Shared Override bit can be set only using C code:
> >>   - by calling l2x0_init() directly, which is deprecated,
> >>   - by setting/clearing the bit in the machine_desc.l2c_aux_val/mask
> >>     fields, but using values differing from 0/~0 is also deprecated.
> >
> > Or you can set it in firmware/boot-loader before Linux starts.
> 
> ... together with all other additional settings cache-l2x0.c does?
> 
> I'm afraid this is not going to happen...

It's not that bad but, well, it requires changes elsewhere (U-Boot
already does this for some SoCs).

> >> Hence add support for an "arm,shared-override" device tree property for
> >> the l2c device node. By specifying this property, affected systems can
> >> indicate that non-cacheable transactions must not be transformed.
> >>
> >> If specified, the actual behavior of the kernel depends on whether CMA
> >> is available or not:
> >>   - If CMA is available, nothing needs to be done, as there won't be a
> >>     kernel linear mappings and cacheable aliases for the DMA buffers,
> >
> > I don't think this is true. See this thread:
> >
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/329492.html
> 
> Doh, and I had hoped to please Russell...
> 
> To bad, will drop this.

You should only drop the "if (dev_get_cma_area(NULL))" check.

> >>   - If CMA is not available, the "shared attribute override enable" bit
> >>     will be set.
> >
> > IMO, this should always be done, independent of any DT or kernel
> > configuration. I stated it several times already that I don't see why we
> > would ever need such bit cleared:
> >
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/330573.html
> >
> > Personally I don't think this configuration belongs to the DT,
> > especially as it may depend on how the OS is configured. But since
> 
> That's why I worded the bindings like "[...] this property must be specified to
> indicate that such transforms are precluded.", not "[...] this property must be
> specified if the Shared Override bit must be set by the OS.".
> It's still up to the OS to decide (e.g. if CMA will get fixed).

We are kind of stretching this definition if the CMA check is removed.
The check could added back if DMA allocations are ever fixed to avoid
memory attributes aliases (right now they still exist, even though
temporarily). A situation where this bit probably does not need to be
set (though it's harmless) is I/O coherent systems ("arm,io-coherent").

My view is that we should always set this bit without any additional DT
properties but if it's easier to get it accepted this way, I'm fine as
well.

BTW, your patch mentions r2p0. My reading of the PL310 TRM shows this
bit as default from r0p0.

-- 
Catalin

[PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Catalin Marinas]

On Tue, May 05, 2015 at 01:42:21PM +0200, Geert Uytterhoeven wrote:
> On Tue, May 5, 2015 at 1:21 PM, Catalin Marinas <catalin.marinas@arm.com> wrote:
> > On Mon, May 04, 2015 at 05:24:27PM +0200, Geert Uytterhoeven wrote:
> >> "CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2
> >> Shareable attribute" states:
> >>
> >>     "The default behavior of the cache controller with respect to the
> >>      shareable attribute is to transform Normal Memory Non-cacheable
> >>      transactions into:
> >>         - cacheable no allocate for reads
> >>         - write through no write allocate for writes."
> >>
> >> Depending on the system architecture, this may cause memory corruption
> >> in the presence of bus mastering devices (e.g. OHCI). To avoid such
> >> corruption, the default behavior can be disabled by setting the Shared
> >> Override bit in the Auxiliary Control register.
> >>
> >> Currently the Shared Override bit can be set only using C code:
> >>   - by calling l2x0_init() directly, which is deprecated,
> >>   - by setting/clearing the bit in the machine_desc.l2c_aux_val/mask
> >>     fields, but using values differing from 0/~0 is also deprecated.
> >
> > Or you can set it in firmware/boot-loader before Linux starts.
> 
> ... together with all other additional settings cache-l2x0.c does?
> 
> I'm afraid this is not going to happen...

It's not that bad but, well, it requires changes elsewhere (U-Boot
already does this for some SoCs).

> >> Hence add support for an "arm,shared-override" device tree property for
> >> the l2c device node. By specifying this property, affected systems can
> >> indicate that non-cacheable transactions must not be transformed.
> >>
> >> If specified, the actual behavior of the kernel depends on whether CMA
> >> is available or not:
> >>   - If CMA is available, nothing needs to be done, as there won't be a
> >>     kernel linear mappings and cacheable aliases for the DMA buffers,
> >
> > I don't think this is true. See this thread:
> >
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/329492.html
> 
> Doh, and I had hoped to please Russell...
> 
> To bad, will drop this.

You should only drop the "if (dev_get_cma_area(NULL))" check.

> >>   - If CMA is not available, the "shared attribute override enable" bit
> >>     will be set.
> >
> > IMO, this should always be done, independent of any DT or kernel
> > configuration. I stated it several times already that I don't see why we
> > would ever need such bit cleared:
> >
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/330573.html
> >
> > Personally I don't think this configuration belongs to the DT,
> > especially as it may depend on how the OS is configured. But since
> 
> That's why I worded the bindings like "[...] this property must be specified to
> indicate that such transforms are precluded.", not "[...] this property must be
> specified if the Shared Override bit must be set by the OS.".
> It's still up to the OS to decide (e.g. if CMA will get fixed).

We are kind of stretching this definition if the CMA check is removed.
The check could added back if DMA allocations are ever fixed to avoid
memory attributes aliases (right now they still exist, even though
temporarily). A situation where this bit probably does not need to be
set (though it's harmless) is I/O coherent systems ("arm,io-coherent").

My view is that we should always set this bit without any additional DT
properties but if it's easier to get it accepted this way, I'm fine as
well.

BTW, your patch mentions r2p0. My reading of the PL310 TRM shows this
bit as default from r0p0.

-- 
Catalin

Re: [PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Geert Uytterhoeven]

Hi Catalin,

On Tue, May 5, 2015 at 4:22 PM, Catalin Marinas <catalin.marinas@arm.com> wrote:
> On Tue, May 05, 2015 at 01:42:21PM +0200, Geert Uytterhoeven wrote:
>> On Tue, May 5, 2015 at 1:21 PM, Catalin Marinas <catalin.marinas@arm.com> wrote:
>> > On Mon, May 04, 2015 at 05:24:27PM +0200, Geert Uytterhoeven wrote:
>> >> Hence add support for an "arm,shared-override" device tree property for
>> >> the l2c device node. By specifying this property, affected systems can
>> >> indicate that non-cacheable transactions must not be transformed.
>> >>
>> >> If specified, the actual behavior of the kernel depends on whether CMA
>> >> is available or not:
>> >>   - If CMA is available, nothing needs to be done, as there won't be a
>> >>     kernel linear mappings and cacheable aliases for the DMA buffers,
>> >
>> > I don't think this is true. See this thread:
>> >
>> > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/329492.html
>>
>> Doh, and I had hoped to please Russell...
>>
>> To bad, will drop this.
>
> You should only drop the "if (dev_get_cma_area(NULL))" check.

Of course.

> BTW, your patch mentions r2p0. My reading of the PL310 TRM shows this
> bit as default from r0p0.

Arnd told me he had read the documentation for r0p0 and couldn't find it.
The r3p2 manual lists the following changes between r1p0-r2p0:
  - new behavior linked to the Shared attribute.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Geert Uytterhoeven]

Hi Catalin,

On Tue, May 5, 2015 at 4:22 PM, Catalin Marinas <catalin.marinas@arm.com> wrote:
> On Tue, May 05, 2015 at 01:42:21PM +0200, Geert Uytterhoeven wrote:
>> On Tue, May 5, 2015 at 1:21 PM, Catalin Marinas <catalin.marinas@arm.com> wrote:
>> > On Mon, May 04, 2015 at 05:24:27PM +0200, Geert Uytterhoeven wrote:
>> >> Hence add support for an "arm,shared-override" device tree property for
>> >> the l2c device node. By specifying this property, affected systems can
>> >> indicate that non-cacheable transactions must not be transformed.
>> >>
>> >> If specified, the actual behavior of the kernel depends on whether CMA
>> >> is available or not:
>> >>   - If CMA is available, nothing needs to be done, as there won't be a
>> >>     kernel linear mappings and cacheable aliases for the DMA buffers,
>> >
>> > I don't think this is true. See this thread:
>> >
>> > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/329492.html
>>
>> Doh, and I had hoped to please Russell...
>>
>> To bad, will drop this.
>
> You should only drop the "if (dev_get_cma_area(NULL))" check.

Of course.

> BTW, your patch mentions r2p0. My reading of the PL310 TRM shows this
> bit as default from r0p0.

Arnd told me he had read the documentation for r0p0 and couldn't find it.
The r3p2 manual lists the following changes between r1p0-r2p0:
  - new behavior linked to the Shared attribute.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Geert Uytterhoeven]

Hi Catalin,

On Tue, May 5, 2015 at 4:22 PM, Catalin Marinas <catalin.marinas@arm.com> wrote:
> On Tue, May 05, 2015 at 01:42:21PM +0200, Geert Uytterhoeven wrote:
>> On Tue, May 5, 2015 at 1:21 PM, Catalin Marinas <catalin.marinas@arm.com> wrote:
>> > On Mon, May 04, 2015 at 05:24:27PM +0200, Geert Uytterhoeven wrote:
>> >> Hence add support for an "arm,shared-override" device tree property for
>> >> the l2c device node. By specifying this property, affected systems can
>> >> indicate that non-cacheable transactions must not be transformed.
>> >>
>> >> If specified, the actual behavior of the kernel depends on whether CMA
>> >> is available or not:
>> >>   - If CMA is available, nothing needs to be done, as there won't be a
>> >>     kernel linear mappings and cacheable aliases for the DMA buffers,
>> >
>> > I don't think this is true. See this thread:
>> >
>> > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/329492.html
>>
>> Doh, and I had hoped to please Russell...
>>
>> To bad, will drop this.
>
> You should only drop the "if (dev_get_cma_area(NULL))" check.

Of course.

> BTW, your patch mentions r2p0. My reading of the PL310 TRM shows this
> bit as default from r0p0.

Arnd told me he had read the documentation for r0p0 and couldn't find it.
The r3p2 manual lists the following changes between r1p0-r2p0:
  - new behavior linked to the Shared attribute.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Catalin Marinas]

On Tue, May 05, 2015 at 04:55:02PM +0200, Geert Uytterhoeven wrote:
> On Tue, May 5, 2015 at 4:22 PM, Catalin Marinas <catalin.marinas@arm.com> wrote:
> > BTW, your patch mentions r2p0. My reading of the PL310 TRM shows this
> > bit as default from r0p0.
> 
> Arnd told me he had read the documentation for r0p0 and couldn't find it.
> The r3p2 manual lists the following changes between r1p0-r2p0:
>   - new behavior linked to the Shared attribute.

Bit 22 is present since r0p0 with the same description as in r2p0 and
later:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246a/Ceggcfcj.html

I guess the new behaviour is about bit 13, Shared Attribute Invalidate
Enable:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246c/Ceggcfcj.html

But that's outside the scope of this patch.

-- 
Catalin

Re: [PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Catalin Marinas]

On Tue, May 05, 2015 at 04:55:02PM +0200, Geert Uytterhoeven wrote:
> On Tue, May 5, 2015 at 4:22 PM, Catalin Marinas <catalin.marinas@arm.com> wrote:
> > BTW, your patch mentions r2p0. My reading of the PL310 TRM shows this
> > bit as default from r0p0.
> 
> Arnd told me he had read the documentation for r0p0 and couldn't find it.
> The r3p2 manual lists the following changes between r1p0-r2p0:
>   - new behavior linked to the Shared attribute.

Bit 22 is present since r0p0 with the same description as in r2p0 and
later:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246a/Ceggcfcj.html

I guess the new behaviour is about bit 13, Shared Attribute Invalidate
Enable:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246c/Ceggcfcj.html

But that's outside the scope of this patch.

-- 
Catalin

[PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Catalin Marinas]

On Tue, May 05, 2015 at 04:55:02PM +0200, Geert Uytterhoeven wrote:
> On Tue, May 5, 2015 at 4:22 PM, Catalin Marinas <catalin.marinas@arm.com> wrote:
> > BTW, your patch mentions r2p0. My reading of the PL310 TRM shows this
> > bit as default from r0p0.
> 
> Arnd told me he had read the documentation for r0p0 and couldn't find it.
> The r3p2 manual lists the following changes between r1p0-r2p0:
>   - new behavior linked to the Shared attribute.

Bit 22 is present since r0p0 with the same description as in r2p0 and
later:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246a/Ceggcfcj.html

I guess the new behaviour is about bit 13, Shared Attribute Invalidate
Enable:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0246c/Ceggcfcj.html

But that's outside the scope of this patch.

-- 
Catalin

Re: [PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Rob Herring]

On Tue, May 5, 2015 at 9:22 AM, Catalin Marinas <catalin.marinas@arm.com> wrote:
> On Tue, May 05, 2015 at 01:42:21PM +0200, Geert Uytterhoeven wrote:
>> On Tue, May 5, 2015 at 1:21 PM, Catalin Marinas <catalin.marinas@arm.com> wrote:
>> > On Mon, May 04, 2015 at 05:24:27PM +0200, Geert Uytterhoeven wrote:
>> >> "CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2
>> >> Shareable attribute" states:
>> >>
>> >>     "The default behavior of the cache controller with respect to the
>> >>      shareable attribute is to transform Normal Memory Non-cacheable
>> >>      transactions into:
>> >>         - cacheable no allocate for reads
>> >>         - write through no write allocate for writes."
>> >>
>> >> Depending on the system architecture, this may cause memory corruption
>> >> in the presence of bus mastering devices (e.g. OHCI). To avoid such
>> >> corruption, the default behavior can be disabled by setting the Shared
>> >> Override bit in the Auxiliary Control register.
>> >>
>> >> Currently the Shared Override bit can be set only using C code:
>> >>   - by calling l2x0_init() directly, which is deprecated,
>> >>   - by setting/clearing the bit in the machine_desc.l2c_aux_val/mask
>> >>     fields, but using values differing from 0/~0 is also deprecated.
>> >
>> > Or you can set it in firmware/boot-loader before Linux starts.
>>
>> ... together with all other additional settings cache-l2x0.c does?
>>
>> I'm afraid this is not going to happen...
>
> It's not that bad but, well, it requires changes elsewhere (U-Boot
> already does this for some SoCs).
>
>> >> Hence add support for an "arm,shared-override" device tree property for
>> >> the l2c device node. By specifying this property, affected systems can
>> >> indicate that non-cacheable transactions must not be transformed.
>> >>
>> >> If specified, the actual behavior of the kernel depends on whether CMA
>> >> is available or not:
>> >>   - If CMA is available, nothing needs to be done, as there won't be a
>> >>     kernel linear mappings and cacheable aliases for the DMA buffers,
>> >
>> > I don't think this is true. See this thread:
>> >
>> > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/329492.html
>>
>> Doh, and I had hoped to please Russell...
>>
>> To bad, will drop this.
>
> You should only drop the "if (dev_get_cma_area(NULL))" check.
>
>> >>   - If CMA is not available, the "shared attribute override enable" bit
>> >>     will be set.
>> >
>> > IMO, this should always be done, independent of any DT or kernel
>> > configuration. I stated it several times already that I don't see why we
>> > would ever need such bit cleared:
>> >
>> > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/330573.html
>> >
>> > Personally I don't think this configuration belongs to the DT,
>> > especially as it may depend on how the OS is configured. But since
>>
>> That's why I worded the bindings like "[...] this property must be specified to
>> indicate that such transforms are precluded.", not "[...] this property must be
>> specified if the Shared Override bit must be set by the OS.".
>> It's still up to the OS to decide (e.g. if CMA will get fixed).
>
> We are kind of stretching this definition if the CMA check is removed.
> The check could added back if DMA allocations are ever fixed to avoid
> memory attributes aliases (right now they still exist, even though
> temporarily). A situation where this bit probably does not need to be
> set (though it's harmless) is I/O coherent systems ("arm,io-coherent").

IIRC, it still had to be set on highbank even when we had coherent i/o.

> My view is that we should always set this bit without any additional DT
> properties but if it's easier to get it accepted this way, I'm fine as
> well.

+1

> BTW, your patch mentions r2p0. My reading of the PL310 TRM shows this
> bit as default from r0p0.

I believe the change in behavior was from the L2x0 to PL310.

Rob

Re: [PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Rob Herring]

On Tue, May 5, 2015 at 9:22 AM, Catalin Marinas <catalin.marinas@arm.com> wrote:
> On Tue, May 05, 2015 at 01:42:21PM +0200, Geert Uytterhoeven wrote:
>> On Tue, May 5, 2015 at 1:21 PM, Catalin Marinas <catalin.marinas@arm.com> wrote:
>> > On Mon, May 04, 2015 at 05:24:27PM +0200, Geert Uytterhoeven wrote:
>> >> "CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2
>> >> Shareable attribute" states:
>> >>
>> >>     "The default behavior of the cache controller with respect to the
>> >>      shareable attribute is to transform Normal Memory Non-cacheable
>> >>      transactions into:
>> >>         - cacheable no allocate for reads
>> >>         - write through no write allocate for writes."
>> >>
>> >> Depending on the system architecture, this may cause memory corruption
>> >> in the presence of bus mastering devices (e.g. OHCI). To avoid such
>> >> corruption, the default behavior can be disabled by setting the Shared
>> >> Override bit in the Auxiliary Control register.
>> >>
>> >> Currently the Shared Override bit can be set only using C code:
>> >>   - by calling l2x0_init() directly, which is deprecated,
>> >>   - by setting/clearing the bit in the machine_desc.l2c_aux_val/mask
>> >>     fields, but using values differing from 0/~0 is also deprecated.
>> >
>> > Or you can set it in firmware/boot-loader before Linux starts.
>>
>> ... together with all other additional settings cache-l2x0.c does?
>>
>> I'm afraid this is not going to happen...
>
> It's not that bad but, well, it requires changes elsewhere (U-Boot
> already does this for some SoCs).
>
>> >> Hence add support for an "arm,shared-override" device tree property for
>> >> the l2c device node. By specifying this property, affected systems can
>> >> indicate that non-cacheable transactions must not be transformed.
>> >>
>> >> If specified, the actual behavior of the kernel depends on whether CMA
>> >> is available or not:
>> >>   - If CMA is available, nothing needs to be done, as there won't be a
>> >>     kernel linear mappings and cacheable aliases for the DMA buffers,
>> >
>> > I don't think this is true. See this thread:
>> >
>> > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/329492.html
>>
>> Doh, and I had hoped to please Russell...
>>
>> To bad, will drop this.
>
> You should only drop the "if (dev_get_cma_area(NULL))" check.
>
>> >>   - If CMA is not available, the "shared attribute override enable" bit
>> >>     will be set.
>> >
>> > IMO, this should always be done, independent of any DT or kernel
>> > configuration. I stated it several times already that I don't see why we
>> > would ever need such bit cleared:
>> >
>> > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/330573.html
>> >
>> > Personally I don't think this configuration belongs to the DT,
>> > especially as it may depend on how the OS is configured. But since
>>
>> That's why I worded the bindings like "[...] this property must be specified to
>> indicate that such transforms are precluded.", not "[...] this property must be
>> specified if the Shared Override bit must be set by the OS.".
>> It's still up to the OS to decide (e.g. if CMA will get fixed).
>
> We are kind of stretching this definition if the CMA check is removed.
> The check could added back if DMA allocations are ever fixed to avoid
> memory attributes aliases (right now they still exist, even though
> temporarily). A situation where this bit probably does not need to be
> set (though it's harmless) is I/O coherent systems ("arm,io-coherent").

IIRC, it still had to be set on highbank even when we had coherent i/o.

> My view is that we should always set this bit without any additional DT
> properties but if it's easier to get it accepted this way, I'm fine as
> well.

+1

> BTW, your patch mentions r2p0. My reading of the PL310 TRM shows this
> bit as default from r0p0.

I believe the change in behavior was from the L2x0 to PL310.

Rob

[PATCH v3 1/6] ARM: l2c: Add DT support for Shared Override

[Rob Herring]

On Tue, May 5, 2015 at 9:22 AM, Catalin Marinas <catalin.marinas@arm.com> wrote:
> On Tue, May 05, 2015 at 01:42:21PM +0200, Geert Uytterhoeven wrote:
>> On Tue, May 5, 2015 at 1:21 PM, Catalin Marinas <catalin.marinas@arm.com> wrote:
>> > On Mon, May 04, 2015 at 05:24:27PM +0200, Geert Uytterhoeven wrote:
>> >> "CoreLink Level 2 Cache Controller L2C-310", p. 2-15, section 2.3.2
>> >> Shareable attribute" states:
>> >>
>> >>     "The default behavior of the cache controller with respect to the
>> >>      shareable attribute is to transform Normal Memory Non-cacheable
>> >>      transactions into:
>> >>         - cacheable no allocate for reads
>> >>         - write through no write allocate for writes."
>> >>
>> >> Depending on the system architecture, this may cause memory corruption
>> >> in the presence of bus mastering devices (e.g. OHCI). To avoid such
>> >> corruption, the default behavior can be disabled by setting the Shared
>> >> Override bit in the Auxiliary Control register.
>> >>
>> >> Currently the Shared Override bit can be set only using C code:
>> >>   - by calling l2x0_init() directly, which is deprecated,
>> >>   - by setting/clearing the bit in the machine_desc.l2c_aux_val/mask
>> >>     fields, but using values differing from 0/~0 is also deprecated.
>> >
>> > Or you can set it in firmware/boot-loader before Linux starts.
>>
>> ... together with all other additional settings cache-l2x0.c does?
>>
>> I'm afraid this is not going to happen...
>
> It's not that bad but, well, it requires changes elsewhere (U-Boot
> already does this for some SoCs).
>
>> >> Hence add support for an "arm,shared-override" device tree property for
>> >> the l2c device node. By specifying this property, affected systems can
>> >> indicate that non-cacheable transactions must not be transformed.
>> >>
>> >> If specified, the actual behavior of the kernel depends on whether CMA
>> >> is available or not:
>> >>   - If CMA is available, nothing needs to be done, as there won't be a
>> >>     kernel linear mappings and cacheable aliases for the DMA buffers,
>> >
>> > I don't think this is true. See this thread:
>> >
>> > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/329492.html
>>
>> Doh, and I had hoped to please Russell...
>>
>> To bad, will drop this.
>
> You should only drop the "if (dev_get_cma_area(NULL))" check.
>
>> >>   - If CMA is not available, the "shared attribute override enable" bit
>> >>     will be set.
>> >
>> > IMO, this should always be done, independent of any DT or kernel
>> > configuration. I stated it several times already that I don't see why we
>> > would ever need such bit cleared:
>> >
>> > http://lists.infradead.org/pipermail/linux-arm-kernel/2015-March/330573.html
>> >
>> > Personally I don't think this configuration belongs to the DT,
>> > especially as it may depend on how the OS is configured. But since
>>
>> That's why I worded the bindings like "[...] this property must be specified to
>> indicate that such transforms are precluded.", not "[...] this property must be
>> specified if the Shared Override bit must be set by the OS.".
>> It's still up to the OS to decide (e.g. if CMA will get fixed).
>
> We are kind of stretching this definition if the CMA check is removed.
> The check could added back if DMA allocations are ever fixed to avoid
> memory attributes aliases (right now they still exist, even though
> temporarily). A situation where this bit probably does not need to be
> set (though it's harmless) is I/O coherent systems ("arm,io-coherent").

IIRC, it still had to be set on highbank even when we had coherent i/o.

> My view is that we should always set this bit without any additional DT
> properties but if it's easier to get it accepted this way, I'm fine as
> well.

+1

> BTW, your patch mentions r2p0. My reading of the PL310 TRM shows this
> bit as default from r0p0.

I believe the change in behavior was from the L2x0 to PL310.

Rob