[Qemu-devel] [RFC 0/4] arm/arm64: KVM: Get around cache incoherency

[Qemu-devel] [RFC 0/4] arm/arm64: KVM: Get around cache incoherency

[Jérémy Fanguède]

This RFC series shows how we can solve cache incohenrency issues on
ARM/ARM64. This implementation uses an ioctl that flushes the data
cache for a given range of the guest physical memory, this possible
solution was already broached in the previous discussion [1][2].

Each access (read or write) to the guest memory that could lead to
inconsistency is flushed if needed. A light optimization is done to
minimize the ioctl call.

Currently tested with the following devices: e1000, megasas,
lsi53c895a, nec-usb-xhci, usb-ehci (with usb-host, usb-tablet, usb-kbd
and usb-mouse), which were failling with KVM and now work fine with
this patch.

The kernel needs this patch: 
[RFC] ARM/ARM64: KVM: Implement KVM_FLUSH_DCACHE_GPA ioctl

[1] https://lists.cs.columbia.edu/pipermail/kvmarm/2015-February/013593.html
[2] https://lists.nongnu.org/archive/html/qemu-devel/2015-03/msg01254.html

Jérémy Fanguède (4):
  linux-headers update
  target-arm/kvm: Flush data cache support
  kvm-all: Pre-run cache coherency maintenance
  exec: Flush data cache when needed

 exec.c                    | 19 ++++++++++++++++++
 include/sysemu/kvm.h      |  3 +++
 kvm-all.c                 |  1 +
 linux-headers/linux/kvm.h |  6 ++++++
 stubs/kvm.c               |  9 +++++++++
 target-arm/kvm.c          | 51 +++++++++++++++++++++++++++++++++++++++++++++++
 6 files changed, 89 insertions(+)

-- 
1.9.1

[RFC 0/4] arm/arm64: KVM: Get around cache incoherency

[Jérémy Fanguède]

This RFC series shows how we can solve cache incohenrency issues on
ARM/ARM64. This implementation uses an ioctl that flushes the data
cache for a given range of the guest physical memory, this possible
solution was already broached in the previous discussion [1][2].

Each access (read or write) to the guest memory that could lead to
inconsistency is flushed if needed. A light optimization is done to
minimize the ioctl call.

Currently tested with the following devices: e1000, megasas,
lsi53c895a, nec-usb-xhci, usb-ehci (with usb-host, usb-tablet, usb-kbd
and usb-mouse), which were failling with KVM and now work fine with
this patch.

The kernel needs this patch: 
[RFC] ARM/ARM64: KVM: Implement KVM_FLUSH_DCACHE_GPA ioctl

[1] https://lists.cs.columbia.edu/pipermail/kvmarm/2015-February/013593.html
[2] https://lists.nongnu.org/archive/html/qemu-devel/2015-03/msg01254.html

Jérémy Fanguède (4):
  linux-headers update
  target-arm/kvm: Flush data cache support
  kvm-all: Pre-run cache coherency maintenance
  exec: Flush data cache when needed

 exec.c                    | 19 ++++++++++++++++++
 include/sysemu/kvm.h      |  3 +++
 kvm-all.c                 |  1 +
 linux-headers/linux/kvm.h |  6 ++++++
 stubs/kvm.c               |  9 +++++++++
 target-arm/kvm.c          | 51 +++++++++++++++++++++++++++++++++++++++++++++++
 6 files changed, 89 insertions(+)

-- 
1.9.1

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kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

[Qemu-devel] [RFC 1/4] linux-headers update

[Jérémy Fanguède]

Add KVM_FLUSH_DCACHE_GPA ioctl.

Signed-off-by: Jérémy Fanguède <j.fanguede@virtualopensystems.com>
---
 linux-headers/linux/kvm.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index b96d978..81d2f64 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -978,6 +978,11 @@ struct kvm_arm_device_addr {
 	__u64 addr;
 };
 
+struct kvm_mem_addr {
+	__u64 addr;
+	__u32 len;
+};
+
 /*
  * Device control API, available with KVM_CAP_DEVICE_CTRL
  */
@@ -1199,6 +1204,7 @@ struct kvm_s390_ucas_mapping {
 /* Available with KVM_CAP_S390_IRQ_STATE */
 #define KVM_S390_SET_IRQ_STATE	  _IOW(KVMIO, 0xb5, struct kvm_s390_irq_state)
 #define KVM_S390_GET_IRQ_STATE	  _IOW(KVMIO, 0xb6, struct kvm_s390_irq_state)
+#define KVM_FLUSH_DCACHE_GPA     _IOW(KVMIO,  0xb7, struct kvm_mem_addr)
 
 #define KVM_DEV_ASSIGN_ENABLE_IOMMU	(1 << 0)
 #define KVM_DEV_ASSIGN_PCI_2_3		(1 << 1)
-- 
1.9.1

[RFC 1/4] linux-headers update

[Jérémy Fanguède]

Add KVM_FLUSH_DCACHE_GPA ioctl.

Signed-off-by: Jérémy Fanguède <j.fanguede@virtualopensystems.com>
---
 linux-headers/linux/kvm.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index b96d978..81d2f64 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -978,6 +978,11 @@ struct kvm_arm_device_addr {
 	__u64 addr;
 };
 
+struct kvm_mem_addr {
+	__u64 addr;
+	__u32 len;
+};
+
 /*
  * Device control API, available with KVM_CAP_DEVICE_CTRL
  */
@@ -1199,6 +1204,7 @@ struct kvm_s390_ucas_mapping {
 /* Available with KVM_CAP_S390_IRQ_STATE */
 #define KVM_S390_SET_IRQ_STATE	  _IOW(KVMIO, 0xb5, struct kvm_s390_irq_state)
 #define KVM_S390_GET_IRQ_STATE	  _IOW(KVMIO, 0xb6, struct kvm_s390_irq_state)
+#define KVM_FLUSH_DCACHE_GPA     _IOW(KVMIO,  0xb7, struct kvm_mem_addr)
 
 #define KVM_DEV_ASSIGN_ENABLE_IOMMU	(1 << 0)
 #define KVM_DEV_ASSIGN_PCI_2_3		(1 << 1)
-- 
1.9.1

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kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

[RFC 2/4] target-arm/kvm: Flush data cache support

[Jérémy Fanguède]

Implement data cache maintenance coherency functions, by using
FLUSH_DCACHE_GPA ioctl. Introduce kvm_arm_maintain_cache_coherency()
for flushing the data cache if necessary, a very simple logic is
implemented to reduce number of flushes due to reads. Two wrapping
functions are exposed, for easier usage.

Signed-off-by: Jérémy Fanguède <j.fanguede@virtualopensystems.com>
---
 include/sysemu/kvm.h |  3 +++
 stubs/kvm.c          |  9 +++++++++
 target-arm/kvm.c     | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 63 insertions(+)

diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 197e6c0..986f365 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -451,4 +451,7 @@ int kvm_set_one_reg(CPUState *cs, uint64_t id, void *source);
  * Returns: 0 on success, or a negative errno on failure.
  */
 int kvm_get_one_reg(CPUState *cs, uint64_t id, void *target);
+
+void kvm_arch_cache_flush_needed(hwaddr addr, int len, bool is_write);
+void kvm_arch_cache_coherency_pre_run(void);
 #endif
diff --git a/stubs/kvm.c b/stubs/kvm.c
index e7c60b6..8ed5380 100644
--- a/stubs/kvm.c
+++ b/stubs/kvm.c
@@ -5,3 +5,12 @@ int kvm_arch_irqchip_create(KVMState *s)
 {
     return 0;
 }
+
+
+void kvm_arch_cache_flush_needed(hwaddr addr, int len, bool is_write)
+{
+}
+
+void kvm_arch_cache_coherency_pre_run(void)
+{
+}
diff --git a/target-arm/kvm.c b/target-arm/kvm.c
index fdd9ba3..548dae2 100644
--- a/target-arm/kvm.c
+++ b/target-arm/kvm.c
@@ -598,3 +598,54 @@ int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
 {
     return 0;
 }
+
+static void kvm_arm_flush_cache_addr(hwaddr addr, int len)
+{
+    int ret;
+    struct kvm_mem_addr mem_addr;
+    mem_addr.addr = addr;
+    mem_addr.len = len;
+    ret = kvm_vm_ioctl(kvm_state, KVM_FLUSH_DCACHE_GPA, &mem_addr);
+    if (ret) {
+        fprintf(stderr, "error: Failed to flush CPU caches %d\n", ret);
+    }
+}
+
+static void kvm_arm_maintain_cache_coherency(hwaddr addr, int len,
+                                             bool enter_guest, bool is_write)
+{
+    static hwaddr prev_addr;
+    static int prev_len;
+    hwaddr end_line, prev_end_line;
+
+    if (enter_guest) {
+        /* We will return to the guest after that, restore the default
+           configuration */
+        prev_addr = 0x0;
+        return;
+    }
+
+    /* Assume the minimal CPU cache line is 32 B */
+    end_line = (addr + len) & ~0x1f;
+    prev_end_line = (prev_addr + prev_len) & ~0x1f;
+
+    /* Don't flush two times in a row the same line"
+       Always flush on a write */
+    if ((prev_addr & ~0x1f) != (addr & ~0x1f)
+        || (prev_end_line < end_line)
+        || is_write) {
+        kvm_arm_flush_cache_addr(addr, len);
+        prev_addr = addr;
+        prev_len = len;
+    }
+}
+
+void kvm_arch_cache_flush_needed(hwaddr addr, int len, bool is_write)
+{
+    kvm_arm_maintain_cache_coherency(addr, len, false, is_write);
+}
+
+void kvm_arch_cache_coherency_pre_run(void)
+{
+    kvm_arm_maintain_cache_coherency(0, 0, true, false);
+}
-- 
1.9.1

[Qemu-devel] [RFC 2/4] target-arm/kvm: Flush data cache support

[Jérémy Fanguède]

Implement data cache maintenance coherency functions, by using
FLUSH_DCACHE_GPA ioctl. Introduce kvm_arm_maintain_cache_coherency()
for flushing the data cache if necessary, a very simple logic is
implemented to reduce number of flushes due to reads. Two wrapping
functions are exposed, for easier usage.

Signed-off-by: Jérémy Fanguède <j.fanguede@virtualopensystems.com>
---
 include/sysemu/kvm.h |  3 +++
 stubs/kvm.c          |  9 +++++++++
 target-arm/kvm.c     | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 63 insertions(+)

diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 197e6c0..986f365 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -451,4 +451,7 @@ int kvm_set_one_reg(CPUState *cs, uint64_t id, void *source);
  * Returns: 0 on success, or a negative errno on failure.
  */
 int kvm_get_one_reg(CPUState *cs, uint64_t id, void *target);
+
+void kvm_arch_cache_flush_needed(hwaddr addr, int len, bool is_write);
+void kvm_arch_cache_coherency_pre_run(void);
 #endif
diff --git a/stubs/kvm.c b/stubs/kvm.c
index e7c60b6..8ed5380 100644
--- a/stubs/kvm.c
+++ b/stubs/kvm.c
@@ -5,3 +5,12 @@ int kvm_arch_irqchip_create(KVMState *s)
 {
     return 0;
 }
+
+
+void kvm_arch_cache_flush_needed(hwaddr addr, int len, bool is_write)
+{
+}
+
+void kvm_arch_cache_coherency_pre_run(void)
+{
+}
diff --git a/target-arm/kvm.c b/target-arm/kvm.c
index fdd9ba3..548dae2 100644
--- a/target-arm/kvm.c
+++ b/target-arm/kvm.c
@@ -598,3 +598,54 @@ int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
 {
     return 0;
 }
+
+static void kvm_arm_flush_cache_addr(hwaddr addr, int len)
+{
+    int ret;
+    struct kvm_mem_addr mem_addr;
+    mem_addr.addr = addr;
+    mem_addr.len = len;
+    ret = kvm_vm_ioctl(kvm_state, KVM_FLUSH_DCACHE_GPA, &mem_addr);
+    if (ret) {
+        fprintf(stderr, "error: Failed to flush CPU caches %d\n", ret);
+    }
+}
+
+static void kvm_arm_maintain_cache_coherency(hwaddr addr, int len,
+                                             bool enter_guest, bool is_write)
+{
+    static hwaddr prev_addr;
+    static int prev_len;
+    hwaddr end_line, prev_end_line;
+
+    if (enter_guest) {
+        /* We will return to the guest after that, restore the default
+           configuration */
+        prev_addr = 0x0;
+        return;
+    }
+
+    /* Assume the minimal CPU cache line is 32 B */
+    end_line = (addr + len) & ~0x1f;
+    prev_end_line = (prev_addr + prev_len) & ~0x1f;
+
+    /* Don't flush two times in a row the same line"
+       Always flush on a write */
+    if ((prev_addr & ~0x1f) != (addr & ~0x1f)
+        || (prev_end_line < end_line)
+        || is_write) {
+        kvm_arm_flush_cache_addr(addr, len);
+        prev_addr = addr;
+        prev_len = len;
+    }
+}
+
+void kvm_arch_cache_flush_needed(hwaddr addr, int len, bool is_write)
+{
+    kvm_arm_maintain_cache_coherency(addr, len, false, is_write);
+}
+
+void kvm_arch_cache_coherency_pre_run(void)
+{
+    kvm_arm_maintain_cache_coherency(0, 0, true, false);
+}
-- 
1.9.1

[RFC 2/4] target-arm/kvm: Flush data cache support

[Jérémy Fanguède]

Implement data cache maintenance coherency functions, by using
FLUSH_DCACHE_GPA ioctl. Introduce kvm_arm_maintain_cache_coherency()
for flushing the data cache if necessary, a very simple logic is
implemented to reduce number of flushes due to reads. Two wrapping
functions are exposed, for easier usage.

Signed-off-by: Jérémy Fanguède <j.fanguede@virtualopensystems.com>
---
 include/sysemu/kvm.h |  3 +++
 stubs/kvm.c          |  9 +++++++++
 target-arm/kvm.c     | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 63 insertions(+)

diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 197e6c0..986f365 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -451,4 +451,7 @@ int kvm_set_one_reg(CPUState *cs, uint64_t id, void *source);
  * Returns: 0 on success, or a negative errno on failure.
  */
 int kvm_get_one_reg(CPUState *cs, uint64_t id, void *target);
+
+void kvm_arch_cache_flush_needed(hwaddr addr, int len, bool is_write);
+void kvm_arch_cache_coherency_pre_run(void);
 #endif
diff --git a/stubs/kvm.c b/stubs/kvm.c
index e7c60b6..8ed5380 100644
--- a/stubs/kvm.c
+++ b/stubs/kvm.c
@@ -5,3 +5,12 @@ int kvm_arch_irqchip_create(KVMState *s)
 {
     return 0;
 }
+
+
+void kvm_arch_cache_flush_needed(hwaddr addr, int len, bool is_write)
+{
+}
+
+void kvm_arch_cache_coherency_pre_run(void)
+{
+}
diff --git a/target-arm/kvm.c b/target-arm/kvm.c
index fdd9ba3..548dae2 100644
--- a/target-arm/kvm.c
+++ b/target-arm/kvm.c
@@ -598,3 +598,54 @@ int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
 {
     return 0;
 }
+
+static void kvm_arm_flush_cache_addr(hwaddr addr, int len)
+{
+    int ret;
+    struct kvm_mem_addr mem_addr;
+    mem_addr.addr = addr;
+    mem_addr.len = len;
+    ret = kvm_vm_ioctl(kvm_state, KVM_FLUSH_DCACHE_GPA, &mem_addr);
+    if (ret) {
+        fprintf(stderr, "error: Failed to flush CPU caches %d\n", ret);
+    }
+}
+
+static void kvm_arm_maintain_cache_coherency(hwaddr addr, int len,
+                                             bool enter_guest, bool is_write)
+{
+    static hwaddr prev_addr;
+    static int prev_len;
+    hwaddr end_line, prev_end_line;
+
+    if (enter_guest) {
+        /* We will return to the guest after that, restore the default
+           configuration */
+        prev_addr = 0x0;
+        return;
+    }
+
+    /* Assume the minimal CPU cache line is 32 B */
+    end_line = (addr + len) & ~0x1f;
+    prev_end_line = (prev_addr + prev_len) & ~0x1f;
+
+    /* Don't flush two times in a row the same line"
+       Always flush on a write */
+    if ((prev_addr & ~0x1f) != (addr & ~0x1f)
+        || (prev_end_line < end_line)
+        || is_write) {
+        kvm_arm_flush_cache_addr(addr, len);
+        prev_addr = addr;
+        prev_len = len;
+    }
+}
+
+void kvm_arch_cache_flush_needed(hwaddr addr, int len, bool is_write)
+{
+    kvm_arm_maintain_cache_coherency(addr, len, false, is_write);
+}
+
+void kvm_arch_cache_coherency_pre_run(void)
+{
+    kvm_arm_maintain_cache_coherency(0, 0, true, false);
+}
-- 
1.9.1

[RFC 3/4] kvm-all: Pre-run cache coherency maintenance

[Jérémy Fanguède]

Inform the cache coherency maintenance of an exit from userspace.

Signed-off-by: Jérémy Fanguède <j.fanguede@virtualopensystems.com>
---
 kvm-all.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/kvm-all.c b/kvm-all.c
index 28f4589..c4b15b0 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -1802,6 +1802,7 @@ int kvm_cpu_exec(CPUState *cpu)
         }
 
         kvm_arch_pre_run(cpu, run);
+        kvm_arch_cache_coherency_pre_run();
         if (cpu->exit_request) {
             DPRINTF("interrupt exit requested\n");
             /*
-- 
1.9.1

[Qemu-devel] [RFC 3/4] kvm-all: Pre-run cache coherency maintenance

[Jérémy Fanguède]

Inform the cache coherency maintenance of an exit from userspace.

Signed-off-by: Jérémy Fanguède <j.fanguede@virtualopensystems.com>
---
 kvm-all.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/kvm-all.c b/kvm-all.c
index 28f4589..c4b15b0 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -1802,6 +1802,7 @@ int kvm_cpu_exec(CPUState *cpu)
         }
 
         kvm_arch_pre_run(cpu, run);
+        kvm_arch_cache_coherency_pre_run();
         if (cpu->exit_request) {
             DPRINTF("interrupt exit requested\n");
             /*
-- 
1.9.1

[RFC 3/4] kvm-all: Pre-run cache coherency maintenance

[Jérémy Fanguède]

Inform the cache coherency maintenance of an exit from userspace.

Signed-off-by: Jérémy Fanguède <j.fanguede@virtualopensystems.com>
---
 kvm-all.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/kvm-all.c b/kvm-all.c
index 28f4589..c4b15b0 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -1802,6 +1802,7 @@ int kvm_cpu_exec(CPUState *cpu)
         }
 
         kvm_arch_pre_run(cpu, run);
+        kvm_arch_cache_coherency_pre_run();
         if (cpu->exit_request) {
             DPRINTF("interrupt exit requested\n");
             /*
-- 
1.9.1

[Qemu-devel] [RFC 4/4] exec: Flush data cache when needed

[Jérémy Fanguède]

Flush the data cache when accesses occur in the guest ram memory.

Signed-off-by: Jérémy Fanguède <j.fanguede@virtualopensystems.com>
---
 exec.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/exec.c b/exec.c
index ae37b98..0f859a3 100644
--- a/exec.c
+++ b/exec.c
@@ -2372,6 +2372,9 @@ MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
                 ptr = qemu_get_ram_ptr(addr1);
                 memcpy(ptr, buf, l);
                 invalidate_and_set_dirty(addr1, l);
+                if (kvm_enabled()) {
+                    kvm_arch_cache_flush_needed(addr, l, is_write);
+                }
             }
         } else {
             if (!memory_access_is_direct(mr, is_write)) {
@@ -2408,6 +2411,9 @@ MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
             } else {
                 /* RAM case */
                 ptr = qemu_get_ram_ptr(mr->ram_addr + addr1);
+                if (kvm_enabled()) {
+                    kvm_arch_cache_flush_needed(addr, l, is_write);
+                }
                 memcpy(buf, ptr, l);
             }
         }
@@ -2646,6 +2652,14 @@ void *address_space_map(AddressSpace *as,
         return bounce.buffer;
     }
 
+    /* Need to be flushed only if we are reading */
+    if (!is_write) {
+        /* Don't flush if it's a cpu_physical_memory_map call */
+        if (kvm_enabled() && as != &address_space_memory) {
+            kvm_arch_cache_flush_needed(addr, l, is_write);
+        }
+    }
+
     base = xlat;
     raddr = memory_region_get_ram_addr(mr);
 
@@ -2679,6 +2693,7 @@ void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
     if (buffer != bounce.buffer) {
         MemoryRegion *mr;
         ram_addr_t addr1;
+        hwaddr base;
 
         mr = qemu_ram_addr_from_host(buffer, &addr1);
         assert(mr != NULL);
@@ -2688,6 +2703,10 @@ void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
         if (xen_enabled()) {
             xen_invalidate_map_cache_entry(buffer);
         }
+        if (kvm_enabled() && as != &address_space_memory) {
+            base = object_property_get_int(OBJECT(mr), "addr", NULL);
+            kvm_arch_cache_flush_needed(addr1 + base, access_len, is_write);
+        }
         memory_region_unref(mr);
         return;
     }
-- 
1.9.1

[RFC 4/4] exec: Flush data cache when needed

[Jérémy Fanguède]

Flush the data cache when accesses occur in the guest ram memory.

Signed-off-by: Jérémy Fanguède <j.fanguede@virtualopensystems.com>
---
 exec.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/exec.c b/exec.c
index ae37b98..0f859a3 100644
--- a/exec.c
+++ b/exec.c
@@ -2372,6 +2372,9 @@ MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
                 ptr = qemu_get_ram_ptr(addr1);
                 memcpy(ptr, buf, l);
                 invalidate_and_set_dirty(addr1, l);
+                if (kvm_enabled()) {
+                    kvm_arch_cache_flush_needed(addr, l, is_write);
+                }
             }
         } else {
             if (!memory_access_is_direct(mr, is_write)) {
@@ -2408,6 +2411,9 @@ MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs,
             } else {
                 /* RAM case */
                 ptr = qemu_get_ram_ptr(mr->ram_addr + addr1);
+                if (kvm_enabled()) {
+                    kvm_arch_cache_flush_needed(addr, l, is_write);
+                }
                 memcpy(buf, ptr, l);
             }
         }
@@ -2646,6 +2652,14 @@ void *address_space_map(AddressSpace *as,
         return bounce.buffer;
     }
 
+    /* Need to be flushed only if we are reading */
+    if (!is_write) {
+        /* Don't flush if it's a cpu_physical_memory_map call */
+        if (kvm_enabled() && as != &address_space_memory) {
+            kvm_arch_cache_flush_needed(addr, l, is_write);
+        }
+    }
+
     base = xlat;
     raddr = memory_region_get_ram_addr(mr);
 
@@ -2679,6 +2693,7 @@ void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
     if (buffer != bounce.buffer) {
         MemoryRegion *mr;
         ram_addr_t addr1;
+        hwaddr base;
 
         mr = qemu_ram_addr_from_host(buffer, &addr1);
         assert(mr != NULL);
@@ -2688,6 +2703,10 @@ void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
         if (xen_enabled()) {
             xen_invalidate_map_cache_entry(buffer);
         }
+        if (kvm_enabled() && as != &address_space_memory) {
+            base = object_property_get_int(OBJECT(mr), "addr", NULL);
+            kvm_arch_cache_flush_needed(addr1 + base, access_len, is_write);
+        }
         memory_region_unref(mr);
         return;
     }
-- 
1.9.1

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