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From: Leon Alrae <leon.alrae@imgtec.com>
To: qemu-devel@nongnu.org
Cc: matthew.fortune@imgtec.com, aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH v2 2/5] hw/mips: Do not clear BEV for MIPS malta kernel load
Date: Tue, 12 May 2015 23:01:38 +0100	[thread overview]
Message-ID: <1431468101-5419-3-git-send-email-leon.alrae@imgtec.com> (raw)
In-Reply-To: <1431468101-5419-1-git-send-email-leon.alrae@imgtec.com>

From: Matthew Fortune <matthew.fortune@imgtec.com>

The BEV flag controls whether the boot exception vector is still
in place when starting a kernel.  When cleared the exception vector
at EBASE (or hard coded address of 0x80000000) is used instead.

The early stages of the linux kernel would benefit from BEV still
being set to ensure any faults get handled by the boot rom exception
handlers.  This is a moot point for system qemu as there aren't really
any BEV handlers, but there are other good reasons to change this...

The UHI (semi-hosting interface) defines special behaviours depending
on whether an application starts in an environment with BEV set or
cleared. When BEV is set then UHI assumes that a bootloader is
relatively dumb and has no advanced exception handling logic.
However, when BEV is cleared then UHI assumes that the bootloader
has the ability to handle UHI exceptions with its exception handlers
and will unwind and forward UHI SYSCALL exceptions to the exception
vector that was installed prior to running the application.

Signed-off-by: Matthew Fortune <matthew.fortune@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 hw/mips/mips_malta.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index d3f2cd3..e1b2e20 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -885,7 +885,7 @@ static void main_cpu_reset(void *opaque)
        read only location. The kernel location and the arguments table
        location does not change. */
     if (loaderparams.kernel_filename) {
-        env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
+        env->CP0_Status &= ~(1 << CP0St_ERL);
     }
 
     malta_mips_config(cpu);

  parent reply	other threads:[~2015-05-12 22:02 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-12 22:01 [Qemu-devel] [PATCH v2 0/5] target-mips: add UHI semihosting support Leon Alrae
2015-05-12 22:01 ` [Qemu-devel] [PATCH v2 1/5] include/softmmu-semi.h: Make semihosting support 64-bit clean Leon Alrae
2015-05-12 22:01 ` Leon Alrae [this message]
2015-05-12 22:01 ` [Qemu-devel] [PATCH v2 3/5] target-mips: remove identical code in different branch Leon Alrae
2015-05-12 22:01 ` [Qemu-devel] [PATCH v2 4/5] target-mips: add Unified Hosting Interface (UHI) support Leon Alrae
2015-05-12 22:01 ` [Qemu-devel] [PATCH v2 5/5] target-mips: convert host to MIPS errno values when required Leon Alrae

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