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From: Leon Alrae <leon.alrae@imgtec.com>
To: qemu-devel@nongnu.org
Cc: matthew.fortune@imgtec.com, aurelien@aurel32.net
Subject: [Qemu-devel] [PATCH v2 3/5] target-mips: remove identical code in different branch
Date: Tue, 12 May 2015 23:01:39 +0100	[thread overview]
Message-ID: <1431468101-5419-4-git-send-email-leon.alrae@imgtec.com> (raw)
In-Reply-To: <1431468101-5419-1-git-send-email-leon.alrae@imgtec.com>

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
 target-mips/translate.c | 25 ++++---------------------
 1 file changed, 4 insertions(+), 21 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index a41fc98..94f17a9 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -11800,11 +11800,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
              *      when in debug mode...
              */
             check_insn(ctx, ISA_MIPS32);
-            if (!(ctx->hflags & MIPS_HFLAG_DM)) {
-                generate_exception(ctx, EXCP_DBp);
-            } else {
-                generate_exception(ctx, EXCP_DBp);
-            }
+            generate_exception(ctx, EXCP_DBp);
             break;
         case RR_SLT:
             gen_slt(ctx, OPC_SLT, 24, rx, ry);
@@ -12655,11 +12651,7 @@ static void gen_pool16c_insn(DisasContext *ctx)
          *      when in debug mode...
          */
         check_insn(ctx, ISA_MIPS32);
-        if (!(ctx->hflags & MIPS_HFLAG_DM)) {
-            generate_exception(ctx, EXCP_DBp);
-        } else {
-            generate_exception(ctx, EXCP_DBp);
-        }
+        generate_exception(ctx, EXCP_DBp);
         break;
     case JRADDIUSP + 0:
     case JRADDIUSP + 1:
@@ -13024,11 +13016,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
             break;
         case SDBBP:
             check_insn(ctx, ISA_MIPS32);
-            if (!(ctx->hflags & MIPS_HFLAG_DM)) {
-                generate_exception(ctx, EXCP_DBp);
-            } else {
-                generate_exception(ctx, EXCP_DBp);
-            }
+            generate_exception(ctx, EXCP_DBp);
             break;
         default:
             goto pool32axf_invalid;
@@ -16797,12 +16785,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
          *      when in debug mode...
          */
         check_insn(ctx, ISA_MIPS32);
-        if (!(ctx->hflags & MIPS_HFLAG_DM)) {
-            generate_exception(ctx, EXCP_DBp);
-        } else {
-            generate_exception(ctx, EXCP_DBp);
-        }
-        /* Treat as NOP. */
+        generate_exception(ctx, EXCP_DBp);
         break;
 #if defined(TARGET_MIPS64)
     case OPC_DCLO:

  parent reply	other threads:[~2015-05-12 22:03 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-12 22:01 [Qemu-devel] [PATCH v2 0/5] target-mips: add UHI semihosting support Leon Alrae
2015-05-12 22:01 ` [Qemu-devel] [PATCH v2 1/5] include/softmmu-semi.h: Make semihosting support 64-bit clean Leon Alrae
2015-05-12 22:01 ` [Qemu-devel] [PATCH v2 2/5] hw/mips: Do not clear BEV for MIPS malta kernel load Leon Alrae
2015-05-12 22:01 ` Leon Alrae [this message]
2015-05-12 22:01 ` [Qemu-devel] [PATCH v2 4/5] target-mips: add Unified Hosting Interface (UHI) support Leon Alrae
2015-05-12 22:01 ` [Qemu-devel] [PATCH v2 5/5] target-mips: convert host to MIPS errno values when required Leon Alrae

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