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* [PATCH 00/12] Tessellation support for nvc0
@ 2015-05-17  5:07 Ilia Mirkin
  2015-05-17  5:07 ` [PATCH 04/12] nvc0: TESSCOORD comes in as a sysval, not an input Ilia Mirkin
                   ` (3 more replies)
  0 siblings, 4 replies; 15+ messages in thread
From: Ilia Mirkin @ 2015-05-17  5:07 UTC (permalink / raw)
  To: mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

This is enough to enable tessellation support on nvc0. It seems to
work a lot better on my GF108 than GK208. I suspect that there's some
sort of scheduling shenanigans that need to be adjusted for
kepler+. Or perhaps some shader header things.

Even with the GF108, I still get occasional blue triangles in Heaven,
but I get a *ton* of them on the GK208 -- seemingly the same issue,
but it's much worse on there.

Also there's about a 100% chance that gl_PrimitiveID doesn't work.

In any case, I plan on pushing this semi-soon unless there are any
loud objections. I don't think it's going to do too much good sitting
in my tree, or too much evil sitting upstream while core + st/mesa are
worked out.

Ilia Mirkin (12):
  nvc0: preliminary tess support
  nvc0: add support for setting patch vertices at draw time
  nvc0: add handling for set_tess_state callback
  nvc0: TESSCOORD comes in as a sysval, not an input
  nvc0/ir: mark varyings as per-patch based on semantic name
  nv50/ir: populate info structure based on new tess properties
  nv50/ir: set perPatch flag on load/stores to per-patch varyings
  nv50/ir: add support for reading outputs in tess control shaders
  nvc0/ir: patch vertex count is stored in the upper bits
  nvc0/ir: handle loads from outputs in control shaders
  nvc0/ir: allow tess eval output loads to be CSE'd
  nv50/ir: cleanup private enums that have graduated to gallium

 src/gallium/drivers/nouveau/codegen/nv50_ir.cpp    |  4 +-
 .../drivers/nouveau/codegen/nv50_ir_driver.h       | 12 ----
 .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp  | 56 +++++++++++++++--
 .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp      |  7 +++
 .../drivers/nouveau/codegen/nv50_ir_peephole.cpp   |  2 +
 src/gallium/drivers/nouveau/nvc0/nvc0_context.h    |  8 ++-
 src/gallium/drivers/nouveau/nvc0/nvc0_program.c    | 56 +++++++----------
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c     |  7 +--
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.h     |  1 +
 .../drivers/nouveau/nvc0/nvc0_shader_state.c       |  3 -
 src/gallium/drivers/nouveau/nvc0/nvc0_state.c      | 71 ++++++++++++++++++++++
 .../drivers/nouveau/nvc0/nvc0_state_validate.c     | 11 ++++
 src/gallium/drivers/nouveau/nvc0/nvc0_tex.c        | 34 +++++------
 src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c        |  9 ++-
 .../drivers/nouveau/nvc0/nvc0_vbo_translate.c      |  3 +-
 15 files changed, 200 insertions(+), 84 deletions(-)

-- 
2.3.6

_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

^ permalink raw reply	[flat|nested] 15+ messages in thread
* [PATCH 01/12] nvc0: preliminary tess support
       [not found] ` <1431839235-10256-1-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
@ 2015-05-17  5:07   ` Ilia Mirkin
  2015-05-17  5:07   ` [PATCH 02/12] nvc0: add support for setting patch vertices at draw time Ilia Mirkin
                     ` (8 subsequent siblings)
  9 siblings, 0 replies; 15+ messages in thread
From: Ilia Mirkin @ 2015-05-17  5:07 UTC (permalink / raw)
  To: mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

Uncomment the various functionality that was already there and add in
obvious missing bits that parallel vp/gp/fp functionality.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
---
 src/gallium/drivers/nouveau/codegen/nv50_ir.cpp    |  4 +-
 .../drivers/nouveau/codegen/nv50_ir_driver.h       |  5 ---
 .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp  |  2 +
 src/gallium/drivers/nouveau/nvc0/nvc0_context.h    |  4 +-
 src/gallium/drivers/nouveau/nvc0/nvc0_program.c    | 29 +++++-------
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c     |  6 +--
 src/gallium/drivers/nouveau/nvc0/nvc0_state.c      | 52 ++++++++++++++++++++++
 src/gallium/drivers/nouveau/nvc0/nvc0_tex.c        | 34 +++++++-------
 src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c        |  3 +-
 .../drivers/nouveau/nvc0/nvc0_vbo_translate.c      |  3 +-
 10 files changed, 87 insertions(+), 55 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
index ca3c806..cce6055 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
@@ -1153,8 +1153,8 @@ nv50_ir_generate_code(struct nv50_ir_prog_info *info)
 
    switch (info->type) {
    PROG_TYPE_CASE(VERTEX, VERTEX);
-// PROG_TYPE_CASE(HULL, TESSELLATION_CONTROL);
-// PROG_TYPE_CASE(DOMAIN, TESSELLATION_EVAL);
+   PROG_TYPE_CASE(TESS_CTRL, TESSELLATION_CONTROL);
+   PROG_TYPE_CASE(TESS_EVAL, TESSELLATION_EVAL);
    PROG_TYPE_CASE(GEOMETRY, GEOMETRY);
    PROG_TYPE_CASE(FRAGMENT, FRAGMENT);
    PROG_TYPE_CASE(COMPUTE, COMPUTE);
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index dba56bf..5203abd 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -74,11 +74,6 @@ struct nv50_ir_varying
 #define NV50_SEMANTIC_TESSCOORD     (TGSI_SEMANTIC_COUNT + 8)
 #define NV50_SEMANTIC_COUNT         (TGSI_SEMANTIC_COUNT + 10)
 
-#define NV50_TESS_PART_FRACT_ODD  0
-#define NV50_TESS_PART_FRACT_EVEN 1
-#define NV50_TESS_PART_POW2       2
-#define NV50_TESS_PART_INTEGER    3
-
 #define NV50_PRIM_PATCHES PIPE_PRIM_MAX
 
 struct nv50_ir_prog_symbol
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 6f7f397..db14587 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -372,6 +372,8 @@ static nv50_ir::SVSemantic translateSysVal(uint sysval)
    case TGSI_SEMANTIC_SAMPLEPOS:  return nv50_ir::SV_SAMPLE_POS;
    case TGSI_SEMANTIC_SAMPLEMASK: return nv50_ir::SV_SAMPLE_MASK;
    case TGSI_SEMANTIC_INVOCATIONID: return nv50_ir::SV_INVOCATION_ID;
+   case TGSI_SEMANTIC_TESSCOORD:  return nv50_ir::SV_TESS_COORD;
+   case TGSI_SEMANTIC_VERTICESIN: return nv50_ir::SV_VERTEX_COUNT;
    default:
       assert(0);
       return nv50_ir::SV_CLOCK;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
index a8d7593..3583a43 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
@@ -195,8 +195,8 @@ nvc0_shader_stage(unsigned pipe)
 {
    switch (pipe) {
    case PIPE_SHADER_VERTEX: return 0;
-/* case PIPE_SHADER_TESSELLATION_CONTROL: return 1; */
-/* case PIPE_SHADER_TESSELLATION_EVALUATION: return 2; */
+   case PIPE_SHADER_TESS_CTRL: return 1;
+   case PIPE_SHADER_TESS_EVAL: return 2;
    case PIPE_SHADER_GEOMETRY: return 3;
    case PIPE_SHADER_FRAGMENT: return 4;
    case PIPE_SHADER_COMPUTE: return 5;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index 5589695..b4ba59a 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -34,7 +34,8 @@ static uint32_t
 nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase)
 {
    switch (sn) {
-   case NV50_SEMANTIC_TESSFACTOR:   return 0x000 + si * 0x4;
+   case TGSI_SEMANTIC_TESSOUTER:    return 0x000 + si * 0x4;
+   case TGSI_SEMANTIC_TESSINNER:    return 0x010 + si * 0x4;
    case TGSI_SEMANTIC_PRIMID:       return 0x060;
    case TGSI_SEMANTIC_LAYER:        return 0x064;
    case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
@@ -48,7 +49,7 @@ nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase)
    case TGSI_SEMANTIC_CLIPDIST:     return 0x2c0 + si * 0x10;
    case TGSI_SEMANTIC_CLIPVERTEX:   return 0x270;
    case TGSI_SEMANTIC_PCOORD:       return 0x2e0;
-   case NV50_SEMANTIC_TESSCOORD:    return 0x2f0;
+   case TGSI_SEMANTIC_TESSCOORD:    return 0x2f0;
    case TGSI_SEMANTIC_INSTANCEID:   return 0x2f8;
    case TGSI_SEMANTIC_VERTEXID:     return 0x2fc;
    case TGSI_SEMANTIC_TEXCOORD:     return 0x300 + si * 0x10;
@@ -63,7 +64,8 @@ static uint32_t
 nvc0_shader_output_address(unsigned sn, unsigned si, unsigned ubase)
 {
    switch (sn) {
-   case NV50_SEMANTIC_TESSFACTOR:    return 0x000 + si * 0x4;
+   case TGSI_SEMANTIC_TESSOUTER:     return 0x000 + si * 0x4;
+   case TGSI_SEMANTIC_TESSINNER:     return 0x010 + si * 0x4;
    case TGSI_SEMANTIC_PRIMID:        return 0x060;
    case TGSI_SEMANTIC_LAYER:         return 0x064;
    case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
@@ -277,7 +279,6 @@ nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
    return nvc0_vtgp_gen_header(vp, info);
 }
 
-#if defined(PIPE_SHADER_HULL) || defined(PIPE_SHADER_DOMAIN)
 static void
 nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
 {
@@ -305,14 +306,13 @@ nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
       tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED;
 
    switch (info->prop.tp.partitioning) {
-   case PIPE_TESS_PART_INTEGER:
-   case PIPE_TESS_PART_POW2:
+   case PIPE_TESS_SPACING_EQUAL:
       tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_EQUAL;
       break;
-   case PIPE_TESS_PART_FRACT_ODD:
+   case PIPE_TESS_SPACING_FRACTIONAL_ODD:
       tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_ODD;
       break;
-   case PIPE_TESS_PART_FRACT_EVEN:
+   case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
       tp->tp.tess_mode |= NVC0_3D_TESS_MODE_SPACING_FRACTIONAL_EVEN;
       break;
    default:
@@ -320,9 +320,7 @@ nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
       break;
    }
 }
-#endif
 
-#ifdef PIPE_SHADER_HULL
 static int
 nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
 {
@@ -346,9 +344,7 @@ nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
 
    return 0;
 }
-#endif
 
-#ifdef PIPE_SHADER_DOMAIN
 static int
 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
 {
@@ -365,7 +361,6 @@ nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
 
    return 0;
 }
-#endif
 
 static int
 nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info)
@@ -598,16 +593,12 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset)
    case PIPE_SHADER_VERTEX:
       ret = nvc0_vp_gen_header(prog, info);
       break;
-#ifdef PIPE_SHADER_HULL
-   case PIPE_SHADER_HULL:
+   case PIPE_SHADER_TESS_CTRL:
       ret = nvc0_tcp_gen_header(prog, info);
       break;
-#endif
-#ifdef PIPE_SHADER_DOMAIN
-   case PIPE_SHADER_DOMAIN:
+   case PIPE_SHADER_TESS_EVAL:
       ret = nvc0_tep_gen_header(prog, info);
       break;
-#endif
    case PIPE_SHADER_GEOMETRY:
       ret = nvc0_gp_gen_header(prog, info);
       break;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 1ca997a..ff552ae 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -226,10 +226,8 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 
    switch (shader) {
    case PIPE_SHADER_VERTEX:
-      /*
-   case PIPE_SHADER_TESSELLATION_CONTROL:
-   case PIPE_SHADER_TESSELLATION_EVALUATION:
-      */
+   case PIPE_SHADER_TESS_CTRL:
+   case PIPE_SHADER_TESS_EVAL:
    case PIPE_SHADER_GEOMETRY:
    case PIPE_SHADER_FRAGMENT:
       break;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
index 63c3c52..83ef021 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
@@ -508,6 +508,14 @@ nvc0_bind_sampler_states(struct pipe_context *pipe, unsigned shader,
       assert(start == 0);
       nvc0_stage_sampler_states_bind(nvc0_context(pipe), 0, nr, s);
       break;
+   case PIPE_SHADER_TESS_CTRL:
+      assert(start == 0);
+      nvc0_stage_sampler_states_bind(nvc0_context(pipe), 1, nr, s);
+      break;
+   case PIPE_SHADER_TESS_EVAL:
+      assert(start == 0);
+      nvc0_stage_sampler_states_bind(nvc0_context(pipe), 2, nr, s);
+      break;
    case PIPE_SHADER_GEOMETRY:
       assert(start == 0);
       nvc0_stage_sampler_states_bind(nvc0_context(pipe), 3, nr, s);
@@ -633,6 +641,12 @@ nvc0_set_sampler_views(struct pipe_context *pipe, unsigned shader,
    case PIPE_SHADER_VERTEX:
       nvc0_stage_set_sampler_views(nvc0_context(pipe), 0, nr, views);
       break;
+   case PIPE_SHADER_TESS_CTRL:
+      nvc0_stage_set_sampler_views(nvc0_context(pipe), 1, nr, views);
+      break;
+   case PIPE_SHADER_TESS_EVAL:
+      nvc0_stage_set_sampler_views(nvc0_context(pipe), 2, nr, views);
+      break;
    case PIPE_SHADER_GEOMETRY:
       nvc0_stage_set_sampler_views(nvc0_context(pipe), 3, nr, views);
       break;
@@ -734,6 +748,38 @@ nvc0_gp_state_bind(struct pipe_context *pipe, void *hwcso)
 }
 
 static void *
+nvc0_tcp_state_create(struct pipe_context *pipe,
+                     const struct pipe_shader_state *cso)
+{
+   return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_CTRL);
+}
+
+static void
+nvc0_tcp_state_bind(struct pipe_context *pipe, void *hwcso)
+{
+    struct nvc0_context *nvc0 = nvc0_context(pipe);
+
+    nvc0->tctlprog = hwcso;
+    nvc0->dirty |= NVC0_NEW_TCTLPROG;
+}
+
+static void *
+nvc0_tep_state_create(struct pipe_context *pipe,
+                     const struct pipe_shader_state *cso)
+{
+   return nvc0_sp_state_create(pipe, cso, PIPE_SHADER_TESS_EVAL);
+}
+
+static void
+nvc0_tep_state_bind(struct pipe_context *pipe, void *hwcso)
+{
+    struct nvc0_context *nvc0 = nvc0_context(pipe);
+
+    nvc0->tevlprog = hwcso;
+    nvc0->dirty |= NVC0_NEW_TEVLPROG;
+}
+
+static void *
 nvc0_cp_state_create(struct pipe_context *pipe,
                      const struct pipe_compute_state *cso)
 {
@@ -1218,12 +1264,18 @@ nvc0_init_state_functions(struct nvc0_context *nvc0)
    pipe->create_vs_state = nvc0_vp_state_create;
    pipe->create_fs_state = nvc0_fp_state_create;
    pipe->create_gs_state = nvc0_gp_state_create;
+   pipe->create_tcs_state = nvc0_tcp_state_create;
+   pipe->create_tes_state = nvc0_tep_state_create;
    pipe->bind_vs_state = nvc0_vp_state_bind;
    pipe->bind_fs_state = nvc0_fp_state_bind;
    pipe->bind_gs_state = nvc0_gp_state_bind;
+   pipe->bind_tcs_state = nvc0_tcp_state_bind;
+   pipe->bind_tes_state = nvc0_tep_state_bind;
    pipe->delete_vs_state = nvc0_sp_state_delete;
    pipe->delete_fs_state = nvc0_sp_state_delete;
    pipe->delete_gs_state = nvc0_sp_state_delete;
+   pipe->delete_tcs_state = nvc0_sp_state_delete;
+   pipe->delete_tes_state = nvc0_sp_state_delete;
 
    pipe->create_compute_state = nvc0_cp_state_create;
    pipe->bind_compute_state = nvc0_cp_state_bind;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
index 457f27c..7d68acd 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
@@ -356,16 +356,14 @@ nve4_validate_tic(struct nvc0_context *nvc0, unsigned s)
 
 void nvc0_validate_textures(struct nvc0_context *nvc0)
 {
-   boolean need_flush;
+   boolean need_flush = FALSE;
+   int i;
 
-   if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS) {
-      need_flush  = nve4_validate_tic(nvc0, 0);
-      need_flush |= nve4_validate_tic(nvc0, 3);
-      need_flush |= nve4_validate_tic(nvc0, 4);
-   } else {
-      need_flush  = nvc0_validate_tic(nvc0, 0);
-      need_flush |= nvc0_validate_tic(nvc0, 3);
-      need_flush |= nvc0_validate_tic(nvc0, 4);
+   for (i = 0; i < 5; i++) {
+      if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS)
+         need_flush |= nve4_validate_tic(nvc0, i);
+      else
+         need_flush |= nvc0_validate_tic(nvc0, i);
    }
 
    if (need_flush) {
@@ -466,16 +464,14 @@ nve4_validate_tsc(struct nvc0_context *nvc0, int s)
 
 void nvc0_validate_samplers(struct nvc0_context *nvc0)
 {
-   boolean need_flush;
-
-   if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS) {
-      need_flush  = nve4_validate_tsc(nvc0, 0);
-      need_flush |= nve4_validate_tsc(nvc0, 3);
-      need_flush |= nve4_validate_tsc(nvc0, 4);
-   } else {
-      need_flush  = nvc0_validate_tsc(nvc0, 0);
-      need_flush |= nvc0_validate_tsc(nvc0, 3);
-      need_flush |= nvc0_validate_tsc(nvc0, 4);
+   boolean need_flush = false;
+   int i;
+
+   for (i = 0; i < 5; i++) {
+      if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS)
+         need_flush |= nve4_validate_tsc(nvc0, i);
+      else
+         need_flush |= nvc0_validate_tsc(nvc0, i);
    }
 
    if (need_flush) {
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
index 657b8c0..f8e2759 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
@@ -547,8 +547,7 @@ nvc0_prim_gl(unsigned prim)
    NVC0_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
    NVC0_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
    NVC0_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
-   /*
-   NVC0_PRIM_GL_CASE(PATCHES); */
+   NVC0_PRIM_GL_CASE(PATCHES);
    default:
       return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
    }
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo_translate.c b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo_translate.c
index f180087..aac92e4 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo_translate.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo_translate.c
@@ -427,8 +427,7 @@ nvc0_prim_gl(unsigned prim)
    NVC0_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
    NVC0_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
    NVC0_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
-   /*
-   NVC0_PRIM_GL_CASE(PATCHES); */
+   NVC0_PRIM_GL_CASE(PATCHES);
    default:
       return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
    }
-- 
2.3.6

_______________________________________________
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Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH 02/12] nvc0: add support for setting patch vertices at draw time
       [not found] ` <1431839235-10256-1-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
  2015-05-17  5:07   ` [PATCH 01/12] nvc0: preliminary tess support Ilia Mirkin
@ 2015-05-17  5:07   ` Ilia Mirkin
  2015-05-17  5:18     ` Ilia Mirkin
  2015-05-17  5:07   ` [PATCH 03/12] nvc0: add handling for set_tess_state callback Ilia Mirkin
                     ` (7 subsequent siblings)
  9 siblings, 1 reply; 15+ messages in thread
From: Ilia Mirkin @ 2015-05-17  5:07 UTC (permalink / raw)
  To: mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
---
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c       | 1 +
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.h       | 1 +
 src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c | 3 ---
 src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c          | 6 ++++++
 4 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index ff552ae..4bc41f2 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -1004,6 +1004,7 @@ nvc0_screen_create(struct nouveau_device *dev)
    PUSH_DATA (push, 0x20);
    BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
    PUSH_DATA (push, 0x00);
+   screen->save_state.patch_vertices = 3;
 
    BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
    PUSH_DATA (push, 0);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
index ef2bd43..c79211e 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
@@ -38,6 +38,7 @@ struct nvc0_graph_state {
    uint32_t constant_elts;
    int32_t index_bias;
    uint16_t scissor;
+   uint8_t patch_vertices;
    uint8_t vbo_mode; /* 0 = normal, 1 = translate, 3 = translate, forced */
    uint8_t num_vtxbufs;
    uint8_t num_vtxelts;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c b/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
index 516b33b..32f4519 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
@@ -147,9 +147,6 @@ nvc0_tctlprog_validate(struct nvc0_context *nvc0)
       PUSH_DATA (push, tp->code_base);
       BEGIN_NVC0(push, NVC0_3D(SP_GPR_ALLOC(2)), 1);
       PUSH_DATA (push, tp->num_gprs);
-
-      if (tp->tp.input_patch_size <= 32)
-         IMMED_NVC0(push, NVC0_3D(PATCH_VERTICES), tp->tp.input_patch_size);
    } else {
       BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
       PUSH_DATA (push, 0x20);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
index f8e2759..fb7b073 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
@@ -887,6 +887,12 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
       }
    }
 
+   if (info->mode == PIPE_PRIM_PATCHES &&
+       nvc0->state.patch_vertices != info->vertices_per_patch) {
+      IMMED_NVC0(push, NVC0_3D(PATCH_VERTICES), nvc0->state.patch_vertices);
+      nvc0->state.patch_vertices = info->vertices_per_patch;
+   }
+
    /* 8 as minimum to avoid immediate double validation of new buffers */
    nvc0_state_validate(nvc0, ~0, 8);
 
-- 
2.3.6

_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH 03/12] nvc0: add handling for set_tess_state callback
       [not found] ` <1431839235-10256-1-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
  2015-05-17  5:07   ` [PATCH 01/12] nvc0: preliminary tess support Ilia Mirkin
  2015-05-17  5:07   ` [PATCH 02/12] nvc0: add support for setting patch vertices at draw time Ilia Mirkin
@ 2015-05-17  5:07   ` Ilia Mirkin
  2015-05-17  5:07   ` [PATCH 05/12] nvc0/ir: mark varyings as per-patch based on semantic name Ilia Mirkin
                     ` (6 subsequent siblings)
  9 siblings, 0 replies; 15+ messages in thread
From: Ilia Mirkin @ 2015-05-17  5:07 UTC (permalink / raw)
  To: mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
---
 src/gallium/drivers/nouveau/nvc0/nvc0_context.h       |  4 ++++
 src/gallium/drivers/nouveau/nvc0/nvc0_state.c         | 19 +++++++++++++++++++
 .../drivers/nouveau/nvc0/nvc0_state_validate.c        | 11 +++++++++++
 3 files changed, 34 insertions(+)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
index 3583a43..55e6427 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
@@ -54,6 +54,7 @@
 #define NVC0_NEW_IDXBUF       (1 << 22)
 #define NVC0_NEW_SURFACES     (1 << 23)
 #define NVC0_NEW_MIN_SAMPLES  (1 << 24)
+#define NVC0_NEW_TESSFACTOR   (1 << 25)
 
 #define NVC0_NEW_CP_PROGRAM   (1 << 0)
 #define NVC0_NEW_CP_SURFACES  (1 << 1)
@@ -164,6 +165,9 @@ struct nvc0_context {
    unsigned sample_mask;
    unsigned min_samples;
 
+   float default_tess_outer[4];
+   float default_tess_inner[2];
+
    boolean vbo_push_hint;
 
    uint8_t tfbbuf_dirty;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
index 83ef021..a5364ef 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
@@ -980,6 +980,18 @@ nvc0_set_viewport_states(struct pipe_context *pipe,
 }
 
 static void
+nvc0_set_tess_state(struct pipe_context *pipe,
+                    float default_tess_outer[4],
+                    float default_tess_inner[2])
+{
+   struct nvc0_context *nvc0 = nvc0_context(pipe);
+
+   memcpy(nvc0->default_tess_outer, default_tess_outer, 4 * sizeof(float));
+   memcpy(nvc0->default_tess_inner, default_tess_inner, 2 * sizeof(float));
+   nvc0->dirty |= NVC0_NEW_TESSFACTOR;
+}
+
+static void
 nvc0_set_vertex_buffers(struct pipe_context *pipe,
                         unsigned start_slot, unsigned count,
                         const struct pipe_vertex_buffer *vb)
@@ -1291,6 +1303,7 @@ nvc0_init_state_functions(struct nvc0_context *nvc0)
    pipe->set_polygon_stipple = nvc0_set_polygon_stipple;
    pipe->set_scissor_states = nvc0_set_scissor_states;
    pipe->set_viewport_states = nvc0_set_viewport_states;
+   pipe->set_tess_state = nvc0_set_tess_state;
 
    pipe->create_vertex_elements_state = nvc0_vertex_state_create;
    pipe->delete_vertex_elements_state = nvc0_vertex_state_delete;
@@ -1309,4 +1322,10 @@ nvc0_init_state_functions(struct nvc0_context *nvc0)
 
    nvc0->sample_mask = ~0;
    nvc0->min_samples = 1;
+   nvc0->default_tess_outer[0] =
+   nvc0->default_tess_outer[1] =
+   nvc0->default_tess_outer[2] =
+   nvc0->default_tess_outer[3] = 1.0;
+   nvc0->default_tess_inner[0] =
+   nvc0->default_tess_inner[1] = 1.0;
 }
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c b/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
index d3ad81d..410c3ef 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c
@@ -536,6 +536,16 @@ nvc0_validate_derived_1(struct nvc0_context *nvc0)
 }
 
 static void
+nvc0_validate_tess_state(struct nvc0_context *nvc0)
+{
+   struct nouveau_pushbuf *push = nvc0->base.pushbuf;
+
+   BEGIN_NVC0(push, NVC0_3D(TESS_LEVEL_OUTER(0)), 6);
+   PUSH_DATAp(push, nvc0->default_tess_outer, 4);
+   PUSH_DATAp(push, nvc0->default_tess_inner, 2);
+}
+
+static void
 nvc0_switch_pipe_context(struct nvc0_context *ctx_to)
 {
    struct nvc0_context *ctx_from = ctx_to->screen->cur_ctx;
@@ -593,6 +603,7 @@ static struct state_validate {
     { nvc0_vertprog_validate,      NVC0_NEW_VERTPROG },
     { nvc0_tctlprog_validate,      NVC0_NEW_TCTLPROG },
     { nvc0_tevlprog_validate,      NVC0_NEW_TEVLPROG },
+    { nvc0_validate_tess_state,    NVC0_NEW_TESSFACTOR },
     { nvc0_gmtyprog_validate,      NVC0_NEW_GMTYPROG },
     { nvc0_fragprog_validate,      NVC0_NEW_FRAGPROG },
     { nvc0_validate_derived_1,     NVC0_NEW_FRAGPROG | NVC0_NEW_ZSA |
-- 
2.3.6

_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH 04/12] nvc0: TESSCOORD comes in as a sysval, not an input
  2015-05-17  5:07 [PATCH 00/12] Tessellation support for nvc0 Ilia Mirkin
@ 2015-05-17  5:07 ` Ilia Mirkin
       [not found] ` <1431839235-10256-1-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 15+ messages in thread
From: Ilia Mirkin @ 2015-05-17  5:07 UTC (permalink / raw)
  To: mesa-dev; +Cc: nouveau

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
---
 src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h |  2 --
 src/gallium/drivers/nouveau/nvc0/nvc0_program.c      | 19 ++++++++++---------
 2 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index 5203abd..0c8e3cb 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -70,8 +70,6 @@ struct nv50_ir_varying
 #endif
 
 #define NV50_SEMANTIC_CLIPDISTANCE  (TGSI_SEMANTIC_COUNT + 0)
-#define NV50_SEMANTIC_TESSFACTOR    (TGSI_SEMANTIC_COUNT + 7)
-#define NV50_SEMANTIC_TESSCOORD     (TGSI_SEMANTIC_COUNT + 8)
 #define NV50_SEMANTIC_COUNT         (TGSI_SEMANTIC_COUNT + 10)
 
 #define NV50_PRIM_PATCHES PIPE_PRIM_MAX
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index b4ba59a..cd8c736 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -123,9 +123,6 @@ nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
       if (info->in[i].patch && offset >= 0x20)
          offset = 0x20 + info->in[i].si * 0x10;
 
-      if (info->in[i].sn == NV50_SEMANTIC_TESSCOORD)
-         info->in[i].mask &= 3;
-
       for (c = 0; c < 4; ++c)
          info->in[i].slot[c] = (offset + c * 0x4) / 4;
    }
@@ -218,12 +215,8 @@ nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
          continue;
       for (c = 0; c < 4; ++c) {
          a = info->in[i].slot[c];
-         if (info->in[i].mask & (1 << c)) {
-            if (info->in[i].sn != NV50_SEMANTIC_TESSCOORD)
-               vp->hdr[5 + a / 32] |= 1 << (a % 32);
-            else
-               nvc0_vtgp_hdr_update_oread(vp, info->in[i].slot[c]);
-         }
+         if (info->in[i].mask & (1 << c))
+            vp->hdr[5 + a / 32] |= 1 << (a % 32);
       }
    }
 
@@ -252,6 +245,14 @@ nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
       case TGSI_SEMANTIC_VERTEXID:
          vp->hdr[10] |= 1 << 31;
          break;
+      case TGSI_SEMANTIC_TESSCOORD:
+         /* We don't have the mask, nor the slots populated. While this could
+          * be achieved, the vast majority of the time if either of the coords
+          * are read, then both will be read.
+          */
+         nvc0_vtgp_hdr_update_oread(vp, 0x2f0 / 4);
+         nvc0_vtgp_hdr_update_oread(vp, 0x2f4 / 4);
+         break;
       default:
          break;
       }
-- 
2.3.6

_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev

^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH 05/12] nvc0/ir: mark varyings as per-patch based on semantic name
       [not found] ` <1431839235-10256-1-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
                     ` (2 preceding siblings ...)
  2015-05-17  5:07   ` [PATCH 03/12] nvc0: add handling for set_tess_state callback Ilia Mirkin
@ 2015-05-17  5:07   ` Ilia Mirkin
  2015-05-17  5:07   ` [PATCH 08/12] nv50/ir: add support for reading outputs in tess control shaders Ilia Mirkin
                     ` (5 subsequent siblings)
  9 siblings, 0 replies; 15+ messages in thread
From: Ilia Mirkin @ 2015-05-17  5:07 UTC (permalink / raw)
  To: mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

Also add proper handling for PATCH semantics

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
---
 src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 14 ++++++++++++++
 src/gallium/drivers/nouveau/nvc0/nvc0_program.c           |  6 ++----
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index db14587..f523318 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -1037,6 +1037,13 @@ bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
                if (decl->Interp.Location || info->io.sampleInterp)
                   info->in[i].centroid = 1;
             }
+
+            if (sn == TGSI_SEMANTIC_PATCH ||
+                sn == TGSI_SEMANTIC_TESSOUTER ||
+                sn == TGSI_SEMANTIC_TESSINNER)
+               info->in[i].patch = 1;
+            if (sn == TGSI_SEMANTIC_PATCH)
+               info->numPatchConstants = MAX2(info->numPatchConstants, si + 1);
          }
       }
       break;
@@ -1071,6 +1078,13 @@ bool Source::scanDeclaration(const struct tgsi_full_declaration *decl)
          case TGSI_SEMANTIC_VIEWPORT_INDEX:
             info->io.viewportId = i;
             break;
+         case TGSI_SEMANTIC_PATCH:
+            info->numPatchConstants = MAX2(info->numPatchConstants, si + 1);
+            /* fallthrough */
+         case TGSI_SEMANTIC_TESSOUTER:
+         case TGSI_SEMANTIC_TESSINNER:
+            info->out[i].patch = 1;
+            break;
          default:
             break;
          }
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index cd8c736..924749e 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -36,6 +36,7 @@ nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase)
    switch (sn) {
    case TGSI_SEMANTIC_TESSOUTER:    return 0x000 + si * 0x4;
    case TGSI_SEMANTIC_TESSINNER:    return 0x010 + si * 0x4;
+   case TGSI_SEMANTIC_PATCH:        return 0x020 + si * 0x10;
    case TGSI_SEMANTIC_PRIMID:       return 0x060;
    case TGSI_SEMANTIC_LAYER:        return 0x064;
    case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
@@ -66,6 +67,7 @@ nvc0_shader_output_address(unsigned sn, unsigned si, unsigned ubase)
    switch (sn) {
    case TGSI_SEMANTIC_TESSOUTER:     return 0x000 + si * 0x4;
    case TGSI_SEMANTIC_TESSINNER:     return 0x010 + si * 0x4;
+   case TGSI_SEMANTIC_PATCH:         return 0x020 + si * 0x10;
    case TGSI_SEMANTIC_PRIMID:        return 0x060;
    case TGSI_SEMANTIC_LAYER:         return 0x064;
    case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
@@ -120,8 +122,6 @@ nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
    for (i = 0; i < info->numInputs; ++i) {
       offset = nvc0_shader_input_address(info->in[i].sn,
                                          info->in[i].si, ubase);
-      if (info->in[i].patch && offset >= 0x20)
-         offset = 0x20 + info->in[i].si * 0x10;
 
       for (c = 0; c < 4; ++c)
          info->in[i].slot[c] = (offset + c * 0x4) / 4;
@@ -163,8 +163,6 @@ nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
    for (i = 0; i < info->numOutputs; ++i) {
       offset = nvc0_shader_output_address(info->out[i].sn,
                                           info->out[i].si, ubase);
-      if (info->out[i].patch && offset >= 0x20)
-         offset = 0x20 + info->out[i].si * 0x10;
 
       for (c = 0; c < 4; ++c)
          info->out[i].slot[c] = (offset + c * 0x4) / 4;
-- 
2.3.6

_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/nouveau

^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH 06/12] nv50/ir: populate info structure based on new tess properties
  2015-05-17  5:07 [PATCH 00/12] Tessellation support for nvc0 Ilia Mirkin
  2015-05-17  5:07 ` [PATCH 04/12] nvc0: TESSCOORD comes in as a sysval, not an input Ilia Mirkin
       [not found] ` <1431839235-10256-1-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
@ 2015-05-17  5:07 ` Ilia Mirkin
  2015-05-17  5:07 ` [PATCH 07/12] nv50/ir: set perPatch flag on load/stores to per-patch varyings Ilia Mirkin
  3 siblings, 0 replies; 15+ messages in thread
From: Ilia Mirkin @ 2015-05-17  5:07 UTC (permalink / raw)
  To: mesa-dev; +Cc: nouveau

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
---
 .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp      | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index f523318..cb9e1be 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -949,6 +949,24 @@ void Source::scanProperty(const struct tgsi_full_property *prop)
    case TGSI_PROPERTY_VS_PROHIBIT_UCPS:
       info->io.genUserClip = -1;
       break;
+   case TGSI_PROPERTY_TCS_VERTICES_OUT:
+      info->prop.tp.outputPatchSize = prop->u[0].Data;
+      break;
+   case TGSI_PROPERTY_TES_PRIM_MODE:
+      info->prop.tp.domain = prop->u[0].Data;
+      break;
+   case TGSI_PROPERTY_TES_SPACING:
+      info->prop.tp.partitioning = prop->u[0].Data;
+      break;
+   case TGSI_PROPERTY_TES_VERTEX_ORDER_CW:
+      info->prop.tp.winding = prop->u[0].Data;
+      break;
+   case TGSI_PROPERTY_TES_POINT_MODE:
+      if (prop->u[0].Data)
+         info->prop.tp.outputPrim = PIPE_PRIM_POINTS;
+      else
+         info->prop.tp.outputPrim = PIPE_PRIM_TRIANGLES; /* anything but points */
+      break;
    default:
       INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
       break;
-- 
2.3.6

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^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH 07/12] nv50/ir: set perPatch flag on load/stores to per-patch varyings
  2015-05-17  5:07 [PATCH 00/12] Tessellation support for nvc0 Ilia Mirkin
                   ` (2 preceding siblings ...)
  2015-05-17  5:07 ` [PATCH 06/12] nv50/ir: populate info structure based on new tess properties Ilia Mirkin
@ 2015-05-17  5:07 ` Ilia Mirkin
  3 siblings, 0 replies; 15+ messages in thread
From: Ilia Mirkin @ 2015-05-17  5:07 UTC (permalink / raw)
  To: mesa-dev; +Cc: nouveau

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
---
 src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index cb9e1be..a95e8f3 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -1574,6 +1574,7 @@ Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
    const int idx2d = src.is2D() ? src.getIndex(1) : 0;
    const int idx = src.getIndex(0);
    const int swz = src.getSwizzle(c);
+   Instruction *ld;
 
    switch (src.getFile()) {
    case TGSI_FILE_IMMEDIATE:
@@ -1601,7 +1602,9 @@ Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
          if (ptr)
             return mkLoadv(TYPE_U32, srcToSym(src, c), ptr);
       }
-      return mkLoadv(TYPE_U32, srcToSym(src, c), shiftAddress(ptr));
+      ld = mkLoad(TYPE_U32, getSSA(), srcToSym(src, c), shiftAddress(ptr));
+      ld->perPatch = info->in[idx].patch;
+      return ld->getDef(0);
    case TGSI_FILE_OUTPUT:
       assert(!"load from output file");
       return NULL;
@@ -1688,7 +1691,8 @@ Converter::storeDst(const tgsi::Instruction::DstRegister dst, int c,
              viewport != NULL)
             mkOp1(OP_MOV, TYPE_U32, viewport, val);
          else
-            mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
+            mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val)->perPatch =
+               info->out[idx].patch;
       }
    } else
    if (f == TGSI_FILE_TEMPORARY ||
-- 
2.3.6

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^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH 08/12] nv50/ir: add support for reading outputs in tess control shaders
       [not found] ` <1431839235-10256-1-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
                     ` (3 preceding siblings ...)
  2015-05-17  5:07   ` [PATCH 05/12] nvc0/ir: mark varyings as per-patch based on semantic name Ilia Mirkin
@ 2015-05-17  5:07   ` Ilia Mirkin
  2015-05-17  5:07   ` [PATCH 09/12] nvc0/ir: patch vertex count is stored in the upper bits Ilia Mirkin
                     ` (4 subsequent siblings)
  9 siblings, 0 replies; 15+ messages in thread
From: Ilia Mirkin @ 2015-05-17  5:07 UTC (permalink / raw)
  To: mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
---
 src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index a95e8f3..4adedec 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -1204,6 +1204,16 @@ bool Source::scanInstruction(const struct tgsi_full_instruction *inst)
          if (src.getIndex(0) == TGSI_RESOURCE_GLOBAL)
             info->io.globalAccess |= (insn.getOpcode() == TGSI_OPCODE_LOAD) ?
                0x1 : 0x2;
+      } else
+      if (src.getFile() == TGSI_FILE_OUTPUT) {
+         if (src.isIndirect(0)) {
+            // We don't know which one is accessed, just mark everything for
+            // reading. This is an extremely unlikely occurrence.
+            for (unsigned i = 0; i < info->numOutputs; ++i)
+               info->out[i].oread = 1;
+         } else {
+            info->out[src.getIndex(0)].oread = 1;
+         }
       }
       if (src.getFile() != TGSI_FILE_INPUT)
          continue;
@@ -1606,8 +1616,8 @@ Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
       ld->perPatch = info->in[idx].patch;
       return ld->getDef(0);
    case TGSI_FILE_OUTPUT:
-      assert(!"load from output file");
-      return NULL;
+      assert(prog->getType() == Program::TYPE_TESSELLATION_CONTROL);
+      return mkLoadv(TYPE_U32, srcToSym(src, c), ptr);
    case TGSI_FILE_SYSTEM_VALUE:
       assert(!ptr);
       return mkOp1v(OP_RDSV, TYPE_U32, getSSA(), srcToSym(src, c));
-- 
2.3.6

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^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH 09/12] nvc0/ir: patch vertex count is stored in the upper bits
       [not found] ` <1431839235-10256-1-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
                     ` (4 preceding siblings ...)
  2015-05-17  5:07   ` [PATCH 08/12] nv50/ir: add support for reading outputs in tess control shaders Ilia Mirkin
@ 2015-05-17  5:07   ` Ilia Mirkin
  2015-05-17  5:07   ` [PATCH 10/12] nvc0/ir: handle loads from outputs in control shaders Ilia Mirkin
                     ` (3 subsequent siblings)
  9 siblings, 0 replies; 15+ messages in thread
From: Ilia Mirkin @ 2015-05-17  5:07 UTC (permalink / raw)
  To: mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

---
 src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index b61f3c4..be82944 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -1480,6 +1480,10 @@ NVC0LoweringPass::handleRDSV(Instruction *i)
          i->op = OP_MOV;
          i->setSrc(0, bld.mkImm((sv == SV_NTID || sv == SV_NCTAID) ? 1 : 0));
       }
+      if (sv == SV_VERTEX_COUNT) {
+         bld.setPosition(i, true);
+         bld.mkOp2(OP_EXTBF, TYPE_U32, i->getDef(0), i->getDef(0), bld.mkImm(0x808));
+      }
       return true;
    }
 
-- 
2.3.6

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^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH 10/12] nvc0/ir: handle loads from outputs in control shaders
       [not found] ` <1431839235-10256-1-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
                     ` (5 preceding siblings ...)
  2015-05-17  5:07   ` [PATCH 09/12] nvc0/ir: patch vertex count is stored in the upper bits Ilia Mirkin
@ 2015-05-17  5:07   ` Ilia Mirkin
  2015-05-17  5:07   ` [PATCH 11/12] nvc0/ir: allow tess eval output loads to be CSE'd Ilia Mirkin
                     ` (2 subsequent siblings)
  9 siblings, 0 replies; 15+ messages in thread
From: Ilia Mirkin @ 2015-05-17  5:07 UTC (permalink / raw)
  To: mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

---
 src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index be82944..b5404c8 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -1773,6 +1773,9 @@ NVC0LoweringPass::visit(Instruction *i)
             i->setIndirect(0, 0, ptr);
             i->subOp = NV50_IR_SUBOP_LDC_IS;
          }
+      } else if (i->src(0).getFile() == FILE_SHADER_OUTPUT) {
+         assert(prog->getType() == Program::TYPE_TESSELLATION_CONTROL);
+         i->op = OP_VFETCH;
       }
       break;
    case OP_ATOM:
-- 
2.3.6

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^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH 11/12] nvc0/ir: allow tess eval output loads to be CSE'd
       [not found] ` <1431839235-10256-1-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
                     ` (6 preceding siblings ...)
  2015-05-17  5:07   ` [PATCH 10/12] nvc0/ir: handle loads from outputs in control shaders Ilia Mirkin
@ 2015-05-17  5:07   ` Ilia Mirkin
  2015-05-17  5:07   ` [PATCH 12/12] nv50/ir: cleanup private enums that have graduated to gallium Ilia Mirkin
  2015-05-17 14:15   ` [Mesa-dev] [PATCH 00/12] Tessellation support for nvc0 Tobias Klausmann
  9 siblings, 0 replies; 15+ messages in thread
From: Ilia Mirkin @ 2015-05-17  5:07 UTC (permalink / raw)
  To: mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

These only happen for gl_TessCoord which are constant.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
---
 src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 14446b6..04fc6d2 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -2443,6 +2443,8 @@ Instruction::isResultEqual(const Instruction *that) const
       case FILE_MEMORY_CONST:
       case FILE_SHADER_INPUT:
          return true;
+      case FILE_SHADER_OUTPUT:
+         return bb->getProgram()->getType() == Program::TYPE_TESSELLATION_EVAL;
       default:
          return false;
       }
-- 
2.3.6

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^ permalink raw reply related	[flat|nested] 15+ messages in thread
* [PATCH 12/12] nv50/ir: cleanup private enums that have graduated to gallium
       [not found] ` <1431839235-10256-1-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
                     ` (7 preceding siblings ...)
  2015-05-17  5:07   ` [PATCH 11/12] nvc0/ir: allow tess eval output loads to be CSE'd Ilia Mirkin
@ 2015-05-17  5:07   ` Ilia Mirkin
  2015-05-17 14:15   ` [Mesa-dev] [PATCH 00/12] Tessellation support for nvc0 Tobias Klausmann
  9 siblings, 0 replies; 15+ messages in thread
From: Ilia Mirkin @ 2015-05-17  5:07 UTC (permalink / raw)
  To: mesa-dev-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
  Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
---
 src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 5 -----
 src/gallium/drivers/nouveau/nvc0/nvc0_program.c      | 2 --
 2 files changed, 7 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index 0c8e3cb..61ce96b 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -69,11 +69,6 @@ struct nv50_ir_varying
 # define NV50_IR_DEBUG_REG_ALLOC 0
 #endif
 
-#define NV50_SEMANTIC_CLIPDISTANCE  (TGSI_SEMANTIC_COUNT + 0)
-#define NV50_SEMANTIC_COUNT         (TGSI_SEMANTIC_COUNT + 10)
-
-#define NV50_PRIM_PATCHES PIPE_PRIM_MAX
-
 struct nv50_ir_prog_symbol
 {
    uint32_t label;
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index 924749e..2e1e442 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -46,7 +46,6 @@ nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase)
    case TGSI_SEMANTIC_FOG:          return 0x2e8;
    case TGSI_SEMANTIC_COLOR:        return 0x280 + si * 0x10;
    case TGSI_SEMANTIC_BCOLOR:       return 0x2a0 + si * 0x10;
-   case NV50_SEMANTIC_CLIPDISTANCE: return 0x2c0 + si * 0x4;
    case TGSI_SEMANTIC_CLIPDIST:     return 0x2c0 + si * 0x10;
    case TGSI_SEMANTIC_CLIPVERTEX:   return 0x270;
    case TGSI_SEMANTIC_PCOORD:       return 0x2e0;
@@ -77,7 +76,6 @@ nvc0_shader_output_address(unsigned sn, unsigned si, unsigned ubase)
    case TGSI_SEMANTIC_FOG:           return 0x2e8;
    case TGSI_SEMANTIC_COLOR:         return 0x280 + si * 0x10;
    case TGSI_SEMANTIC_BCOLOR:        return 0x2a0 + si * 0x10;
-   case NV50_SEMANTIC_CLIPDISTANCE:  return 0x2c0 + si * 0x4;
    case TGSI_SEMANTIC_CLIPDIST:      return 0x2c0 + si * 0x10;
    case TGSI_SEMANTIC_CLIPVERTEX:    return 0x270;
    case TGSI_SEMANTIC_TEXCOORD:      return 0x300 + si * 0x10;
-- 
2.3.6

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^ permalink raw reply related	[flat|nested] 15+ messages in thread
* Re: [PATCH 02/12] nvc0: add support for setting patch vertices at draw time
  2015-05-17  5:07   ` [PATCH 02/12] nvc0: add support for setting patch vertices at draw time Ilia Mirkin
@ 2015-05-17  5:18     ` Ilia Mirkin
  0 siblings, 0 replies; 15+ messages in thread
From: Ilia Mirkin @ 2015-05-17  5:18 UTC (permalink / raw)
  To: mesa-dev; +Cc: nouveau

On Sun, May 17, 2015 at 1:07 AM, Ilia Mirkin <imirkin@alum.mit.edu> wrote:
> Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
> ---
>  src/gallium/drivers/nouveau/nvc0/nvc0_screen.c       | 1 +
>  src/gallium/drivers/nouveau/nvc0/nvc0_screen.h       | 1 +
>  src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c | 3 ---
>  src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c          | 6 ++++++
>  4 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> index ff552ae..4bc41f2 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
> @@ -1004,6 +1004,7 @@ nvc0_screen_create(struct nouveau_device *dev)
>     PUSH_DATA (push, 0x20);
>     BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1);
>     PUSH_DATA (push, 0x00);
> +   screen->save_state.patch_vertices = 3;
>
>     BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1);
>     PUSH_DATA (push, 0);
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
> index ef2bd43..c79211e 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
> @@ -38,6 +38,7 @@ struct nvc0_graph_state {
>     uint32_t constant_elts;
>     int32_t index_bias;
>     uint16_t scissor;
> +   uint8_t patch_vertices;
>     uint8_t vbo_mode; /* 0 = normal, 1 = translate, 3 = translate, forced */
>     uint8_t num_vtxbufs;
>     uint8_t num_vtxelts;
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c b/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
> index 516b33b..32f4519 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
> @@ -147,9 +147,6 @@ nvc0_tctlprog_validate(struct nvc0_context *nvc0)
>        PUSH_DATA (push, tp->code_base);
>        BEGIN_NVC0(push, NVC0_3D(SP_GPR_ALLOC(2)), 1);
>        PUSH_DATA (push, tp->num_gprs);
> -
> -      if (tp->tp.input_patch_size <= 32)
> -         IMMED_NVC0(push, NVC0_3D(PATCH_VERTICES), tp->tp.input_patch_size);
>     } else {
>        BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1);
>        PUSH_DATA (push, 0x20);
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
> index f8e2759..fb7b073 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c
> @@ -887,6 +887,12 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
>        }
>     }
>
> +   if (info->mode == PIPE_PRIM_PATCHES &&
> +       nvc0->state.patch_vertices != info->vertices_per_patch) {
> +      IMMED_NVC0(push, NVC0_3D(PATCH_VERTICES), nvc0->state.patch_vertices);
> +      nvc0->state.patch_vertices = info->vertices_per_patch;

Naturally those lines are swapped, fixed locally. That's what I get
for last-second untested changes :(

> +   }
> +
>     /* 8 as minimum to avoid immediate double validation of new buffers */
>     nvc0_state_validate(nvc0, ~0, 8);
>
> --
> 2.3.6
>
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^ permalink raw reply	[flat|nested] 15+ messages in thread
* Re: [Mesa-dev] [PATCH 00/12] Tessellation support for nvc0
       [not found] ` <1431839235-10256-1-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
                     ` (8 preceding siblings ...)
  2015-05-17  5:07   ` [PATCH 12/12] nv50/ir: cleanup private enums that have graduated to gallium Ilia Mirkin
@ 2015-05-17 14:15   ` Tobias Klausmann
  9 siblings, 0 replies; 15+ messages in thread
From: Tobias Klausmann @ 2015-05-17 14:15 UTC (permalink / raw)
  To: Ilia Mirkin; +Cc: nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW

as far as i can evaluate this without deeper insight into tess, this 
patchseries looks good to me!

Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>

On 17.05.2015 07:07, Ilia Mirkin wrote:
> This is enough to enable tessellation support on nvc0. It seems to
> work a lot better on my GF108 than GK208. I suspect that there's some
> sort of scheduling shenanigans that need to be adjusted for
> kepler+. Or perhaps some shader header things.
>
> Even with the GF108, I still get occasional blue triangles in Heaven,
> but I get a *ton* of them on the GK208 -- seemingly the same issue,
> but it's much worse on there.
>
> Also there's about a 100% chance that gl_PrimitiveID doesn't work.
>
> In any case, I plan on pushing this semi-soon unless there are any
> loud objections. I don't think it's going to do too much good sitting
> in my tree, or too much evil sitting upstream while core + st/mesa are
> worked out.
>
> Ilia Mirkin (12):
>    nvc0: preliminary tess support
>    nvc0: add support for setting patch vertices at draw time
>    nvc0: add handling for set_tess_state callback
>    nvc0: TESSCOORD comes in as a sysval, not an input
>    nvc0/ir: mark varyings as per-patch based on semantic name
>    nv50/ir: populate info structure based on new tess properties
>    nv50/ir: set perPatch flag on load/stores to per-patch varyings
>    nv50/ir: add support for reading outputs in tess control shaders
>    nvc0/ir: patch vertex count is stored in the upper bits
>    nvc0/ir: handle loads from outputs in control shaders
>    nvc0/ir: allow tess eval output loads to be CSE'd
>    nv50/ir: cleanup private enums that have graduated to gallium
>
>   src/gallium/drivers/nouveau/codegen/nv50_ir.cpp    |  4 +-
>   .../drivers/nouveau/codegen/nv50_ir_driver.h       | 12 ----
>   .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp  | 56 +++++++++++++++--
>   .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp      |  7 +++
>   .../drivers/nouveau/codegen/nv50_ir_peephole.cpp   |  2 +
>   src/gallium/drivers/nouveau/nvc0/nvc0_context.h    |  8 ++-
>   src/gallium/drivers/nouveau/nvc0/nvc0_program.c    | 56 +++++++----------
>   src/gallium/drivers/nouveau/nvc0/nvc0_screen.c     |  7 +--
>   src/gallium/drivers/nouveau/nvc0/nvc0_screen.h     |  1 +
>   .../drivers/nouveau/nvc0/nvc0_shader_state.c       |  3 -
>   src/gallium/drivers/nouveau/nvc0/nvc0_state.c      | 71 ++++++++++++++++++++++
>   .../drivers/nouveau/nvc0/nvc0_state_validate.c     | 11 ++++
>   src/gallium/drivers/nouveau/nvc0/nvc0_tex.c        | 34 +++++------
>   src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c        |  9 ++-
>   .../drivers/nouveau/nvc0/nvc0_vbo_translate.c      |  3 +-
>   15 files changed, 200 insertions(+), 84 deletions(-)
>

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^ permalink raw reply	[flat|nested] 15+ messages in thread
end of thread, other threads:[~2015-05-17 14:15 UTC | newest]

Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-05-17  5:07 [PATCH 00/12] Tessellation support for nvc0 Ilia Mirkin
2015-05-17  5:07 ` [PATCH 04/12] nvc0: TESSCOORD comes in as a sysval, not an input Ilia Mirkin
     [not found] ` <1431839235-10256-1-git-send-email-imirkin-FrUbXkNCsVf2fBVCVOL8/A@public.gmane.org>
2015-05-17  5:07   ` [PATCH 01/12] nvc0: preliminary tess support Ilia Mirkin
2015-05-17  5:07   ` [PATCH 02/12] nvc0: add support for setting patch vertices at draw time Ilia Mirkin
2015-05-17  5:18     ` Ilia Mirkin
2015-05-17  5:07   ` [PATCH 03/12] nvc0: add handling for set_tess_state callback Ilia Mirkin
2015-05-17  5:07   ` [PATCH 05/12] nvc0/ir: mark varyings as per-patch based on semantic name Ilia Mirkin
2015-05-17  5:07   ` [PATCH 08/12] nv50/ir: add support for reading outputs in tess control shaders Ilia Mirkin
2015-05-17  5:07   ` [PATCH 09/12] nvc0/ir: patch vertex count is stored in the upper bits Ilia Mirkin
2015-05-17  5:07   ` [PATCH 10/12] nvc0/ir: handle loads from outputs in control shaders Ilia Mirkin
2015-05-17  5:07   ` [PATCH 11/12] nvc0/ir: allow tess eval output loads to be CSE'd Ilia Mirkin
2015-05-17  5:07   ` [PATCH 12/12] nv50/ir: cleanup private enums that have graduated to gallium Ilia Mirkin
2015-05-17 14:15   ` [Mesa-dev] [PATCH 00/12] Tessellation support for nvc0 Tobias Klausmann
2015-05-17  5:07 ` [PATCH 06/12] nv50/ir: populate info structure based on new tess properties Ilia Mirkin
2015-05-17  5:07 ` [PATCH 07/12] nv50/ir: set perPatch flag on load/stores to per-patch varyings Ilia Mirkin

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