* [PATCH v2 1/2] drm/i915/bxt: Port PLL programming BUN
@ 2015-05-07 6:30 Vandana Kannan
2015-05-07 6:30 ` [PATCH 2/2] drm/i915/bxt: Move around lane stagger calculation Vandana Kannan
2015-05-07 9:27 ` [PATCH v2 1/2] drm/i915/bxt: Port PLL programming BUN Imre Deak
0 siblings, 2 replies; 11+ messages in thread
From: Vandana Kannan @ 2015-05-07 6:30 UTC (permalink / raw)
To: intel-gfx
BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to
VCO frequencies. Program i_lockthresh in PORT_PLL_9.
VCO calculated based on the formula:
Desired Output = Port bit rate in MHz (DisplayPort HBR2 is 5400 MHz)
Fast Clock = Desired Output / 2
VCO = Fast Clock * P1 * P2
Prop_coeff, int_coeff, and tdctargetcnt modified according to above
calculation.
BUN 2: Port PLLs require additional programming at certain frequencies -
DCO amplitude in PORT_PLL_10
Review comments from Siva which were addressed in the initial version of the
patch.
- Change PORT_PLL_LOCK_THRESHOLD to PORT_PLL_LOCK_THRESHOLD_MASK
- Calculate for HDMI
- Correct values for vco = 5.4
- return in case of invalid vco range
v2: Imre's review comments addressed
- change dcoampovr_en to dcoampovr_en_h
- change PORT_PLL_DCO_AMP_OVR_EN to PORT_PLL_DCO_AMP_OVR_EN_H
- Correct lane stagger value for 324MHz
- Make coef common for HDMI and DP
- remove superfluous comments
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 6 ++++
drivers/gpu/drm/i915/intel_ddi.c | 69 ++++++++++++++++++++++++++++++----------
3 files changed, 60 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 136d42a..05a4e1c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -304,7 +304,7 @@ struct intel_dpll_hw_state {
uint32_t cfgcr1, cfgcr2;
/* bxt */
- uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pcsdw12;
+ uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pll10, pcsdw12;
};
struct intel_shared_dpll_config {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1b31238..b086d26 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1185,6 +1185,12 @@ enum skl_disp_power_wells {
#define PORT_PLL_GAIN_CTL(x) ((x) << 16)
/* PORT_PLL_8_A */
#define PORT_PLL_TARGET_CNT_MASK 0x3FF
+/* PORT_PLL_9_A */
+#define PORT_PLL_LOCK_THRESHOLD_MASK 0xe
+/* PORT_PLL_10_A */
+#define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27)
+#define PORT_PLL_DCO_AMP_MASK 0x3c00
+#define PORT_PLL_DCO_AMP(x) (x<<10)
#define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \
_PORT_PLL_0_B, \
_PORT_PLL_0_C)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9c1e74a..49b9fd8 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1337,18 +1337,20 @@ struct bxt_clk_div {
uint32_t int_coef;
uint32_t gain_ctl;
uint32_t targ_cnt;
+ uint32_t dcoampovr_en_h;
+ uint32_t dco_amp;
uint32_t lanestagger;
};
/* pre-calculated values for DP linkrates */
static struct bxt_clk_div bxt_dp_clk_val[7] = {
- /* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
- /* 270 */ {4, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0xd},
- /* 540 */ {2, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0x18},
- /* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
- /* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
- /* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
- /* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
+ /* 162 */ {4, 2, 32, 1677722, 1, 1, 4, 9, 3, 8, 0, 15, 0xd},
+ /* 270 */ {4, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0, 15, 0xd},
+ /* 540 */ {2, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0, 15, 0x18},
+ /* 216 */ {3, 2, 32, 1677722, 1, 1, 4, 9, 3, 8, 0, 15, 0xd},
+ /* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 3, 9, 1, 15, 0xd},
+ /* 324 */ {4, 1, 32, 1677722, 1, 1, 4, 9, 3, 8, 0, 15, 0x18},
+ /* 432 */ {3, 1, 32, 1677722, 1, 1, 4, 9, 3, 8, 0, 15, 0x18}
};
static bool
@@ -1359,6 +1361,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
{
struct intel_shared_dpll *pll;
struct bxt_clk_div clk_div = {0};
+ int vco = 0;
if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
intel_clock_t best_clock;
@@ -1382,11 +1385,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
clk_div.m2_frac_en = clk_div.m2_frac != 0;
- /* FIXME: set coef, gain, targcnt based on freq band */
- clk_div.prop_coef = 5;
- clk_div.int_coef = 11;
- clk_div.gain_ctl = 2;
- clk_div.targ_cnt = 9;
+ vco = best_clock.vco;
if (clock > 270000)
clk_div.lanestagger = 0x18;
else if (clock > 135000)
@@ -1416,6 +1415,32 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
clk_div = bxt_dp_clk_val[0];
DRM_ERROR("Unknown link rate\n");
}
+ vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
+ }
+
+ clk_div.dco_amp = 15;
+ clk_div.dcoampovr_en_h = 0;
+ if (vco >= 6200000 && vco <= 6480000) {
+ clk_div.prop_coef = 4;
+ clk_div.int_coef = 9;
+ clk_div.gain_ctl = 3;
+ clk_div.targ_cnt = 8;
+ } else if ((vco > 5400000 && vco < 6200000) ||
+ (vco >= 4800000 && vco < 5400000)) {
+ clk_div.prop_coef = 5;
+ clk_div.int_coef = 11;
+ clk_div.gain_ctl = 3;
+ clk_div.targ_cnt = 9;
+ if (vco >= 4800000 && vco < 5400000)
+ clk_div.dcoampovr_en_h = 1;
+ } else if (vco == 5400000) {
+ clk_div.prop_coef = 3;
+ clk_div.int_coef = 8;
+ clk_div.gain_ctl = 1;
+ clk_div.targ_cnt = 9;
+ } else {
+ DRM_ERROR("Invalid VCO\n");
+ return false;
}
crtc_state->dpll_hw_state.ebb0 =
@@ -1435,6 +1460,11 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
crtc_state->dpll_hw_state.pll8 = clk_div.targ_cnt;
+ if (clk_div.dcoampovr_en_h)
+ crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H;
+
+ crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(clk_div.dco_amp);
+
crtc_state->dpll_hw_state.pcsdw12 =
LANESTAGGER_STRAP_OVRD | clk_div.lanestagger;
@@ -2366,10 +2396,16 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
temp |= pll->config.hw_state.pll8;
I915_WRITE(BXT_PORT_PLL(port, 8), temp);
- /*
- * FIXME: program PORT_PLL_9/i_lockthresh according to the latest
- * specification update.
- */
+ temp = I915_READ(BXT_PORT_PLL(port, 9));
+ temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
+ temp |= (5 << 1);
+ I915_WRITE(BXT_PORT_PLL(port, 9), temp);
+
+ temp = I915_READ(BXT_PORT_PLL(port, 10));
+ temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
+ temp &= ~PORT_PLL_DCO_AMP_MASK;
+ temp |= pll->config.hw_state.pll10;
+ I915_WRITE(BXT_PORT_PLL(port, 10), temp);
/* Recalibrate with new settings */
temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
@@ -2433,6 +2469,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
+ hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
/*
* While we write to the group register to program all lanes at once we
* can read only lane registers. We configure all lanes the same way, so
--
2.0.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/2] drm/i915/bxt: Move around lane stagger calculation
2015-05-07 6:30 [PATCH v2 1/2] drm/i915/bxt: Port PLL programming BUN Vandana Kannan
@ 2015-05-07 6:30 ` Vandana Kannan
2015-05-07 13:07 ` Imre Deak
2015-05-07 21:22 ` [PATCH " shuang.he
2015-05-07 9:27 ` [PATCH v2 1/2] drm/i915/bxt: Port PLL programming BUN Imre Deak
1 sibling, 2 replies; 11+ messages in thread
From: Vandana Kannan @ 2015-05-07 6:30 UTC (permalink / raw)
To: intel-gfx
Making lane stagger calculation common for HDMI and DP
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 49b9fd8..144d544 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1386,16 +1386,6 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
clk_div.m2_frac_en = clk_div.m2_frac != 0;
vco = best_clock.vco;
- if (clock > 270000)
- clk_div.lanestagger = 0x18;
- else if (clock > 135000)
- clk_div.lanestagger = 0x0d;
- else if (clock > 67000)
- clk_div.lanestagger = 0x07;
- else if (clock > 33000)
- clk_div.lanestagger = 0x04;
- else
- clk_div.lanestagger = 0x02;
} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
intel_encoder->type == INTEL_OUTPUT_EDP) {
struct drm_encoder *encoder = &intel_encoder->base;
@@ -1443,6 +1433,17 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
return false;
}
+ if (clock > 270000)
+ clk_div.lanestagger = 0x18;
+ else if (clock > 135000)
+ clk_div.lanestagger = 0x0d;
+ else if (clock > 67000)
+ clk_div.lanestagger = 0x07;
+ else if (clock > 33000)
+ clk_div.lanestagger = 0x04;
+ else
+ clk_div.lanestagger = 0x02;
+
crtc_state->dpll_hw_state.ebb0 =
PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
--
2.0.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/2] drm/i915/bxt: Port PLL programming BUN
2015-05-07 6:30 [PATCH v2 1/2] drm/i915/bxt: Port PLL programming BUN Vandana Kannan
2015-05-07 6:30 ` [PATCH 2/2] drm/i915/bxt: Move around lane stagger calculation Vandana Kannan
@ 2015-05-07 9:27 ` Imre Deak
2015-05-11 14:39 ` Kannan, Vandana
1 sibling, 1 reply; 11+ messages in thread
From: Imre Deak @ 2015-05-07 9:27 UTC (permalink / raw)
To: Vandana Kannan; +Cc: intel-gfx
On to, 2015-05-07 at 12:00 +0530, Vandana Kannan wrote:
> BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to
> VCO frequencies. Program i_lockthresh in PORT_PLL_9.
>
> VCO calculated based on the formula:
> Desired Output = Port bit rate in MHz (DisplayPort HBR2 is 5400 MHz)
> Fast Clock = Desired Output / 2
> VCO = Fast Clock * P1 * P2
>
> Prop_coeff, int_coeff, and tdctargetcnt modified according to above
> calculation.
>
> BUN 2: Port PLLs require additional programming at certain frequencies -
> DCO amplitude in PORT_PLL_10
>
> Review comments from Siva which were addressed in the initial version of the
> patch.
> - Change PORT_PLL_LOCK_THRESHOLD to PORT_PLL_LOCK_THRESHOLD_MASK
> - Calculate for HDMI
> - Correct values for vco = 5.4
> - return in case of invalid vco range
>
> v2: Imre's review comments addressed
> - change dcoampovr_en to dcoampovr_en_h
> - change PORT_PLL_DCO_AMP_OVR_EN to PORT_PLL_DCO_AMP_OVR_EN_H
> - Correct lane stagger value for 324MHz
> - Make coef common for HDMI and DP
> - remove superfluous comments
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
> Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++
> drivers/gpu/drm/i915/intel_ddi.c | 69 ++++++++++++++++++++++++++++++----------
> 3 files changed, 60 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 136d42a..05a4e1c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -304,7 +304,7 @@ struct intel_dpll_hw_state {
> uint32_t cfgcr1, cfgcr2;
>
> /* bxt */
> - uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pcsdw12;
> + uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pll10, pcsdw12;
> };
>
> struct intel_shared_dpll_config {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1b31238..b086d26 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1185,6 +1185,12 @@ enum skl_disp_power_wells {
> #define PORT_PLL_GAIN_CTL(x) ((x) << 16)
> /* PORT_PLL_8_A */
> #define PORT_PLL_TARGET_CNT_MASK 0x3FF
> +/* PORT_PLL_9_A */
> +#define PORT_PLL_LOCK_THRESHOLD_MASK 0xe
> +/* PORT_PLL_10_A */
> +#define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27)
> +#define PORT_PLL_DCO_AMP_MASK 0x3c00
> +#define PORT_PLL_DCO_AMP(x) (x<<10)
> #define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \
> _PORT_PLL_0_B, \
> _PORT_PLL_0_C)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 9c1e74a..49b9fd8 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1337,18 +1337,20 @@ struct bxt_clk_div {
> uint32_t int_coef;
> uint32_t gain_ctl;
> uint32_t targ_cnt;
> + uint32_t dcoampovr_en_h;
> + uint32_t dco_amp;
> uint32_t lanestagger;
> };
>
> /* pre-calculated values for DP linkrates */
> static struct bxt_clk_div bxt_dp_clk_val[7] = {
> - /* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> - /* 270 */ {4, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0xd},
> - /* 540 */ {2, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0x18},
> - /* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> - /* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
> - /* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> - /* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
> + /* 162 */ {4, 2, 32, 1677722, 1, 1, 4, 9, 3, 8, 0, 15, 0xd},
> + /* 270 */ {4, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0, 15, 0xd},
> + /* 540 */ {2, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0, 15, 0x18},
> + /* 216 */ {3, 2, 32, 1677722, 1, 1, 4, 9, 3, 8, 0, 15, 0xd},
> + /* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 3, 9, 1, 15, 0xd},
> + /* 324 */ {4, 1, 32, 1677722, 1, 1, 4, 9, 3, 8, 0, 15, 0x18},
> + /* 432 */ {3, 1, 32, 1677722, 1, 1, 4, 9, 3, 8, 0, 15, 0x18}
We calculate all of prop_coef, int_coef, gain_ctl, targ_cnt,
dcoapovr_en_h, dco_amp, so no need to have fixed values for these. The
corresponding fields should be removed from bxt_clk_div and replaced
with local vars in bxt_ddi_pll_select.
> };
>
> static bool
> @@ -1359,6 +1361,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
> {
> struct intel_shared_dpll *pll;
> struct bxt_clk_div clk_div = {0};
> + int vco = 0;
>
> if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
> intel_clock_t best_clock;
> @@ -1382,11 +1385,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
> clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
> clk_div.m2_frac_en = clk_div.m2_frac != 0;
>
> - /* FIXME: set coef, gain, targcnt based on freq band */
> - clk_div.prop_coef = 5;
> - clk_div.int_coef = 11;
> - clk_div.gain_ctl = 2;
> - clk_div.targ_cnt = 9;
> + vco = best_clock.vco;
> if (clock > 270000)
> clk_div.lanestagger = 0x18;
> else if (clock > 135000)
> @@ -1416,6 +1415,32 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
> clk_div = bxt_dp_clk_val[0];
> DRM_ERROR("Unknown link rate\n");
> }
> + vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
> + }
> +
> + clk_div.dco_amp = 15;
> + clk_div.dcoampovr_en_h = 0;
> + if (vco >= 6200000 && vco <= 6480000) {
> + clk_div.prop_coef = 4;
> + clk_div.int_coef = 9;
> + clk_div.gain_ctl = 3;
> + clk_div.targ_cnt = 8;
> + } else if ((vco > 5400000 && vco < 6200000) ||
> + (vco >= 4800000 && vco < 5400000)) {
> + clk_div.prop_coef = 5;
> + clk_div.int_coef = 11;
> + clk_div.gain_ctl = 3;
> + clk_div.targ_cnt = 9;
> + if (vco >= 4800000 && vco < 5400000)
> + clk_div.dcoampovr_en_h = 1;
> + } else if (vco == 5400000) {
> + clk_div.prop_coef = 3;
> + clk_div.int_coef = 8;
> + clk_div.gain_ctl = 1;
> + clk_div.targ_cnt = 9;
> + } else {
> + DRM_ERROR("Invalid VCO\n");
> + return false;
> }
>
> crtc_state->dpll_hw_state.ebb0 =
> @@ -1435,6 +1460,11 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>
> crtc_state->dpll_hw_state.pll8 = clk_div.targ_cnt;
>
> + if (clk_div.dcoampovr_en_h)
> + crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H;
> +
> + crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(clk_div.dco_amp);
> +
> crtc_state->dpll_hw_state.pcsdw12 =
> LANESTAGGER_STRAP_OVRD | clk_div.lanestagger;
>
> @@ -2366,10 +2396,16 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
> temp |= pll->config.hw_state.pll8;
> I915_WRITE(BXT_PORT_PLL(port, 8), temp);
>
> - /*
> - * FIXME: program PORT_PLL_9/i_lockthresh according to the latest
> - * specification update.
> - */
> + temp = I915_READ(BXT_PORT_PLL(port, 9));
> + temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
> + temp |= (5 << 1);
> + I915_WRITE(BXT_PORT_PLL(port, 9), temp);
> +
> + temp = I915_READ(BXT_PORT_PLL(port, 10));
> + temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
> + temp &= ~PORT_PLL_DCO_AMP_MASK;
> + temp |= pll->config.hw_state.pll10;
> + I915_WRITE(BXT_PORT_PLL(port, 10), temp);
>
> /* Recalibrate with new settings */
> temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
> @@ -2433,6 +2469,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
> hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
> hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
> hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
> + hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
> /*
> * While we write to the group register to program all lanes at once we
> * can read only lane registers. We configure all lanes the same way, so
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] drm/i915/bxt: Move around lane stagger calculation
2015-05-07 6:30 ` [PATCH 2/2] drm/i915/bxt: Move around lane stagger calculation Vandana Kannan
@ 2015-05-07 13:07 ` Imre Deak
2015-05-13 6:50 ` [PATCH v2 " Vandana Kannan
2015-05-07 21:22 ` [PATCH " shuang.he
1 sibling, 1 reply; 11+ messages in thread
From: Imre Deak @ 2015-05-07 13:07 UTC (permalink / raw)
To: Vandana Kannan; +Cc: intel-gfx
On to, 2015-05-07 at 12:00 +0530, Vandana Kannan wrote:
> Making lane stagger calculation common for HDMI and DP
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 21 +++++++++++----------
> 1 file changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 49b9fd8..144d544 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1386,16 +1386,6 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
> clk_div.m2_frac_en = clk_div.m2_frac != 0;
>
> vco = best_clock.vco;
> - if (clock > 270000)
> - clk_div.lanestagger = 0x18;
> - else if (clock > 135000)
> - clk_div.lanestagger = 0x0d;
> - else if (clock > 67000)
> - clk_div.lanestagger = 0x07;
> - else if (clock > 33000)
> - clk_div.lanestagger = 0x04;
> - else
> - clk_div.lanestagger = 0x02;
> } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
> intel_encoder->type == INTEL_OUTPUT_EDP) {
> struct drm_encoder *encoder = &intel_encoder->base;
> @@ -1443,6 +1433,17 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
> return false;
> }
>
> + if (clock > 270000)
> + clk_div.lanestagger = 0x18;
> + else if (clock > 135000)
> + clk_div.lanestagger = 0x0d;
> + else if (clock > 67000)
> + clk_div.lanestagger = 0x07;
> + else if (clock > 33000)
> + clk_div.lanestagger = 0x04;
> + else
> + clk_div.lanestagger = 0x02;
> +
Here as in patch 1/2 we don't need to have fixed values for lanestagger
any more, so you can remove it from bxt_clk_div and use a local var
instead.
> crtc_state->dpll_hw_state.ebb0 =
> PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
> crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/2] drm/i915/bxt: Move around lane stagger calculation
2015-05-07 6:30 ` [PATCH 2/2] drm/i915/bxt: Move around lane stagger calculation Vandana Kannan
2015-05-07 13:07 ` Imre Deak
@ 2015-05-07 21:22 ` shuang.he
1 sibling, 0 replies; 11+ messages in thread
From: shuang.he @ 2015-05-07 21:22 UTC (permalink / raw)
To: shuang.he, ethan.gao, intel-gfx, vandana.kannan
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6340
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 276/276 276/276
ILK 302/302 302/302
SNB 316/316 316/316
IVB 342/342 342/342
BYT 286/286 286/286
BDW 321/321 321/321
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
Note: You need to pay more attention to line start with '*'
_______________________________________________
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/2] drm/i915/bxt: Port PLL programming BUN
2015-05-07 9:27 ` [PATCH v2 1/2] drm/i915/bxt: Port PLL programming BUN Imre Deak
@ 2015-05-11 14:39 ` Kannan, Vandana
2015-05-13 6:48 ` [PATCH v3 " Vandana Kannan
0 siblings, 1 reply; 11+ messages in thread
From: Kannan, Vandana @ 2015-05-11 14:39 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx
On 5/7/2015 2:57 PM, Imre Deak wrote:
> On to, 2015-05-07 at 12:00 +0530, Vandana Kannan wrote:
>> BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to
>> VCO frequencies. Program i_lockthresh in PORT_PLL_9.
>>
>> VCO calculated based on the formula:
>> Desired Output = Port bit rate in MHz (DisplayPort HBR2 is 5400 MHz)
>> Fast Clock = Desired Output / 2
>> VCO = Fast Clock * P1 * P2
>>
>> Prop_coeff, int_coeff, and tdctargetcnt modified according to above
>> calculation.
>>
>> BUN 2: Port PLLs require additional programming at certain frequencies -
>> DCO amplitude in PORT_PLL_10
>>
>> Review comments from Siva which were addressed in the initial version of the
>> patch.
>> - Change PORT_PLL_LOCK_THRESHOLD to PORT_PLL_LOCK_THRESHOLD_MASK
>> - Calculate for HDMI
>> - Correct values for vco = 5.4
>> - return in case of invalid vco range
>>
>> v2: Imre's review comments addressed
>> - change dcoampovr_en to dcoampovr_en_h
>> - change PORT_PLL_DCO_AMP_OVR_EN to PORT_PLL_DCO_AMP_OVR_EN_H
>> - Correct lane stagger value for 324MHz
>> - Make coef common for HDMI and DP
>> - remove superfluous comments
>>
>> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
>> Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
>> Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 2 +-
>> drivers/gpu/drm/i915/i915_reg.h | 6 ++++
>> drivers/gpu/drm/i915/intel_ddi.c | 69 ++++++++++++++++++++++++++++++----------
>> 3 files changed, 60 insertions(+), 17 deletions(-)
[...]
>> /* pre-calculated values for DP linkrates */
>> static struct bxt_clk_div bxt_dp_clk_val[7] = {
>> - /* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
>> - /* 270 */ {4, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0xd},
>> - /* 540 */ {2, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0x18},
>> - /* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
>> - /* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
>> - /* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
>> - /* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
>> + /* 162 */ {4, 2, 32, 1677722, 1, 1, 4, 9, 3, 8, 0, 15, 0xd},
>> + /* 270 */ {4, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0, 15, 0xd},
>> + /* 540 */ {2, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0, 15, 0x18},
>> + /* 216 */ {3, 2, 32, 1677722, 1, 1, 4, 9, 3, 8, 0, 15, 0xd},
>> + /* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 3, 9, 1, 15, 0xd},
>> + /* 324 */ {4, 1, 32, 1677722, 1, 1, 4, 9, 3, 8, 0, 15, 0x18},
>> + /* 432 */ {3, 1, 32, 1677722, 1, 1, 4, 9, 3, 8, 0, 15, 0x18}
>
> We calculate all of prop_coef, int_coef, gain_ctl, targ_cnt,
> dcoapovr_en_h, dco_amp, so no need to have fixed values for these. The
> corresponding fields should be removed from bxt_clk_div and replaced
> with local vars in bxt_ddi_pll_select.
>
Agree.
Made changes separately and thought of sending as another patch a little
later, but I'll include the changes in this patch and resend.
Thanks,
Vandana
>> };
>>
>> static bool
>> @@ -1359,6 +1361,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>> {
>> struct intel_shared_dpll *pll;
>> struct bxt_clk_div clk_div = {0};
>> + int vco = 0;
>>
>> if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
>> intel_clock_t best_clock;
>> @@ -1382,11 +1385,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>> clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
>> clk_div.m2_frac_en = clk_div.m2_frac != 0;
>>
>> - /* FIXME: set coef, gain, targcnt based on freq band */
>> - clk_div.prop_coef = 5;
>> - clk_div.int_coef = 11;
>> - clk_div.gain_ctl = 2;
>> - clk_div.targ_cnt = 9;
>> + vco = best_clock.vco;
>> if (clock > 270000)
>> clk_div.lanestagger = 0x18;
>> else if (clock > 135000)
>> @@ -1416,6 +1415,32 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
>> clk_div = bxt_dp_clk_val[0];
>> DRM_ERROR("Unknown link rate\n");
>> }
>> + vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
>> + }
>> +
[...]
>> /* Recalibrate with new settings */
>> temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
>> @@ -2433,6 +2469,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
>> hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
>> hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
>> hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
>> + hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
>> /*
>> * While we write to the group register to program all lanes at once we
>> * can read only lane registers. We configure all lanes the same way, so
>
>
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 1/2] drm/i915/bxt: Port PLL programming BUN
2015-05-11 14:39 ` Kannan, Vandana
@ 2015-05-13 6:48 ` Vandana Kannan
2015-05-18 16:26 ` Imre Deak
0 siblings, 1 reply; 11+ messages in thread
From: Vandana Kannan @ 2015-05-13 6:48 UTC (permalink / raw)
To: intel-gfx
BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to
VCO frequencies. Program i_lockthresh in PORT_PLL_9.
VCO calculated based on the formula:
Desired Output = Port bit rate in MHz (DisplayPort HBR2 is 5400 MHz)
Fast Clock = Desired Output / 2
VCO = Fast Clock * P1 * P2
Prop_coeff, int_coeff, and tdctargetcnt modified according to above
calculation.
BUN 2: Port PLLs require additional programming at certain frequencies -
DCO amplitude in PORT_PLL_10
Review comments from Siva which were addressed in the initial version of the
patch.
- Change PORT_PLL_LOCK_THRESHOLD to PORT_PLL_LOCK_THRESHOLD_MASK
- Calculate for HDMI
- Correct values for vco = 5.4
- return in case of invalid vco range
v2: Imre's review comments addressed
- change dcoampovr_en to dcoampovr_en_h
- change PORT_PLL_DCO_AMP_OVR_EN to PORT_PLL_DCO_AMP_OVR_EN_H
- Correct lane stagger value for 324MHz
- Make coef common for HDMI and DP
- remove superfluous comments
v3: Imre's comments addressed
- Remove Prop_coeff, int_coeff, tdctargetcnt, dcoampovr_en, gain_ctl,
dcoampovr_en_h from bxt_clk_div and make them local variables.
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com> [v1]
Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 6 +++
drivers/gpu/drm/i915/intel_ddi.c | 79 ++++++++++++++++++++++++++++------------
3 files changed, 63 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 136d42a..05a4e1c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -304,7 +304,7 @@ struct intel_dpll_hw_state {
uint32_t cfgcr1, cfgcr2;
/* bxt */
- uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pcsdw12;
+ uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pll10, pcsdw12;
};
struct intel_shared_dpll_config {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1b31238..b086d26 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1185,6 +1185,12 @@ enum skl_disp_power_wells {
#define PORT_PLL_GAIN_CTL(x) ((x) << 16)
/* PORT_PLL_8_A */
#define PORT_PLL_TARGET_CNT_MASK 0x3FF
+/* PORT_PLL_9_A */
+#define PORT_PLL_LOCK_THRESHOLD_MASK 0xe
+/* PORT_PLL_10_A */
+#define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27)
+#define PORT_PLL_DCO_AMP_MASK 0x3c00
+#define PORT_PLL_DCO_AMP(x) (x<<10)
#define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \
_PORT_PLL_0_B, \
_PORT_PLL_0_C)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9c1e74a..a56613c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1333,22 +1333,18 @@ struct bxt_clk_div {
uint32_t m2_frac;
bool m2_frac_en;
uint32_t n;
- uint32_t prop_coef;
- uint32_t int_coef;
- uint32_t gain_ctl;
- uint32_t targ_cnt;
uint32_t lanestagger;
};
/* pre-calculated values for DP linkrates */
static struct bxt_clk_div bxt_dp_clk_val[7] = {
- /* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
- /* 270 */ {4, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0xd},
- /* 540 */ {2, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0x18},
- /* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
- /* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
- /* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
- /* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
+ /* 162 */ {4, 2, 32, 1677722, 1, 1, 0xd},
+ /* 270 */ {4, 1, 27, 0, 0, 1, 0xd},
+ /* 540 */ {2, 1, 27, 0, 0, 1, 0x18},
+ /* 216 */ {3, 2, 32, 1677722, 1, 1, 0xd},
+ /* 243 */ {4, 1, 24, 1258291, 1, 1, 0xd},
+ /* 324 */ {4, 1, 32, 1677722, 1, 1, 0x18},
+ /* 432 */ {3, 1, 32, 1677722, 1, 1, 0x18}
};
static bool
@@ -1359,6 +1355,9 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
{
struct intel_shared_dpll *pll;
struct bxt_clk_div clk_div = {0};
+ int vco = 0;
+ uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
+ uint32_t dcoampovr_en_h, dco_amp;
if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
intel_clock_t best_clock;
@@ -1382,11 +1381,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
clk_div.m2_frac_en = clk_div.m2_frac != 0;
- /* FIXME: set coef, gain, targcnt based on freq band */
- clk_div.prop_coef = 5;
- clk_div.int_coef = 11;
- clk_div.gain_ctl = 2;
- clk_div.targ_cnt = 9;
+ vco = best_clock.vco;
if (clock > 270000)
clk_div.lanestagger = 0x18;
else if (clock > 135000)
@@ -1416,6 +1411,32 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
clk_div = bxt_dp_clk_val[0];
DRM_ERROR("Unknown link rate\n");
}
+ vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
+ }
+
+ dco_amp = 15;
+ dcoampovr_en_h = 0;
+ if (vco >= 6200000 && vco <= 6480000) {
+ prop_coef = 4;
+ int_coef = 9;
+ gain_ctl = 3;
+ targ_cnt = 8;
+ } else if ((vco > 5400000 && vco < 6200000) ||
+ (vco >= 4800000 && vco < 5400000)) {
+ prop_coef = 5;
+ int_coef = 11;
+ gain_ctl = 3;
+ targ_cnt = 9;
+ if (vco >= 4800000 && vco < 5400000)
+ dcoampovr_en_h = 1;
+ } else if (vco == 5400000) {
+ prop_coef = 3;
+ int_coef = 8;
+ gain_ctl = 1;
+ targ_cnt = 9;
+ } else {
+ DRM_ERROR("Invalid VCO\n");
+ return false;
}
crtc_state->dpll_hw_state.ebb0 =
@@ -1429,11 +1450,16 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
PORT_PLL_M2_FRAC_ENABLE;
crtc_state->dpll_hw_state.pll6 =
- clk_div.prop_coef | PORT_PLL_INT_COEFF(clk_div.int_coef);
+ prop_coef | PORT_PLL_INT_COEFF(int_coef);
crtc_state->dpll_hw_state.pll6 |=
- PORT_PLL_GAIN_CTL(clk_div.gain_ctl);
+ PORT_PLL_GAIN_CTL(gain_ctl);
+
+ crtc_state->dpll_hw_state.pll8 = targ_cnt;
- crtc_state->dpll_hw_state.pll8 = clk_div.targ_cnt;
+ if (dcoampovr_en_h)
+ crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H;
+
+ crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp);
crtc_state->dpll_hw_state.pcsdw12 =
LANESTAGGER_STRAP_OVRD | clk_div.lanestagger;
@@ -2366,10 +2392,16 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
temp |= pll->config.hw_state.pll8;
I915_WRITE(BXT_PORT_PLL(port, 8), temp);
- /*
- * FIXME: program PORT_PLL_9/i_lockthresh according to the latest
- * specification update.
- */
+ temp = I915_READ(BXT_PORT_PLL(port, 9));
+ temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
+ temp |= (5 << 1);
+ I915_WRITE(BXT_PORT_PLL(port, 9), temp);
+
+ temp = I915_READ(BXT_PORT_PLL(port, 10));
+ temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
+ temp &= ~PORT_PLL_DCO_AMP_MASK;
+ temp |= pll->config.hw_state.pll10;
+ I915_WRITE(BXT_PORT_PLL(port, 10), temp);
/* Recalibrate with new settings */
temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
@@ -2433,6 +2465,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
+ hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
/*
* While we write to the group register to program all lanes at once we
* can read only lane registers. We configure all lanes the same way, so
--
2.0.1
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 2/2] drm/i915/bxt: Move around lane stagger calculation
2015-05-07 13:07 ` Imre Deak
@ 2015-05-13 6:50 ` Vandana Kannan
2015-05-18 16:28 ` Imre Deak
0 siblings, 1 reply; 11+ messages in thread
From: Vandana Kannan @ 2015-05-13 6:50 UTC (permalink / raw)
To: intel-gfx
Making lane stagger calculation common for HDMI and DP
v2: Imre's comments addressed
- Remove lane stagger from bxt_clk_div and make it a local variable in
ddi_pll_select
Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 40 ++++++++++++++++++++--------------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index a56613c..aadd29e 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1333,18 +1333,17 @@ struct bxt_clk_div {
uint32_t m2_frac;
bool m2_frac_en;
uint32_t n;
- uint32_t lanestagger;
};
/* pre-calculated values for DP linkrates */
static struct bxt_clk_div bxt_dp_clk_val[7] = {
- /* 162 */ {4, 2, 32, 1677722, 1, 1, 0xd},
- /* 270 */ {4, 1, 27, 0, 0, 1, 0xd},
- /* 540 */ {2, 1, 27, 0, 0, 1, 0x18},
- /* 216 */ {3, 2, 32, 1677722, 1, 1, 0xd},
- /* 243 */ {4, 1, 24, 1258291, 1, 1, 0xd},
- /* 324 */ {4, 1, 32, 1677722, 1, 1, 0x18},
- /* 432 */ {3, 1, 32, 1677722, 1, 1, 0x18}
+ /* 162 */ {4, 2, 32, 1677722, 1, 1},
+ /* 270 */ {4, 1, 27, 0, 0, 1},
+ /* 540 */ {2, 1, 27, 0, 0, 1},
+ /* 216 */ {3, 2, 32, 1677722, 1, 1},
+ /* 243 */ {4, 1, 24, 1258291, 1, 1},
+ /* 324 */ {4, 1, 32, 1677722, 1, 1},
+ /* 432 */ {3, 1, 32, 1677722, 1, 1}
};
static bool
@@ -1357,7 +1356,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
struct bxt_clk_div clk_div = {0};
int vco = 0;
uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
- uint32_t dcoampovr_en_h, dco_amp;
+ uint32_t dcoampovr_en_h, dco_amp, lanestagger;
if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
intel_clock_t best_clock;
@@ -1382,16 +1381,6 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
clk_div.m2_frac_en = clk_div.m2_frac != 0;
vco = best_clock.vco;
- if (clock > 270000)
- clk_div.lanestagger = 0x18;
- else if (clock > 135000)
- clk_div.lanestagger = 0x0d;
- else if (clock > 67000)
- clk_div.lanestagger = 0x07;
- else if (clock > 33000)
- clk_div.lanestagger = 0x04;
- else
- clk_div.lanestagger = 0x02;
} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
intel_encoder->type == INTEL_OUTPUT_EDP) {
struct drm_encoder *encoder = &intel_encoder->base;
@@ -1439,6 +1428,17 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
return false;
}
+ if (clock > 270000)
+ lanestagger = 0x18;
+ else if (clock > 135000)
+ lanestagger = 0x0d;
+ else if (clock > 67000)
+ lanestagger = 0x07;
+ else if (clock > 33000)
+ lanestagger = 0x04;
+ else
+ lanestagger = 0x02;
+
crtc_state->dpll_hw_state.ebb0 =
PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
@@ -1462,7 +1462,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp);
crtc_state->dpll_hw_state.pcsdw12 =
- LANESTAGGER_STRAP_OVRD | clk_div.lanestagger;
+ LANESTAGGER_STRAP_OVRD | lanestagger;
pll = intel_get_shared_dpll(intel_crtc, crtc_state);
if (pll == NULL) {
--
2.0.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v3 1/2] drm/i915/bxt: Port PLL programming BUN
2015-05-13 6:48 ` [PATCH v3 " Vandana Kannan
@ 2015-05-18 16:26 ` Imre Deak
0 siblings, 0 replies; 11+ messages in thread
From: Imre Deak @ 2015-05-18 16:26 UTC (permalink / raw)
To: Vandana Kannan; +Cc: intel-gfx
On ke, 2015-05-13 at 12:18 +0530, Vandana Kannan wrote:
> BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to
> VCO frequencies. Program i_lockthresh in PORT_PLL_9.
>
> VCO calculated based on the formula:
> Desired Output = Port bit rate in MHz (DisplayPort HBR2 is 5400 MHz)
> Fast Clock = Desired Output / 2
> VCO = Fast Clock * P1 * P2
>
> Prop_coeff, int_coeff, and tdctargetcnt modified according to above
> calculation.
>
> BUN 2: Port PLLs require additional programming at certain frequencies -
> DCO amplitude in PORT_PLL_10
>
> Review comments from Siva which were addressed in the initial version of the
> patch.
> - Change PORT_PLL_LOCK_THRESHOLD to PORT_PLL_LOCK_THRESHOLD_MASK
> - Calculate for HDMI
> - Correct values for vco = 5.4
> - return in case of invalid vco range
>
> v2: Imre's review comments addressed
> - change dcoampovr_en to dcoampovr_en_h
> - change PORT_PLL_DCO_AMP_OVR_EN to PORT_PLL_DCO_AMP_OVR_EN_H
> - Correct lane stagger value for 324MHz
> - Make coef common for HDMI and DP
> - remove superfluous comments
>
> v3: Imre's comments addressed
> - Remove Prop_coeff, int_coeff, tdctargetcnt, dcoampovr_en, gain_ctl,
> dcoampovr_en_h from bxt_clk_div and make them local variables.
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com> [v1]
> Cc: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Looks ok:
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 6 +++
> drivers/gpu/drm/i915/intel_ddi.c | 79 ++++++++++++++++++++++++++++------------
> 3 files changed, 63 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 136d42a..05a4e1c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -304,7 +304,7 @@ struct intel_dpll_hw_state {
> uint32_t cfgcr1, cfgcr2;
>
> /* bxt */
> - uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pcsdw12;
> + uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pll10, pcsdw12;
> };
>
> struct intel_shared_dpll_config {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1b31238..b086d26 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1185,6 +1185,12 @@ enum skl_disp_power_wells {
> #define PORT_PLL_GAIN_CTL(x) ((x) << 16)
> /* PORT_PLL_8_A */
> #define PORT_PLL_TARGET_CNT_MASK 0x3FF
> +/* PORT_PLL_9_A */
> +#define PORT_PLL_LOCK_THRESHOLD_MASK 0xe
> +/* PORT_PLL_10_A */
> +#define PORT_PLL_DCO_AMP_OVR_EN_H (1<<27)
> +#define PORT_PLL_DCO_AMP_MASK 0x3c00
> +#define PORT_PLL_DCO_AMP(x) (x<<10)
> #define _PORT_PLL_BASE(port) _PORT3(port, _PORT_PLL_0_A, \
> _PORT_PLL_0_B, \
> _PORT_PLL_0_C)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 9c1e74a..a56613c 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1333,22 +1333,18 @@ struct bxt_clk_div {
> uint32_t m2_frac;
> bool m2_frac_en;
> uint32_t n;
> - uint32_t prop_coef;
> - uint32_t int_coef;
> - uint32_t gain_ctl;
> - uint32_t targ_cnt;
> uint32_t lanestagger;
> };
>
> /* pre-calculated values for DP linkrates */
> static struct bxt_clk_div bxt_dp_clk_val[7] = {
> - /* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> - /* 270 */ {4, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0xd},
> - /* 540 */ {2, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0x18},
> - /* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> - /* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd},
> - /* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd},
> - /* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18}
> + /* 162 */ {4, 2, 32, 1677722, 1, 1, 0xd},
> + /* 270 */ {4, 1, 27, 0, 0, 1, 0xd},
> + /* 540 */ {2, 1, 27, 0, 0, 1, 0x18},
> + /* 216 */ {3, 2, 32, 1677722, 1, 1, 0xd},
> + /* 243 */ {4, 1, 24, 1258291, 1, 1, 0xd},
> + /* 324 */ {4, 1, 32, 1677722, 1, 1, 0x18},
> + /* 432 */ {3, 1, 32, 1677722, 1, 1, 0x18}
> };
>
> static bool
> @@ -1359,6 +1355,9 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
> {
> struct intel_shared_dpll *pll;
> struct bxt_clk_div clk_div = {0};
> + int vco = 0;
> + uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
> + uint32_t dcoampovr_en_h, dco_amp;
>
> if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
> intel_clock_t best_clock;
> @@ -1382,11 +1381,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
> clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
> clk_div.m2_frac_en = clk_div.m2_frac != 0;
>
> - /* FIXME: set coef, gain, targcnt based on freq band */
> - clk_div.prop_coef = 5;
> - clk_div.int_coef = 11;
> - clk_div.gain_ctl = 2;
> - clk_div.targ_cnt = 9;
> + vco = best_clock.vco;
> if (clock > 270000)
> clk_div.lanestagger = 0x18;
> else if (clock > 135000)
> @@ -1416,6 +1411,32 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
> clk_div = bxt_dp_clk_val[0];
> DRM_ERROR("Unknown link rate\n");
> }
> + vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
> + }
> +
> + dco_amp = 15;
> + dcoampovr_en_h = 0;
> + if (vco >= 6200000 && vco <= 6480000) {
> + prop_coef = 4;
> + int_coef = 9;
> + gain_ctl = 3;
> + targ_cnt = 8;
> + } else if ((vco > 5400000 && vco < 6200000) ||
> + (vco >= 4800000 && vco < 5400000)) {
> + prop_coef = 5;
> + int_coef = 11;
> + gain_ctl = 3;
> + targ_cnt = 9;
> + if (vco >= 4800000 && vco < 5400000)
> + dcoampovr_en_h = 1;
> + } else if (vco == 5400000) {
> + prop_coef = 3;
> + int_coef = 8;
> + gain_ctl = 1;
> + targ_cnt = 9;
> + } else {
> + DRM_ERROR("Invalid VCO\n");
> + return false;
> }
>
> crtc_state->dpll_hw_state.ebb0 =
> @@ -1429,11 +1450,16 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
> PORT_PLL_M2_FRAC_ENABLE;
>
> crtc_state->dpll_hw_state.pll6 =
> - clk_div.prop_coef | PORT_PLL_INT_COEFF(clk_div.int_coef);
> + prop_coef | PORT_PLL_INT_COEFF(int_coef);
> crtc_state->dpll_hw_state.pll6 |=
> - PORT_PLL_GAIN_CTL(clk_div.gain_ctl);
> + PORT_PLL_GAIN_CTL(gain_ctl);
> +
> + crtc_state->dpll_hw_state.pll8 = targ_cnt;
>
> - crtc_state->dpll_hw_state.pll8 = clk_div.targ_cnt;
> + if (dcoampovr_en_h)
> + crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H;
> +
> + crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp);
>
> crtc_state->dpll_hw_state.pcsdw12 =
> LANESTAGGER_STRAP_OVRD | clk_div.lanestagger;
> @@ -2366,10 +2392,16 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
> temp |= pll->config.hw_state.pll8;
> I915_WRITE(BXT_PORT_PLL(port, 8), temp);
>
> - /*
> - * FIXME: program PORT_PLL_9/i_lockthresh according to the latest
> - * specification update.
> - */
> + temp = I915_READ(BXT_PORT_PLL(port, 9));
> + temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
> + temp |= (5 << 1);
> + I915_WRITE(BXT_PORT_PLL(port, 9), temp);
> +
> + temp = I915_READ(BXT_PORT_PLL(port, 10));
> + temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
> + temp &= ~PORT_PLL_DCO_AMP_MASK;
> + temp |= pll->config.hw_state.pll10;
> + I915_WRITE(BXT_PORT_PLL(port, 10), temp);
>
> /* Recalibrate with new settings */
> temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
> @@ -2433,6 +2465,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
> hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
> hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
> hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
> + hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
> /*
> * While we write to the group register to program all lanes at once we
> * can read only lane registers. We configure all lanes the same way, so
_______________________________________________
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 2/2] drm/i915/bxt: Move around lane stagger calculation
2015-05-13 6:50 ` [PATCH v2 " Vandana Kannan
@ 2015-05-18 16:28 ` Imre Deak
2015-05-19 8:04 ` Daniel Vetter
0 siblings, 1 reply; 11+ messages in thread
From: Imre Deak @ 2015-05-18 16:28 UTC (permalink / raw)
To: Vandana Kannan; +Cc: intel-gfx
On ke, 2015-05-13 at 12:20 +0530, Vandana Kannan wrote:
> Making lane stagger calculation common for HDMI and DP
>
> v2: Imre's comments addressed
> - Remove lane stagger from bxt_clk_div and make it a local variable in
> ddi_pll_select
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 40 ++++++++++++++++++++--------------------
> 1 file changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index a56613c..aadd29e 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1333,18 +1333,17 @@ struct bxt_clk_div {
> uint32_t m2_frac;
> bool m2_frac_en;
> uint32_t n;
> - uint32_t lanestagger;
> };
>
> /* pre-calculated values for DP linkrates */
> static struct bxt_clk_div bxt_dp_clk_val[7] = {
> - /* 162 */ {4, 2, 32, 1677722, 1, 1, 0xd},
> - /* 270 */ {4, 1, 27, 0, 0, 1, 0xd},
> - /* 540 */ {2, 1, 27, 0, 0, 1, 0x18},
> - /* 216 */ {3, 2, 32, 1677722, 1, 1, 0xd},
> - /* 243 */ {4, 1, 24, 1258291, 1, 1, 0xd},
> - /* 324 */ {4, 1, 32, 1677722, 1, 1, 0x18},
> - /* 432 */ {3, 1, 32, 1677722, 1, 1, 0x18}
> + /* 162 */ {4, 2, 32, 1677722, 1, 1},
> + /* 270 */ {4, 1, 27, 0, 0, 1},
> + /* 540 */ {2, 1, 27, 0, 0, 1},
> + /* 216 */ {3, 2, 32, 1677722, 1, 1},
> + /* 243 */ {4, 1, 24, 1258291, 1, 1},
> + /* 324 */ {4, 1, 32, 1677722, 1, 1},
> + /* 432 */ {3, 1, 32, 1677722, 1, 1}
> };
>
> static bool
> @@ -1357,7 +1356,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
> struct bxt_clk_div clk_div = {0};
> int vco = 0;
> uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
> - uint32_t dcoampovr_en_h, dco_amp;
> + uint32_t dcoampovr_en_h, dco_amp, lanestagger;
>
> if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
> intel_clock_t best_clock;
> @@ -1382,16 +1381,6 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
> clk_div.m2_frac_en = clk_div.m2_frac != 0;
>
> vco = best_clock.vco;
> - if (clock > 270000)
> - clk_div.lanestagger = 0x18;
> - else if (clock > 135000)
> - clk_div.lanestagger = 0x0d;
> - else if (clock > 67000)
> - clk_div.lanestagger = 0x07;
> - else if (clock > 33000)
> - clk_div.lanestagger = 0x04;
> - else
> - clk_div.lanestagger = 0x02;
> } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
> intel_encoder->type == INTEL_OUTPUT_EDP) {
> struct drm_encoder *encoder = &intel_encoder->base;
> @@ -1439,6 +1428,17 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
> return false;
> }
>
> + if (clock > 270000)
> + lanestagger = 0x18;
> + else if (clock > 135000)
> + lanestagger = 0x0d;
> + else if (clock > 67000)
> + lanestagger = 0x07;
> + else if (clock > 33000)
> + lanestagger = 0x04;
> + else
> + lanestagger = 0x02;
> +
> crtc_state->dpll_hw_state.ebb0 =
> PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
> crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
> @@ -1462,7 +1462,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
> crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp);
>
> crtc_state->dpll_hw_state.pcsdw12 =
> - LANESTAGGER_STRAP_OVRD | clk_div.lanestagger;
> + LANESTAGGER_STRAP_OVRD | lanestagger;
>
> pll = intel_get_shared_dpll(intel_crtc, crtc_state);
> if (pll == NULL) {
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 2/2] drm/i915/bxt: Move around lane stagger calculation
2015-05-18 16:28 ` Imre Deak
@ 2015-05-19 8:04 ` Daniel Vetter
0 siblings, 0 replies; 11+ messages in thread
From: Daniel Vetter @ 2015-05-19 8:04 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Mon, May 18, 2015 at 07:28:04PM +0300, Imre Deak wrote:
> On ke, 2015-05-13 at 12:20 +0530, Vandana Kannan wrote:
> > Making lane stagger calculation common for HDMI and DP
> >
> > v2: Imre's comments addressed
> > - Remove lane stagger from bxt_clk_div and make it a local variable in
> > ddi_pll_select
> >
> > Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
>
> Reviewed-by: Imre Deak <imre.deak@intel.com>
Both patches applied, thanks.
-Daniel
>
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 40 ++++++++++++++++++++--------------------
> > 1 file changed, 20 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index a56613c..aadd29e 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1333,18 +1333,17 @@ struct bxt_clk_div {
> > uint32_t m2_frac;
> > bool m2_frac_en;
> > uint32_t n;
> > - uint32_t lanestagger;
> > };
> >
> > /* pre-calculated values for DP linkrates */
> > static struct bxt_clk_div bxt_dp_clk_val[7] = {
> > - /* 162 */ {4, 2, 32, 1677722, 1, 1, 0xd},
> > - /* 270 */ {4, 1, 27, 0, 0, 1, 0xd},
> > - /* 540 */ {2, 1, 27, 0, 0, 1, 0x18},
> > - /* 216 */ {3, 2, 32, 1677722, 1, 1, 0xd},
> > - /* 243 */ {4, 1, 24, 1258291, 1, 1, 0xd},
> > - /* 324 */ {4, 1, 32, 1677722, 1, 1, 0x18},
> > - /* 432 */ {3, 1, 32, 1677722, 1, 1, 0x18}
> > + /* 162 */ {4, 2, 32, 1677722, 1, 1},
> > + /* 270 */ {4, 1, 27, 0, 0, 1},
> > + /* 540 */ {2, 1, 27, 0, 0, 1},
> > + /* 216 */ {3, 2, 32, 1677722, 1, 1},
> > + /* 243 */ {4, 1, 24, 1258291, 1, 1},
> > + /* 324 */ {4, 1, 32, 1677722, 1, 1},
> > + /* 432 */ {3, 1, 32, 1677722, 1, 1}
> > };
> >
> > static bool
> > @@ -1357,7 +1356,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
> > struct bxt_clk_div clk_div = {0};
> > int vco = 0;
> > uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
> > - uint32_t dcoampovr_en_h, dco_amp;
> > + uint32_t dcoampovr_en_h, dco_amp, lanestagger;
> >
> > if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
> > intel_clock_t best_clock;
> > @@ -1382,16 +1381,6 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
> > clk_div.m2_frac_en = clk_div.m2_frac != 0;
> >
> > vco = best_clock.vco;
> > - if (clock > 270000)
> > - clk_div.lanestagger = 0x18;
> > - else if (clock > 135000)
> > - clk_div.lanestagger = 0x0d;
> > - else if (clock > 67000)
> > - clk_div.lanestagger = 0x07;
> > - else if (clock > 33000)
> > - clk_div.lanestagger = 0x04;
> > - else
> > - clk_div.lanestagger = 0x02;
> > } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
> > intel_encoder->type == INTEL_OUTPUT_EDP) {
> > struct drm_encoder *encoder = &intel_encoder->base;
> > @@ -1439,6 +1428,17 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
> > return false;
> > }
> >
> > + if (clock > 270000)
> > + lanestagger = 0x18;
> > + else if (clock > 135000)
> > + lanestagger = 0x0d;
> > + else if (clock > 67000)
> > + lanestagger = 0x07;
> > + else if (clock > 33000)
> > + lanestagger = 0x04;
> > + else
> > + lanestagger = 0x02;
> > +
> > crtc_state->dpll_hw_state.ebb0 =
> > PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
> > crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
> > @@ -1462,7 +1462,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
> > crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp);
> >
> > crtc_state->dpll_hw_state.pcsdw12 =
> > - LANESTAGGER_STRAP_OVRD | clk_div.lanestagger;
> > + LANESTAGGER_STRAP_OVRD | lanestagger;
> >
> > pll = intel_get_shared_dpll(intel_crtc, crtc_state);
> > if (pll == NULL) {
>
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2015-05-19 8:02 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-05-07 6:30 [PATCH v2 1/2] drm/i915/bxt: Port PLL programming BUN Vandana Kannan
2015-05-07 6:30 ` [PATCH 2/2] drm/i915/bxt: Move around lane stagger calculation Vandana Kannan
2015-05-07 13:07 ` Imre Deak
2015-05-13 6:50 ` [PATCH v2 " Vandana Kannan
2015-05-18 16:28 ` Imre Deak
2015-05-19 8:04 ` Daniel Vetter
2015-05-07 21:22 ` [PATCH " shuang.he
2015-05-07 9:27 ` [PATCH v2 1/2] drm/i915/bxt: Port PLL programming BUN Imre Deak
2015-05-11 14:39 ` Kannan, Vandana
2015-05-13 6:48 ` [PATCH v3 " Vandana Kannan
2015-05-18 16:26 ` Imre Deak
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