* [PATCH 0/2] pinctrl: zynq: fix two bugs of zynq pinmux function
@ 2015-05-20 8:38 ` Masahiro Yamada
0 siblings, 0 replies; 6+ messages in thread
From: Masahiro Yamada @ 2015-05-20 8:38 UTC (permalink / raw)
To: linux-serial
Cc: Masahiro Yamada, Sören Brinkmann, Michal Simek,
Linus Walleij, linux-kernel, linux-gpio, linux-arm-kernel
Masahiro Yamada (2):
pinctrl: zynq: fix DEFINE_ZYNQ_PINMUX_FUNCTION_MUX macro
pinctrl: zynq: fix offset address for {SD0,SD1}_WP_CD_SEL
drivers/pinctrl/pinctrl-zynq.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 0/2] pinctrl: zynq: fix two bugs of zynq pinmux function
@ 2015-05-20 8:38 ` Masahiro Yamada
0 siblings, 0 replies; 6+ messages in thread
From: Masahiro Yamada @ 2015-05-20 8:38 UTC (permalink / raw)
To: linux-arm-kernel
Masahiro Yamada (2):
pinctrl: zynq: fix DEFINE_ZYNQ_PINMUX_FUNCTION_MUX macro
pinctrl: zynq: fix offset address for {SD0,SD1}_WP_CD_SEL
drivers/pinctrl/pinctrl-zynq.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] pinctrl: zynq: fix DEFINE_ZYNQ_PINMUX_FUNCTION_MUX macro
2015-05-20 8:38 ` Masahiro Yamada
@ 2015-05-20 8:38 ` Masahiro Yamada
-1 siblings, 0 replies; 6+ messages in thread
From: Masahiro Yamada @ 2015-05-20 8:38 UTC (permalink / raw)
To: linux-serial
Cc: Masahiro Yamada, Sören Brinkmann, Michal Simek,
Linus Walleij, linux-kernel, linux-gpio, linux-arm-kernel
The offset to the mux register is missing.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/pinctrl/pinctrl-zynq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c
index 3d5453a..77c5a98 100644
--- a/drivers/pinctrl/pinctrl-zynq.c
+++ b/drivers/pinctrl/pinctrl-zynq.c
@@ -714,12 +714,13 @@ static const char * const gpio0_groups[] = {"gpio0_0_grp",
.mux_val = mval, \
}
-#define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, mux, mask, shift) \
+#define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, offset, mask, shift)\
[ZYNQ_PMUX_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
.mux_val = mval, \
+ .mux = offset, \
.mux_mask = mask, \
.mux_shift = shift, \
}
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 1/2] pinctrl: zynq: fix DEFINE_ZYNQ_PINMUX_FUNCTION_MUX macro
@ 2015-05-20 8:38 ` Masahiro Yamada
0 siblings, 0 replies; 6+ messages in thread
From: Masahiro Yamada @ 2015-05-20 8:38 UTC (permalink / raw)
To: linux-arm-kernel
The offset to the mux register is missing.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/pinctrl/pinctrl-zynq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c
index 3d5453a..77c5a98 100644
--- a/drivers/pinctrl/pinctrl-zynq.c
+++ b/drivers/pinctrl/pinctrl-zynq.c
@@ -714,12 +714,13 @@ static const char * const gpio0_groups[] = {"gpio0_0_grp",
.mux_val = mval, \
}
-#define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, mux, mask, shift) \
+#define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, offset, mask, shift)\
[ZYNQ_PMUX_##fname] = { \
.name = #fname, \
.groups = fname##_groups, \
.ngroups = ARRAY_SIZE(fname##_groups), \
.mux_val = mval, \
+ .mux = offset, \
.mux_mask = mask, \
.mux_shift = shift, \
}
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] pinctrl: zynq: fix offset address for {SD0,SD1}_WP_CD_SEL
2015-05-20 8:38 ` Masahiro Yamada
@ 2015-05-20 8:38 ` Masahiro Yamada
-1 siblings, 0 replies; 6+ messages in thread
From: Masahiro Yamada @ 2015-05-20 8:38 UTC (permalink / raw)
To: linux-serial
Cc: Masahiro Yamada, Sören Brinkmann, Michal Simek,
Linus Walleij, linux-kernel, linux-gpio, linux-arm-kernel
The address for SD0_WP_CD_SEL, SD1_WP_CD_SEL is 0xf8000830,
0xf8000834, respectively.
Each offset address must be prefixed with 0x.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/pinctrl/pinctrl-zynq.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c
index 77c5a98..04748a4 100644
--- a/drivers/pinctrl/pinctrl-zynq.c
+++ b/drivers/pinctrl/pinctrl-zynq.c
@@ -745,15 +745,15 @@ static const struct zynq_pinmux_function zynq_pmux_functions[] = {
DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50),
DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40),
DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc),
- DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 130, ZYNQ_SDIO_WP_MASK,
+ DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 0x130, ZYNQ_SDIO_WP_MASK,
ZYNQ_SDIO_WP_SHIFT),
- DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 130, ZYNQ_SDIO_CD_MASK,
+ DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 0x130, ZYNQ_SDIO_CD_MASK,
ZYNQ_SDIO_CD_SHIFT),
DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1, 0x40),
DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1_pc, 0xc),
- DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 134, ZYNQ_SDIO_WP_MASK,
+ DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 0x134, ZYNQ_SDIO_WP_MASK,
ZYNQ_SDIO_WP_SHIFT),
- DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 134, ZYNQ_SDIO_CD_MASK,
+ DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 0x134, ZYNQ_SDIO_CD_MASK,
ZYNQ_SDIO_CD_SHIFT),
DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor, 4),
DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_cs1, 8),
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] pinctrl: zynq: fix offset address for {SD0, SD1}_WP_CD_SEL
@ 2015-05-20 8:38 ` Masahiro Yamada
0 siblings, 0 replies; 6+ messages in thread
From: Masahiro Yamada @ 2015-05-20 8:38 UTC (permalink / raw)
To: linux-arm-kernel
The address for SD0_WP_CD_SEL, SD1_WP_CD_SEL is 0xf8000830,
0xf8000834, respectively.
Each offset address must be prefixed with 0x.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
drivers/pinctrl/pinctrl-zynq.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c
index 77c5a98..04748a4 100644
--- a/drivers/pinctrl/pinctrl-zynq.c
+++ b/drivers/pinctrl/pinctrl-zynq.c
@@ -745,15 +745,15 @@ static const struct zynq_pinmux_function zynq_pmux_functions[] = {
DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50),
DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40),
DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc),
- DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 130, ZYNQ_SDIO_WP_MASK,
+ DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 0x130, ZYNQ_SDIO_WP_MASK,
ZYNQ_SDIO_WP_SHIFT),
- DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 130, ZYNQ_SDIO_CD_MASK,
+ DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 0x130, ZYNQ_SDIO_CD_MASK,
ZYNQ_SDIO_CD_SHIFT),
DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1, 0x40),
DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1_pc, 0xc),
- DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 134, ZYNQ_SDIO_WP_MASK,
+ DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 0x134, ZYNQ_SDIO_WP_MASK,
ZYNQ_SDIO_WP_SHIFT),
- DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 134, ZYNQ_SDIO_CD_MASK,
+ DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 0x134, ZYNQ_SDIO_CD_MASK,
ZYNQ_SDIO_CD_SHIFT),
DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor, 4),
DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_cs1, 8),
--
1.9.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-05-20 8:38 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-05-20 8:38 [PATCH 0/2] pinctrl: zynq: fix two bugs of zynq pinmux function Masahiro Yamada
2015-05-20 8:38 ` Masahiro Yamada
2015-05-20 8:38 ` [PATCH 1/2] pinctrl: zynq: fix DEFINE_ZYNQ_PINMUX_FUNCTION_MUX macro Masahiro Yamada
2015-05-20 8:38 ` Masahiro Yamada
2015-05-20 8:38 ` [PATCH 2/2] pinctrl: zynq: fix offset address for {SD0,SD1}_WP_CD_SEL Masahiro Yamada
2015-05-20 8:38 ` [PATCH 2/2] pinctrl: zynq: fix offset address for {SD0, SD1}_WP_CD_SEL Masahiro Yamada
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