* [PATCH 0/3] drm/i915: CHV DPIO and PFI stuff
@ 2015-05-26 17:22 ville.syrjala
2015-05-26 17:22 ` [PATCH 1/3] drm/i915: Use the default 600ns LDO programming sequence delay ville.syrjala
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: ville.syrjala @ 2015-05-26 17:22 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The two DPIO patches here were part of my DPIO powergating series, but as the
actualy DPIO powergating needs further work I've left that particular patch
behind for now. These other two are good to go without it however so here they
are. I clarified the pipe-a power well comment a bit for Deepak, and I decided
to rename it to "display" to make dmesg less confusing for people.
The PFI credit thing I've had around for a while, just forgot to send it out.
Ville Syrjälä (3):
drm/i915: Use the default 600ns LDO programming sequence delay
drm/i915: Throw out WIP CHV power well definitions
drm/i915: Bump CHV PFI credits to 63 when cdclk>=czclk
drivers/gpu/drm/i915/i915_reg.h | 8 +--
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 100 ++------------------------------
3 files changed, 11 insertions(+), 99 deletions(-)
--
2.3.6
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^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 1/3] drm/i915: Use the default 600ns LDO programming sequence delay 2015-05-26 17:22 [PATCH 0/3] drm/i915: CHV DPIO and PFI stuff ville.syrjala @ 2015-05-26 17:22 ` ville.syrjala 2015-05-26 17:22 ` [PATCH 2/3] drm/i915: Throw out WIP CHV power well definitions ville.syrjala 2015-05-26 17:22 ` [PATCH 3/3] drm/i915: Bump CHV PFI credits to 63 when cdclk>=czclk ville.syrjala 2 siblings, 0 replies; 8+ messages in thread From: ville.syrjala @ 2015-05-26 17:22 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Not sure which LDO programming sequence delay should be used for the CHV PHY, but the spec says that 600ns is "Used by default for initial bringup", and the BIOS seems to use that, so let's do the same. Reviewed-by: Deepak S <deepak.s@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 4 ++++ drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6eeba63..fb49989 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2145,6 +2145,10 @@ enum skl_disp_power_wells { #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240) #define DPLL_PORTD_READY_MASK (0xf) #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100) +#define PHY_LDO_DELAY_0NS 0x0 +#define PHY_LDO_DELAY_200NS 0x1 +#define PHY_LDO_DELAY_600NS 0x2 +#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2*(phy)+23)) #define PHY_CH_SU_PSR 0x1 #define PHY_CH_DEEP_PSR 0x7 #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2)) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 3800be4..720b0c6 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -1724,6 +1724,8 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv) * value. */ dev_priv->chv_phy_control = + PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | + PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY0, DPIO_CH0) | PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY0, DPIO_CH1) | PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY1, DPIO_CH0); -- 2.3.6 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/3] drm/i915: Throw out WIP CHV power well definitions 2015-05-26 17:22 [PATCH 0/3] drm/i915: CHV DPIO and PFI stuff ville.syrjala 2015-05-26 17:22 ` [PATCH 1/3] drm/i915: Use the default 600ns LDO programming sequence delay ville.syrjala @ 2015-05-26 17:22 ` ville.syrjala 2015-05-27 12:06 ` Daniel Vetter 2015-05-26 17:22 ` [PATCH 3/3] drm/i915: Bump CHV PFI credits to 63 when cdclk>=czclk ville.syrjala 2 siblings, 1 reply; 8+ messages in thread From: ville.syrjala @ 2015-05-26 17:22 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Expecting CHV power wells to be just an extended versions of the VLV power wells, a bunch of commented out power wells were added in anticipation when Punit folks would implement it all. Turns out they never did, and instead CHV has fewer power wells than VLV. Rip out all the #if 0'ed junk that's not needed. v2: Rename the "pipe-a" well to "display" to match VLV Clarify the pipe A power well relationship to pipes B and C (Deepak) Reviewed-by: Deepak S <deepak.s@linux.intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 4 -- drivers/gpu/drm/i915/intel_runtime_pm.c | 98 ++------------------------------- 2 files changed, 4 insertions(+), 98 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fb49989..f5edb35 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -595,10 +595,6 @@ enum punit_power_well { PUNIT_POWER_WELL_DPIO_RX0 = 10, PUNIT_POWER_WELL_DPIO_RX1 = 11, PUNIT_POWER_WELL_DPIO_CMN_D = 12, - /* FIXME: guesswork below */ - PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 = 13, - PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 = 14, - PUNIT_POWER_WELL_DPIO_RX2 = 15, PUNIT_POWER_WELL_NUM, }; diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 720b0c6..1a45385 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -1233,18 +1233,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, BIT(POWER_DOMAIN_AUX_C) | \ BIT(POWER_DOMAIN_INIT)) -#define CHV_PIPE_A_POWER_DOMAINS ( \ - BIT(POWER_DOMAIN_PIPE_A) | \ - BIT(POWER_DOMAIN_INIT)) - -#define CHV_PIPE_B_POWER_DOMAINS ( \ - BIT(POWER_DOMAIN_PIPE_B) | \ - BIT(POWER_DOMAIN_INIT)) - -#define CHV_PIPE_C_POWER_DOMAINS ( \ - BIT(POWER_DOMAIN_PIPE_C) | \ - BIT(POWER_DOMAIN_INIT)) - #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ @@ -1260,17 +1248,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, BIT(POWER_DOMAIN_AUX_D) | \ BIT(POWER_DOMAIN_INIT)) -#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \ - BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ - BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ - BIT(POWER_DOMAIN_AUX_D) | \ - BIT(POWER_DOMAIN_INIT)) - -#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \ - BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ - BIT(POWER_DOMAIN_AUX_D) | \ - BIT(POWER_DOMAIN_INIT)) - static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { .sync_hw = i9xx_always_on_power_well_noop, .enable = i9xx_always_on_power_well_noop, @@ -1428,40 +1405,17 @@ static struct i915_power_well chv_power_wells[] = { .domains = VLV_ALWAYS_ON_POWER_DOMAINS, .ops = &i9xx_always_on_power_well_ops, }, -#if 0 { .name = "display", - .domains = VLV_DISPLAY_POWER_DOMAINS, - .data = PUNIT_POWER_WELL_DISP2D, - .ops = &vlv_display_power_well_ops, - }, -#endif - { - .name = "pipe-a", /* - * FIXME: pipe A power well seems to be the new disp2d well. - * At least all registers seem to be housed there. Figure - * out if this a a temporary situation in pre-production - * hardware or a permanent state of affairs. + * Pipe A power well is the new disp2d well. Pipe B and C + * power wells don't actually exist. Pipe A power well is + * required for any pipe to work. */ - .domains = CHV_PIPE_A_POWER_DOMAINS | VLV_DISPLAY_POWER_DOMAINS, + .domains = VLV_DISPLAY_POWER_DOMAINS, .data = PIPE_A, .ops = &chv_pipe_power_well_ops, }, -#if 0 - { - .name = "pipe-b", - .domains = CHV_PIPE_B_POWER_DOMAINS, - .data = PIPE_B, - .ops = &chv_pipe_power_well_ops, - }, - { - .name = "pipe-c", - .domains = CHV_PIPE_C_POWER_DOMAINS, - .data = PIPE_C, - .ops = &chv_pipe_power_well_ops, - }, -#endif { .name = "dpio-common-bc", .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, @@ -1474,50 +1428,6 @@ static struct i915_power_well chv_power_wells[] = { .data = PUNIT_POWER_WELL_DPIO_CMN_D, .ops = &chv_dpio_cmn_power_well_ops, }, -#if 0 - { - .name = "dpio-tx-b-01", - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, - .ops = &vlv_dpio_power_well_ops, - .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, - }, - { - .name = "dpio-tx-b-23", - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, - .ops = &vlv_dpio_power_well_ops, - .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, - }, - { - .name = "dpio-tx-c-01", - .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, - .ops = &vlv_dpio_power_well_ops, - .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, - }, - { - .name = "dpio-tx-c-23", - .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, - .ops = &vlv_dpio_power_well_ops, - .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, - }, - { - .name = "dpio-tx-d-01", - .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | - CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, - .ops = &vlv_dpio_power_well_ops, - .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01, - }, - { - .name = "dpio-tx-d-23", - .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | - CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, - .ops = &vlv_dpio_power_well_ops, - .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23, - }, -#endif }; static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, -- 2.3.6 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] drm/i915: Throw out WIP CHV power well definitions 2015-05-26 17:22 ` [PATCH 2/3] drm/i915: Throw out WIP CHV power well definitions ville.syrjala @ 2015-05-27 12:06 ` Daniel Vetter 2015-05-28 6:29 ` Ville Syrjälä 0 siblings, 1 reply; 8+ messages in thread From: Daniel Vetter @ 2015-05-27 12:06 UTC (permalink / raw) To: ville.syrjala; +Cc: intel-gfx On Tue, May 26, 2015 at 08:22:39PM +0300, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Expecting CHV power wells to be just an extended versions of the VLV > power wells, a bunch of commented out power wells were added in > anticipation when Punit folks would implement it all. Turns out they > never did, and instead CHV has fewer power wells than VLV. Rip out all > the #if 0'ed junk that's not needed. > > v2: Rename the "pipe-a" well to "display" to match VLV > Clarify the pipe A power well relationship to pipes B and C (Deepak) > > Reviewed-by: Deepak S <deepak.s@linux.intel.com> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Merged patches 1&2 from this series, thanks. Btw did I not pull them in because of conflicts (since the other part of the original series aren't ready) or because I missed them? Thanks, Daniel > --- > drivers/gpu/drm/i915/i915_reg.h | 4 -- > drivers/gpu/drm/i915/intel_runtime_pm.c | 98 ++------------------------------- > 2 files changed, 4 insertions(+), 98 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index fb49989..f5edb35 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -595,10 +595,6 @@ enum punit_power_well { > PUNIT_POWER_WELL_DPIO_RX0 = 10, > PUNIT_POWER_WELL_DPIO_RX1 = 11, > PUNIT_POWER_WELL_DPIO_CMN_D = 12, > - /* FIXME: guesswork below */ > - PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 = 13, > - PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 = 14, > - PUNIT_POWER_WELL_DPIO_RX2 = 15, > > PUNIT_POWER_WELL_NUM, > }; > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > index 720b0c6..1a45385 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -1233,18 +1233,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, > BIT(POWER_DOMAIN_AUX_C) | \ > BIT(POWER_DOMAIN_INIT)) > > -#define CHV_PIPE_A_POWER_DOMAINS ( \ > - BIT(POWER_DOMAIN_PIPE_A) | \ > - BIT(POWER_DOMAIN_INIT)) > - > -#define CHV_PIPE_B_POWER_DOMAINS ( \ > - BIT(POWER_DOMAIN_PIPE_B) | \ > - BIT(POWER_DOMAIN_INIT)) > - > -#define CHV_PIPE_C_POWER_DOMAINS ( \ > - BIT(POWER_DOMAIN_PIPE_C) | \ > - BIT(POWER_DOMAIN_INIT)) > - > #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ > BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ > BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ > @@ -1260,17 +1248,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, > BIT(POWER_DOMAIN_AUX_D) | \ > BIT(POWER_DOMAIN_INIT)) > > -#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \ > - BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ > - BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ > - BIT(POWER_DOMAIN_AUX_D) | \ > - BIT(POWER_DOMAIN_INIT)) > - > -#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \ > - BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ > - BIT(POWER_DOMAIN_AUX_D) | \ > - BIT(POWER_DOMAIN_INIT)) > - > static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { > .sync_hw = i9xx_always_on_power_well_noop, > .enable = i9xx_always_on_power_well_noop, > @@ -1428,40 +1405,17 @@ static struct i915_power_well chv_power_wells[] = { > .domains = VLV_ALWAYS_ON_POWER_DOMAINS, > .ops = &i9xx_always_on_power_well_ops, > }, > -#if 0 > { > .name = "display", > - .domains = VLV_DISPLAY_POWER_DOMAINS, > - .data = PUNIT_POWER_WELL_DISP2D, > - .ops = &vlv_display_power_well_ops, > - }, > -#endif > - { > - .name = "pipe-a", > /* > - * FIXME: pipe A power well seems to be the new disp2d well. > - * At least all registers seem to be housed there. Figure > - * out if this a a temporary situation in pre-production > - * hardware or a permanent state of affairs. > + * Pipe A power well is the new disp2d well. Pipe B and C > + * power wells don't actually exist. Pipe A power well is > + * required for any pipe to work. > */ > - .domains = CHV_PIPE_A_POWER_DOMAINS | VLV_DISPLAY_POWER_DOMAINS, > + .domains = VLV_DISPLAY_POWER_DOMAINS, > .data = PIPE_A, > .ops = &chv_pipe_power_well_ops, > }, > -#if 0 > - { > - .name = "pipe-b", > - .domains = CHV_PIPE_B_POWER_DOMAINS, > - .data = PIPE_B, > - .ops = &chv_pipe_power_well_ops, > - }, > - { > - .name = "pipe-c", > - .domains = CHV_PIPE_C_POWER_DOMAINS, > - .data = PIPE_C, > - .ops = &chv_pipe_power_well_ops, > - }, > -#endif > { > .name = "dpio-common-bc", > .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, > @@ -1474,50 +1428,6 @@ static struct i915_power_well chv_power_wells[] = { > .data = PUNIT_POWER_WELL_DPIO_CMN_D, > .ops = &chv_dpio_cmn_power_well_ops, > }, > -#if 0 > - { > - .name = "dpio-tx-b-01", > - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | > - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, > - .ops = &vlv_dpio_power_well_ops, > - .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, > - }, > - { > - .name = "dpio-tx-b-23", > - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | > - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, > - .ops = &vlv_dpio_power_well_ops, > - .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, > - }, > - { > - .name = "dpio-tx-c-01", > - .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | > - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, > - .ops = &vlv_dpio_power_well_ops, > - .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, > - }, > - { > - .name = "dpio-tx-c-23", > - .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | > - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, > - .ops = &vlv_dpio_power_well_ops, > - .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, > - }, > - { > - .name = "dpio-tx-d-01", > - .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | > - CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, > - .ops = &vlv_dpio_power_well_ops, > - .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01, > - }, > - { > - .name = "dpio-tx-d-23", > - .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | > - CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, > - .ops = &vlv_dpio_power_well_ops, > - .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23, > - }, > -#endif > }; > > static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, > -- > 2.3.6 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/3] drm/i915: Throw out WIP CHV power well definitions 2015-05-27 12:06 ` Daniel Vetter @ 2015-05-28 6:29 ` Ville Syrjälä 0 siblings, 0 replies; 8+ messages in thread From: Ville Syrjälä @ 2015-05-28 6:29 UTC (permalink / raw) To: Daniel Vetter; +Cc: intel-gfx On Wed, May 27, 2015 at 02:06:27PM +0200, Daniel Vetter wrote: > On Tue, May 26, 2015 at 08:22:39PM +0300, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Expecting CHV power wells to be just an extended versions of the VLV > > power wells, a bunch of commented out power wells were added in > > anticipation when Punit folks would implement it all. Turns out they > > never did, and instead CHV has fewer power wells than VLV. Rip out all > > the #if 0'ed junk that's not needed. > > > > v2: Rename the "pipe-a" well to "display" to match VLV > > Clarify the pipe A power well relationship to pipes B and C (Deepak) > > > > Reviewed-by: Deepak S <deepak.s@linux.intel.com> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Merged patches 1&2 from this series, thanks. > > Btw did I not pull them in because of conflicts (since the other part of > the original series aren't ready) or because I missed them? I don't think there were conflicts. For patch 2 here I guess you just stopped merging at the previous patch which wasn't ready for primetime, and Deepak wanted some extra comments. Not sure why the other patch didn't get merged. And now I'm wondering why I sent them as a new thread instead of replying to the original. Oh well, the end result is good anyway. > > Thanks, Daniel > > > --- > > drivers/gpu/drm/i915/i915_reg.h | 4 -- > > drivers/gpu/drm/i915/intel_runtime_pm.c | 98 ++------------------------------- > > 2 files changed, 4 insertions(+), 98 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index fb49989..f5edb35 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -595,10 +595,6 @@ enum punit_power_well { > > PUNIT_POWER_WELL_DPIO_RX0 = 10, > > PUNIT_POWER_WELL_DPIO_RX1 = 11, > > PUNIT_POWER_WELL_DPIO_CMN_D = 12, > > - /* FIXME: guesswork below */ > > - PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 = 13, > > - PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 = 14, > > - PUNIT_POWER_WELL_DPIO_RX2 = 15, > > > > PUNIT_POWER_WELL_NUM, > > }; > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > > index 720b0c6..1a45385 100644 > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > > @@ -1233,18 +1233,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, > > BIT(POWER_DOMAIN_AUX_C) | \ > > BIT(POWER_DOMAIN_INIT)) > > > > -#define CHV_PIPE_A_POWER_DOMAINS ( \ > > - BIT(POWER_DOMAIN_PIPE_A) | \ > > - BIT(POWER_DOMAIN_INIT)) > > - > > -#define CHV_PIPE_B_POWER_DOMAINS ( \ > > - BIT(POWER_DOMAIN_PIPE_B) | \ > > - BIT(POWER_DOMAIN_INIT)) > > - > > -#define CHV_PIPE_C_POWER_DOMAINS ( \ > > - BIT(POWER_DOMAIN_PIPE_C) | \ > > - BIT(POWER_DOMAIN_INIT)) > > - > > #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ > > BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ > > BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ > > @@ -1260,17 +1248,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv, > > BIT(POWER_DOMAIN_AUX_D) | \ > > BIT(POWER_DOMAIN_INIT)) > > > > -#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \ > > - BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ > > - BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ > > - BIT(POWER_DOMAIN_AUX_D) | \ > > - BIT(POWER_DOMAIN_INIT)) > > - > > -#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \ > > - BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ > > - BIT(POWER_DOMAIN_AUX_D) | \ > > - BIT(POWER_DOMAIN_INIT)) > > - > > static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { > > .sync_hw = i9xx_always_on_power_well_noop, > > .enable = i9xx_always_on_power_well_noop, > > @@ -1428,40 +1405,17 @@ static struct i915_power_well chv_power_wells[] = { > > .domains = VLV_ALWAYS_ON_POWER_DOMAINS, > > .ops = &i9xx_always_on_power_well_ops, > > }, > > -#if 0 > > { > > .name = "display", > > - .domains = VLV_DISPLAY_POWER_DOMAINS, > > - .data = PUNIT_POWER_WELL_DISP2D, > > - .ops = &vlv_display_power_well_ops, > > - }, > > -#endif > > - { > > - .name = "pipe-a", > > /* > > - * FIXME: pipe A power well seems to be the new disp2d well. > > - * At least all registers seem to be housed there. Figure > > - * out if this a a temporary situation in pre-production > > - * hardware or a permanent state of affairs. > > + * Pipe A power well is the new disp2d well. Pipe B and C > > + * power wells don't actually exist. Pipe A power well is > > + * required for any pipe to work. > > */ > > - .domains = CHV_PIPE_A_POWER_DOMAINS | VLV_DISPLAY_POWER_DOMAINS, > > + .domains = VLV_DISPLAY_POWER_DOMAINS, > > .data = PIPE_A, > > .ops = &chv_pipe_power_well_ops, > > }, > > -#if 0 > > - { > > - .name = "pipe-b", > > - .domains = CHV_PIPE_B_POWER_DOMAINS, > > - .data = PIPE_B, > > - .ops = &chv_pipe_power_well_ops, > > - }, > > - { > > - .name = "pipe-c", > > - .domains = CHV_PIPE_C_POWER_DOMAINS, > > - .data = PIPE_C, > > - .ops = &chv_pipe_power_well_ops, > > - }, > > -#endif > > { > > .name = "dpio-common-bc", > > .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, > > @@ -1474,50 +1428,6 @@ static struct i915_power_well chv_power_wells[] = { > > .data = PUNIT_POWER_WELL_DPIO_CMN_D, > > .ops = &chv_dpio_cmn_power_well_ops, > > }, > > -#if 0 > > - { > > - .name = "dpio-tx-b-01", > > - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | > > - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, > > - .ops = &vlv_dpio_power_well_ops, > > - .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, > > - }, > > - { > > - .name = "dpio-tx-b-23", > > - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | > > - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, > > - .ops = &vlv_dpio_power_well_ops, > > - .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, > > - }, > > - { > > - .name = "dpio-tx-c-01", > > - .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | > > - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, > > - .ops = &vlv_dpio_power_well_ops, > > - .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, > > - }, > > - { > > - .name = "dpio-tx-c-23", > > - .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | > > - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, > > - .ops = &vlv_dpio_power_well_ops, > > - .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, > > - }, > > - { > > - .name = "dpio-tx-d-01", > > - .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | > > - CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, > > - .ops = &vlv_dpio_power_well_ops, > > - .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01, > > - }, > > - { > > - .name = "dpio-tx-d-23", > > - .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | > > - CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, > > - .ops = &vlv_dpio_power_well_ops, > > - .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23, > > - }, > > -#endif > > }; > > > > static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, > > -- > > 2.3.6 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > -- > Daniel Vetter > Software Engineer, Intel Corporation > http://blog.ffwll.ch -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/3] drm/i915: Bump CHV PFI credits to 63 when cdclk>=czclk 2015-05-26 17:22 [PATCH 0/3] drm/i915: CHV DPIO and PFI stuff ville.syrjala 2015-05-26 17:22 ` [PATCH 1/3] drm/i915: Use the default 600ns LDO programming sequence delay ville.syrjala 2015-05-26 17:22 ` [PATCH 2/3] drm/i915: Throw out WIP CHV power well definitions ville.syrjala @ 2015-05-26 17:22 ` ville.syrjala 2015-06-12 16:24 ` Clint Taylor 2 siblings, 1 reply; 8+ messages in thread From: ville.syrjala @ 2015-05-26 17:22 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> Switch from using 31 PFI credits to 63 PFI credits when cdclk>=czclk on CHV. The spec lists both 31 and 63 as "suggested" values, but based on feedback from hardware folks we should actually be using 63. Originally I picked the 31 basically by flipping a coin. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/intel_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 067b1de..44b9c54 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5986,7 +5986,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { /* CHV suggested value is 31 or 63 */ if (IS_CHERRYVIEW(dev_priv)) - credits = PFI_CREDIT_31; + credits = PFI_CREDIT_63; else credits = PFI_CREDIT(15); } else { -- 2.3.6 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] drm/i915: Bump CHV PFI credits to 63 when cdclk>=czclk 2015-05-26 17:22 ` [PATCH 3/3] drm/i915: Bump CHV PFI credits to 63 when cdclk>=czclk ville.syrjala @ 2015-06-12 16:24 ` Clint Taylor 2015-06-15 10:26 ` Daniel Vetter 0 siblings, 1 reply; 8+ messages in thread From: Clint Taylor @ 2015-06-12 16:24 UTC (permalink / raw) To: ville.syrjala, intel-gfx On 05/26/2015 10:22 AM, ville.syrjala@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Switch from using 31 PFI credits to 63 PFI credits when cdclk>=czclk on > CHV. The spec lists both 31 and 63 as "suggested" values, but based on > feedback from hardware folks we should actually be using 63. Originally > I picked the 31 basically by flipping a coin. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 067b1de..44b9c54 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5986,7 +5986,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) > if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { > /* CHV suggested value is 31 or 63 */ > if (IS_CHERRYVIEW(dev_priv)) > - credits = PFI_CREDIT_31; > + credits = PFI_CREDIT_63; > else > credits = PFI_CREDIT(15); > } else { > Although not part of this review the else clause is setting PFI_CREDIT to 15 when the BPSEC states that the default of 8 should be used when cdclk/czclk < 1. According to the original patch, 15 is the optimal value as stated by another driver team. Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 3/3] drm/i915: Bump CHV PFI credits to 63 when cdclk>=czclk 2015-06-12 16:24 ` Clint Taylor @ 2015-06-15 10:26 ` Daniel Vetter 0 siblings, 0 replies; 8+ messages in thread From: Daniel Vetter @ 2015-06-15 10:26 UTC (permalink / raw) To: Clint Taylor; +Cc: intel-gfx On Fri, Jun 12, 2015 at 09:24:24AM -0700, Clint Taylor wrote: > On 05/26/2015 10:22 AM, ville.syrjala@linux.intel.com wrote: > >From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > >Switch from using 31 PFI credits to 63 PFI credits when cdclk>=czclk on > >CHV. The spec lists both 31 and 63 as "suggested" values, but based on > >feedback from hardware folks we should actually be using 63. Originally > >I picked the 31 basically by flipping a coin. > > > >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > >--- > > drivers/gpu/drm/i915/intel_display.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > >diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > >index 067b1de..44b9c54 100644 > >--- a/drivers/gpu/drm/i915/intel_display.c > >+++ b/drivers/gpu/drm/i915/intel_display.c > >@@ -5986,7 +5986,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) > > if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { > > /* CHV suggested value is 31 or 63 */ > > if (IS_CHERRYVIEW(dev_priv)) > >- credits = PFI_CREDIT_31; > >+ credits = PFI_CREDIT_63; > > else > > credits = PFI_CREDIT(15); > > } else { > > > > Although not part of this review the else clause is setting PFI_CREDIT to 15 > when the BPSEC states that the default of 8 should be used when cdclk/czclk > < 1. According to the original patch, 15 is the optimal value as stated by > another driver team. Can you please file a bspec correction notice to fix the issue with the 15 vs. 8? > Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com> Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2015-06-15 10:23 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2015-05-26 17:22 [PATCH 0/3] drm/i915: CHV DPIO and PFI stuff ville.syrjala 2015-05-26 17:22 ` [PATCH 1/3] drm/i915: Use the default 600ns LDO programming sequence delay ville.syrjala 2015-05-26 17:22 ` [PATCH 2/3] drm/i915: Throw out WIP CHV power well definitions ville.syrjala 2015-05-27 12:06 ` Daniel Vetter 2015-05-28 6:29 ` Ville Syrjälä 2015-05-26 17:22 ` [PATCH 3/3] drm/i915: Bump CHV PFI credits to 63 when cdclk>=czclk ville.syrjala 2015-06-12 16:24 ` Clint Taylor 2015-06-15 10:26 ` Daniel Vetter
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