* [Qemu-devel] [PATCH 0/2] Add cortex-a53 cpu support for kvm-arm and virt @ 2015-06-01 10:34 shannon.zhao 2015-06-01 10:34 ` [Qemu-devel] [PATCH 1/2] target-arm/kvm64: Add cortex-a53 cpu support shannon.zhao 2015-06-01 10:34 ` [Qemu-devel] [PATCH 2/2] hw/arm/virt: Add cortex-a53 cpu support in machine virt shannon.zhao 0 siblings, 2 replies; 7+ messages in thread From: shannon.zhao @ 2015-06-01 10:34 UTC (permalink / raw) To: qemu-devel, peter.maydell; +Cc: shannon.zhao, zhaoshenglong From: Shannon Zhao <shannon.zhao@linaro.org> This first patch adds cortex-a53 cpu support in kvm-arm and the second adds cortex-a53 cpu support in machine virt. Shannon Zhao (2): target-arm/kvm64: Add cortex-a53 cpu support hw/arm/virt: Add cortex-a53 cpu support in machine virt hw/arm/virt.c | 5 +++++ target-arm/cpu64.c | 1 + target-arm/kvm-consts.h | 2 ++ target-arm/kvm64.c | 1 + 4 files changed, 9 insertions(+) -- 2.1.0 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Qemu-devel] [PATCH 1/2] target-arm/kvm64: Add cortex-a53 cpu support 2015-06-01 10:34 [Qemu-devel] [PATCH 0/2] Add cortex-a53 cpu support for kvm-arm and virt shannon.zhao @ 2015-06-01 10:34 ` shannon.zhao 2015-06-01 10:54 ` Peter Crosthwaite 2015-06-01 10:34 ` [Qemu-devel] [PATCH 2/2] hw/arm/virt: Add cortex-a53 cpu support in machine virt shannon.zhao 1 sibling, 1 reply; 7+ messages in thread From: shannon.zhao @ 2015-06-01 10:34 UTC (permalink / raw) To: qemu-devel, peter.maydell; +Cc: shannon.zhao, zhaoshenglong From: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> --- target-arm/cpu64.c | 1 + target-arm/kvm-consts.h | 2 ++ target-arm/kvm64.c | 1 + 3 files changed, 4 insertions(+) diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index bf7dd68..dd6f9d8 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -159,6 +159,7 @@ static void aarch64_a53_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); + cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; cpu->midr = 0x410fd034; cpu->reset_fpsid = 0x41034070; cpu->mvfr0 = 0x10110222; diff --git a/target-arm/kvm-consts.h b/target-arm/kvm-consts.h index aea12f1..4c10476 100644 --- a/target-arm/kvm-consts.h +++ b/target-arm/kvm-consts.h @@ -127,6 +127,7 @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED) #define QEMU_KVM_ARM_TARGET_AEM_V8 0 #define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1 #define QEMU_KVM_ARM_TARGET_CORTEX_A57 2 +#define QEMU_KVM_ARM_TARGET_CORTEX_A53 4 /* There's no kernel define for this: sentinel value which * matches no KVM target value for either 64 or 32 bit @@ -137,6 +138,7 @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED) MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_AEM_V8) MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8) MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57) +MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53) #else MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15) MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7) diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c index 93c1ca8..0f1cd29 100644 --- a/target-arm/kvm64.c +++ b/target-arm/kvm64.c @@ -50,6 +50,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc) KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_CORTEX_A57, + KVM_ARM_TARGET_CORTEX_A53 = 4, QEMU_KVM_ARM_TARGET_NONE }; struct kvm_vcpu_init init; -- 2.1.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH 1/2] target-arm/kvm64: Add cortex-a53 cpu support 2015-06-01 10:34 ` [Qemu-devel] [PATCH 1/2] target-arm/kvm64: Add cortex-a53 cpu support shannon.zhao @ 2015-06-01 10:54 ` Peter Crosthwaite 2015-06-01 12:48 ` Shannon Zhao 0 siblings, 1 reply; 7+ messages in thread From: Peter Crosthwaite @ 2015-06-01 10:54 UTC (permalink / raw) To: shannon.zhao Cc: Peter Maydell, qemu-devel@nongnu.org Developers, zhaoshenglong On Mon, Jun 1, 2015 at 3:34 AM, <shannon.zhao@linaro.org> wrote: > From: Shannon Zhao <shannon.zhao@linaro.org> > Say more about the changes. Why the gap to index 4? > Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> > --- > target-arm/cpu64.c | 1 + > target-arm/kvm-consts.h | 2 ++ > target-arm/kvm64.c | 1 + > 3 files changed, 4 insertions(+) > > diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c > index bf7dd68..dd6f9d8 100644 > --- a/target-arm/cpu64.c > +++ b/target-arm/cpu64.c > @@ -159,6 +159,7 @@ static void aarch64_a53_initfn(Object *obj) > set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); > set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); > set_feature(&cpu->env, ARM_FEATURE_CRC); > + cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; > cpu->midr = 0x410fd034; > cpu->reset_fpsid = 0x41034070; > cpu->mvfr0 = 0x10110222; > diff --git a/target-arm/kvm-consts.h b/target-arm/kvm-consts.h > index aea12f1..4c10476 100644 > --- a/target-arm/kvm-consts.h > +++ b/target-arm/kvm-consts.h > @@ -127,6 +127,7 @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED) > #define QEMU_KVM_ARM_TARGET_AEM_V8 0 > #define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1 > #define QEMU_KVM_ARM_TARGET_CORTEX_A57 2 > +#define QEMU_KVM_ARM_TARGET_CORTEX_A53 4 > > /* There's no kernel define for this: sentinel value which > * matches no KVM target value for either 64 or 32 bit > @@ -137,6 +138,7 @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED) > MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_AEM_V8) > MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8) > MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57) > +MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53) > #else > MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15) > MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7) > diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c > index 93c1ca8..0f1cd29 100644 > --- a/target-arm/kvm64.c > +++ b/target-arm/kvm64.c > @@ -50,6 +50,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc) > KVM_ARM_TARGET_AEM_V8, > KVM_ARM_TARGET_FOUNDATION_V8, > KVM_ARM_TARGET_CORTEX_A57, > + KVM_ARM_TARGET_CORTEX_A53 = 4, Do you need the = 4? This seems to be a continuous list of indicies terminated by _TARGET_NONE. Regards, Peter > QEMU_KVM_ARM_TARGET_NONE > }; > struct kvm_vcpu_init init; > -- > 2.1.0 > > ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH 1/2] target-arm/kvm64: Add cortex-a53 cpu support 2015-06-01 10:54 ` Peter Crosthwaite @ 2015-06-01 12:48 ` Shannon Zhao 2015-06-01 14:27 ` Peter Maydell 0 siblings, 1 reply; 7+ messages in thread From: Shannon Zhao @ 2015-06-01 12:48 UTC (permalink / raw) To: Peter Crosthwaite Cc: Peter Maydell, qemu-devel@nongnu.org Developers, zhaoshenglong On 2015/6/1 18:54, Peter Crosthwaite wrote: > On Mon, Jun 1, 2015 at 3:34 AM, <shannon.zhao@linaro.org> wrote: >> From: Shannon Zhao <shannon.zhao@linaro.org> >> > > Say more about the changes. Why the gap to index 4? > You mean why the KVM_ARM_TARGET_CORTEX_A53 is 4? linux-headers/asm-arm64/kvm.h defines it to 4. /* Supported Processor Types */ #define KVM_ARM_TARGET_AEM_V8 0 #define KVM_ARM_TARGET_FOUNDATION_V8 1 #define KVM_ARM_TARGET_CORTEX_A57 2 #define KVM_ARM_TARGET_XGENE_POTENZA 3 #define KVM_ARM_TARGET_CORTEX_A53 4 >> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> >> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> >> --- >> target-arm/cpu64.c | 1 + >> target-arm/kvm-consts.h | 2 ++ >> target-arm/kvm64.c | 1 + >> 3 files changed, 4 insertions(+) >> >> diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c >> index bf7dd68..dd6f9d8 100644 >> --- a/target-arm/cpu64.c >> +++ b/target-arm/cpu64.c >> @@ -159,6 +159,7 @@ static void aarch64_a53_initfn(Object *obj) >> set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); >> set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); >> set_feature(&cpu->env, ARM_FEATURE_CRC); >> + cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53; >> cpu->midr = 0x410fd034; >> cpu->reset_fpsid = 0x41034070; >> cpu->mvfr0 = 0x10110222; >> diff --git a/target-arm/kvm-consts.h b/target-arm/kvm-consts.h >> index aea12f1..4c10476 100644 >> --- a/target-arm/kvm-consts.h >> +++ b/target-arm/kvm-consts.h >> @@ -127,6 +127,7 @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED) >> #define QEMU_KVM_ARM_TARGET_AEM_V8 0 >> #define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1 >> #define QEMU_KVM_ARM_TARGET_CORTEX_A57 2 >> +#define QEMU_KVM_ARM_TARGET_CORTEX_A53 4 >> >> /* There's no kernel define for this: sentinel value which >> * matches no KVM target value for either 64 or 32 bit >> @@ -137,6 +138,7 @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED) >> MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_AEM_V8) >> MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATION_V8) >> MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57) >> +MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53) >> #else >> MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15) >> MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7) >> diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c >> index 93c1ca8..0f1cd29 100644 >> --- a/target-arm/kvm64.c >> +++ b/target-arm/kvm64.c >> @@ -50,6 +50,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc) >> KVM_ARM_TARGET_AEM_V8, >> KVM_ARM_TARGET_FOUNDATION_V8, >> KVM_ARM_TARGET_CORTEX_A57, >> + KVM_ARM_TARGET_CORTEX_A53 = 4, > > Do you need the = 4? This seems to be a continuous list of indicies > terminated by _TARGET_NONE. > > Regards, > Peter > >> QEMU_KVM_ARM_TARGET_NONE >> }; >> struct kvm_vcpu_init init; >> -- >> 2.1.0 >> >> -- Shannon ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH 1/2] target-arm/kvm64: Add cortex-a53 cpu support 2015-06-01 12:48 ` Shannon Zhao @ 2015-06-01 14:27 ` Peter Maydell 0 siblings, 0 replies; 7+ messages in thread From: Peter Maydell @ 2015-06-01 14:27 UTC (permalink / raw) To: Shannon Zhao Cc: Peter Crosthwaite, qemu-devel@nongnu.org Developers, Shannon Zhao On 1 June 2015 at 13:48, Shannon Zhao <shannon.zhao@linaro.org> wrote: > > > On 2015/6/1 18:54, Peter Crosthwaite wrote: >> >> On Mon, Jun 1, 2015 at 3:34 AM, <shannon.zhao@linaro.org> wrote: >>> >>> From: Shannon Zhao <shannon.zhao@linaro.org> >>> >> >> Say more about the changes. Why the gap to index 4? >> > You mean why the KVM_ARM_TARGET_CORTEX_A53 is 4? > > linux-headers/asm-arm64/kvm.h defines it to 4. > > /* Supported Processor Types */ > #define KVM_ARM_TARGET_AEM_V8 0 > #define KVM_ARM_TARGET_FOUNDATION_V8 1 > #define KVM_ARM_TARGET_CORTEX_A57 2 > #define KVM_ARM_TARGET_XGENE_POTENZA 3 > #define KVM_ARM_TARGET_CORTEX_A53 4 I think it would make more sense to include the XGENE_POTENZA in the enum too; we already have a few in the list (AEM, FOUNDATION_V8) which we don't have QEMU support for. That way there isn't a confusing gap in the enumeration. thanks -- PMM ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Qemu-devel] [PATCH 2/2] hw/arm/virt: Add cortex-a53 cpu support in machine virt 2015-06-01 10:34 [Qemu-devel] [PATCH 0/2] Add cortex-a53 cpu support for kvm-arm and virt shannon.zhao 2015-06-01 10:34 ` [Qemu-devel] [PATCH 1/2] target-arm/kvm64: Add cortex-a53 cpu support shannon.zhao @ 2015-06-01 10:34 ` shannon.zhao 2015-06-01 17:25 ` Peter Maydell 1 sibling, 1 reply; 7+ messages in thread From: shannon.zhao @ 2015-06-01 10:34 UTC (permalink / raw) To: qemu-devel, peter.maydell; +Cc: shannon.zhao, zhaoshenglong From: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> --- hw/arm/virt.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 05db8cb..76763b8 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -133,6 +133,11 @@ static VirtBoardInfo machines[] = { .irqmap = a15irqmap, }, { + .cpu_model = "cortex-a53", + .memmap = a15memmap, + .irqmap = a15irqmap, + }, + { .cpu_model = "cortex-a57", .memmap = a15memmap, .irqmap = a15irqmap, -- 2.1.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH 2/2] hw/arm/virt: Add cortex-a53 cpu support in machine virt 2015-06-01 10:34 ` [Qemu-devel] [PATCH 2/2] hw/arm/virt: Add cortex-a53 cpu support in machine virt shannon.zhao @ 2015-06-01 17:25 ` Peter Maydell 0 siblings, 0 replies; 7+ messages in thread From: Peter Maydell @ 2015-06-01 17:25 UTC (permalink / raw) To: Shannon Zhao; +Cc: QEMU Developers, Shannon Zhao On 1 June 2015 at 11:34, <shannon.zhao@linaro.org> wrote: > From: Shannon Zhao <shannon.zhao@linaro.org> > > Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> > --- > hw/arm/virt.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index 05db8cb..76763b8 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -133,6 +133,11 @@ static VirtBoardInfo machines[] = { > .irqmap = a15irqmap, > }, > { > + .cpu_model = "cortex-a53", > + .memmap = a15memmap, > + .irqmap = a15irqmap, > + }, > + { > .cpu_model = "cortex-a57", > .memmap = a15memmap, > .irqmap = a15irqmap, Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2015-06-01 17:25 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2015-06-01 10:34 [Qemu-devel] [PATCH 0/2] Add cortex-a53 cpu support for kvm-arm and virt shannon.zhao 2015-06-01 10:34 ` [Qemu-devel] [PATCH 1/2] target-arm/kvm64: Add cortex-a53 cpu support shannon.zhao 2015-06-01 10:54 ` Peter Crosthwaite 2015-06-01 12:48 ` Shannon Zhao 2015-06-01 14:27 ` Peter Maydell 2015-06-01 10:34 ` [Qemu-devel] [PATCH 2/2] hw/arm/virt: Add cortex-a53 cpu support in machine virt shannon.zhao 2015-06-01 17:25 ` Peter Maydell
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