* [PATCH 1/3] drm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv code
@ 2015-06-02 12:37 ville.syrjala
2015-06-02 12:37 ` [PATCH 2/3] drm/i915: Set INSTPM_FORCE_ORDERING via LRI on gen8, drop it on gen9+ ville.syrjala
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: ville.syrjala @ 2015-06-02 12:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
commit 65ca7514e21adbee25b8175fc909759c735d00ff
Author: Damien Lespiau <damien.lespiau@intel.com>
Date: Mon Feb 9 19:33:22 2015 +0000
drm/i915/skl: Implement WaBarrierPerformanceFixDisable
got misapplied and the code landed in chv_init_workarounds() instead of
the intended skl_init_workarounds(). Move it over to the right place.
Cc: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d934f85..edd47ba 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -901,13 +901,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
GEN6_WIZ_HASHING_MASK,
GEN6_WIZ_HASHING_16x4);
- if (INTEL_REVID(dev) == SKL_REVID_C0 ||
- INTEL_REVID(dev) == SKL_REVID_D0)
- /* WaBarrierPerformanceFixDisable:skl */
- WA_SET_BIT_MASKED(HDC_CHICKEN0,
- HDC_FENCE_DEST_SLM_DISABLE |
- HDC_BARRIER_PERFORMANCE_DISABLE);
-
return 0;
}
@@ -1041,6 +1034,13 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
HDC_FORCE_NON_COHERENT);
}
+ if (INTEL_REVID(dev) == SKL_REVID_C0 ||
+ INTEL_REVID(dev) == SKL_REVID_D0)
+ /* WaBarrierPerformanceFixDisable:skl */
+ WA_SET_BIT_MASKED(HDC_CHICKEN0,
+ HDC_FENCE_DEST_SLM_DISABLE |
+ HDC_BARRIER_PERFORMANCE_DISABLE);
+
return skl_tune_iz_hashing(ring);
}
--
2.3.6
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/3] drm/i915: Set INSTPM_FORCE_ORDERING via LRI on gen8, drop it on gen9+
2015-06-02 12:37 [PATCH 1/3] drm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv code ville.syrjala
@ 2015-06-02 12:37 ` ville.syrjala
2015-06-03 10:25 ` Damien Lespiau
2015-06-02 12:37 ` [PATCH 3/3] drm/i915: Apply WaDisableAsyncFlipPerfMode via LRIs on gen8 ville.syrjala
2015-06-02 12:53 ` [PATCH 1/3] drm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv code Damien Lespiau
2 siblings, 1 reply; 10+ messages in thread
From: ville.syrjala @ 2015-06-02 12:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
INSTPM is saved in the logical context so we should initialize it using
LRIs on gen8. It actually defaults to 1 starting from HSW, but let's
keep the write around anyway.
Also drop the INSTPM_FORCE_ORDERING setup entirely on gen9+ since it's
now a reserved bit.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index edd47ba..06f4b22 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -800,6 +800,8 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
+
/* WaDisablePartialInstShootdown:bdw */
/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
@@ -861,6 +863,8 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
struct drm_device *dev = ring->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
+
/* WaDisablePartialInstShootdown:chv */
/* WaDisableThreadStallDopClockGating:chv */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
@@ -1132,7 +1136,7 @@ static int init_render_ring(struct intel_engine_cs *ring)
_MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
}
- if (INTEL_INFO(dev)->gen >= 6)
+ if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
if (HAS_L3_DPF(dev))
--
2.3.6
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/3] drm/i915: Apply WaDisableAsyncFlipPerfMode via LRIs on gen8
2015-06-02 12:37 [PATCH 1/3] drm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv code ville.syrjala
2015-06-02 12:37 ` [PATCH 2/3] drm/i915: Set INSTPM_FORCE_ORDERING via LRI on gen8, drop it on gen9+ ville.syrjala
@ 2015-06-02 12:37 ` ville.syrjala
2015-06-02 22:31 ` shuang.he
2015-06-03 10:26 ` Damien Lespiau
2015-06-02 12:53 ` [PATCH 1/3] drm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv code Damien Lespiau
2 siblings, 2 replies; 10+ messages in thread
From: ville.syrjala @ 2015-06-02 12:37 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
MI_MODE is saved in the logical context so WaDisableAsyncFlipPerfMode
must be applied using LRIs on gen8.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 06f4b22..b70d25b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -802,6 +802,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
+ /* WaDisableAsyncFlipPerfMode:bdw */
+ WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
+
/* WaDisablePartialInstShootdown:bdw */
/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
@@ -865,6 +868,9 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
+ /* WaDisableAsyncFlipPerfMode:chv */
+ WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
+
/* WaDisablePartialInstShootdown:chv */
/* WaDisableThreadStallDopClockGating:chv */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
@@ -1109,9 +1115,9 @@ static int init_render_ring(struct intel_engine_cs *ring)
* to use MI_WAIT_FOR_EVENT within the CS. It should already be
* programmed to '1' on all products.
*
- * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
+ * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
*/
- if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
+ if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
/* Required for the hardware to program scanline values for waiting */
--
2.3.6
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] drm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv code
2015-06-02 12:37 [PATCH 1/3] drm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv code ville.syrjala
2015-06-02 12:37 ` [PATCH 2/3] drm/i915: Set INSTPM_FORCE_ORDERING via LRI on gen8, drop it on gen9+ ville.syrjala
2015-06-02 12:37 ` [PATCH 3/3] drm/i915: Apply WaDisableAsyncFlipPerfMode via LRIs on gen8 ville.syrjala
@ 2015-06-02 12:53 ` Damien Lespiau
2015-06-03 7:45 ` Jani Nikula
2 siblings, 1 reply; 10+ messages in thread
From: Damien Lespiau @ 2015-06-02 12:53 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Tue, Jun 02, 2015 at 03:37:35PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> commit 65ca7514e21adbee25b8175fc909759c735d00ff
> Author: Damien Lespiau <damien.lespiau@intel.com>
> Date: Mon Feb 9 19:33:22 2015 +0000
>
> drm/i915/skl: Implement WaBarrierPerformanceFixDisable
>
> got misapplied and the code landed in chv_init_workarounds() instead of
> the intended skl_init_workarounds(). Move it over to the right place.
>
> Cc: Damien Lespiau <damien.lespiau@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
> drivers/gpu/drm/i915/intel_ringbuffer.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index d934f85..edd47ba 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -901,13 +901,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
> GEN6_WIZ_HASHING_MASK,
> GEN6_WIZ_HASHING_16x4);
>
> - if (INTEL_REVID(dev) == SKL_REVID_C0 ||
> - INTEL_REVID(dev) == SKL_REVID_D0)
> - /* WaBarrierPerformanceFixDisable:skl */
> - WA_SET_BIT_MASKED(HDC_CHICKEN0,
> - HDC_FENCE_DEST_SLM_DISABLE |
> - HDC_BARRIER_PERFORMANCE_DISABLE);
> -
> return 0;
> }
>
> @@ -1041,6 +1034,13 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
> HDC_FORCE_NON_COHERENT);
> }
>
> + if (INTEL_REVID(dev) == SKL_REVID_C0 ||
> + INTEL_REVID(dev) == SKL_REVID_D0)
> + /* WaBarrierPerformanceFixDisable:skl */
> + WA_SET_BIT_MASKED(HDC_CHICKEN0,
> + HDC_FENCE_DEST_SLM_DISABLE |
> + HDC_BARRIER_PERFORMANCE_DISABLE);
> +
> return skl_tune_iz_hashing(ring);
> }
>
> --
> 2.3.6
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] drm/i915: Apply WaDisableAsyncFlipPerfMode via LRIs on gen8
2015-06-02 12:37 ` [PATCH 3/3] drm/i915: Apply WaDisableAsyncFlipPerfMode via LRIs on gen8 ville.syrjala
@ 2015-06-02 22:31 ` shuang.he
2015-06-03 10:26 ` Damien Lespiau
1 sibling, 0 replies; 10+ messages in thread
From: shuang.he @ 2015-06-02 22:31 UTC (permalink / raw)
To: shuang.he, lei.a.liu, intel-gfx, ville.syrjala
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6524
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 276/276 276/276
ILK 303/303 303/303
SNB -1 315/315 314/315
IVB 343/343 343/343
BYT 287/287 287/287
BDW 321/321 321/321
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*SNB igt@pm_rpm@dpms-mode-unset-non-lpsp PASS(1) DMESG_WARN(1)
(dmesg patch applied)WARNING:at_drivers/gpu/drm/i915/intel_uncore.c:#assert_device_not_suspended[i915]()@WARNING:.* at .* assert_device_not_suspended+0x
Note: You need to pay more attention to line start with '*'
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] drm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv code
2015-06-02 12:53 ` [PATCH 1/3] drm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv code Damien Lespiau
@ 2015-06-03 7:45 ` Jani Nikula
2015-06-04 11:22 ` Jani Nikula
0 siblings, 1 reply; 10+ messages in thread
From: Jani Nikula @ 2015-06-03 7:45 UTC (permalink / raw)
To: Damien Lespiau, ville.syrjala; +Cc: intel-gfx
On Tue, 02 Jun 2015, Damien Lespiau <damien.lespiau@intel.com> wrote:
> On Tue, Jun 02, 2015 at 03:37:35PM +0300, ville.syrjala@linux.intel.com wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> commit 65ca7514e21adbee25b8175fc909759c735d00ff
>> Author: Damien Lespiau <damien.lespiau@intel.com>
>> Date: Mon Feb 9 19:33:22 2015 +0000
>>
>> drm/i915/skl: Implement WaBarrierPerformanceFixDisable
>>
>> got misapplied and the code landed in chv_init_workarounds() instead of
>> the intended skl_init_workarounds(). Move it over to the right place.
>>
>> Cc: Damien Lespiau <damien.lespiau@intel.com>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> ---
>
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Pushed this one patch to drm-intel-next-queued, thanks for the patch and
review.
I presume the r-b was for patch 1 only, any chance you could look at the
other two, Damien?
BR,
Jani.
>
> --
> Damien
>
>> drivers/gpu/drm/i915/intel_ringbuffer.c | 14 +++++++-------
>> 1 file changed, 7 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index d934f85..edd47ba 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -901,13 +901,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
>> GEN6_WIZ_HASHING_MASK,
>> GEN6_WIZ_HASHING_16x4);
>>
>> - if (INTEL_REVID(dev) == SKL_REVID_C0 ||
>> - INTEL_REVID(dev) == SKL_REVID_D0)
>> - /* WaBarrierPerformanceFixDisable:skl */
>> - WA_SET_BIT_MASKED(HDC_CHICKEN0,
>> - HDC_FENCE_DEST_SLM_DISABLE |
>> - HDC_BARRIER_PERFORMANCE_DISABLE);
>> -
>> return 0;
>> }
>>
>> @@ -1041,6 +1034,13 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
>> HDC_FORCE_NON_COHERENT);
>> }
>>
>> + if (INTEL_REVID(dev) == SKL_REVID_C0 ||
>> + INTEL_REVID(dev) == SKL_REVID_D0)
>> + /* WaBarrierPerformanceFixDisable:skl */
>> + WA_SET_BIT_MASKED(HDC_CHICKEN0,
>> + HDC_FENCE_DEST_SLM_DISABLE |
>> + HDC_BARRIER_PERFORMANCE_DISABLE);
>> +
>> return skl_tune_iz_hashing(ring);
>> }
>>
>> --
>> 2.3.6
>>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] drm/i915: Set INSTPM_FORCE_ORDERING via LRI on gen8, drop it on gen9+
2015-06-02 12:37 ` [PATCH 2/3] drm/i915: Set INSTPM_FORCE_ORDERING via LRI on gen8, drop it on gen9+ ville.syrjala
@ 2015-06-03 10:25 ` Damien Lespiau
0 siblings, 0 replies; 10+ messages in thread
From: Damien Lespiau @ 2015-06-03 10:25 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Tue, Jun 02, 2015 at 03:37:36PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> INSTPM is saved in the logical context so we should initialize it using
> LRIs on gen8. It actually defaults to 1 starting from HSW, but let's
> keep the write around anyway.
>
> Also drop the INSTPM_FORCE_ORDERING setup entirely on gen9+ since it's
> now a reserved bit.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index edd47ba..06f4b22 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -800,6 +800,8 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
> struct drm_device *dev = ring->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> + WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
> +
> /* WaDisablePartialInstShootdown:bdw */
> /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> @@ -861,6 +863,8 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
> struct drm_device *dev = ring->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> + WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
> +
> /* WaDisablePartialInstShootdown:chv */
> /* WaDisableThreadStallDopClockGating:chv */
> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> @@ -1132,7 +1136,7 @@ static int init_render_ring(struct intel_engine_cs *ring)
> _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
> }
>
> - if (INTEL_INFO(dev)->gen >= 6)
> + if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
> I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
>
> if (HAS_L3_DPF(dev))
> --
> 2.3.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] drm/i915: Apply WaDisableAsyncFlipPerfMode via LRIs on gen8
2015-06-02 12:37 ` [PATCH 3/3] drm/i915: Apply WaDisableAsyncFlipPerfMode via LRIs on gen8 ville.syrjala
2015-06-02 22:31 ` shuang.he
@ 2015-06-03 10:26 ` Damien Lespiau
2015-06-03 11:18 ` Jani Nikula
1 sibling, 1 reply; 10+ messages in thread
From: Damien Lespiau @ 2015-06-03 10:26 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Tue, Jun 02, 2015 at 03:37:37PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> MI_MODE is saved in the logical context so WaDisableAsyncFlipPerfMode
> must be applied using LRIs on gen8.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 06f4b22..b70d25b 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -802,6 +802,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
>
> WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
>
> + /* WaDisableAsyncFlipPerfMode:bdw */
> + WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
> +
> /* WaDisablePartialInstShootdown:bdw */
> /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> @@ -865,6 +868,9 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
>
> WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
>
> + /* WaDisableAsyncFlipPerfMode:chv */
> + WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
> +
> /* WaDisablePartialInstShootdown:chv */
> /* WaDisableThreadStallDopClockGating:chv */
> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> @@ -1109,9 +1115,9 @@ static int init_render_ring(struct intel_engine_cs *ring)
> * to use MI_WAIT_FOR_EVENT within the CS. It should already be
> * programmed to '1' on all products.
> *
> - * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
> + * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
> */
> - if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
> + if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
> I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
>
> /* Required for the hardware to program scanline values for waiting */
> --
> 2.3.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] drm/i915: Apply WaDisableAsyncFlipPerfMode via LRIs on gen8
2015-06-03 10:26 ` Damien Lespiau
@ 2015-06-03 11:18 ` Jani Nikula
0 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2015-06-03 11:18 UTC (permalink / raw)
To: Damien Lespiau, ville.syrjala; +Cc: intel-gfx
On Wed, 03 Jun 2015, Damien Lespiau <damien.lespiau@intel.com> wrote:
> On Tue, Jun 02, 2015 at 03:37:37PM +0300, ville.syrjala@linux.intel.com wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> MI_MODE is saved in the logical context so WaDisableAsyncFlipPerfMode
>> must be applied using LRIs on gen8.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Thanks, pushed all patches to drm-intel-next-queued.
BR,
Jani.
>
> --
> Damien
>
>> ---
>> drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++++++++--
>> 1 file changed, 8 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index 06f4b22..b70d25b 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -802,6 +802,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
>>
>> WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
>>
>> + /* WaDisableAsyncFlipPerfMode:bdw */
>> + WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
>> +
>> /* WaDisablePartialInstShootdown:bdw */
>> /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
>> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>> @@ -865,6 +868,9 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
>>
>> WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
>>
>> + /* WaDisableAsyncFlipPerfMode:chv */
>> + WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
>> +
>> /* WaDisablePartialInstShootdown:chv */
>> /* WaDisableThreadStallDopClockGating:chv */
>> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>> @@ -1109,9 +1115,9 @@ static int init_render_ring(struct intel_engine_cs *ring)
>> * to use MI_WAIT_FOR_EVENT within the CS. It should already be
>> * programmed to '1' on all products.
>> *
>> - * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
>> + * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
>> */
>> - if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9)
>> + if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
>> I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
>>
>> /* Required for the hardware to program scanline values for waiting */
>> --
>> 2.3.6
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] drm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv code
2015-06-03 7:45 ` Jani Nikula
@ 2015-06-04 11:22 ` Jani Nikula
0 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2015-06-04 11:22 UTC (permalink / raw)
To: Damien Lespiau, ville.syrjala; +Cc: intel-gfx
On Wed, 03 Jun 2015, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Tue, 02 Jun 2015, Damien Lespiau <damien.lespiau@intel.com> wrote:
>> On Tue, Jun 02, 2015 at 03:37:35PM +0300, ville.syrjala@linux.intel.com wrote:
>>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>>
>>> commit 65ca7514e21adbee25b8175fc909759c735d00ff
>>> Author: Damien Lespiau <damien.lespiau@intel.com>
>>> Date: Mon Feb 9 19:33:22 2015 +0000
>>>
>>> drm/i915/skl: Implement WaBarrierPerformanceFixDisable
>>>
>>> got misapplied and the code landed in chv_init_workarounds() instead of
>>> the intended skl_init_workarounds(). Move it over to the right place.
>>>
>>> Cc: Damien Lespiau <damien.lespiau@intel.com>
>>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>> ---
>>
>> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
>
> Pushed this one patch to drm-intel-next-queued, thanks for the patch and
> review.
...and cherry-picked to drm-intel-fixes because it affects CHV code.
BR,
Jani.
>
> I presume the r-b was for patch 1 only, any chance you could look at the
> other two, Damien?
>
> BR,
> Jani.
>
>
>
>>
>> --
>> Damien
>>
>>> drivers/gpu/drm/i915/intel_ringbuffer.c | 14 +++++++-------
>>> 1 file changed, 7 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> index d934f85..edd47ba 100644
>>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>>> @@ -901,13 +901,6 @@ static int chv_init_workarounds(struct intel_engine_cs *ring)
>>> GEN6_WIZ_HASHING_MASK,
>>> GEN6_WIZ_HASHING_16x4);
>>>
>>> - if (INTEL_REVID(dev) == SKL_REVID_C0 ||
>>> - INTEL_REVID(dev) == SKL_REVID_D0)
>>> - /* WaBarrierPerformanceFixDisable:skl */
>>> - WA_SET_BIT_MASKED(HDC_CHICKEN0,
>>> - HDC_FENCE_DEST_SLM_DISABLE |
>>> - HDC_BARRIER_PERFORMANCE_DISABLE);
>>> -
>>> return 0;
>>> }
>>>
>>> @@ -1041,6 +1034,13 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
>>> HDC_FORCE_NON_COHERENT);
>>> }
>>>
>>> + if (INTEL_REVID(dev) == SKL_REVID_C0 ||
>>> + INTEL_REVID(dev) == SKL_REVID_D0)
>>> + /* WaBarrierPerformanceFixDisable:skl */
>>> + WA_SET_BIT_MASKED(HDC_CHICKEN0,
>>> + HDC_FENCE_DEST_SLM_DISABLE |
>>> + HDC_BARRIER_PERFORMANCE_DISABLE);
>>> +
>>> return skl_tune_iz_hashing(ring);
>>> }
>>>
>>> --
>>> 2.3.6
>>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Technology Center
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
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^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2015-06-04 11:20 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-06-02 12:37 [PATCH 1/3] drm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv code ville.syrjala
2015-06-02 12:37 ` [PATCH 2/3] drm/i915: Set INSTPM_FORCE_ORDERING via LRI on gen8, drop it on gen9+ ville.syrjala
2015-06-03 10:25 ` Damien Lespiau
2015-06-02 12:37 ` [PATCH 3/3] drm/i915: Apply WaDisableAsyncFlipPerfMode via LRIs on gen8 ville.syrjala
2015-06-02 22:31 ` shuang.he
2015-06-03 10:26 ` Damien Lespiau
2015-06-03 11:18 ` Jani Nikula
2015-06-02 12:53 ` [PATCH 1/3] drm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv code Damien Lespiau
2015-06-03 7:45 ` Jani Nikula
2015-06-04 11:22 ` Jani Nikula
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