* drm/i915/hsw/bdw: Enable resource streamer v3
@ 2015-06-08 10:04 Abdiel Janulgue
2015-06-08 10:04 ` [PATCH 1/3] drm/i915: Enable resource streamer bits on MI_BATCH_BUFFER_START Abdiel Janulgue
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Abdiel Janulgue @ 2015-06-08 10:04 UTC (permalink / raw)
To: intel-gfx
Hi,
Although most of this patches were alread reviewed, I am resending them
due to additional changes suggested by Jani Nikula. In addition
Mesa folks want RS to be working with hiccups on GEN8 as well so
I added the necessary support for that platform as well.
Changes since last posting:
- Make RS context save and restore work properly on GEN8
- Add I915_PARAM_HAS_RESOURCE_STREAMER params.
[PATCH 1/3] drm/i915: Enable resource streamer bits on
[PATCH 2/3] drm/i915: Enable Resource Streamer state save/restore
[PATCH 3/3] drm/i915: Expose I915_EXEC_RESOURCE_STREAMER flag
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/3] drm/i915: Enable resource streamer bits on MI_BATCH_BUFFER_START
2015-06-08 10:04 drm/i915/hsw/bdw: Enable resource streamer v3 Abdiel Janulgue
@ 2015-06-08 10:04 ` Abdiel Janulgue
2015-06-08 16:10 ` Ville Syrjälä
2015-06-08 10:04 ` [PATCH 2/3] drm/i915: Enable Resource Streamer state save/restore Abdiel Janulgue
` (2 subsequent siblings)
3 siblings, 1 reply; 10+ messages in thread
From: Abdiel Janulgue @ 2015-06-08 10:04 UTC (permalink / raw)
To: intel-gfx
Adds support for executing the resource streamer on BDW and HSW
v2: Add support for Execlists (Minu Mathai <minu.mathai@intel.com>)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_lrc.c | 4 +++-
drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
4 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b522eb6..238bb25 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -356,6 +356,7 @@
#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
+#define MI_BATCH_RESOURCE_STREAMER (1<<10)
#define MI_PREDICATE_SRC0 (0x2400)
#define MI_PREDICATE_SRC1 (0x2408)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index fcb074b..3b168f6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1172,7 +1172,9 @@ static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
return ret;
/* FIXME(BDW): Address space and security selectors. */
- intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
+ intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
+ (ppgtt<<8) | (I915_DISPATCH_RS ?
+ MI_BATCH_RESOURCE_STREAMER : 0));
intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
intel_logical_ring_emit(ringbuf, MI_NOOP);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 441e250..715cb2a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2385,7 +2385,9 @@ gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
return ret;
/* FIXME(BDW): Address space and security selectors. */
- intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
+ intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
+ (dispatch_flags & I915_DISPATCH_RS ?
+ MI_BATCH_RESOURCE_STREAMER : 0));
intel_ring_emit(ring, lower_32_bits(offset));
intel_ring_emit(ring, upper_32_bits(offset));
intel_ring_emit(ring, MI_NOOP);
@@ -2408,7 +2410,9 @@ hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
intel_ring_emit(ring,
MI_BATCH_BUFFER_START |
(dispatch_flags & I915_DISPATCH_SECURE ?
- 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
+ 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
+ (dispatch_flags & I915_DISPATCH_RS ?
+ MI_BATCH_RESOURCE_STREAMER : 0));
/* bit0-7 is the length on GEN6+ */
intel_ring_emit(ring, offset);
intel_ring_advance(ring);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index c761fe0..3521bc0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -167,6 +167,7 @@ struct intel_engine_cs {
unsigned dispatch_flags);
#define I915_DISPATCH_SECURE 0x1
#define I915_DISPATCH_PINNED 0x2
+#define I915_DISPATCH_RS 0x4
void (*cleanup)(struct intel_engine_cs *ring);
/* GEN8 signal/wait table - never trust comments!
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/3] drm/i915: Enable Resource Streamer state save/restore
2015-06-08 10:04 drm/i915/hsw/bdw: Enable resource streamer v3 Abdiel Janulgue
2015-06-08 10:04 ` [PATCH 1/3] drm/i915: Enable resource streamer bits on MI_BATCH_BUFFER_START Abdiel Janulgue
@ 2015-06-08 10:04 ` Abdiel Janulgue
2015-06-08 10:04 ` [PATCH 3/3] drm/i915: Expose I915_EXEC_RESOURCE_STREAMER flag Abdiel Janulgue
2015-06-08 15:40 ` drm/i915/hsw/bdw: Enable resource streamer v3 Abdiel Janulgue
3 siblings, 0 replies; 10+ messages in thread
From: Abdiel Janulgue @ 2015-06-08 10:04 UTC (permalink / raw)
To: intel-gfx
Also clarify comments on context size that the extra state for
Resource Streamer is included.
v2: Don't remove the extended save/restore enabled for older
platforms. (Ville)
Use new MI_SET_CONTEXT defines for HSW RS save/restore state
instead of extended save/restore. (Daniel)
v3: Add RS save restore for GEN8
Cc: ville.syrjala@linux.intel.com
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem_context.c | 4 +++-
drivers/gpu/drm/i915/i915_reg.h | 5 ++++-
drivers/gpu/drm/i915/intel_lrc.c | 3 ++-
drivers/gpu/drm/i915/intel_lrc.h | 1 +
4 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index f3e84c4..a29dbcd 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -509,7 +509,9 @@ mi_set_context(struct intel_engine_cs *ring,
}
/* These flags are for resource streamer on HSW+ */
- if (!IS_HASWELL(ring->dev) && INTEL_INFO(ring->dev)->gen < 8)
+ if (IS_HASWELL(ring->dev) || INTEL_INFO(ring->dev)->gen >= 8)
+ flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
+ else if (INTEL_INFO(ring->dev)->gen < 8)
flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 238bb25..2b1321d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -316,6 +316,8 @@
#define MI_RESTORE_EXT_STATE_EN (1<<2)
#define MI_FORCE_RESTORE (1<<1)
#define MI_RESTORE_INHIBIT (1<<0)
+#define HSW_MI_RS_SAVE_STATE_EN (1<<3)
+#define HSW_MI_RS_RESTORE_STATE_EN (1<<2)
#define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */
#define MI_SEMAPHORE_TARGET(engine) ((engine)<<15)
#define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */
@@ -2498,7 +2500,8 @@ enum skl_disp_power_wells {
* valid. Now, docs explain in dwords what is in the context object. The full
* size is 70720 bytes, however, the power context and execlist context will
* never be saved (power context is stored elsewhere, and execlists don't work
- * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages.
+ * on HSW) - so the final size, including the extra state required for the
+ * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
*/
#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
/* Same as Haswell, but 72064 bytes now. */
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 3b168f6..50af986 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1728,7 +1728,8 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o
reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);
reg_state[CTX_CONTEXT_CONTROL+1] =
_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
- CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
+ CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
+ CTX_CTRL_RS_CTX_ENABLE);
reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);
reg_state[CTX_RING_HEAD+1] = 0;
reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index adb731e4..de6087a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -32,6 +32,7 @@
#define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244)
#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
+#define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
#define RING_CONTEXT_STATUS_BUF(ring) ((ring)->mmio_base+0x370)
#define RING_CONTEXT_STATUS_PTR(ring) ((ring)->mmio_base+0x3a0)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/3] drm/i915: Expose I915_EXEC_RESOURCE_STREAMER flag
2015-06-08 10:04 drm/i915/hsw/bdw: Enable resource streamer v3 Abdiel Janulgue
2015-06-08 10:04 ` [PATCH 1/3] drm/i915: Enable resource streamer bits on MI_BATCH_BUFFER_START Abdiel Janulgue
2015-06-08 10:04 ` [PATCH 2/3] drm/i915: Enable Resource Streamer state save/restore Abdiel Janulgue
@ 2015-06-08 10:04 ` Abdiel Janulgue
2015-06-13 15:41 ` shuang.he
2015-06-08 15:40 ` drm/i915/hsw/bdw: Enable resource streamer v3 Abdiel Janulgue
3 siblings, 1 reply; 10+ messages in thread
From: Abdiel Janulgue @ 2015-06-08 10:04 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Ensures that the batch buffer is executed by the resource streamer
v2: Don't skip 1<<15 for the exec flags (Jani Nikula).
Add I915_PARAM_HAS_RESOURCE_STREAMER to check if kernel has RS support
baked in (Kenneth Graunke).
Testcase: igt/gem_exec_params
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: kenneth@whitecape.org
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
---
drivers/gpu/drm/i915/i915_dma.c | 3 +++
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 14 ++++++++++++++
include/uapi/drm/i915_drm.h | 8 +++++++-
3 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 68e0c85..10d4ead 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -163,6 +163,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
if (!value)
return -ENODEV;
break;
+ case I915_PARAM_HAS_RESOURCE_STREAMER:
+ value = 1;
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index a3190e79..ae064f0 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1485,6 +1485,20 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
return -EINVAL;
}
+ if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
+ if (!IS_HASWELL(dev) && INTEL_INFO(dev)->gen < 8) {
+ DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
+ return -EINVAL;
+ }
+ if (ring->id != RCS) {
+ DRM_DEBUG("RS is not available on %s\n",
+ ring->name);
+ return -EINVAL;
+ }
+
+ dispatch_flags |= I915_DISPATCH_RS;
+ }
+
intel_runtime_pm_get(dev_priv);
ret = i915_mutex_lock_interruptible(dev);
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 551b673..debccd34 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -350,6 +350,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_REVISION 32
#define I915_PARAM_SUBSLICE_TOTAL 33
#define I915_PARAM_EU_TOTAL 34
+#define I915_PARAM_HAS_RESOURCE_STREAMER 35
typedef struct drm_i915_getparam {
int param;
@@ -760,7 +761,12 @@ struct drm_i915_gem_execbuffer2 {
#define I915_EXEC_BSD_RING1 (1<<13)
#define I915_EXEC_BSD_RING2 (2<<13)
-#define __I915_EXEC_UNKNOWN_FLAGS -(1<<15)
+/** Tell the kernel that the batchbuffer is processed by
+ * the resource streamer.
+ */
+#define I915_EXEC_RESOURCE_STREAMER (1<<15)
+
+#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1)
#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
#define i915_execbuffer2_set_context_id(eb2, context) \
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: drm/i915/hsw/bdw: Enable resource streamer v3
2015-06-08 10:04 drm/i915/hsw/bdw: Enable resource streamer v3 Abdiel Janulgue
` (2 preceding siblings ...)
2015-06-08 10:04 ` [PATCH 3/3] drm/i915: Expose I915_EXEC_RESOURCE_STREAMER flag Abdiel Janulgue
@ 2015-06-08 15:40 ` Abdiel Janulgue
3 siblings, 0 replies; 10+ messages in thread
From: Abdiel Janulgue @ 2015-06-08 15:40 UTC (permalink / raw)
To: intel-gfx
terribly sorry for the typos:
On 06/08/2015 01:04 PM, Abdiel Janulgue wrote:
>
> Although most of this patches were alread reviewed, I am resending them
*already
> due to additional changes suggested by Jani Nikula. In addition
> Mesa folks want RS to be working with hiccups on GEN8 as well so
*without
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] drm/i915: Enable resource streamer bits on MI_BATCH_BUFFER_START
2015-06-08 10:04 ` [PATCH 1/3] drm/i915: Enable resource streamer bits on MI_BATCH_BUFFER_START Abdiel Janulgue
@ 2015-06-08 16:10 ` Ville Syrjälä
2015-06-08 17:42 ` Abdiel Janulgue
0 siblings, 1 reply; 10+ messages in thread
From: Ville Syrjälä @ 2015-06-08 16:10 UTC (permalink / raw)
To: Abdiel Janulgue; +Cc: intel-gfx
On Mon, Jun 08, 2015 at 01:04:07PM +0300, Abdiel Janulgue wrote:
> Adds support for executing the resource streamer on BDW and HSW
>
> v2: Add support for Execlists (Minu Mathai <minu.mathai@intel.com>)
>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_lrc.c | 4 +++-
> drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++++--
> drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
> 4 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b522eb6..238bb25 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -356,6 +356,7 @@
> #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
> #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
> #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
> +#define MI_BATCH_RESOURCE_STREAMER (1<<10)
>
> #define MI_PREDICATE_SRC0 (0x2400)
> #define MI_PREDICATE_SRC1 (0x2408)
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index fcb074b..3b168f6 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1172,7 +1172,9 @@ static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
> return ret;
>
> /* FIXME(BDW): Address space and security selectors. */
> - intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
> + intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
> + (ppgtt<<8) | (I915_DISPATCH_RS ?
That doesn't look right.
> + MI_BATCH_RESOURCE_STREAMER : 0));
> intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
> intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
> intel_logical_ring_emit(ringbuf, MI_NOOP);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 441e250..715cb2a 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2385,7 +2385,9 @@ gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
> return ret;
>
> /* FIXME(BDW): Address space and security selectors. */
> - intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
> + intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
> + (dispatch_flags & I915_DISPATCH_RS ?
> + MI_BATCH_RESOURCE_STREAMER : 0));
> intel_ring_emit(ring, lower_32_bits(offset));
> intel_ring_emit(ring, upper_32_bits(offset));
> intel_ring_emit(ring, MI_NOOP);
> @@ -2408,7 +2410,9 @@ hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
> intel_ring_emit(ring,
> MI_BATCH_BUFFER_START |
> (dispatch_flags & I915_DISPATCH_SECURE ?
> - 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
> + 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
> + (dispatch_flags & I915_DISPATCH_RS ?
> + MI_BATCH_RESOURCE_STREAMER : 0));
> /* bit0-7 is the length on GEN6+ */
> intel_ring_emit(ring, offset);
> intel_ring_advance(ring);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index c761fe0..3521bc0 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -167,6 +167,7 @@ struct intel_engine_cs {
> unsigned dispatch_flags);
> #define I915_DISPATCH_SECURE 0x1
> #define I915_DISPATCH_PINNED 0x2
> +#define I915_DISPATCH_RS 0x4
> void (*cleanup)(struct intel_engine_cs *ring);
>
> /* GEN8 signal/wait table - never trust comments!
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] drm/i915: Enable resource streamer bits on MI_BATCH_BUFFER_START
2015-06-08 16:10 ` Ville Syrjälä
@ 2015-06-08 17:42 ` Abdiel Janulgue
2015-06-08 17:55 ` Chris Wilson
2015-06-09 11:48 ` Dave Gordon
0 siblings, 2 replies; 10+ messages in thread
From: Abdiel Janulgue @ 2015-06-08 17:42 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On 06/08/2015 07:10 PM, Ville Syrjälä wrote:
> On Mon, Jun 08, 2015 at 01:04:07PM +0300, Abdiel Janulgue wrote:
>> Adds support for executing the resource streamer on BDW and HSW
>>
>> v2: Add support for Execlists (Minu Mathai <minu.mathai@intel.com>)
>>
>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
>> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>> drivers/gpu/drm/i915/intel_lrc.c | 4 +++-
>> drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++++--
>> drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
>> 4 files changed, 11 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index b522eb6..238bb25 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -356,6 +356,7 @@
>> #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
>> #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
>> #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
>> +#define MI_BATCH_RESOURCE_STREAMER (1<<10)
>>
>> #define MI_PREDICATE_SRC0 (0x2400)
>> #define MI_PREDICATE_SRC1 (0x2408)
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>> index fcb074b..3b168f6 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -1172,7 +1172,9 @@ static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
>> return ret;
>>
>> /* FIXME(BDW): Address space and security selectors. */
>> - intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
>> + intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
>> + (ppgtt<<8) | (I915_DISPATCH_RS ?
>
> That doesn't look right.
Yay.. Didn't catch these since this path never gets executed under GEN8
anyway which uses execlist not legacy batch buffer execution. Better
remove this then.
>
>> + MI_BATCH_RESOURCE_STREAMER : 0));
>> intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
>> intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
>> intel_logical_ring_emit(ringbuf, MI_NOOP);
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index 441e250..715cb2a 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -2385,7 +2385,9 @@ gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
>> return ret;
>>
>> /* FIXME(BDW): Address space and security selectors. */
>> - intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
>> + intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
>> + (dispatch_flags & I915_DISPATCH_RS ?
>> + MI_BATCH_RESOURCE_STREAMER : 0));
>> intel_ring_emit(ring, lower_32_bits(offset));
>> intel_ring_emit(ring, upper_32_bits(offset));
>> intel_ring_emit(ring, MI_NOOP);
>> @@ -2408,7 +2410,9 @@ hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring,
>> intel_ring_emit(ring,
>> MI_BATCH_BUFFER_START |
>> (dispatch_flags & I915_DISPATCH_SECURE ?
>> - 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW));
>> + 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
>> + (dispatch_flags & I915_DISPATCH_RS ?
>> + MI_BATCH_RESOURCE_STREAMER : 0));
>> /* bit0-7 is the length on GEN6+ */
>> intel_ring_emit(ring, offset);
>> intel_ring_advance(ring);
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
>> index c761fe0..3521bc0 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
>> @@ -167,6 +167,7 @@ struct intel_engine_cs {
>> unsigned dispatch_flags);
>> #define I915_DISPATCH_SECURE 0x1
>> #define I915_DISPATCH_PINNED 0x2
>> +#define I915_DISPATCH_RS 0x4
>> void (*cleanup)(struct intel_engine_cs *ring);
>>
>> /* GEN8 signal/wait table - never trust comments!
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
_______________________________________________
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] drm/i915: Enable resource streamer bits on MI_BATCH_BUFFER_START
2015-06-08 17:42 ` Abdiel Janulgue
@ 2015-06-08 17:55 ` Chris Wilson
2015-06-09 11:48 ` Dave Gordon
1 sibling, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2015-06-08 17:55 UTC (permalink / raw)
To: Abdiel Janulgue; +Cc: intel-gfx
On Mon, Jun 08, 2015 at 08:42:20PM +0300, Abdiel Janulgue wrote:
>
>
> On 06/08/2015 07:10 PM, Ville Syrjälä wrote:
> > On Mon, Jun 08, 2015 at 01:04:07PM +0300, Abdiel Janulgue wrote:
> >> Adds support for executing the resource streamer on BDW and HSW
> >>
> >> v2: Add support for Execlists (Minu Mathai <minu.mathai@intel.com>)
> >>
> >> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> >> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> >> ---
> >> drivers/gpu/drm/i915/i915_reg.h | 1 +
> >> drivers/gpu/drm/i915/intel_lrc.c | 4 +++-
> >> drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++++--
> >> drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
> >> 4 files changed, 11 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index b522eb6..238bb25 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -356,6 +356,7 @@
> >> #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
> >> #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
> >> #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
> >> +#define MI_BATCH_RESOURCE_STREAMER (1<<10)
> >>
> >> #define MI_PREDICATE_SRC0 (0x2400)
> >> #define MI_PREDICATE_SRC1 (0x2408)
> >> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> >> index fcb074b..3b168f6 100644
> >> --- a/drivers/gpu/drm/i915/intel_lrc.c
> >> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> >> @@ -1172,7 +1172,9 @@ static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
> >> return ret;
> >>
> >> /* FIXME(BDW): Address space and security selectors. */
> >> - intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
> >> + intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
> >> + (ppgtt<<8) | (I915_DISPATCH_RS ?
> >
> > That doesn't look right.
>
> Yay.. Didn't catch these since this path never gets executed under GEN8
> anyway which uses execlist not legacy batch buffer execution. Better
> remove this then.
Which makes gen8 support conditional and so needs reflecting in the
interface.
Just test the flag correctly.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] drm/i915: Enable resource streamer bits on MI_BATCH_BUFFER_START
2015-06-08 17:42 ` Abdiel Janulgue
2015-06-08 17:55 ` Chris Wilson
@ 2015-06-09 11:48 ` Dave Gordon
1 sibling, 0 replies; 10+ messages in thread
From: Dave Gordon @ 2015-06-09 11:48 UTC (permalink / raw)
To: Abdiel Janulgue, Ville Syrjälä; +Cc: intel-gfx
On 08/06/15 18:42, Abdiel Janulgue wrote:
>
> On 06/08/2015 07:10 PM, Ville Syrjälä wrote:
>> On Mon, Jun 08, 2015 at 01:04:07PM +0300, Abdiel Janulgue wrote:
>>> Adds support for executing the resource streamer on BDW and HSW
>>>
>>> v2: Add support for Execlists (Minu Mathai <minu.mathai@intel.com>)
>>>
>>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
>>> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
>>> ---
>>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>>> drivers/gpu/drm/i915/intel_lrc.c | 4 +++-
>>> drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++++--
>>> drivers/gpu/drm/i915/intel_ringbuffer.h | 1 +
>>> 4 files changed, 11 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index b522eb6..238bb25 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -356,6 +356,7 @@
>>> #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
>>> #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
>>> #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
>>> +#define MI_BATCH_RESOURCE_STREAMER (1<<10)
>>>
>>> #define MI_PREDICATE_SRC0 (0x2400)
>>> #define MI_PREDICATE_SRC1 (0x2408)
>>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>>> index fcb074b..3b168f6 100644
>>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>>> @@ -1172,7 +1172,9 @@ static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf,
>>> return ret;
>>>
>>> /* FIXME(BDW): Address space and security selectors. */
>>> - intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
>>> + intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
>>> + (ppgtt<<8) | (I915_DISPATCH_RS ?
>>
>> That doesn't look right.
>
> Yay.. Didn't catch these since this path never gets executed under GEN8
> anyway which uses execlist not legacy batch buffer execution. Better
> remove this then.
But GEN8 HW can run in legacy ringbuffer mode, and the driver continues
to support it, at least for now, so AFAIK there's nothing preventing you
using the Resource Streamer in ringbuffer mode; indeed I note that the
MI_RS_CONTEXT instruction can ONLY be used in ringbuffer mode.
Please don't conflate changes that are (or ought to be) orthogonal, such
as 32- vs 48-bit addressing and ringbuffer vs. execlists, just because
they were introduced in the same h/w generation ...
.Dave.
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] drm/i915: Expose I915_EXEC_RESOURCE_STREAMER flag
2015-06-08 10:04 ` [PATCH 3/3] drm/i915: Expose I915_EXEC_RESOURCE_STREAMER flag Abdiel Janulgue
@ 2015-06-13 15:41 ` shuang.he
0 siblings, 0 replies; 10+ messages in thread
From: shuang.he @ 2015-06-13 15:41 UTC (permalink / raw)
To: shuang.he, lei.a.liu, intel-gfx, abdiel.janulgue
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6555
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 276/276 276/276
ILK 303/303 303/303
SNB 312/312 312/312
IVB 343/343 343/343
BYT 287/287 287/287
BDW 321/321 321/321
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
Note: You need to pay more attention to line start with '*'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2015-06-13 15:41 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-06-08 10:04 drm/i915/hsw/bdw: Enable resource streamer v3 Abdiel Janulgue
2015-06-08 10:04 ` [PATCH 1/3] drm/i915: Enable resource streamer bits on MI_BATCH_BUFFER_START Abdiel Janulgue
2015-06-08 16:10 ` Ville Syrjälä
2015-06-08 17:42 ` Abdiel Janulgue
2015-06-08 17:55 ` Chris Wilson
2015-06-09 11:48 ` Dave Gordon
2015-06-08 10:04 ` [PATCH 2/3] drm/i915: Enable Resource Streamer state save/restore Abdiel Janulgue
2015-06-08 10:04 ` [PATCH 3/3] drm/i915: Expose I915_EXEC_RESOURCE_STREAMER flag Abdiel Janulgue
2015-06-13 15:41 ` shuang.he
2015-06-08 15:40 ` drm/i915/hsw/bdw: Enable resource streamer v3 Abdiel Janulgue
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