From: Caesar Wang <wxt@rock-chips.com> To: Heiko Stuebner <heiko@sntech.de> Cc: dianders@chromium.org, Dmitry Torokhov <dmitry.torokhov@gmail.com>, linux-rockchip@lists.infradead.org, Caesar Wang <wxt@rock-chips.com>, Russell King <linux@arm.linux.org.uk>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 3/3] ARM: rockchip: fix the SMP code style Date: Tue, 9 Jun 2015 17:49:59 +0800 [thread overview] Message-ID: <1433843400-24831-4-git-send-email-wxt@rock-chips.com> (raw) In-Reply-To: <1433843400-24831-1-git-send-email-wxt@rock-chips.com> Use the below scripts to check: scripts/checkpatch.pl -f --subject arch/arm/mach-rockchip/platsmp.c Signed-off-by: Caesar Wang <wxt@rock-chips.com> --- Changes in v6: - fix the commnet Unified format. Series-changes: 5 - Add the changelog. Series-changes: 2 - Use the checkpatch.pl -f --subjective to check. arch/arm/mach-rockchip/platsmp.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index d629206..30ccb82 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -100,7 +100,7 @@ static int pmu_set_power_domain(int pd, bool on) ret = pmu_power_domain_is_on(pd); if (ret < 0) { pr_err("%s: could not read power domain state\n", - __func__); + __func__); return ret; } } @@ -130,7 +130,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu, if (cpu >= ncores) { pr_err("%s: cpu %d outside maximum number of cpus %d\n", - __func__, cpu, ncores); + __func__, cpu, ncores); return -ENXIO; } @@ -140,7 +140,8 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu, return ret; if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) { - /* We communicate with the bootrom to active the cpus other + /* + * We communicate with the bootrom to active the cpus other * than cpu0, after a blob of initialize code, they will * stay at wfe state, once they are actived, they will check * the mailbox: @@ -149,11 +150,11 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu, * The cpu0 need to wait the other cpus other than cpu0 entering * the wfe state.The wait time is affected by many aspects. * (e.g: cpu frequency, bootrom frequency, sram frequency, ...) - * */ + */ mdelay(1); /* ensure the cpus other than cpu0 to startup */ writel(virt_to_phys(rockchip_secondary_startup), - sram_base_addr + 8); + sram_base_addr + 8); writel(0xDEADBEAF, sram_base_addr + 4); dsb_sev(); } @@ -336,7 +337,7 @@ static int rockchip_cpu_kill(unsigned int cpu) static void rockchip_cpu_die(unsigned int cpu) { v7_exit_coherency_flush(louis); - while(1) + while (1) cpu_do_idle(); } #endif @@ -349,4 +350,5 @@ static struct smp_operations rockchip_smp_ops __initdata = { .cpu_die = rockchip_cpu_die, #endif }; + CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops); -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: wxt@rock-chips.com (Caesar Wang) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 3/3] ARM: rockchip: fix the SMP code style Date: Tue, 9 Jun 2015 17:49:59 +0800 [thread overview] Message-ID: <1433843400-24831-4-git-send-email-wxt@rock-chips.com> (raw) In-Reply-To: <1433843400-24831-1-git-send-email-wxt@rock-chips.com> Use the below scripts to check: scripts/checkpatch.pl -f --subject arch/arm/mach-rockchip/platsmp.c Signed-off-by: Caesar Wang <wxt@rock-chips.com> --- Changes in v6: - fix the commnet Unified format. Series-changes: 5 - Add the changelog. Series-changes: 2 - Use the checkpatch.pl -f --subjective to check. arch/arm/mach-rockchip/platsmp.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c index d629206..30ccb82 100644 --- a/arch/arm/mach-rockchip/platsmp.c +++ b/arch/arm/mach-rockchip/platsmp.c @@ -100,7 +100,7 @@ static int pmu_set_power_domain(int pd, bool on) ret = pmu_power_domain_is_on(pd); if (ret < 0) { pr_err("%s: could not read power domain state\n", - __func__); + __func__); return ret; } } @@ -130,7 +130,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu, if (cpu >= ncores) { pr_err("%s: cpu %d outside maximum number of cpus %d\n", - __func__, cpu, ncores); + __func__, cpu, ncores); return -ENXIO; } @@ -140,7 +140,8 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu, return ret; if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) { - /* We communicate with the bootrom to active the cpus other + /* + * We communicate with the bootrom to active the cpus other * than cpu0, after a blob of initialize code, they will * stay at wfe state, once they are actived, they will check * the mailbox: @@ -149,11 +150,11 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu, * The cpu0 need to wait the other cpus other than cpu0 entering * the wfe state.The wait time is affected by many aspects. * (e.g: cpu frequency, bootrom frequency, sram frequency, ...) - * */ + */ mdelay(1); /* ensure the cpus other than cpu0 to startup */ writel(virt_to_phys(rockchip_secondary_startup), - sram_base_addr + 8); + sram_base_addr + 8); writel(0xDEADBEAF, sram_base_addr + 4); dsb_sev(); } @@ -336,7 +337,7 @@ static int rockchip_cpu_kill(unsigned int cpu) static void rockchip_cpu_die(unsigned int cpu) { v7_exit_coherency_flush(louis); - while(1) + while (1) cpu_do_idle(); } #endif @@ -349,4 +350,5 @@ static struct smp_operations rockchip_smp_ops __initdata = { .cpu_die = rockchip_cpu_die, #endif }; + CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops); -- 1.9.1
next prev parent reply other threads:[~2015-06-09 9:50 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-06-09 9:49 [PATCH v6 0/3] ARM: rockchip: fix the SMP Caesar Wang 2015-06-09 9:49 ` Caesar Wang 2015-06-09 9:49 ` [PATCH v6 1/3] ARM: rockchip: fix the CPU soft reset Caesar Wang 2015-06-09 9:49 ` Caesar Wang 2015-06-09 9:49 ` Caesar Wang 2015-06-09 18:16 ` Doug Anderson 2015-06-09 18:16 ` Doug Anderson 2015-06-09 18:16 ` Doug Anderson 2015-06-10 5:58 ` Kever Yang 2015-06-10 5:58 ` Kever Yang 2015-06-09 9:49 ` [PATCH v6 2/3] ARM: rockchip: ensure CPU to enter WFI/WFE state Caesar Wang 2015-06-09 9:49 ` Caesar Wang 2015-06-09 18:13 ` Doug Anderson 2015-06-09 18:13 ` Doug Anderson 2015-06-09 18:13 ` Doug Anderson 2015-06-10 5:59 ` Kever Yang 2015-06-10 5:59 ` Kever Yang 2015-06-09 9:49 ` Caesar Wang [this message] 2015-06-09 9:49 ` [PATCH v6 3/3] ARM: rockchip: fix the SMP code style Caesar Wang 2015-06-09 18:17 ` Doug Anderson 2015-06-09 18:17 ` Doug Anderson 2015-06-09 18:17 ` Doug Anderson 2015-06-10 5:59 ` Kever Yang 2015-06-10 5:59 ` Kever Yang 2015-06-09 20:04 ` [PATCH v6 0/3] ARM: rockchip: fix the SMP Heiko Stübner 2015-06-09 20:04 ` Heiko Stübner 2015-06-13 21:02 ` Heiko Stübner 2015-06-13 21:02 ` Heiko Stübner
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