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* [PATCH v2] ARM: tegra124: pmu support
@ 2015-06-15 18:46 ` Kyle Huey
  0 siblings, 0 replies; 10+ messages in thread
From: Kyle Huey @ 2015-06-15 18:46 UTC (permalink / raw)
  To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
	Russell King, Stephen Warren, Thierry Reding, Alexandre Courbot,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA
  Cc: Jon Hunter, Kyle Huey

This patch modifies the device tree for tegra124 based devices to enable the Cortex A15 PMU.  The interrupt numbers are taken from NVIDIA TRM DP-06905-001_v03p.  This patch was tested on a Jetson TK1.

Signed-off-by: Kyle Huey <khuey-OhBmq/TcCDJWk0Htik3J/w@public.gmane.org>
---
 arch/arm/boot/dts/tegra124.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 4be06c6..d966d4e 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -906,16 +906,24 @@
 
 		cpu@3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <3>;
 		};
 	};
 
+	pmu {
+		compatible = "arm,cortex-a15-pmu";
+		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
 	thermal-zones {
 		cpu {
 			polling-delay-passive = <1000>;
 			polling-delay = <1000>;
 
 			thermal-sensors =
 				<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
 		};
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 10+ messages in thread
* [PATCH v2] ARM: tegra124: pmu support
@ 2015-06-15 18:46 ` Kyle Huey
  0 siblings, 0 replies; 10+ messages in thread
From: Kyle Huey @ 2015-06-15 18:46 UTC (permalink / raw)
  To: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
	Russell King, Stephen Warren, Thierry Reding, Alexandre Courbot,
	devicetree, linux-arm-kernel, linux-tegra, linux-kernel
  Cc: Jon Hunter, Kyle Huey

This patch modifies the device tree for tegra124 based devices to enable the Cortex A15 PMU.  The interrupt numbers are taken from NVIDIA TRM DP-06905-001_v03p.  This patch was tested on a Jetson TK1.

Signed-off-by: Kyle Huey <khuey@kylehuey.com>
---
 arch/arm/boot/dts/tegra124.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 4be06c6..d966d4e 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -906,16 +906,24 @@
 
 		cpu@3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <3>;
 		};
 	};
 
+	pmu {
+		compatible = "arm,cortex-a15-pmu";
+		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
 	thermal-zones {
 		cpu {
 			polling-delay-passive = <1000>;
 			polling-delay = <1000>;
 
 			thermal-sensors =
 				<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
 		};
-- 
1.9.1


^ permalink raw reply related	[flat|nested] 10+ messages in thread
* [PATCH v2] ARM: tegra124: pmu support
@ 2015-06-15 18:46 ` Kyle Huey
  0 siblings, 0 replies; 10+ messages in thread
From: Kyle Huey @ 2015-06-15 18:46 UTC (permalink / raw)
  To: linux-arm-kernel

This patch modifies the device tree for tegra124 based devices to enable the Cortex A15 PMU.  The interrupt numbers are taken from NVIDIA TRM DP-06905-001_v03p.  This patch was tested on a Jetson TK1.

Signed-off-by: Kyle Huey <khuey@kylehuey.com>
---
 arch/arm/boot/dts/tegra124.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 4be06c6..d966d4e 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -906,16 +906,24 @@
 
 		cpu at 3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a15";
 			reg = <3>;
 		};
 	};
 
+	pmu {
+		compatible = "arm,cortex-a15-pmu";
+		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
 	thermal-zones {
 		cpu {
 			polling-delay-passive = <1000>;
 			polling-delay = <1000>;
 
 			thermal-sensors =
 				<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
 		};
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 10+ messages in thread
* Re: [PATCH v2] ARM: tegra124: pmu support
  2015-06-15 18:46 ` Kyle Huey
  (?)
@ 2015-06-15 23:45   ` Jon Hunter
  -1 siblings, 0 replies; 10+ messages in thread
From: Jon Hunter @ 2015-06-15 23:45 UTC (permalink / raw)
  To: Kyle Huey, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell,
	Kumar Gala, Russell King, Stephen Warren, Thierry Reding,
	Alexandre Courbot, devicetree, linux-arm-kernel, linux-tegra,
	linux-kernel
  Cc: Kyle Huey


On 15/06/15 19:46, Kyle Huey wrote:
> This patch modifies the device tree for tegra124 based devices to enable the Cortex A15 PMU.  The interrupt numbers are taken from NVIDIA TRM DP-06905-001_v03p.  This patch was tested on a Jetson TK1.
> 
> Signed-off-by: Kyle Huey <khuey@kylehuey.com>
> ---
>  arch/arm/boot/dts/tegra124.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
> index 4be06c6..d966d4e 100644
> --- a/arch/arm/boot/dts/tegra124.dtsi
> +++ b/arch/arm/boot/dts/tegra124.dtsi
> @@ -906,16 +906,24 @@
>  
>  		cpu@3 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a15";
>  			reg = <3>;
>  		};
>  	};
>  
> +	pmu {
> +		compatible = "arm,cortex-a15-pmu";
> +		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
>  	thermal-zones {
>  		cpu {
>  			polling-delay-passive = <1000>;
>  			polling-delay = <1000>;
>  
>  			thermal-sensors =
>  				<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
>  		};
> 

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Jon

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH v2] ARM: tegra124: pmu support
@ 2015-06-15 23:45   ` Jon Hunter
  0 siblings, 0 replies; 10+ messages in thread
From: Jon Hunter @ 2015-06-15 23:45 UTC (permalink / raw)
  To: Kyle Huey, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell,
	Kumar Gala, Russell King, Stephen Warren, Thierry Reding,
	Alexandre Courbot, devicetree, linux-arm-kernel, linux-tegra,
	linux-kernel
  Cc: Kyle Huey


On 15/06/15 19:46, Kyle Huey wrote:
> This patch modifies the device tree for tegra124 based devices to enable the Cortex A15 PMU.  The interrupt numbers are taken from NVIDIA TRM DP-06905-001_v03p.  This patch was tested on a Jetson TK1.
> 
> Signed-off-by: Kyle Huey <khuey@kylehuey.com>
> ---
>  arch/arm/boot/dts/tegra124.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
> index 4be06c6..d966d4e 100644
> --- a/arch/arm/boot/dts/tegra124.dtsi
> +++ b/arch/arm/boot/dts/tegra124.dtsi
> @@ -906,16 +906,24 @@
>  
>  		cpu@3 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a15";
>  			reg = <3>;
>  		};
>  	};
>  
> +	pmu {
> +		compatible = "arm,cortex-a15-pmu";
> +		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
>  	thermal-zones {
>  		cpu {
>  			polling-delay-passive = <1000>;
>  			polling-delay = <1000>;
>  
>  			thermal-sensors =
>  				<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
>  		};
> 

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Jon

^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH v2] ARM: tegra124: pmu support
@ 2015-06-15 23:45   ` Jon Hunter
  0 siblings, 0 replies; 10+ messages in thread
From: Jon Hunter @ 2015-06-15 23:45 UTC (permalink / raw)
  To: linux-arm-kernel


On 15/06/15 19:46, Kyle Huey wrote:
> This patch modifies the device tree for tegra124 based devices to enable the Cortex A15 PMU.  The interrupt numbers are taken from NVIDIA TRM DP-06905-001_v03p.  This patch was tested on a Jetson TK1.
> 
> Signed-off-by: Kyle Huey <khuey@kylehuey.com>
> ---
>  arch/arm/boot/dts/tegra124.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
> index 4be06c6..d966d4e 100644
> --- a/arch/arm/boot/dts/tegra124.dtsi
> +++ b/arch/arm/boot/dts/tegra124.dtsi
> @@ -906,16 +906,24 @@
>  
>  		cpu at 3 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a15";
>  			reg = <3>;
>  		};
>  	};
>  
> +	pmu {
> +		compatible = "arm,cortex-a15-pmu";
> +		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +
>  	thermal-zones {
>  		cpu {
>  			polling-delay-passive = <1000>;
>  			polling-delay = <1000>;
>  
>  			thermal-sensors =
>  				<&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
>  		};
> 

Acked-by: Jon Hunter <jonathanh@nvidia.com>

Jon

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH v2] ARM: tegra124: pmu support
  2015-06-15 18:46 ` Kyle Huey
  (?)
@ 2015-06-16  9:16   ` Mark Rutland
  -1 siblings, 0 replies; 10+ messages in thread
From: Mark Rutland @ 2015-06-16  9:16 UTC (permalink / raw)
  To: Kyle Huey
  Cc: Rob Herring, Pawel Moll, Ian Campbell, Kumar Gala, Russell King,
	Stephen Warren, Thierry Reding, Alexandre Courbot, devicetree,
	linux-arm-kernel, linux-tegra, linux-kernel, Jon Hunter,
	Kyle Huey

On Mon, Jun 15, 2015 at 07:46:08PM +0100, Kyle Huey wrote:
> This patch modifies the device tree for tegra124 based devices to enable the Cortex A15 PMU.  The interrupt numbers are taken from NVIDIA TRM DP-06905-001_v03p.  This patch was tested on a Jetson TK1.
> 
> Signed-off-by: Kyle Huey <khuey@kylehuey.com>
> ---
>  arch/arm/boot/dts/tegra124.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
> index 4be06c6..d966d4e 100644
> --- a/arch/arm/boot/dts/tegra124.dtsi
> +++ b/arch/arm/boot/dts/tegra124.dtsi
> @@ -906,16 +906,24 @@
>  
>  		cpu@3 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a15";
>  			reg = <3>;
>  		};
>  	};
>  
> +	pmu {
> +		compatible = "arm,cortex-a15-pmu";
> +		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> +	};

As these are SPIs, you should fill in the interrupt-affinity property
(see Documentation/devicetree/bindings/arm/pmu.txt). That'll avoid
potential problems with CPU renumbering, and prevent the kernel from
complaining at boot time.

Otherwise, this looks fine.

Thanks,
Mark.

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH v2] ARM: tegra124: pmu support
@ 2015-06-16  9:16   ` Mark Rutland
  0 siblings, 0 replies; 10+ messages in thread
From: Mark Rutland @ 2015-06-16  9:16 UTC (permalink / raw)
  To: Kyle Huey
  Cc: Rob Herring, Pawel Moll, Ian Campbell, Kumar Gala, Russell King,
	Stephen Warren, Thierry Reding, Alexandre Courbot, devicetree,
	linux-arm-kernel, linux-tegra, linux-kernel, Jon Hunter,
	Kyle Huey

On Mon, Jun 15, 2015 at 07:46:08PM +0100, Kyle Huey wrote:
> This patch modifies the device tree for tegra124 based devices to enable the Cortex A15 PMU.  The interrupt numbers are taken from NVIDIA TRM DP-06905-001_v03p.  This patch was tested on a Jetson TK1.
> 
> Signed-off-by: Kyle Huey <khuey@kylehuey.com>
> ---
>  arch/arm/boot/dts/tegra124.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
> index 4be06c6..d966d4e 100644
> --- a/arch/arm/boot/dts/tegra124.dtsi
> +++ b/arch/arm/boot/dts/tegra124.dtsi
> @@ -906,16 +906,24 @@
>  
>  		cpu@3 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a15";
>  			reg = <3>;
>  		};
>  	};
>  
> +	pmu {
> +		compatible = "arm,cortex-a15-pmu";
> +		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> +	};

As these are SPIs, you should fill in the interrupt-affinity property
(see Documentation/devicetree/bindings/arm/pmu.txt). That'll avoid
potential problems with CPU renumbering, and prevent the kernel from
complaining at boot time.

Otherwise, this looks fine.

Thanks,
Mark.

^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH v2] ARM: tegra124: pmu support
@ 2015-06-16  9:16   ` Mark Rutland
  0 siblings, 0 replies; 10+ messages in thread
From: Mark Rutland @ 2015-06-16  9:16 UTC (permalink / raw)
  To: linux-arm-kernel

On Mon, Jun 15, 2015 at 07:46:08PM +0100, Kyle Huey wrote:
> This patch modifies the device tree for tegra124 based devices to enable the Cortex A15 PMU.  The interrupt numbers are taken from NVIDIA TRM DP-06905-001_v03p.  This patch was tested on a Jetson TK1.
> 
> Signed-off-by: Kyle Huey <khuey@kylehuey.com>
> ---
>  arch/arm/boot/dts/tegra124.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
> index 4be06c6..d966d4e 100644
> --- a/arch/arm/boot/dts/tegra124.dtsi
> +++ b/arch/arm/boot/dts/tegra124.dtsi
> @@ -906,16 +906,24 @@
>  
>  		cpu at 3 {
>  			device_type = "cpu";
>  			compatible = "arm,cortex-a15";
>  			reg = <3>;
>  		};
>  	};
>  
> +	pmu {
> +		compatible = "arm,cortex-a15-pmu";
> +		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> +			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> +	};

As these are SPIs, you should fill in the interrupt-affinity property
(see Documentation/devicetree/bindings/arm/pmu.txt). That'll avoid
potential problems with CPU renumbering, and prevent the kernel from
complaining at boot time.

Otherwise, this looks fine.

Thanks,
Mark.

^ permalink raw reply	[flat|nested] 10+ messages in thread
* Re: [PATCH v2] ARM: tegra124: pmu support
  2015-06-16  9:16   ` Mark Rutland
  (?)
  (?)
@ 2015-06-16 21:29   ` Kyle Huey
  -1 siblings, 0 replies; 10+ messages in thread
From: Kyle Huey @ 2015-06-16 21:29 UTC (permalink / raw)
  To: Mark Rutland
  Cc: Rob Herring, Pawel Moll, Ian Campbell, Kumar Gala, Russell King,
	Stephen Warren, Thierry Reding, Alexandre Courbot, devicetree,
	linux-arm-kernel, linux-tegra, linux-kernel, Jon Hunter,
	Kyle Huey

[-- Attachment #1: Type: text/plain, Size: 1651 bytes --]

On Tue, Jun 16, 2015 at 2:16 AM, Mark Rutland <mark.rutland@arm.com> wrote:

> On Mon, Jun 15, 2015 at 07:46:08PM +0100, Kyle Huey wrote:
> > This patch modifies the device tree for tegra124 based devices to enable
> the Cortex A15 PMU.  The interrupt numbers are taken from NVIDIA TRM
> DP-06905-001_v03p.  This patch was tested on a Jetson TK1.
> >
> > Signed-off-by: Kyle Huey <khuey@kylehuey.com>
> > ---
> >  arch/arm/boot/dts/tegra124.dtsi | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/tegra124.dtsi
> b/arch/arm/boot/dts/tegra124.dtsi
> > index 4be06c6..d966d4e 100644
> > --- a/arch/arm/boot/dts/tegra124.dtsi
> > +++ b/arch/arm/boot/dts/tegra124.dtsi
> > @@ -906,16 +906,24 @@
> >
> >               cpu@3 {
> >                       device_type = "cpu";
> >                       compatible = "arm,cortex-a15";
> >                       reg = <3>;
> >               };
> >       };
> >
> > +     pmu {
> > +             compatible = "arm,cortex-a15-pmu";
> > +             interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> > +                          <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
> > +     };
>
> As these are SPIs, you should fill in the interrupt-affinity property
> (see Documentation/devicetree/bindings/arm/pmu.txt). That'll avoid
> potential problems with CPU renumbering, and prevent the kernel from
> complaining at boot time.
>
> Otherwise, this looks fine.
>
> Thanks,
> Mark.
>

Thanks for the review.  I just sent a v3 with this addressed.

- Kyle

[-- Attachment #2: Type: text/html, Size: 2430 bytes --]

^ permalink raw reply	[flat|nested] 10+ messages in thread
end of thread, other threads:[~2015-06-16 21:29 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-06-15 18:46 [PATCH v2] ARM: tegra124: pmu support Kyle Huey
2015-06-15 18:46 ` Kyle Huey
2015-06-15 18:46 ` Kyle Huey
2015-06-15 23:45 ` Jon Hunter
2015-06-15 23:45   ` Jon Hunter
2015-06-15 23:45   ` Jon Hunter
2015-06-16  9:16 ` Mark Rutland
2015-06-16  9:16   ` Mark Rutland
2015-06-16  9:16   ` Mark Rutland
2015-06-16 21:29   ` Kyle Huey

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