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* [PATCH v3] spi: img-spfi: Same Edge bit set to double supported transfer speed
@ 2015-06-17 10:48 ` Sifan Naeem
  0 siblings, 0 replies; 4+ messages in thread
From: Sifan Naeem @ 2015-06-17 10:48 UTC (permalink / raw)
  To: broonie; +Cc: linux-spi, linux-kernel, abrestic, Sifan Naeem

Same edge bit set in SPFI Control register to double the supported
spfi clock speed. Setting this bit increases the supported spfi
frequency from 1/8 to 1/4 of the core clock frequency.

Without this bit set the maximum speed supported was 25MHz on
Pistachio.

Signed-off-by: Sifan Naeem <sifan.naeem@imgtec.com>
---
 changes from v2: Gerrit Change-Id removed from commit message
 drivers/spi/spi-img-spfi.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/spi/spi-img-spfi.c b/drivers/spi/spi-img-spfi.c
index 788e2b1..acce90a 100644
--- a/drivers/spi/spi-img-spfi.c
+++ b/drivers/spi/spi-img-spfi.c
@@ -40,6 +40,7 @@
 #define SPFI_CONTROL_SOFT_RESET			BIT(11)
 #define SPFI_CONTROL_SEND_DMA			BIT(10)
 #define SPFI_CONTROL_GET_DMA			BIT(9)
+#define SPFI_CONTROL_SE			BIT(8)
 #define SPFI_CONTROL_TMODE_SHIFT		5
 #define SPFI_CONTROL_TMODE_MASK			0x7
 #define SPFI_CONTROL_TMODE_SINGLE		0
@@ -491,6 +492,7 @@ static void img_spfi_config(struct spi_master *master, struct spi_device *spi,
 	else if (xfer->tx_nbits == SPI_NBITS_QUAD &&
 		 xfer->rx_nbits == SPI_NBITS_QUAD)
 		val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT;
+	val |= SPFI_CONTROL_SE;
 	spfi_writel(spfi, val, SPFI_CONTROL);
 }
 
-- 
1.7.9.5


^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [PATCH v3] spi: img-spfi: Same Edge bit set to double supported transfer speed
@ 2015-06-17 10:48 ` Sifan Naeem
  0 siblings, 0 replies; 4+ messages in thread
From: Sifan Naeem @ 2015-06-17 10:48 UTC (permalink / raw)
  To: broonie-DgEjT+Ai2ygdnm+yROfE0A
  Cc: linux-spi-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	abrestic-F7+t8E8rja9g9hUCZPvPmw, Sifan Naeem

Same edge bit set in SPFI Control register to double the supported
spfi clock speed. Setting this bit increases the supported spfi
frequency from 1/8 to 1/4 of the core clock frequency.

Without this bit set the maximum speed supported was 25MHz on
Pistachio.

Signed-off-by: Sifan Naeem <sifan.naeem-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
---
 changes from v2: Gerrit Change-Id removed from commit message
 drivers/spi/spi-img-spfi.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/spi/spi-img-spfi.c b/drivers/spi/spi-img-spfi.c
index 788e2b1..acce90a 100644
--- a/drivers/spi/spi-img-spfi.c
+++ b/drivers/spi/spi-img-spfi.c
@@ -40,6 +40,7 @@
 #define SPFI_CONTROL_SOFT_RESET			BIT(11)
 #define SPFI_CONTROL_SEND_DMA			BIT(10)
 #define SPFI_CONTROL_GET_DMA			BIT(9)
+#define SPFI_CONTROL_SE			BIT(8)
 #define SPFI_CONTROL_TMODE_SHIFT		5
 #define SPFI_CONTROL_TMODE_MASK			0x7
 #define SPFI_CONTROL_TMODE_SINGLE		0
@@ -491,6 +492,7 @@ static void img_spfi_config(struct spi_master *master, struct spi_device *spi,
 	else if (xfer->tx_nbits == SPI_NBITS_QUAD &&
 		 xfer->rx_nbits == SPI_NBITS_QUAD)
 		val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT;
+	val |= SPFI_CONTROL_SE;
 	spfi_writel(spfi, val, SPFI_CONTROL);
 }
 
-- 
1.7.9.5

--
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^ permalink raw reply related	[flat|nested] 4+ messages in thread
* RE: [PATCH v3] spi: img-spfi: Same Edge bit set to double supported transfer speed
@ 2015-06-18 12:52   ` Sifan Naeem
  0 siblings, 0 replies; 4+ messages in thread
From: Sifan Naeem @ 2015-06-18 12:52 UTC (permalink / raw)
  To: broonie; +Cc: linux-spi, linux-kernel, abrestic

Please ignore this patch. I have posted a new patch as a fix after the discussion with Jonas Gorski.

https://patchwork.kernel.org/patch/6636761/ spi: img-spfi: fix support for speeds up to 1/4th input clock

Thanks,
Sifan

> -----Original Message-----
> From: Sifan Naeem
> Sent: 17 June 2015 11:48
> To: broonie@kernel.org
> Cc: linux-spi@vger.kernel.org; linux-kernel@vger.kernel.org;
> abrestic@chromium.org; Sifan Naeem
> Subject: [PATCH v3] spi: img-spfi: Same Edge bit set to double supported
> transfer speed
> 
> Same edge bit set in SPFI Control register to double the supported spfi clock
> speed. Setting this bit increases the supported spfi frequency from 1/8 to 1/4
> of the core clock frequency.
> 
> Without this bit set the maximum speed supported was 25MHz on Pistachio.
> 
> Signed-off-by: Sifan Naeem <sifan.naeem@imgtec.com>
> ---
>  changes from v2: Gerrit Change-Id removed from commit message
>  drivers/spi/spi-img-spfi.c |    2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/spi/spi-img-spfi.c b/drivers/spi/spi-img-spfi.c index
> 788e2b1..acce90a 100644
> --- a/drivers/spi/spi-img-spfi.c
> +++ b/drivers/spi/spi-img-spfi.c
> @@ -40,6 +40,7 @@
>  #define SPFI_CONTROL_SOFT_RESET			BIT(11)
>  #define SPFI_CONTROL_SEND_DMA			BIT(10)
>  #define SPFI_CONTROL_GET_DMA			BIT(9)
> +#define SPFI_CONTROL_SE			BIT(8)
>  #define SPFI_CONTROL_TMODE_SHIFT		5
>  #define SPFI_CONTROL_TMODE_MASK			0x7
>  #define SPFI_CONTROL_TMODE_SINGLE		0
> @@ -491,6 +492,7 @@ static void img_spfi_config(struct spi_master
> *master, struct spi_device *spi,
>  	else if (xfer->tx_nbits == SPI_NBITS_QUAD &&
>  		 xfer->rx_nbits == SPI_NBITS_QUAD)
>  		val |= SPFI_CONTROL_TMODE_QUAD <<
> SPFI_CONTROL_TMODE_SHIFT;
> +	val |= SPFI_CONTROL_SE;
>  	spfi_writel(spfi, val, SPFI_CONTROL);
>  }
> 
> --
> 1.7.9.5


^ permalink raw reply	[flat|nested] 4+ messages in thread
* RE: [PATCH v3] spi: img-spfi: Same Edge bit set to double supported transfer speed
@ 2015-06-18 12:52   ` Sifan Naeem
  0 siblings, 0 replies; 4+ messages in thread
From: Sifan Naeem @ 2015-06-18 12:52 UTC (permalink / raw)
  To: broonie-DgEjT+Ai2ygdnm+yROfE0A
  Cc: linux-spi-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	abrestic-F7+t8E8rja9g9hUCZPvPmw

Please ignore this patch. I have posted a new patch as a fix after the discussion with Jonas Gorski.

https://patchwork.kernel.org/patch/6636761/ spi: img-spfi: fix support for speeds up to 1/4th input clock

Thanks,
Sifan

> -----Original Message-----
> From: Sifan Naeem
> Sent: 17 June 2015 11:48
> To: broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
> Cc: linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org;
> abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org; Sifan Naeem
> Subject: [PATCH v3] spi: img-spfi: Same Edge bit set to double supported
> transfer speed
> 
> Same edge bit set in SPFI Control register to double the supported spfi clock
> speed. Setting this bit increases the supported spfi frequency from 1/8 to 1/4
> of the core clock frequency.
> 
> Without this bit set the maximum speed supported was 25MHz on Pistachio.
> 
> Signed-off-by: Sifan Naeem <sifan.naeem-1AXoQHu6uovQT0dZR+AlfA@public.gmane.org>
> ---
>  changes from v2: Gerrit Change-Id removed from commit message
>  drivers/spi/spi-img-spfi.c |    2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/spi/spi-img-spfi.c b/drivers/spi/spi-img-spfi.c index
> 788e2b1..acce90a 100644
> --- a/drivers/spi/spi-img-spfi.c
> +++ b/drivers/spi/spi-img-spfi.c
> @@ -40,6 +40,7 @@
>  #define SPFI_CONTROL_SOFT_RESET			BIT(11)
>  #define SPFI_CONTROL_SEND_DMA			BIT(10)
>  #define SPFI_CONTROL_GET_DMA			BIT(9)
> +#define SPFI_CONTROL_SE			BIT(8)
>  #define SPFI_CONTROL_TMODE_SHIFT		5
>  #define SPFI_CONTROL_TMODE_MASK			0x7
>  #define SPFI_CONTROL_TMODE_SINGLE		0
> @@ -491,6 +492,7 @@ static void img_spfi_config(struct spi_master
> *master, struct spi_device *spi,
>  	else if (xfer->tx_nbits == SPI_NBITS_QUAD &&
>  		 xfer->rx_nbits == SPI_NBITS_QUAD)
>  		val |= SPFI_CONTROL_TMODE_QUAD <<
> SPFI_CONTROL_TMODE_SHIFT;
> +	val |= SPFI_CONTROL_SE;
>  	spfi_writel(spfi, val, SPFI_CONTROL);
>  }
> 
> --
> 1.7.9.5

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^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2015-06-18 12:52 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2015-06-17 10:48 [PATCH v3] spi: img-spfi: Same Edge bit set to double supported transfer speed Sifan Naeem
2015-06-17 10:48 ` Sifan Naeem
2015-06-18 12:52 ` Sifan Naeem
2015-06-18 12:52   ` Sifan Naeem

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