From: Hanjun Guo <hanjun.guo@linaro.org> To: Marc Zyngier <marc.zyngier@arm.com>, Jason Cooper <jason@lakedaemon.net>, Will Deacon <will.deacon@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, "Rafael J. Wysocki" <rjw@rjwysocki.net> Cc: Thomas Gleixner <tglx@linutronix.de>, Jiang Liu <jiang.liu@linux.intel.com>, Lorenzo Pieralisi <Lorenzo.Pieralisi@arm.com>, Arnd Bergmann <arnd@arndb.de>, Tomasz Nowicki <tomasz.nowicki@linaro.org>, Grant Likely <grant.likely@linaro.org>, Olof Johansson <olof@lixom.net>, Wei Huang <wei@redhat.com>, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, linux-kernel@vger.kernel.org, linaro-acpi@lists.linaro.org, Hanjun Guo <hanjun.guo@linaro.org> Subject: [PATCH v2 7/9] irqchip / GICv3: Refactor gic_of_init() for GICv3 driver Date: Fri, 19 Jun 2015 16:46:10 +0800 [thread overview] Message-ID: <1434703572-26221-8-git-send-email-hanjun.guo@linaro.org> (raw) In-Reply-To: <1434703572-26221-1-git-send-email-hanjun.guo@linaro.org> From: Tomasz Nowicki <tomasz.nowicki@linaro.org> Isolate hardware abstraction (FDT) code to gic_of_init(). Rest of the logic goes to gic_init_bases() and expects well defined data to initialize GIC properly. The same solution is used for GICv2 driver. This is needed for ACPI initialization later. Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> --- drivers/irqchip/irq-gic-v3.c | 105 +++++++++++++++++++++++++------------------ 1 file changed, 61 insertions(+), 44 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 49875ad..87cf81b 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -765,17 +765,69 @@ static const struct irq_domain_ops gic_irq_domain_ops = { .free = gic_irq_domain_free, }; +static int __init gic_init_bases(void __iomem *dist_base, + struct redist_region *rdist_regs, + u32 nr_redist_regions, + u64 redist_stride, + struct device_node *node) +{ + u32 typer; + int gic_irqs; + int err; + + gic_data.dist_base = dist_base; + gic_data.redist_regions = rdist_regs; + gic_data.nr_redist_regions = nr_redist_regions; + gic_data.redist_stride = redist_stride; + + /* + * Find out how many interrupts are supported. + * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) + */ + typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); + gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); + gic_irqs = GICD_TYPER_IRQS(typer); + if (gic_irqs > 1020) + gic_irqs = 1020; + gic_data.irq_nr = gic_irqs; + + gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops, + &gic_data); + gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); + + if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { + err = -ENOMEM; + goto out_free; + } + + set_handle_irq(gic_handle_irq); + + if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) + its_init(node, &gic_data.rdists, gic_data.domain); + + gic_smp_init(); + gic_dist_init(); + gic_cpu_init(); + gic_cpu_pm_init(); + + return 0; + +out_free: + if (gic_data.domain) + irq_domain_remove(gic_data.domain); + free_percpu(gic_data.rdists.rdist); + return err; +} + +#ifdef CONFIG_OF static int __init gic_of_init(struct device_node *node, struct device_node *parent) { void __iomem *dist_base; struct redist_region *rdist_regs; u64 redist_stride; u32 nr_redist_regions; - u32 typer; u32 reg; - int gic_irqs; - int err; - int i; + int err, i; dist_base = of_iomap(node, 0); if (!dist_base) { @@ -819,47 +871,11 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) redist_stride = 0; - gic_data.dist_base = dist_base; - gic_data.redist_regions = rdist_regs; - gic_data.nr_redist_regions = nr_redist_regions; - gic_data.redist_stride = redist_stride; - - /* - * Find out how many interrupts are supported. - * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) - */ - typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); - gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); - gic_irqs = GICD_TYPER_IRQS(typer); - if (gic_irqs > 1020) - gic_irqs = 1020; - gic_data.irq_nr = gic_irqs; + err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, + redist_stride, node); + if (!err) + return 0; - gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops, - &gic_data); - gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); - - if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { - err = -ENOMEM; - goto out_free; - } - - set_handle_irq(gic_handle_irq); - - if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) - its_init(node, &gic_data.rdists, gic_data.domain); - - gic_smp_init(); - gic_dist_init(); - gic_cpu_init(); - gic_cpu_pm_init(); - - return 0; - -out_free: - if (gic_data.domain) - irq_domain_remove(gic_data.domain); - free_percpu(gic_data.rdists.rdist); out_unmap_rdist: for (i = 0; i < nr_redist_regions; i++) if (rdist_regs[i].redist_base) @@ -871,3 +887,4 @@ out_unmap_dist: } IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); +#endif -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: hanjun.guo@linaro.org (Hanjun Guo) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 7/9] irqchip / GICv3: Refactor gic_of_init() for GICv3 driver Date: Fri, 19 Jun 2015 16:46:10 +0800 [thread overview] Message-ID: <1434703572-26221-8-git-send-email-hanjun.guo@linaro.org> (raw) In-Reply-To: <1434703572-26221-1-git-send-email-hanjun.guo@linaro.org> From: Tomasz Nowicki <tomasz.nowicki@linaro.org> Isolate hardware abstraction (FDT) code to gic_of_init(). Rest of the logic goes to gic_init_bases() and expects well defined data to initialize GIC properly. The same solution is used for GICv2 driver. This is needed for ACPI initialization later. Signed-off-by: Tomasz Nowicki <tomasz.nowicki@linaro.org> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org> --- drivers/irqchip/irq-gic-v3.c | 105 +++++++++++++++++++++++++------------------ 1 file changed, 61 insertions(+), 44 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 49875ad..87cf81b 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -765,17 +765,69 @@ static const struct irq_domain_ops gic_irq_domain_ops = { .free = gic_irq_domain_free, }; +static int __init gic_init_bases(void __iomem *dist_base, + struct redist_region *rdist_regs, + u32 nr_redist_regions, + u64 redist_stride, + struct device_node *node) +{ + u32 typer; + int gic_irqs; + int err; + + gic_data.dist_base = dist_base; + gic_data.redist_regions = rdist_regs; + gic_data.nr_redist_regions = nr_redist_regions; + gic_data.redist_stride = redist_stride; + + /* + * Find out how many interrupts are supported. + * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) + */ + typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); + gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); + gic_irqs = GICD_TYPER_IRQS(typer); + if (gic_irqs > 1020) + gic_irqs = 1020; + gic_data.irq_nr = gic_irqs; + + gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops, + &gic_data); + gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); + + if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { + err = -ENOMEM; + goto out_free; + } + + set_handle_irq(gic_handle_irq); + + if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) + its_init(node, &gic_data.rdists, gic_data.domain); + + gic_smp_init(); + gic_dist_init(); + gic_cpu_init(); + gic_cpu_pm_init(); + + return 0; + +out_free: + if (gic_data.domain) + irq_domain_remove(gic_data.domain); + free_percpu(gic_data.rdists.rdist); + return err; +} + +#ifdef CONFIG_OF static int __init gic_of_init(struct device_node *node, struct device_node *parent) { void __iomem *dist_base; struct redist_region *rdist_regs; u64 redist_stride; u32 nr_redist_regions; - u32 typer; u32 reg; - int gic_irqs; - int err; - int i; + int err, i; dist_base = of_iomap(node, 0); if (!dist_base) { @@ -819,47 +871,11 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) redist_stride = 0; - gic_data.dist_base = dist_base; - gic_data.redist_regions = rdist_regs; - gic_data.nr_redist_regions = nr_redist_regions; - gic_data.redist_stride = redist_stride; - - /* - * Find out how many interrupts are supported. - * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) - */ - typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); - gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); - gic_irqs = GICD_TYPER_IRQS(typer); - if (gic_irqs > 1020) - gic_irqs = 1020; - gic_data.irq_nr = gic_irqs; + err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, + redist_stride, node); + if (!err) + return 0; - gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops, - &gic_data); - gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); - - if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { - err = -ENOMEM; - goto out_free; - } - - set_handle_irq(gic_handle_irq); - - if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) - its_init(node, &gic_data.rdists, gic_data.domain); - - gic_smp_init(); - gic_dist_init(); - gic_cpu_init(); - gic_cpu_pm_init(); - - return 0; - -out_free: - if (gic_data.domain) - irq_domain_remove(gic_data.domain); - free_percpu(gic_data.rdists.rdist); out_unmap_rdist: for (i = 0; i < nr_redist_regions; i++) if (rdist_regs[i].redist_base) @@ -871,3 +887,4 @@ out_unmap_dist: } IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); +#endif -- 1.9.1
next prev parent reply other threads:[~2015-06-19 8:47 UTC|newest] Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-06-19 8:46 [PATCH v2 0/9] Add self-probe infrastructure and stacked irqdomain support for ACPI based GICv2/3 init Hanjun Guo 2015-06-19 8:46 ` Hanjun Guo 2015-06-19 8:46 ` [PATCH v2 1/9] ACPICA: ACPI 6.0: Add changes for MADT table Hanjun Guo 2015-06-19 8:46 ` Hanjun Guo 2015-06-19 8:46 ` [PATCH v2 2/9] ACPICA: ACPI 6.0: Add values for MADT GIC version field Hanjun Guo 2015-06-19 8:46 ` Hanjun Guo 2015-06-19 8:46 ` [PATCH v2 3/9] irqchip / GIC: Add GIC version support in ACPI MADT Hanjun Guo 2015-06-19 8:46 ` Hanjun Guo 2015-06-22 16:45 ` Lorenzo Pieralisi 2015-06-22 16:45 ` Lorenzo Pieralisi 2015-06-22 16:45 ` Lorenzo Pieralisi 2015-06-23 11:18 ` Hanjun Guo 2015-06-23 11:18 ` Hanjun Guo 2015-06-23 11:18 ` Hanjun Guo 2015-06-27 6:07 ` Hanjun Guo 2015-06-27 6:07 ` Hanjun Guo 2015-06-27 6:07 ` Hanjun Guo 2015-06-19 8:46 ` [PATCH v2 4/9] ACPI / irqchip: Add self-probe infrastructure to initialize IRQ controller Hanjun Guo 2015-06-19 8:46 ` Hanjun Guo 2015-06-19 8:46 ` [PATCH v2 5/9] irqchip / GIC / ACPI: Use IRQCHIP_ACPI_DECLARE to simplify GICv2 init code Hanjun Guo 2015-06-19 8:46 ` Hanjun Guo 2015-06-19 8:46 ` [PATCH v2 6/9] irqchip / gic: Add stacked irqdomain support for ACPI based GICv2 init Hanjun Guo 2015-06-19 8:46 ` Hanjun Guo 2015-06-22 17:20 ` Lorenzo Pieralisi 2015-06-22 17:20 ` Lorenzo Pieralisi 2015-06-22 17:20 ` Lorenzo Pieralisi 2015-06-23 15:11 ` Hanjun Guo 2015-06-23 15:11 ` Hanjun Guo 2015-06-23 15:11 ` Hanjun Guo 2015-06-23 17:38 ` Lorenzo Pieralisi 2015-06-23 17:38 ` Lorenzo Pieralisi 2015-06-23 17:38 ` Lorenzo Pieralisi 2015-06-27 3:52 ` Hanjun Guo 2015-06-27 3:52 ` Hanjun Guo 2015-06-27 3:52 ` Hanjun Guo 2015-06-29 8:39 ` Marc Zyngier 2015-06-29 8:39 ` Marc Zyngier 2015-06-29 8:39 ` Marc Zyngier 2015-06-30 11:50 ` Hanjun Guo 2015-06-30 11:50 ` Hanjun Guo 2015-06-30 11:50 ` Hanjun Guo 2015-06-30 12:17 ` Marc Zyngier 2015-06-30 12:17 ` Marc Zyngier 2015-06-30 12:17 ` Marc Zyngier 2015-06-30 15:07 ` Graeme Gregory 2015-06-30 15:07 ` Graeme Gregory 2015-06-30 15:07 ` Graeme Gregory 2015-07-03 8:47 ` Hanjun Guo 2015-07-03 8:47 ` Hanjun Guo 2015-07-03 8:47 ` Hanjun Guo 2015-07-08 3:40 ` Hanjun Guo 2015-07-08 3:40 ` Hanjun Guo 2015-07-08 3:40 ` Hanjun Guo 2015-07-10 9:41 ` Marc Zyngier 2015-07-10 9:41 ` Marc Zyngier 2015-07-10 9:41 ` Marc Zyngier 2015-06-19 8:46 ` Hanjun Guo [this message] 2015-06-19 8:46 ` [PATCH v2 7/9] irqchip / GICv3: Refactor gic_of_init() for GICv3 driver Hanjun Guo 2015-06-19 8:46 ` [PATCH v2 8/9] irqchip / GICv3: Add ACPI support for GICv3+ initialization Hanjun Guo 2015-06-19 8:46 ` Hanjun Guo 2015-06-19 8:46 ` [PATCH v2 9/9] irqchip / GICv3: Add stacked irqdomain support for ACPI based init Hanjun Guo 2015-06-19 8:46 ` Hanjun Guo
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