[PATCH v2 0/6] Ring frequency & Rpe changes for SKL

[PATCH v2 0/6] Ring frequency & Rpe changes for SKL

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

This patch series adds the changes for supporting the Ring frequency table
programming and retrieving the efficient frequency (aka RPe) value from the
pcode for SKL.
Addressed review comments from Ville, Daniel & added r-b tag from
Rodrigo on the 3 patches

Akash Goel (6):
  drm/i915/skl: Retrieve the Rpe value from Pcode
  drm/i915/skl: Ring frequency table programming changes
  drm/i915/skl: Restrict the ring frequency table programming to SKL
  drm/i915: Corrected the platform checks in i915_ring_freq_table
    function
  drm/i915/skl: Updated the i915_ring_freq_table debugfs function
  drm/i915: Added BXT check in i915_ring_freq_table function

 drivers/gpu/drm/i915/i915_debugfs.c | 22 +++++++++++++----
 drivers/gpu/drm/i915/intel_pm.c     | 47 ++++++++++++++++++++++++++-----------
 2 files changed, 50 insertions(+), 19 deletions(-)

-- 
1.9.2

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[PATCH 1/6] drm/i915/skl: Retrieve the Rpe value from Pcode

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Read the efficient frequency (aka RPe) value through the the mailbox
command (0x1A) from the pcode, as done on Haswell and Broadwell.
The turbo minimum frequency softlimit is not revised as per the
efficient frequency value.

v2: Replaced the conditional expression operator with 'if' statement (Tom)
v3: Corrected the derivation of efficient frequency & shifted the
    GEN9_FREQ_SCALER multiplications downwards (Ville)

Issue: VIZ-5143
Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 32ff034..8185a23 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4295,18 +4295,11 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
 	dev_priv->rps.rp0_freq		= (rp_state_cap >>  0) & 0xff;
 	dev_priv->rps.rp1_freq		= (rp_state_cap >>  8) & 0xff;
 	dev_priv->rps.min_freq		= (rp_state_cap >> 16) & 0xff;
-	if (IS_SKYLAKE(dev)) {
-		/* Store the frequency values in 16.66 MHZ units, which is
-		   the natural hardware unit for SKL */
-		dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
-		dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
-		dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
-	}
 	/* hw_max = RP0 until we check for overclocking */
 	dev_priv->rps.max_freq		= dev_priv->rps.rp0_freq;
 
 	dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
-	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+	if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
 		ret = sandybridge_pcode_read(dev_priv,
 					HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
 					&ddcc_status);
@@ -4318,6 +4311,16 @@ static void gen6_init_rps_frequencies(struct drm_device *dev)
 					dev_priv->rps.max_freq);
 	}
 
+	if (IS_SKYLAKE(dev)) {
+		/* Store the frequency values in 16.66 MHZ units, which is
+		   the natural hardware unit for SKL */
+		dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
+		dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
+		dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
+		dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
+		dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
+	}
+
 	dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
 
 	/* Preserve min/max settings in case of re-init */
-- 
1.9.2

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[PATCH 2/6] drm/i915/skl: Ring frequency table programming changes

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Ring frequency table programming changes for SKL. No need for a
floor on ring frequency, as the issue of performance impact with
ring running below DDR frequency, is believed to be fixed on SKL

v2: Removed the check for avoiding ring frequency programming for BXT (Rodrigo)

Issue: VIZ-5144
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++++++++++----
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8185a23..89c1b73 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4613,6 +4613,7 @@ static void __gen6_update_ring_freq(struct drm_device *dev)
 	int min_freq = 15;
 	unsigned int gpu_freq;
 	unsigned int max_ia_freq, min_ring_freq;
+	unsigned int max_gpu_freq, min_gpu_freq;
 	int scaling_factor = 180;
 	struct cpufreq_policy *policy;
 
@@ -4637,17 +4638,31 @@ static void __gen6_update_ring_freq(struct drm_device *dev)
 	/* convert DDR frequency from units of 266.6MHz to bandwidth */
 	min_ring_freq = mult_frac(min_ring_freq, 8, 3);
 
+	if (IS_SKYLAKE(dev)) {
+		/* Convert GT frequency to 50 HZ units */
+		min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
+		max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
+	} else {
+		min_gpu_freq = dev_priv->rps.min_freq;
+		max_gpu_freq = dev_priv->rps.max_freq;
+	}
+
 	/*
 	 * For each potential GPU frequency, load a ring frequency we'd like
 	 * to use for memory access.  We do this by specifying the IA frequency
 	 * the PCU should use as a reference to determine the ring frequency.
 	 */
-	for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
-	     gpu_freq--) {
-		int diff = dev_priv->rps.max_freq - gpu_freq;
+	for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
+		int diff = max_gpu_freq - gpu_freq;
 		unsigned int ia_freq = 0, ring_freq = 0;
 
-		if (INTEL_INFO(dev)->gen >= 8) {
+		if (IS_SKYLAKE(dev)) {
+			/*
+			 * ring_freq = 2 * GT. ring_freq is in 100MHz units
+			 * No floor required for ring frequency on SKL.
+			 */
+			ring_freq = gpu_freq;
+		} else if (INTEL_INFO(dev)->gen >= 8) {
 			/* max(2 * GT, DDR). NB: GT is 50MHz units */
 			ring_freq = max(min_ring_freq, gpu_freq);
 		} else if (IS_HASWELL(dev)) {
-- 
1.9.2

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[PATCH 3/6] drm/i915/skl: Restrict the ring frequency table programming to SKL

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Ring frequency table programming is not required on BXT. Added separate
checks to enable the programming only for SKL & skip for BXT.

Issue: VIZ-5144
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 89c1b73..31d2fa0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4696,7 +4696,7 @@ void gen6_update_ring_freq(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
+	if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev) || IS_BROXTON(dev))
 		return;
 
 	mutex_lock(&dev_priv->rps.hw_lock);
@@ -5811,7 +5811,8 @@ static void intel_gen6_powersave_work(struct work_struct *work)
 	} else if (INTEL_INFO(dev)->gen >= 9) {
 		gen9_enable_rc6(dev);
 		gen9_enable_rps(dev);
-		__gen6_update_ring_freq(dev);
+		if (IS_SKYLAKE(dev))
+			__gen6_update_ring_freq(dev);
 	} else if (IS_BROADWELL(dev)) {
 		gen8_enable_rps(dev);
 		__gen6_update_ring_freq(dev);
-- 
1.9.2

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[PATCH 4/6] drm/i915: Corrected the platform checks in i915_ring_freq_table function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Corrected the platform checks in i915_ring_freq_table debugfs function
so as to allow the read of ring frequency table for BDW and disallow for VLV

v2: Simplified the checks to avoid the double negation (Daniel)

Issue: VIZ-5144
Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index c49fe2a..438c10b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1746,7 +1746,8 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
 	int ret = 0;
 	int gpu_freq, ia_freq;
 
-	if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
+	if (!(IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
+	      IS_BROADWELL(dev))) {
 		seq_puts(m, "unsupported on this chipset\n");
 		return 0;
 	}
-- 
1.9.2

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[PATCH 5/6] drm/i915/skl: Updated the i915_ring_freq_table debugfs function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Updated the i915_ring_freq_table debugfs function to support the read
of ring frequency table, through Punit interface, for SKL also.

Issue: VIZ-5144
Signed-off-by: Akash Goel <akash.goel@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 22 ++++++++++++++++------
 1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 438c10b..2666d8a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1745,9 +1745,9 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret = 0;
 	int gpu_freq, ia_freq;
+	unsigned int max_gpu_freq, min_gpu_freq;
 
-	if (!(IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
-	      IS_BROADWELL(dev))) {
+	if ((INTEL_INFO(dev)->gen < 6) || IS_VALLEYVIEW(dev)) {
 		seq_puts(m, "unsupported on this chipset\n");
 		return 0;
 	}
@@ -1760,17 +1760,27 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
 	if (ret)
 		goto out;
 
+	if (IS_SKYLAKE(dev)) {
+		/* Convert GT frequency to 50 HZ units */
+		min_gpu_freq =
+			dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
+		max_gpu_freq =
+			dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
+	} else {
+		min_gpu_freq = dev_priv->rps.min_freq_softlimit;
+		max_gpu_freq = dev_priv->rps.max_freq_softlimit;
+	}
+
 	seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
 
-	for (gpu_freq = dev_priv->rps.min_freq_softlimit;
-	     gpu_freq <= dev_priv->rps.max_freq_softlimit;
-	     gpu_freq++) {
+	for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
 		ia_freq = gpu_freq;
 		sandybridge_pcode_read(dev_priv,
 				       GEN6_PCODE_READ_MIN_FREQ_TABLE,
 				       &ia_freq);
 		seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
-			   intel_gpu_freq(dev_priv, gpu_freq),
+			   intel_gpu_freq(dev_priv, (gpu_freq *
+				(IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))),
 			   ((ia_freq >> 0) & 0xff) * 100,
 			   ((ia_freq >> 8) & 0xff) * 100);
 	}
-- 
1.9.2

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[PATCH 6/6] drm/i915: Added BXT check in i915_ring_freq_table function

[akash.goel]

From: Akash Goel <akash.goel@intel.com>

Updated the i915_ring_freq_table debugfs function to add
the broxton check, so as to disallow the read of ring frequency
table for it.

Issue: VIZ-5144
Signed-off-by: Akash Goel <akash.goel@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2666d8a..daf6bdc 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1747,7 +1747,8 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
 	int gpu_freq, ia_freq;
 	unsigned int max_gpu_freq, min_gpu_freq;
 
-	if ((INTEL_INFO(dev)->gen < 6) || IS_VALLEYVIEW(dev)) {
+	if ((INTEL_INFO(dev)->gen < 6) || IS_VALLEYVIEW(dev) ||
+	    IS_BROXTON(dev)) {
 		seq_puts(m, "unsupported on this chipset\n");
 		return 0;
 	}
-- 
1.9.2

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Re: [PATCH 4/6] drm/i915: Corrected the platform checks in i915_ring_freq_table function

[Daniel Vetter]

On Fri, Jun 19, 2015 at 11:07:29PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> Corrected the platform checks in i915_ring_freq_table debugfs function
> so as to allow the read of ring frequency table for BDW and disallow for VLV
> 
> v2: Simplified the checks to avoid the double negation (Daniel)
> 
> Issue: VIZ-5144
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index c49fe2a..438c10b 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1746,7 +1746,8 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
>  	int ret = 0;
>  	int gpu_freq, ia_freq;
>  
> -	if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
> +	if (!(IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
> +	      IS_BROADWELL(dev))) {

Still complicated and also duplicated. What about a HAS_CORE_RING_FREQ()
feature macro, maybe even as a bitmask somewhere? We have them for rps
too, so lots of precendence.
-Daniel

>  		seq_puts(m, "unsupported on this chipset\n");
>  		return 0;
>  	}
> -- 
> 1.9.2
> 
> _______________________________________________
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 6/6] drm/i915: Added BXT check in i915_ring_freq_table function

[Daniel Vetter]

On Fri, Jun 19, 2015 at 11:07:31PM +0530, akash.goel@intel.com wrote:
> From: Akash Goel <akash.goel@intel.com>
> 
> Updated the i915_ring_freq_table debugfs function to add
> the broxton check, so as to disallow the read of ring frequency
> table for it.
> 
> Issue: VIZ-5144
> Signed-off-by: Akash Goel <akash.goel@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 2666d8a..daf6bdc 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1747,7 +1747,8 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
>  	int gpu_freq, ia_freq;
>  	unsigned int max_gpu_freq, min_gpu_freq;
>  
> -	if ((INTEL_INFO(dev)->gen < 6) || IS_VALLEYVIEW(dev)) {
> +	if ((INTEL_INFO(dev)->gen < 6) || IS_VALLEYVIEW(dev) ||
> +	    IS_BROXTON(dev)) {

Yup, imo add a HAS_FOO feature macro here over all the place in one patch,
then do 1 patch to fix things up to exclude bxt everywhere. Lots of
different patches with lots of different checks makes reviewing this
properly unecesarily hard imo.
-Daniel

>  		seq_puts(m, "unsupported on this chipset\n");
>  		return 0;
>  	}
> -- 
> 1.9.2
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 4/6] drm/i915: Corrected the platform checks in i915_ring_freq_table function

[Akash Goel]

On Mon, 2015-06-22 at 17:43 +0200, Daniel Vetter wrote:
> On Fri, Jun 19, 2015 at 11:07:29PM +0530, akash.goel@intel.com wrote:
> > From: Akash Goel <akash.goel@intel.com>
> > 
> > Corrected the platform checks in i915_ring_freq_table debugfs function
> > so as to allow the read of ring frequency table for BDW and disallow for VLV
> > 
> > v2: Simplified the checks to avoid the double negation (Daniel)
> > 
> > Issue: VIZ-5144
> > Signed-off-by: Akash Goel <akash.goel@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index c49fe2a..438c10b 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -1746,7 +1746,8 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
> >  	int ret = 0;
> >  	int gpu_freq, ia_freq;
> >  
> > -	if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
> > +	if (!(IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
> > +	      IS_BROADWELL(dev))) {
> 
> Still complicated and also duplicated. What about a HAS_CORE_RING_FREQ()
> feature macro, maybe even as a bitmask somewhere? We have them for rps
> too, so lots of precendence.
> -Daniel

Sincere apologies for this blooper. Messed up on my side & sent the old
patch only (with the double negation)..
Will introduce the new macro, as you suggested.

> 
> >  		seq_puts(m, "unsupported on this chipset\n");
> >  		return 0;
> >  	}
> > -- 
> > 1.9.2
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 


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Re: [PATCH 6/6] drm/i915: Added BXT check in i915_ring_freq_table function

[shuang.he]

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6578
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
ILK                                  303/303              303/303
SNB                                  312/312              312/312
IVB                                  343/343              343/343
BYT                                  284/284              284/284
HSW                                  380/380              380/380
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
Note: You need to pay more attention to line start with '*'
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