* [PATCH v10 01/13] x86: add socket_cpumask
2015-06-26 8:43 [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs Chao Peng
@ 2015-06-26 8:43 ` Chao Peng
2015-07-07 22:32 ` Boris Ostrovsky
2015-06-26 8:43 ` [PATCH v10 02/13] x86: detect and initialize Intel CAT feature Chao Peng
` (12 subsequent siblings)
13 siblings, 1 reply; 23+ messages in thread
From: Chao Peng @ 2015-06-26 8:43 UTC (permalink / raw)
To: xen-devel
Cc: keir, Ian.Campbell, stefano.stabellini, andrew.cooper3,
dario.faggioli, Ian.Jackson, will.auld, JBeulich, wei.liu2,
dgdegra
Maintain socket_cpumask which contains all the HT and core siblings
in the same socket.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
Changes in v9:
* Add comments for set_nr_sockets.
* Move set_nr_sockets() invocation from __start_xen() to smp_prepare_cpus().
Changes in v8:
* Remove total_cpus and retrofit the algorithm for calculating nr_sockets.
* Change per-socket cpumask allocation as on demand.
* socket_to_cpumask => socket_cpumask.
Changes in v7:
* Introduce total_cpus to calculate nr_sockets.
* Minor code sequence improvement in set_cpu_sibling_map.
* Improve comments for nr_sockets.
---
xen/arch/x86/mpparse.c | 17 +++++++++++++++++
xen/arch/x86/smpboot.c | 26 +++++++++++++++++++++++++-
xen/include/asm-x86/smp.h | 11 +++++++++++
3 files changed, 53 insertions(+), 1 deletion(-)
diff --git a/xen/arch/x86/mpparse.c b/xen/arch/x86/mpparse.c
index 003c56e..8609f4a 100644
--- a/xen/arch/x86/mpparse.c
+++ b/xen/arch/x86/mpparse.c
@@ -87,6 +87,23 @@ void __init set_nr_cpu_ids(unsigned int max_cpus)
#endif
}
+void __init set_nr_sockets(void)
+{
+ /*
+ * Count the actual cpus in the socket 0 and use it to calculate nr_sockets
+ * so that the latter will be always >= the actual socket number in the
+ * system even when APIC IDs from MP table are too sparse.
+ */
+ unsigned int cpus = bitmap_weight(phys_cpu_present_map.mask,
+ boot_cpu_data.x86_max_cores *
+ boot_cpu_data.x86_num_siblings);
+
+ if ( cpus == 0 )
+ cpus = 1;
+
+ nr_sockets = DIV_ROUND_UP(num_processors + disabled_cpus, cpus);
+}
+
/*
* Intel MP BIOS table parsing routines:
*/
diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c
index 2289284..e75bbd3 100644
--- a/xen/arch/x86/smpboot.c
+++ b/xen/arch/x86/smpboot.c
@@ -60,6 +60,9 @@ DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_mask);
cpumask_t cpu_online_map __read_mostly;
EXPORT_SYMBOL(cpu_online_map);
+unsigned int __read_mostly nr_sockets;
+cpumask_var_t *__read_mostly socket_cpumask;
+
struct cpuinfo_x86 cpu_data[NR_CPUS];
u32 x86_cpu_to_apicid[NR_CPUS] __read_mostly =
@@ -245,6 +248,8 @@ static void set_cpu_sibling_map(int cpu)
cpumask_set_cpu(cpu, &cpu_sibling_setup_map);
+ cpumask_set_cpu(cpu, socket_cpumask[cpu_to_socket(cpu)]);
+
if ( c[cpu].x86_num_siblings > 1 )
{
for_each_cpu ( i, &cpu_sibling_setup_map )
@@ -649,7 +654,13 @@ void cpu_exit_clear(unsigned int cpu)
static void cpu_smpboot_free(unsigned int cpu)
{
- unsigned int order;
+ unsigned int order, socket = cpu_to_socket(cpu);
+
+ if ( cpumask_empty(socket_cpumask[socket]) )
+ {
+ free_cpumask_var(socket_cpumask[socket]);
+ socket_cpumask[socket] = NULL;
+ }
free_cpumask_var(per_cpu(cpu_sibling_mask, cpu));
free_cpumask_var(per_cpu(cpu_core_mask, cpu));
@@ -694,6 +705,7 @@ static int cpu_smpboot_alloc(unsigned int cpu)
nodeid_t node = cpu_to_node(cpu);
struct desc_struct *gdt;
unsigned long stub_page;
+ unsigned int socket = cpu_to_socket(cpu);
if ( node != NUMA_NO_NODE )
memflags = MEMF_node(node);
@@ -736,6 +748,10 @@ static int cpu_smpboot_alloc(unsigned int cpu)
goto oom;
per_cpu(stubs.addr, cpu) = stub_page + STUB_BUF_CPU_OFFS(cpu);
+ if ( !socket_cpumask[socket] &&
+ !zalloc_cpumask_var(socket_cpumask + socket) )
+ goto oom;
+
if ( zalloc_cpumask_var(&per_cpu(cpu_sibling_mask, cpu)) &&
zalloc_cpumask_var(&per_cpu(cpu_core_mask, cpu)) )
return 0;
@@ -786,6 +802,12 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
stack_base[0] = stack_start;
+ set_nr_sockets();
+
+ socket_cpumask = xzalloc_array(cpumask_var_t, nr_sockets);
+ if ( !socket_cpumask || !zalloc_cpumask_var(socket_cpumask) )
+ panic("No memory for socket CPU siblings map");
+
if ( !zalloc_cpumask_var(&per_cpu(cpu_sibling_mask, 0)) ||
!zalloc_cpumask_var(&per_cpu(cpu_core_mask, 0)) )
panic("No memory for boot CPU sibling/core maps");
@@ -851,6 +873,8 @@ remove_siblinginfo(int cpu)
int sibling;
struct cpuinfo_x86 *c = cpu_data;
+ cpumask_clear_cpu(cpu, socket_cpumask[cpu_to_socket(cpu)]);
+
for_each_cpu ( sibling, per_cpu(cpu_core_mask, cpu) )
{
cpumask_clear_cpu(cpu, per_cpu(cpu_core_mask, sibling));
diff --git a/xen/include/asm-x86/smp.h b/xen/include/asm-x86/smp.h
index 67518cf..e594062 100644
--- a/xen/include/asm-x86/smp.h
+++ b/xen/include/asm-x86/smp.h
@@ -58,6 +58,17 @@ int hard_smp_processor_id(void);
void __stop_this_cpu(void);
+/*
+ * The value may be greater than the actual socket number in the system and
+ * is required not to change from the initial startup.
+ */
+extern unsigned int nr_sockets;
+
+void set_nr_sockets(void);
+
+/* Representing HT and core siblings in each socket. */
+extern cpumask_var_t *socket_cpumask;
+
#endif /* !__ASSEMBLY__ */
#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v10 01/13] x86: add socket_cpumask
2015-06-26 8:43 ` [PATCH v10 01/13] x86: add socket_cpumask Chao Peng
@ 2015-07-07 22:32 ` Boris Ostrovsky
2015-07-08 2:43 ` Chao Peng
0 siblings, 1 reply; 23+ messages in thread
From: Boris Ostrovsky @ 2015-07-07 22:32 UTC (permalink / raw)
To: Chao Peng, xen-devel
Cc: keir, Ian.Campbell, stefano.stabellini, andrew.cooper3,
dario.faggioli, Ian.Jackson, will.auld, JBeulich, wei.liu2,
dgdegra
On 06/26/2015 04:43 AM, Chao Peng wrote:
> Maintain socket_cpumask which contains all the HT and core siblings
> in the same socket.
>
> Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
> Acked-by: Jan Beulich <jbeulich@suse.com>
> ---
> Changes in v9:
> * Add comments for set_nr_sockets.
> * Move set_nr_sockets() invocation from __start_xen() to smp_prepare_cpus().
> Changes in v8:
> * Remove total_cpus and retrofit the algorithm for calculating nr_sockets.
> * Change per-socket cpumask allocation as on demand.
> * socket_to_cpumask => socket_cpumask.
> Changes in v7:
> * Introduce total_cpus to calculate nr_sockets.
> * Minor code sequence improvement in set_cpu_sibling_map.
> * Improve comments for nr_sockets.
> ---
> xen/arch/x86/mpparse.c | 17 +++++++++++++++++
> xen/arch/x86/smpboot.c | 26 +++++++++++++++++++++++++-
> xen/include/asm-x86/smp.h | 11 +++++++++++
> 3 files changed, 53 insertions(+), 1 deletion(-)
>
> diff --git a/xen/arch/x86/mpparse.c b/xen/arch/x86/mpparse.c
> index 003c56e..8609f4a 100644
> --- a/xen/arch/x86/mpparse.c
> +++ b/xen/arch/x86/mpparse.c
> @@ -87,6 +87,23 @@ void __init set_nr_cpu_ids(unsigned int max_cpus)
> #endif
> }
>
> +void __init set_nr_sockets(void)
> +{
> + /*
> + * Count the actual cpus in the socket 0 and use it to calculate nr_sockets
> + * so that the latter will be always >= the actual socket number in the
> + * system even when APIC IDs from MP table are too sparse.
> + */
> + unsigned int cpus = bitmap_weight(phys_cpu_present_map.mask,
> + boot_cpu_data.x86_max_cores *
> + boot_cpu_data.x86_num_siblings);
> +
> + if ( cpus == 0 )
> + cpus = 1;
> +
> + nr_sockets = DIV_ROUND_UP(num_processors + disabled_cpus, cpus);
> +}
> +
> /*
> * Intel MP BIOS table parsing routines:
> */
> diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c
> index 2289284..e75bbd3 100644
> --- a/xen/arch/x86/smpboot.c
> +++ b/xen/arch/x86/smpboot.c
> @@ -60,6 +60,9 @@ DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_mask);
> cpumask_t cpu_online_map __read_mostly;
> EXPORT_SYMBOL(cpu_online_map);
>
> +unsigned int __read_mostly nr_sockets;
> +cpumask_var_t *__read_mostly socket_cpumask;
> +
> struct cpuinfo_x86 cpu_data[NR_CPUS];
>
> u32 x86_cpu_to_apicid[NR_CPUS] __read_mostly =
> @@ -245,6 +248,8 @@ static void set_cpu_sibling_map(int cpu)
>
> cpumask_set_cpu(cpu, &cpu_sibling_setup_map);
>
> + cpumask_set_cpu(cpu, socket_cpumask[cpu_to_socket(cpu)]);
This patch crashes Xen on my 32-cpu Intel box here for cpu 16, which is
the first CPU on the second socket (i.e. on socket 1).
The reason appears to be that cpu_to_socket(16) is (correctly) 1 here,
but ...
> +
> if ( c[cpu].x86_num_siblings > 1 )
> {
> for_each_cpu ( i, &cpu_sibling_setup_map )
> @@ -649,7 +654,13 @@ void cpu_exit_clear(unsigned int cpu)
>
> static void cpu_smpboot_free(unsigned int cpu)
> {
> - unsigned int order;
> + unsigned int order, socket = cpu_to_socket(cpu);
> +
> + if ( cpumask_empty(socket_cpumask[socket]) )
> + {
> + free_cpumask_var(socket_cpumask[socket]);
> + socket_cpumask[socket] = NULL;
> + }
>
> free_cpumask_var(per_cpu(cpu_sibling_mask, cpu));
> free_cpumask_var(per_cpu(cpu_core_mask, cpu));
> @@ -694,6 +705,7 @@ static int cpu_smpboot_alloc(unsigned int cpu)
> nodeid_t node = cpu_to_node(cpu);
> struct desc_struct *gdt;
> unsigned long stub_page;
> + unsigned int socket = cpu_to_socket(cpu);
... is zero here, meaning that socket_cpumask[1] is NULL. I suspect that
phys_proc_id is probably not set at this point but is by the time we get
to set_cpu_sibling_map(). I haven't looked any further yet. I might do
this tomorrow unless Chao does it before me.
Here is what I have
[root@ovs104 ~]# numactl --hardware
available: 2 nodes (0-1)
node 0 cpus: 0 1 2 3 4 5 6 7 16 17 18 19 20 21 22 23
node 0 size: 15748 MB
node 0 free: 15466 MB
node 1 cpus: 8 9 10 11 12 13 14 15 24 25 26 27 28 29 30 31
node 1 size: 16118 MB
node 1 free: 15896 MB
node distances:
node 0 1
0: 10 21
1: 21 10
[root@ovs104 ~]# grep processor /proc/cpuinfo |wc -l
32
[root@ovs104 ~]# head -20 /proc/cpuinfo
processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 45
model name : Genuine Intel(R) CPU @ 2.30GHz
stepping : 2
microcode : 0x8000020c
cpu MHz : 1231.937
cache size : 20480 KB
physical id : 0
siblings : 16
core id : 0
cpu cores : 8
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 13
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca
cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall
nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl
xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor
ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm pcid dca sse4_1 sse4_2
x2apic popcnt tsc_deadline_timer aes xsave avx lahf_lm ida arat epb pln
pts dtherm tpr_shadow vnmi flexpriority ept vpid xsaveopt
-boris
>
> if ( node != NUMA_NO_NODE )
> memflags = MEMF_node(node);
> @@ -736,6 +748,10 @@ static int cpu_smpboot_alloc(unsigned int cpu)
> goto oom;
> per_cpu(stubs.addr, cpu) = stub_page + STUB_BUF_CPU_OFFS(cpu);
>
> + if ( !socket_cpumask[socket] &&
> + !zalloc_cpumask_var(socket_cpumask + socket) )
> + goto oom;
> +
> if ( zalloc_cpumask_var(&per_cpu(cpu_sibling_mask, cpu)) &&
> zalloc_cpumask_var(&per_cpu(cpu_core_mask, cpu)) )
> return 0;
> @@ -786,6 +802,12 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
>
> stack_base[0] = stack_start;
>
> + set_nr_sockets();
> +
> + socket_cpumask = xzalloc_array(cpumask_var_t, nr_sockets);
> + if ( !socket_cpumask || !zalloc_cpumask_var(socket_cpumask) )
> + panic("No memory for socket CPU siblings map");
> +
> if ( !zalloc_cpumask_var(&per_cpu(cpu_sibling_mask, 0)) ||
> !zalloc_cpumask_var(&per_cpu(cpu_core_mask, 0)) )
> panic("No memory for boot CPU sibling/core maps");
> @@ -851,6 +873,8 @@ remove_siblinginfo(int cpu)
> int sibling;
> struct cpuinfo_x86 *c = cpu_data;
>
> + cpumask_clear_cpu(cpu, socket_cpumask[cpu_to_socket(cpu)]);
> +
> for_each_cpu ( sibling, per_cpu(cpu_core_mask, cpu) )
> {
> cpumask_clear_cpu(cpu, per_cpu(cpu_core_mask, sibling));
> diff --git a/xen/include/asm-x86/smp.h b/xen/include/asm-x86/smp.h
> index 67518cf..e594062 100644
> --- a/xen/include/asm-x86/smp.h
> +++ b/xen/include/asm-x86/smp.h
> @@ -58,6 +58,17 @@ int hard_smp_processor_id(void);
>
> void __stop_this_cpu(void);
>
> +/*
> + * The value may be greater than the actual socket number in the system and
> + * is required not to change from the initial startup.
> + */
> +extern unsigned int nr_sockets;
> +
> +void set_nr_sockets(void);
> +
> +/* Representing HT and core siblings in each socket. */
> +extern cpumask_var_t *socket_cpumask;
> +
> #endif /* !__ASSEMBLY__ */
>
> #endif
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v10 01/13] x86: add socket_cpumask
2015-07-07 22:32 ` Boris Ostrovsky
@ 2015-07-08 2:43 ` Chao Peng
2015-07-08 7:42 ` Jan Beulich
0 siblings, 1 reply; 23+ messages in thread
From: Chao Peng @ 2015-07-08 2:43 UTC (permalink / raw)
To: Boris Ostrovsky
Cc: keir, Ian.Campbell, stefano.stabellini, andrew.cooper3,
dario.faggioli, Ian.Jackson, xen-devel, will.auld, JBeulich,
wei.liu2, dgdegra
On Tue, Jul 07, 2015 at 06:32:55PM -0400, Boris Ostrovsky wrote:
> On 06/26/2015 04:43 AM, Chao Peng wrote:
> >Maintain socket_cpumask which contains all the HT and core siblings
> >in the same socket.
> >
> >Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
> >Acked-by: Jan Beulich <jbeulich@suse.com>
> >---
> >Changes in v9:
> >* Add comments for set_nr_sockets.
> >* Move set_nr_sockets() invocation from __start_xen() to smp_prepare_cpus().
> >Changes in v8:
> >* Remove total_cpus and retrofit the algorithm for calculating nr_sockets.
> >* Change per-socket cpumask allocation as on demand.
> >* socket_to_cpumask => socket_cpumask.
> >Changes in v7:
> >* Introduce total_cpus to calculate nr_sockets.
> >* Minor code sequence improvement in set_cpu_sibling_map.
> >* Improve comments for nr_sockets.
> >---
> > xen/arch/x86/mpparse.c | 17 +++++++++++++++++
> > xen/arch/x86/smpboot.c | 26 +++++++++++++++++++++++++-
> > xen/include/asm-x86/smp.h | 11 +++++++++++
> > 3 files changed, 53 insertions(+), 1 deletion(-)
> >
> >diff --git a/xen/arch/x86/mpparse.c b/xen/arch/x86/mpparse.c
> >index 003c56e..8609f4a 100644
> >--- a/xen/arch/x86/mpparse.c
> >+++ b/xen/arch/x86/mpparse.c
> >@@ -87,6 +87,23 @@ void __init set_nr_cpu_ids(unsigned int max_cpus)
> > #endif
> > }
> >+void __init set_nr_sockets(void)
> >+{
> >+ /*
> >+ * Count the actual cpus in the socket 0 and use it to calculate nr_sockets
> >+ * so that the latter will be always >= the actual socket number in the
> >+ * system even when APIC IDs from MP table are too sparse.
> >+ */
> >+ unsigned int cpus = bitmap_weight(phys_cpu_present_map.mask,
> >+ boot_cpu_data.x86_max_cores *
> >+ boot_cpu_data.x86_num_siblings);
> >+
> >+ if ( cpus == 0 )
> >+ cpus = 1;
> >+
> >+ nr_sockets = DIV_ROUND_UP(num_processors + disabled_cpus, cpus);
> >+}
> >+
> > /*
> > * Intel MP BIOS table parsing routines:
> > */
> >diff --git a/xen/arch/x86/smpboot.c b/xen/arch/x86/smpboot.c
> >index 2289284..e75bbd3 100644
> >--- a/xen/arch/x86/smpboot.c
> >+++ b/xen/arch/x86/smpboot.c
> >@@ -60,6 +60,9 @@ DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_mask);
> > cpumask_t cpu_online_map __read_mostly;
> > EXPORT_SYMBOL(cpu_online_map);
> >+unsigned int __read_mostly nr_sockets;
> >+cpumask_var_t *__read_mostly socket_cpumask;
> >+
> > struct cpuinfo_x86 cpu_data[NR_CPUS];
> > u32 x86_cpu_to_apicid[NR_CPUS] __read_mostly =
> >@@ -245,6 +248,8 @@ static void set_cpu_sibling_map(int cpu)
> > cpumask_set_cpu(cpu, &cpu_sibling_setup_map);
> >+ cpumask_set_cpu(cpu, socket_cpumask[cpu_to_socket(cpu)]);
>
> This patch crashes Xen on my 32-cpu Intel box here for cpu 16, which is the
> first CPU on the second socket (i.e. on socket 1).
>
> The reason appears to be that cpu_to_socket(16) is (correctly) 1 here, but
> ...
>
> >+
> > if ( c[cpu].x86_num_siblings > 1 )
> > {
> > for_each_cpu ( i, &cpu_sibling_setup_map )
> >@@ -649,7 +654,13 @@ void cpu_exit_clear(unsigned int cpu)
> > static void cpu_smpboot_free(unsigned int cpu)
> > {
> >- unsigned int order;
> >+ unsigned int order, socket = cpu_to_socket(cpu);
> >+
> >+ if ( cpumask_empty(socket_cpumask[socket]) )
> >+ {
> >+ free_cpumask_var(socket_cpumask[socket]);
> >+ socket_cpumask[socket] = NULL;
> >+ }
> > free_cpumask_var(per_cpu(cpu_sibling_mask, cpu));
> > free_cpumask_var(per_cpu(cpu_core_mask, cpu));
> >@@ -694,6 +705,7 @@ static int cpu_smpboot_alloc(unsigned int cpu)
> > nodeid_t node = cpu_to_node(cpu);
> > struct desc_struct *gdt;
> > unsigned long stub_page;
> >+ unsigned int socket = cpu_to_socket(cpu);
>
> ... is zero here, meaning that socket_cpumask[1] is NULL. I suspect that
> phys_proc_id is probably not set at this point but is by the time we get to
> set_cpu_sibling_map(). I haven't looked any further yet. I might do this
> tomorrow unless Chao does it before me.
Thanks for testing.
I think I have found the reason. For AP, phys_proc_id is set in:
start_secondary()=>smp_callin()=>smp_store_cpu_info()=>identify_cpu()
which is behind cpu_smpboot_alloc() called from CPU_PREPARE.
One way would move 'zalloc_cpumask_var(socket_cpumask + socket)' to
set_cpu_sibling_map() to fix it if Jan agrees that, otherwise other
solution needs to be found.
Chao
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v10 01/13] x86: add socket_cpumask
2015-07-08 2:43 ` Chao Peng
@ 2015-07-08 7:42 ` Jan Beulich
0 siblings, 0 replies; 23+ messages in thread
From: Jan Beulich @ 2015-07-08 7:42 UTC (permalink / raw)
To: Chao Peng
Cc: wei.liu2, Ian.Campbell, stefano.stabellini, andrew.cooper3,
dario.faggioli, Ian.Jackson, xen-devel, will.auld, keir,
Boris Ostrovsky, dgdegra
>>> On 08.07.15 at 04:43, <chao.p.peng@linux.intel.com> wrote:
> On Tue, Jul 07, 2015 at 06:32:55PM -0400, Boris Ostrovsky wrote:
>> >@@ -245,6 +248,8 @@ static void set_cpu_sibling_map(int cpu)
>> > cpumask_set_cpu(cpu, &cpu_sibling_setup_map);
>> >+ cpumask_set_cpu(cpu, socket_cpumask[cpu_to_socket(cpu)]);
>>
>> This patch crashes Xen on my 32-cpu Intel box here for cpu 16, which is the
>> first CPU on the second socket (i.e. on socket 1).
>>
>> The reason appears to be that cpu_to_socket(16) is (correctly) 1 here, but
>> ...
>>
>> >+
>> > if ( c[cpu].x86_num_siblings > 1 )
>> > {
>> > for_each_cpu ( i, &cpu_sibling_setup_map )
>> >@@ -649,7 +654,13 @@ void cpu_exit_clear(unsigned int cpu)
>> > static void cpu_smpboot_free(unsigned int cpu)
>> > {
>> >- unsigned int order;
>> >+ unsigned int order, socket = cpu_to_socket(cpu);
>> >+
>> >+ if ( cpumask_empty(socket_cpumask[socket]) )
>> >+ {
>> >+ free_cpumask_var(socket_cpumask[socket]);
>> >+ socket_cpumask[socket] = NULL;
>> >+ }
>> > free_cpumask_var(per_cpu(cpu_sibling_mask, cpu));
>> > free_cpumask_var(per_cpu(cpu_core_mask, cpu));
>> >@@ -694,6 +705,7 @@ static int cpu_smpboot_alloc(unsigned int cpu)
>> > nodeid_t node = cpu_to_node(cpu);
>> > struct desc_struct *gdt;
>> > unsigned long stub_page;
>> >+ unsigned int socket = cpu_to_socket(cpu);
>>
>> ... is zero here, meaning that socket_cpumask[1] is NULL. I suspect that
>> phys_proc_id is probably not set at this point but is by the time we get to
>> set_cpu_sibling_map(). I haven't looked any further yet. I might do this
>> tomorrow unless Chao does it before me.
>
> Thanks for testing.
Boris' report first of all raises the question: Did you test this at all
on a multi-socket system? Considering you not having tested the
CPU removal case either, I'm starting to wonder how much testing
this series has seen overall...
> I think I have found the reason. For AP, phys_proc_id is set in:
> start_secondary()=>smp_callin()=>smp_store_cpu_info()=>identify_cpu()
> which is behind cpu_smpboot_alloc() called from CPU_PREPARE.
>
> One way would move 'zalloc_cpumask_var(socket_cpumask + socket)' to
> set_cpu_sibling_map() to fix it if Jan agrees that, otherwise other
> solution needs to be found.
Looks sensible at a first glance, but in order to be able to do
proper error handling the allocation needs to remain in
cpu_smpboot_alloc(). I.e. you'd add a static variable, pre-
allocate a cpumask into it if it's currently NULL, and consume the
allocation in set_cpu_sibling_map() (or maybe even better in
smp_store_cpu_info() right after the identify_cpu() call) if
socket_cpumask[socket] is NULL.
And then you test this on an affected system, and submit
asap, so we can preferably avoid reverting the whole series.
Jan
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v10 02/13] x86: detect and initialize Intel CAT feature
2015-06-26 8:43 [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs Chao Peng
2015-06-26 8:43 ` [PATCH v10 01/13] x86: add socket_cpumask Chao Peng
@ 2015-06-26 8:43 ` Chao Peng
2015-07-07 10:25 ` Jan Beulich
2015-06-26 8:43 ` [PATCH v10 03/13] x86: maintain COS to CBM mapping for each socket Chao Peng
` (11 subsequent siblings)
13 siblings, 1 reply; 23+ messages in thread
From: Chao Peng @ 2015-06-26 8:43 UTC (permalink / raw)
To: xen-devel
Cc: keir, Ian.Campbell, stefano.stabellini, andrew.cooper3,
dario.faggioli, Ian.Jackson, will.auld, JBeulich, wei.liu2,
dgdegra
Detect Intel Cache Allocation Technology(CAT) feature and store the
cpuid information for later use. Currently only L3 cache allocation is
supported. The L3 CAT features may vary among sockets so per-socket
feature information is stored. The initialization can happen either at
boot time or when CPU(s) is hot plugged after booting.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
Changes in v0:
* Add comment for cpu notification priority.
Changes in v9:
* Add __read_mostly for opt_cos_max.
* Add check for cpuid_level.
* Add priority for cpu notifier.
Changes in v8:
* Remove cat_socket_init_bitmap and rename cat_socket_enable_bitmap.
* Ensure opt_cos_max is not too small.
* Use CPU_DEAD instead of CPU_DYING.
* indentation fix.
Changes in v7:
* Clear the init/enable flag when a socket going offline.
* Reorder the statements in init_psr_cat.
Changes in v6:
* Introduce cat_socket_init(_enable)_bitmap.
Changes in v5:
* Add cos_max boot option.
Changes in v4:
* check X86_FEATURE_CAT available before doing initialization.
Changes in v3:
* Remove num_sockets boot option instead calculate it at boot time.
* Name hardcoded CAT cpuid leaf as PSR_CPUID_LEVEL_CAT.
Changes in v2:
* socket_num => num_sockets and fix several documentaion issues.
* refactor boot line parameters parsing into standlone patch.
* set opt_num_sockets = NR_CPUS when opt_num_sockets > NR_CPUS.
* replace CPU_ONLINE with CPU_STARTING and integrate that into scheduling
improvement patch.
* reimplement get_max_socket() with cpu_to_socket();
* cbm is still uint64 as there is a path forward for supporting long masks.
---
docs/misc/xen-command-line.markdown | 15 +++++-
xen/arch/x86/psr.c | 105 ++++++++++++++++++++++++++++++++++--
xen/include/asm-x86/cpufeature.h | 1 +
xen/include/asm-x86/psr.h | 3 ++
4 files changed, 119 insertions(+), 5 deletions(-)
diff --git a/docs/misc/xen-command-line.markdown b/docs/misc/xen-command-line.markdown
index aa684c0..25b9bea 100644
--- a/docs/misc/xen-command-line.markdown
+++ b/docs/misc/xen-command-line.markdown
@@ -1149,9 +1149,9 @@ This option can be specified more than once (up to 8 times at present).
> `= <integer>`
### psr (Intel)
-> `= List of ( cmt:<boolean> | rmid_max:<integer> )`
+> `= List of ( cmt:<boolean> | rmid_max:<integer> | cat:<boolean> | cos_max:<integer> )`
-> Default: `psr=cmt:0,rmid_max:255`
+> Default: `psr=cmt:0,rmid_max:255,cat:0,cos_max:255`
Platform Shared Resource(PSR) Services. Intel Haswell and later server
platforms offer information about the sharing of resources.
@@ -1161,6 +1161,12 @@ Monitoring ID(RMID) is used to bind the domain to corresponding shared
resource. RMID is a hardware-provided layer of abstraction between software
and logical processors.
+To use the PSR cache allocation service for a certain domain, a capacity
+bitmasks(CBM) is used to bind the domain to corresponding shared resource.
+CBM represents cache capacity and indicates the degree of overlap and isolation
+between domains. In hypervisor a Class of Service(COS) ID is allocated for each
+unique CBM.
+
The following resources are available:
* Cache Monitoring Technology (Haswell and later). Information regarding the
@@ -1171,6 +1177,11 @@ The following resources are available:
total/local memory bandwidth. Follow the same options with Cache Monitoring
Technology.
+* Cache Alllocation Technology (Broadwell and later). Information regarding
+ the cache allocation.
+ * `cat` instructs Xen to enable/disable Cache Allocation Technology.
+ * `cos_max` indicates the max value for COS ID.
+
### reboot
> `= t[riple] | k[bd] | a[cpi] | p[ci] | P[ower] | e[fi] | n[o] [, [w]arm | [c]old]`
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 2490d22..c1bf7d7 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -19,14 +19,25 @@
#include <asm/psr.h>
#define PSR_CMT (1<<0)
+#define PSR_CAT (1<<1)
+
+struct psr_cat_socket_info {
+ unsigned int cbm_len;
+ unsigned int cos_max;
+};
struct psr_assoc {
uint64_t val;
};
struct psr_cmt *__read_mostly psr_cmt;
+
+static unsigned long *__read_mostly cat_socket_enable;
+static struct psr_cat_socket_info *__read_mostly cat_socket_info;
+
static unsigned int __initdata opt_psr;
static unsigned int __initdata opt_rmid_max = 255;
+static unsigned int __read_mostly opt_cos_max = 255;
static uint64_t rmid_mask;
static DEFINE_PER_CPU(struct psr_assoc, psr_assoc);
@@ -63,10 +74,14 @@ static void __init parse_psr_param(char *s)
*val_str++ = '\0';
parse_psr_bool(s, val_str, "cmt", PSR_CMT);
+ parse_psr_bool(s, val_str, "cat", PSR_CAT);
if ( val_str && !strcmp(s, "rmid_max") )
opt_rmid_max = simple_strtoul(val_str, NULL, 0);
+ if ( val_str && !strcmp(s, "cos_max") )
+ opt_cos_max = simple_strtoul(val_str, NULL, 0);
+
s = ss + 1;
} while ( ss );
}
@@ -194,22 +209,103 @@ void psr_ctxt_switch_to(struct domain *d)
}
}
+static void cat_cpu_init(void)
+{
+ unsigned int eax, ebx, ecx, edx;
+ struct psr_cat_socket_info *info;
+ unsigned int socket;
+ unsigned int cpu = smp_processor_id();
+ const struct cpuinfo_x86 *c = cpu_data + cpu;
+
+ if ( !cpu_has(c, X86_FEATURE_CAT) || c->cpuid_level < PSR_CPUID_LEVEL_CAT )
+ return;
+
+ socket = cpu_to_socket(cpu);
+ if ( test_bit(socket, cat_socket_enable) )
+ return;
+
+ cpuid_count(PSR_CPUID_LEVEL_CAT, 0, &eax, &ebx, &ecx, &edx);
+ if ( ebx & PSR_RESOURCE_TYPE_L3 )
+ {
+ cpuid_count(PSR_CPUID_LEVEL_CAT, 1, &eax, &ebx, &ecx, &edx);
+ info = cat_socket_info + socket;
+ info->cbm_len = (eax & 0x1f) + 1;
+ info->cos_max = min(opt_cos_max, edx & 0xffff);
+
+ set_bit(socket, cat_socket_enable);
+ printk(XENLOG_INFO "CAT: enabled on socket %u, cos_max:%u, cbm_len:%u\n",
+ socket, info->cos_max, info->cbm_len);
+ }
+}
+
+static void cat_cpu_fini(unsigned int cpu)
+{
+ unsigned int socket = cpu_to_socket(cpu);
+
+ if ( !socket_cpumask[socket] || cpumask_empty(socket_cpumask[socket]) )
+ clear_bit(socket, cat_socket_enable);
+}
+
+static void __init init_psr_cat(void)
+{
+ if ( opt_cos_max < 1 )
+ {
+ printk(XENLOG_INFO "CAT: disabled, cos_max is too small\n");
+ return;
+ }
+
+ cat_socket_enable = xzalloc_array(unsigned long, BITS_TO_LONGS(nr_sockets));
+ cat_socket_info = xzalloc_array(struct psr_cat_socket_info, nr_sockets);
+
+ if ( !cat_socket_enable || !cat_socket_info )
+ {
+ xfree(cat_socket_enable);
+ cat_socket_enable = NULL;
+ xfree(cat_socket_info);
+ cat_socket_info = NULL;
+ }
+}
+
static void psr_cpu_init(void)
{
+ if ( cat_socket_info )
+ cat_cpu_init();
+
psr_assoc_init();
}
+static void psr_cpu_fini(unsigned int cpu)
+{
+ if ( cat_socket_info )
+ cat_cpu_fini(cpu);
+}
+
static int cpu_callback(
struct notifier_block *nfb, unsigned long action, void *hcpu)
{
- if ( action == CPU_STARTING )
+ unsigned int cpu = (unsigned long)hcpu;
+
+ switch ( action )
+ {
+ case CPU_STARTING:
psr_cpu_init();
+ break;
+ case CPU_DEAD:
+ psr_cpu_fini(cpu);
+ break;
+ }
return NOTIFY_DONE;
}
static struct notifier_block cpu_nfb = {
- .notifier_call = cpu_callback
+ .notifier_call = cpu_callback,
+ /*
+ * Ensure socket_cpumask is still valid in CPU_DEAD notification
+ * (E.g. the CPU_DEAD notification should be called ahead of
+ * cpu_smpboot_free).
+ */
+ .priority = 1
};
static int __init psr_presmp_init(void)
@@ -217,8 +313,11 @@ static int __init psr_presmp_init(void)
if ( (opt_psr & PSR_CMT) && opt_rmid_max )
init_psr_cmt(opt_rmid_max);
+ if ( opt_psr & PSR_CAT )
+ init_psr_cat();
+
psr_cpu_init();
- if ( psr_cmt_enabled() )
+ if ( psr_cmt_enabled() || cat_socket_info )
register_cpu_notifier(&cpu_nfb);
return 0;
diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index 7963a3a..8c0f0a6 100644
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -149,6 +149,7 @@
#define X86_FEATURE_CMT (7*32+12) /* Cache Monitoring Technology */
#define X86_FEATURE_NO_FPU_SEL (7*32+13) /* FPU CS/DS stored as zero */
#define X86_FEATURE_MPX (7*32+14) /* Memory Protection Extensions */
+#define X86_FEATURE_CAT (7*32+15) /* Cache Allocation Technology */
#define X86_FEATURE_RDSEED (7*32+18) /* RDSEED instruction */
#define X86_FEATURE_ADX (7*32+19) /* ADCX, ADOX instructions */
#define X86_FEATURE_SMAP (7*32+20) /* Supervisor Mode Access Prevention */
diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
index 12d593b..bdda111 100644
--- a/xen/include/asm-x86/psr.h
+++ b/xen/include/asm-x86/psr.h
@@ -18,6 +18,9 @@
#include <xen/types.h>
+/* CAT cpuid level */
+#define PSR_CPUID_LEVEL_CAT 0x10
+
/* Resource Type Enumeration */
#define PSR_RESOURCE_TYPE_L3 0x2
--
1.9.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v10 02/13] x86: detect and initialize Intel CAT feature
2015-06-26 8:43 ` [PATCH v10 02/13] x86: detect and initialize Intel CAT feature Chao Peng
@ 2015-07-07 10:25 ` Jan Beulich
2015-07-08 2:24 ` Chao Peng
0 siblings, 1 reply; 23+ messages in thread
From: Jan Beulich @ 2015-07-07 10:25 UTC (permalink / raw)
To: Chao Peng
Cc: wei.liu2, Ian.Campbell, stefano.stabellini, andrew.cooper3,
dario.faggioli, Ian.Jackson, xen-devel, will.auld, keir, dgdegra
>>> On 26.06.15 at 10:43, <chao.p.peng@linux.intel.com> wrote:
> Detect Intel Cache Allocation Technology(CAT) feature and store the
> cpuid information for later use. Currently only L3 cache allocation is
> supported. The L3 CAT features may vary among sockets so per-socket
> feature information is stored. The initialization can happen either at
> boot time or when CPU(s) is hot plugged after booting.
>
> Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
> Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
> ---
> Changes in v0:
> * Add comment for cpu notification priority.
I'm afraid you did this just mechanically, while I implied you to also
verify that what you chose is correct:
> static struct notifier_block cpu_nfb = {
> - .notifier_call = cpu_callback
> + .notifier_call = cpu_callback,
> + /*
> + * Ensure socket_cpumask is still valid in CPU_DEAD notification
> + * (E.g. the CPU_DEAD notification should be called ahead of
> + * cpu_smpboot_free).
> + */
> + .priority = 1
CPU_DEAD is a NOTIFY_REVERSE notification, i.e. lowest priority
first. I.e. your comment now contradicts the code afaict. Unless
I'm mistaken with that, I assume you didn't really test this code
path? Since everything else is fine with this patch, I'd be fine
with doing the adjustment while committing, but I need your
confirmation which variant actually works.
Jan
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v10 02/13] x86: detect and initialize Intel CAT feature
2015-07-07 10:25 ` Jan Beulich
@ 2015-07-08 2:24 ` Chao Peng
0 siblings, 0 replies; 23+ messages in thread
From: Chao Peng @ 2015-07-08 2:24 UTC (permalink / raw)
To: Jan Beulich
Cc: wei.liu2, Ian.Campbell, stefano.stabellini, andrew.cooper3,
dario.faggioli, Ian.Jackson, xen-devel, will.auld, keir, dgdegra
On Tue, Jul 07, 2015 at 11:25:46AM +0100, Jan Beulich wrote:
> >>> On 26.06.15 at 10:43, <chao.p.peng@linux.intel.com> wrote:
> > Detect Intel Cache Allocation Technology(CAT) feature and store the
> > cpuid information for later use. Currently only L3 cache allocation is
> > supported. The L3 CAT features may vary among sockets so per-socket
> > feature information is stored. The initialization can happen either at
> > boot time or when CPU(s) is hot plugged after booting.
> >
> > Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
> > Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
> > ---
> > Changes in v0:
> > * Add comment for cpu notification priority.
>
> I'm afraid you did this just mechanically, while I implied you to also
> verify that what you chose is correct:
>
> > static struct notifier_block cpu_nfb = {
> > - .notifier_call = cpu_callback
> > + .notifier_call = cpu_callback,
> > + /*
> > + * Ensure socket_cpumask is still valid in CPU_DEAD notification
> > + * (E.g. the CPU_DEAD notification should be called ahead of
> > + * cpu_smpboot_free).
> > + */
> > + .priority = 1
>
> CPU_DEAD is a NOTIFY_REVERSE notification, i.e. lowest priority
> first. I.e. your comment now contradicts the code afaict. Unless
> I'm mistaken with that, I assume you didn't really test this code
> path? Since everything else is fine with this patch, I'd be fine
> with doing the adjustment while committing, but I need your
> confirmation which variant actually works.
>
Sorry for this. But It's really your change is correct.
Also see your typo fix, looks much better and thanks.
Chao
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v10 03/13] x86: maintain COS to CBM mapping for each socket
2015-06-26 8:43 [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs Chao Peng
2015-06-26 8:43 ` [PATCH v10 01/13] x86: add socket_cpumask Chao Peng
2015-06-26 8:43 ` [PATCH v10 02/13] x86: detect and initialize Intel CAT feature Chao Peng
@ 2015-06-26 8:43 ` Chao Peng
2015-06-26 8:43 ` [PATCH v10 04/13] x86: add COS information for each domain Chao Peng
` (10 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Chao Peng @ 2015-06-26 8:43 UTC (permalink / raw)
To: xen-devel
Cc: keir, Ian.Campbell, stefano.stabellini, andrew.cooper3,
dario.faggioli, Ian.Jackson, will.auld, JBeulich, wei.liu2,
dgdegra
For each socket, a COS to CBM mapping structure is maintained for each
COS. The mapping is indexed by COS and the value is the corresponding
CBM. Different VMs may use the same CBM, a reference count is used to
indicate if the CBM is available.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
---
Changes in v10:
* Check socket < nr_sockets in cat_cpu_prepare().
Changes in v9:
* Allocate cos_to_cbm with opt_cos_max instead the actual cos_max from cpuid.
* Move CAT initialization code back to CPU_STARTING.
* Correct initialization logic for boot cpu.
Changes in v8:
* Move the memory allocation and CAT initialization code to CPU_UP_PREPARE.
* Add memory freeing code in CPU_DEAD path.
Changes in v5:
* rename cos_cbm_map to cos_to_cbm.
---
xen/arch/x86/psr.c | 68 ++++++++++++++++++++++++++++++++++++++++++++++++------
1 file changed, 61 insertions(+), 7 deletions(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index c1bf7d7..623aca1 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -21,9 +21,15 @@
#define PSR_CMT (1<<0)
#define PSR_CAT (1<<1)
+struct psr_cat_cbm {
+ uint64_t cbm;
+ unsigned int ref;
+};
+
struct psr_cat_socket_info {
unsigned int cbm_len;
unsigned int cos_max;
+ struct psr_cat_cbm *cos_to_cbm;
};
struct psr_assoc {
@@ -209,6 +215,26 @@ void psr_ctxt_switch_to(struct domain *d)
}
}
+static int cat_cpu_prepare(unsigned int cpu)
+{
+ struct psr_cat_socket_info *info;
+ unsigned int socket;
+
+ if ( !cat_socket_info )
+ return 0;
+
+ socket = cpu_to_socket(cpu);
+ if ( socket >= nr_sockets )
+ return -ENOSPC;
+
+ info = cat_socket_info + socket;
+ if ( info->cos_to_cbm )
+ return 0;
+
+ info->cos_to_cbm = xzalloc_array(struct psr_cat_cbm, opt_cos_max + 1UL);
+ return info->cos_to_cbm ? 0 : -ENOMEM;
+}
+
static void cat_cpu_init(void)
{
unsigned int eax, ebx, ecx, edx;
@@ -232,6 +258,9 @@ static void cat_cpu_init(void)
info->cbm_len = (eax & 0x1f) + 1;
info->cos_max = min(opt_cos_max, edx & 0xffff);
+ /* cos=0 is reserved as default cbm(all ones). */
+ info->cos_to_cbm[0].cbm = (1ull << info->cbm_len) - 1;
+
set_bit(socket, cat_socket_enable);
printk(XENLOG_INFO "CAT: enabled on socket %u, cos_max:%u, cbm_len:%u\n",
socket, info->cos_max, info->cbm_len);
@@ -243,7 +272,24 @@ static void cat_cpu_fini(unsigned int cpu)
unsigned int socket = cpu_to_socket(cpu);
if ( !socket_cpumask[socket] || cpumask_empty(socket_cpumask[socket]) )
+ {
+ struct psr_cat_socket_info *info = cat_socket_info + socket;
+
+ if ( info->cos_to_cbm )
+ {
+ xfree(info->cos_to_cbm);
+ info->cos_to_cbm = NULL;
+ }
clear_bit(socket, cat_socket_enable);
+ }
+}
+
+static void __init psr_cat_free(void)
+{
+ xfree(cat_socket_enable);
+ cat_socket_enable = NULL;
+ xfree(cat_socket_info);
+ cat_socket_info = NULL;
}
static void __init init_psr_cat(void)
@@ -258,12 +304,12 @@ static void __init init_psr_cat(void)
cat_socket_info = xzalloc_array(struct psr_cat_socket_info, nr_sockets);
if ( !cat_socket_enable || !cat_socket_info )
- {
- xfree(cat_socket_enable);
- cat_socket_enable = NULL;
- xfree(cat_socket_info);
- cat_socket_info = NULL;
- }
+ psr_cat_free();
+}
+
+static int psr_cpu_prepare(unsigned int cpu)
+{
+ return cat_cpu_prepare(cpu);
}
static void psr_cpu_init(void)
@@ -283,19 +329,24 @@ static void psr_cpu_fini(unsigned int cpu)
static int cpu_callback(
struct notifier_block *nfb, unsigned long action, void *hcpu)
{
+ int rc = 0;
unsigned int cpu = (unsigned long)hcpu;
switch ( action )
{
+ case CPU_UP_PREPARE:
+ rc = psr_cpu_prepare(cpu);
+ break;
case CPU_STARTING:
psr_cpu_init();
break;
+ case CPU_UP_CANCELED:
case CPU_DEAD:
psr_cpu_fini(cpu);
break;
}
- return NOTIFY_DONE;
+ return !rc ? NOTIFY_DONE : notifier_from_errno(rc);
}
static struct notifier_block cpu_nfb = {
@@ -316,6 +367,9 @@ static int __init psr_presmp_init(void)
if ( opt_psr & PSR_CAT )
init_psr_cat();
+ if ( psr_cpu_prepare(0) )
+ psr_cat_free();
+
psr_cpu_init();
if ( psr_cmt_enabled() || cat_socket_info )
register_cpu_notifier(&cpu_nfb);
--
1.9.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v10 04/13] x86: add COS information for each domain
2015-06-26 8:43 [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs Chao Peng
` (2 preceding siblings ...)
2015-06-26 8:43 ` [PATCH v10 03/13] x86: maintain COS to CBM mapping for each socket Chao Peng
@ 2015-06-26 8:43 ` Chao Peng
2015-06-26 8:43 ` [PATCH v10 05/13] x86: expose CBM length and COS number information Chao Peng
` (9 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Chao Peng @ 2015-06-26 8:43 UTC (permalink / raw)
To: xen-devel
Cc: keir, Ian.Campbell, stefano.stabellini, andrew.cooper3,
dario.faggioli, Ian.Jackson, will.auld, JBeulich, wei.liu2,
dgdegra
In Xen's implementation, the CAT enforcement granularity is per domain.
Due to the length of CBM and the number of COS may be socket-different,
each domain has COS ID for each socket. The domain get COS=0 by default
and at runtime its COS is then allocated dynamically when user specifies
a CBM for the domain.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
Changes in v10:
* Use for_each_set_bit().
Changes in v6:
* Add spinlock for cos_to_cbm.
---
xen/arch/x86/domain.c | 6 +++++-
xen/arch/x86/psr.c | 46 ++++++++++++++++++++++++++++++++++++++++++++
xen/include/asm-x86/domain.h | 5 ++++-
xen/include/asm-x86/psr.h | 3 +++
4 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c
index 0363650..a055f0b 100644
--- a/xen/arch/x86/domain.c
+++ b/xen/arch/x86/domain.c
@@ -620,6 +620,9 @@ int arch_domain_create(struct domain *d, unsigned int domcr_flags,
/* 64-bit PV guest by default. */
d->arch.is_32bit_pv = d->arch.has_32bit_shinfo = 0;
+ if ( (rc = psr_domain_init(d)) != 0 )
+ goto fail;
+
/* initialize default tsc behavior in case tools don't */
tsc_set_info(d, TSC_MODE_DEFAULT, 0UL, 0, 0);
spin_lock_init(&d->arch.vtsc_lock);
@@ -638,6 +641,7 @@ int arch_domain_create(struct domain *d, unsigned int domcr_flags,
free_perdomain_mappings(d);
if ( is_pv_domain(d) )
free_xenheap_page(d->arch.pv_domain.gdt_ldt_l1tab);
+ psr_domain_free(d);
return rc;
}
@@ -661,7 +665,7 @@ void arch_domain_destroy(struct domain *d)
free_xenheap_page(d->shared_info);
cleanup_domain_irq_mapping(d);
- psr_free_rmid(d);
+ psr_domain_free(d);
}
void arch_domain_shutdown(struct domain *d)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 623aca1..547e5fe 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -30,6 +30,7 @@ struct psr_cat_socket_info {
unsigned int cbm_len;
unsigned int cos_max;
struct psr_cat_cbm *cos_to_cbm;
+ spinlock_t cbm_lock;
};
struct psr_assoc {
@@ -215,6 +216,49 @@ void psr_ctxt_switch_to(struct domain *d)
}
}
+/* Called with domain lock held, no extra lock needed for 'psr_cos_ids' */
+static void psr_free_cos(struct domain *d)
+{
+ unsigned int socket;
+ unsigned int cos;
+ struct psr_cat_socket_info *info;
+
+ if( !d->arch.psr_cos_ids )
+ return;
+
+ for_each_set_bit(socket, cat_socket_enable, nr_sockets)
+ {
+ if ( (cos = d->arch.psr_cos_ids[socket]) == 0 )
+ continue;
+
+ info = cat_socket_info + socket;
+ spin_lock(&info->cbm_lock);
+ info->cos_to_cbm[cos].ref--;
+ spin_unlock(&info->cbm_lock);
+ }
+
+ xfree(d->arch.psr_cos_ids);
+ d->arch.psr_cos_ids = NULL;
+}
+
+int psr_domain_init(struct domain *d)
+{
+ if ( cat_socket_info )
+ {
+ d->arch.psr_cos_ids = xzalloc_array(unsigned int, nr_sockets);
+ if ( !d->arch.psr_cos_ids )
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+void psr_domain_free(struct domain *d)
+{
+ psr_free_rmid(d);
+ psr_free_cos(d);
+}
+
static int cat_cpu_prepare(unsigned int cpu)
{
struct psr_cat_socket_info *info;
@@ -261,6 +305,8 @@ static void cat_cpu_init(void)
/* cos=0 is reserved as default cbm(all ones). */
info->cos_to_cbm[0].cbm = (1ull << info->cbm_len) - 1;
+ spin_lock_init(&info->cbm_lock);
+
set_bit(socket, cat_socket_enable);
printk(XENLOG_INFO "CAT: enabled on socket %u, cos_max:%u, cbm_len:%u\n",
socket, info->cos_max, info->cbm_len);
diff --git a/xen/include/asm-x86/domain.h b/xen/include/asm-x86/domain.h
index 5eb6832..9dba161 100644
--- a/xen/include/asm-x86/domain.h
+++ b/xen/include/asm-x86/domain.h
@@ -338,7 +338,10 @@ struct arch_domain
struct e820entry *e820;
unsigned int nr_e820;
- unsigned int psr_rmid; /* RMID assigned to the domain for CMT */
+ /* RMID assigned to the domain for CMT */
+ unsigned int psr_rmid;
+ /* COS assigned to the domain for each socket */
+ unsigned int *psr_cos_ids;
/* Shared page for notifying that explicit PIRQ EOI is required. */
unsigned long *pirq_eoi_map;
diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
index bdda111..1023d5f 100644
--- a/xen/include/asm-x86/psr.h
+++ b/xen/include/asm-x86/psr.h
@@ -51,6 +51,9 @@ int psr_alloc_rmid(struct domain *d);
void psr_free_rmid(struct domain *d);
void psr_ctxt_switch_to(struct domain *d);
+int psr_domain_init(struct domain *d);
+void psr_domain_free(struct domain *d);
+
#endif /* __ASM_PSR_H__ */
/*
--
1.9.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v10 05/13] x86: expose CBM length and COS number information
2015-06-26 8:43 [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs Chao Peng
` (3 preceding siblings ...)
2015-06-26 8:43 ` [PATCH v10 04/13] x86: add COS information for each domain Chao Peng
@ 2015-06-26 8:43 ` Chao Peng
2015-06-26 8:43 ` [PATCH v10 06/13] x86: dynamically get/set CBM for a domain Chao Peng
` (8 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Chao Peng @ 2015-06-26 8:43 UTC (permalink / raw)
To: xen-devel
Cc: keir, Ian.Campbell, stefano.stabellini, andrew.cooper3,
dario.faggioli, Ian.Jackson, will.auld, JBeulich, wei.liu2,
dgdegra
General CAT information such as maximum COS and CBM length are exposed to
user space by a SYSCTL hypercall, to help user space to construct the CBM.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
Changes in v10:
* Change psr_get_cat_l3_info to return either errno or psr_cat_socket_info.
Changes in v9:
* Initialize 'info' explictly so that compiler would not complain.
* Simplify the code and remove multiple return points.
* Remove confused comment for 'target'.
Changes in v7:
* Copyback psr_cat_op only for XEN_SYSCTL_PSR_CAT_get_l3_info.
---
xen/arch/x86/psr.c | 28 ++++++++++++++++++++++++++++
xen/arch/x86/sysctl.c | 18 ++++++++++++++++++
xen/include/asm-x86/psr.h | 3 +++
xen/include/public/sysctl.h | 16 ++++++++++++++++
4 files changed, 65 insertions(+)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 547e5fe..81f9901 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -15,6 +15,7 @@
*/
#include <xen/init.h>
#include <xen/cpu.h>
+#include <xen/err.h>
#include <xen/sched.h>
#include <asm/psr.h>
@@ -215,6 +216,33 @@ void psr_ctxt_switch_to(struct domain *d)
psra->val = reg;
}
}
+static struct psr_cat_socket_info *get_cat_socket_info(unsigned int socket)
+{
+ if ( !cat_socket_info )
+ return ERR_PTR(-ENODEV);
+
+ if ( socket >= nr_sockets )
+ return ERR_PTR(-EBADSLT);
+
+ if ( !test_bit(socket, cat_socket_enable) )
+ return ERR_PTR(-ENOENT);
+
+ return cat_socket_info + socket;
+}
+
+int psr_get_cat_l3_info(unsigned int socket, uint32_t *cbm_len,
+ uint32_t *cos_max)
+{
+ struct psr_cat_socket_info *info = get_cat_socket_info(socket);
+
+ if ( IS_ERR(info) )
+ return PTR_ERR(info);
+
+ *cbm_len = info->cbm_len;
+ *cos_max = info->cos_max;
+
+ return 0;
+}
/* Called with domain lock held, no extra lock needed for 'psr_cos_ids' */
static void psr_free_cos(struct domain *d)
diff --git a/xen/arch/x86/sysctl.c b/xen/arch/x86/sysctl.c
index 611a291..f36b52f 100644
--- a/xen/arch/x86/sysctl.c
+++ b/xen/arch/x86/sysctl.c
@@ -171,6 +171,24 @@ long arch_do_sysctl(
break;
+ case XEN_SYSCTL_psr_cat_op:
+ switch ( sysctl->u.psr_cat_op.cmd )
+ {
+ case XEN_SYSCTL_PSR_CAT_get_l3_info:
+ ret = psr_get_cat_l3_info(sysctl->u.psr_cat_op.target,
+ &sysctl->u.psr_cat_op.u.l3_info.cbm_len,
+ &sysctl->u.psr_cat_op.u.l3_info.cos_max);
+
+ if ( !ret && __copy_field_to_guest(u_sysctl, sysctl, u.psr_cat_op) )
+ ret = -EFAULT;
+
+ break;
+ default:
+ ret = -EOPNOTSUPP;
+ break;
+ }
+ break;
+
default:
ret = -ENOSYS;
break;
diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
index 1023d5f..d364e8c 100644
--- a/xen/include/asm-x86/psr.h
+++ b/xen/include/asm-x86/psr.h
@@ -51,6 +51,9 @@ int psr_alloc_rmid(struct domain *d);
void psr_free_rmid(struct domain *d);
void psr_ctxt_switch_to(struct domain *d);
+int psr_get_cat_l3_info(unsigned int socket, uint32_t *cbm_len,
+ uint32_t *cos_max);
+
int psr_domain_init(struct domain *d);
void psr_domain_free(struct domain *d);
diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h
index 0cf9277..cd544c0 100644
--- a/xen/include/public/sysctl.h
+++ b/xen/include/public/sysctl.h
@@ -694,6 +694,20 @@ struct xen_sysctl_pcitopoinfo {
typedef struct xen_sysctl_pcitopoinfo xen_sysctl_pcitopoinfo_t;
DEFINE_XEN_GUEST_HANDLE(xen_sysctl_pcitopoinfo_t);
+#define XEN_SYSCTL_PSR_CAT_get_l3_info 0
+struct xen_sysctl_psr_cat_op {
+ uint32_t cmd; /* IN: XEN_SYSCTL_PSR_CAT_* */
+ uint32_t target; /* IN */
+ union {
+ struct {
+ uint32_t cbm_len; /* OUT: CBM length */
+ uint32_t cos_max; /* OUT: Maximum COS */
+ } l3_info;
+ } u;
+};
+typedef struct xen_sysctl_psr_cat_op xen_sysctl_psr_cat_op_t;
+DEFINE_XEN_GUEST_HANDLE(xen_sysctl_psr_cat_op_t);
+
struct xen_sysctl {
uint32_t cmd;
#define XEN_SYSCTL_readconsole 1
@@ -717,6 +731,7 @@ struct xen_sysctl {
#define XEN_SYSCTL_coverage_op 20
#define XEN_SYSCTL_psr_cmt_op 21
#define XEN_SYSCTL_pcitopoinfo 22
+#define XEN_SYSCTL_psr_cat_op 23
uint32_t interface_version; /* XEN_SYSCTL_INTERFACE_VERSION */
union {
struct xen_sysctl_readconsole readconsole;
@@ -740,6 +755,7 @@ struct xen_sysctl {
struct xen_sysctl_scheduler_op scheduler_op;
struct xen_sysctl_coverage_op coverage_op;
struct xen_sysctl_psr_cmt_op psr_cmt_op;
+ struct xen_sysctl_psr_cat_op psr_cat_op;
uint8_t pad[128];
} u;
};
--
1.9.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v10 06/13] x86: dynamically get/set CBM for a domain
2015-06-26 8:43 [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs Chao Peng
` (4 preceding siblings ...)
2015-06-26 8:43 ` [PATCH v10 05/13] x86: expose CBM length and COS number information Chao Peng
@ 2015-06-26 8:43 ` Chao Peng
2015-06-26 8:43 ` [PATCH v10 07/13] x86: add scheduling support for Intel CAT Chao Peng
` (7 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Chao Peng @ 2015-06-26 8:43 UTC (permalink / raw)
To: xen-devel
Cc: keir, Ian.Campbell, stefano.stabellini, andrew.cooper3,
dario.faggioli, Ian.Jackson, will.auld, JBeulich, wei.liu2,
dgdegra
For CAT, COS is maintained in hypervisor only while CBM is exposed to
user space directly to allow getting/setting domain's cache capacity.
For each specified CBM, hypervisor will either use a existed COS which
has the same CBM or allocate a new one if the same CBM is not found. If
the allocation fails because of no enough COS available then error is
returned. The getting/setting are always operated on a specified socket.
For multiple sockets system, the interface may be called several times.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Reviewed-by: Dario Faggioli <dario.faggioli@citrix.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
Changes in v10:
* Align the return type change for get_cat_socket_info.
* Add ASSERT(cos == 0 || map[cos].ref != 0);
Changes in v9:
* Initialize 'info' explictly so that compiler would not complain.
* Simplify the code and remove multiple return points.
* Remove confused comment for 'target'.
* Add an additional check for cbm to make sure at least one bit is set(which is required).
Changes in v8:
* Add likely for 'socket < nr_sockets' in get_socket_cpu.
Changes in v7:
* find => found in psr_set_l3_cbm().
Changes in v6:
* Correct spin_lock scope.
Changes in v5:
* Add spin_lock to protect cbm_map.
---
xen/arch/x86/domctl.c | 20 ++++++
xen/arch/x86/psr.c | 141 ++++++++++++++++++++++++++++++++++++++++
xen/include/asm-x86/msr-index.h | 1 +
xen/include/asm-x86/psr.h | 2 +
xen/include/public/domctl.h | 12 ++++
5 files changed, 176 insertions(+)
diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index d8ffe2b..abf2be4 100644
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1162,6 +1162,26 @@ long arch_do_domctl(
}
break;
+ case XEN_DOMCTL_psr_cat_op:
+ switch ( domctl->u.psr_cat_op.cmd )
+ {
+ case XEN_DOMCTL_PSR_CAT_OP_SET_L3_CBM:
+ ret = psr_set_l3_cbm(d, domctl->u.psr_cat_op.target,
+ domctl->u.psr_cat_op.data);
+ break;
+
+ case XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM:
+ ret = psr_get_l3_cbm(d, domctl->u.psr_cat_op.target,
+ &domctl->u.psr_cat_op.data);
+ copyback = 1;
+ break;
+
+ default:
+ ret = -EOPNOTSUPP;
+ break;
+ }
+ break;
+
default:
ret = iommu_do_domctl(domctl, d, u_domctl);
break;
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 81f9901..97034a9 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -49,6 +49,14 @@ static unsigned int __read_mostly opt_cos_max = 255;
static uint64_t rmid_mask;
static DEFINE_PER_CPU(struct psr_assoc, psr_assoc);
+static unsigned int get_socket_cpu(unsigned int socket)
+{
+ if ( likely(socket < nr_sockets) )
+ return cpumask_any(socket_cpumask[socket]);
+
+ return nr_cpu_ids;
+}
+
static void __init parse_psr_bool(char *s, char *value, char *feature,
unsigned int mask)
{
@@ -244,6 +252,139 @@ int psr_get_cat_l3_info(unsigned int socket, uint32_t *cbm_len,
return 0;
}
+int psr_get_l3_cbm(struct domain *d, unsigned int socket, uint64_t *cbm)
+{
+ struct psr_cat_socket_info *info = get_cat_socket_info(socket);
+
+ if ( IS_ERR(info) )
+ return PTR_ERR(info);
+
+ *cbm = info->cos_to_cbm[d->arch.psr_cos_ids[socket]].cbm;
+
+ return 0;
+}
+
+static bool_t psr_check_cbm(unsigned int cbm_len, uint64_t cbm)
+{
+ unsigned int first_bit, zero_bit;
+
+ /* Set bits should only in the range of [0, cbm_len). */
+ if ( cbm & (~0ull << cbm_len) )
+ return 0;
+
+ /* At least one bit need to be set. */
+ if ( cbm == 0 )
+ return 0;
+
+ first_bit = find_first_bit(&cbm, cbm_len);
+ zero_bit = find_next_zero_bit(&cbm, cbm_len, first_bit);
+
+ /* Set bits should be contiguous. */
+ if ( zero_bit < cbm_len &&
+ find_next_bit(&cbm, cbm_len, zero_bit) < cbm_len )
+ return 0;
+
+ return 1;
+}
+
+struct cos_cbm_info
+{
+ unsigned int cos;
+ uint64_t cbm;
+};
+
+static void do_write_l3_cbm(void *data)
+{
+ struct cos_cbm_info *info = data;
+
+ wrmsrl(MSR_IA32_PSR_L3_MASK(info->cos), info->cbm);
+}
+
+static int write_l3_cbm(unsigned int socket, unsigned int cos, uint64_t cbm)
+{
+ struct cos_cbm_info info = { .cos = cos, .cbm = cbm };
+
+ if ( socket == cpu_to_socket(smp_processor_id()) )
+ do_write_l3_cbm(&info);
+ else
+ {
+ unsigned int cpu = get_socket_cpu(socket);
+
+ if ( cpu >= nr_cpu_ids )
+ return -EBADSLT;
+ on_selected_cpus(cpumask_of(cpu), do_write_l3_cbm, &info, 1);
+ }
+
+ return 0;
+}
+
+int psr_set_l3_cbm(struct domain *d, unsigned int socket, uint64_t cbm)
+{
+ unsigned int old_cos, cos;
+ struct psr_cat_cbm *map, *found = NULL;
+ struct psr_cat_socket_info *info = get_cat_socket_info(socket);
+
+ if ( IS_ERR(info) )
+ return PTR_ERR(info);
+
+ if ( !psr_check_cbm(info->cbm_len, cbm) )
+ return -EINVAL;
+
+ old_cos = d->arch.psr_cos_ids[socket];
+ map = info->cos_to_cbm;
+
+ spin_lock(&info->cbm_lock);
+
+ for ( cos = 0; cos <= info->cos_max; cos++ )
+ {
+ /* If still not found, then keep unused one. */
+ if ( !found && cos != 0 && map[cos].ref == 0 )
+ found = map + cos;
+ else if ( map[cos].cbm == cbm )
+ {
+ if ( unlikely(cos == old_cos) )
+ {
+ ASSERT(cos == 0 || map[cos].ref != 0);
+ spin_unlock(&info->cbm_lock);
+ return 0;
+ }
+ found = map + cos;
+ break;
+ }
+ }
+
+ /* If old cos is referred only by the domain, then use it. */
+ if ( !found && map[old_cos].ref == 1 )
+ found = map + old_cos;
+
+ if ( !found )
+ {
+ spin_unlock(&info->cbm_lock);
+ return -EUSERS;
+ }
+
+ cos = found - map;
+ if ( found->cbm != cbm )
+ {
+ int ret = write_l3_cbm(socket, cos, cbm);
+
+ if ( ret )
+ {
+ spin_unlock(&info->cbm_lock);
+ return ret;
+ }
+ found->cbm = cbm;
+ }
+
+ found->ref++;
+ map[old_cos].ref--;
+ spin_unlock(&info->cbm_lock);
+
+ d->arch.psr_cos_ids[socket] = cos;
+
+ return 0;
+}
+
/* Called with domain lock held, no extra lock needed for 'psr_cos_ids' */
static void psr_free_cos(struct domain *d)
{
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 83f2f70..5425f77 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -327,6 +327,7 @@
#define MSR_IA32_CMT_EVTSEL 0x00000c8d
#define MSR_IA32_CMT_CTR 0x00000c8e
#define MSR_IA32_PSR_ASSOC 0x00000c8f
+#define MSR_IA32_PSR_L3_MASK(n) (0x00000c90 + (n))
/* Intel Model 6 */
#define MSR_P6_PERFCTR(n) (0x000000c1 + (n))
diff --git a/xen/include/asm-x86/psr.h b/xen/include/asm-x86/psr.h
index d364e8c..081750f 100644
--- a/xen/include/asm-x86/psr.h
+++ b/xen/include/asm-x86/psr.h
@@ -53,6 +53,8 @@ void psr_ctxt_switch_to(struct domain *d);
int psr_get_cat_l3_info(unsigned int socket, uint32_t *cbm_len,
uint32_t *cos_max);
+int psr_get_l3_cbm(struct domain *d, unsigned int socket, uint64_t *cbm);
+int psr_set_l3_cbm(struct domain *d, unsigned int socket, uint64_t cbm);
int psr_domain_init(struct domain *d);
void psr_domain_free(struct domain *d);
diff --git a/xen/include/public/domctl.h b/xen/include/public/domctl.h
index bc45ea5..90db0f6 100644
--- a/xen/include/public/domctl.h
+++ b/xen/include/public/domctl.h
@@ -1039,6 +1039,16 @@ struct xen_domctl_monitor_op {
typedef struct xen_domctl_monitor_op xen_domctl_monitor_op_t;
DEFINE_XEN_GUEST_HANDLE(xen_domctl_monitor_op_t);
+struct xen_domctl_psr_cat_op {
+#define XEN_DOMCTL_PSR_CAT_OP_SET_L3_CBM 0
+#define XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM 1
+ uint32_t cmd; /* IN: XEN_DOMCTL_PSR_CAT_OP_* */
+ uint32_t target; /* IN */
+ uint64_t data; /* IN/OUT */
+};
+typedef struct xen_domctl_psr_cat_op xen_domctl_psr_cat_op_t;
+DEFINE_XEN_GUEST_HANDLE(xen_domctl_psr_cat_op_t);
+
struct xen_domctl {
uint32_t cmd;
#define XEN_DOMCTL_createdomain 1
@@ -1114,6 +1124,7 @@ struct xen_domctl {
#define XEN_DOMCTL_setvnumainfo 74
#define XEN_DOMCTL_psr_cmt_op 75
#define XEN_DOMCTL_monitor_op 77
+#define XEN_DOMCTL_psr_cat_op 78
#define XEN_DOMCTL_gdbsx_guestmemio 1000
#define XEN_DOMCTL_gdbsx_pausevcpu 1001
#define XEN_DOMCTL_gdbsx_unpausevcpu 1002
@@ -1175,6 +1186,7 @@ struct xen_domctl {
struct xen_domctl_vnuma vnuma;
struct xen_domctl_psr_cmt_op psr_cmt_op;
struct xen_domctl_monitor_op monitor_op;
+ struct xen_domctl_psr_cat_op psr_cat_op;
uint8_t pad[128];
} u;
};
--
1.9.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v10 07/13] x86: add scheduling support for Intel CAT
2015-06-26 8:43 [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs Chao Peng
` (5 preceding siblings ...)
2015-06-26 8:43 ` [PATCH v10 06/13] x86: dynamically get/set CBM for a domain Chao Peng
@ 2015-06-26 8:43 ` Chao Peng
2015-06-26 8:43 ` [PATCH v10 08/13] xsm: add CAT related xsm policies Chao Peng
` (6 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Chao Peng @ 2015-06-26 8:43 UTC (permalink / raw)
To: xen-devel
Cc: keir, Ian.Campbell, stefano.stabellini, andrew.cooper3,
dario.faggioli, Ian.Jackson, will.auld, JBeulich, wei.liu2,
dgdegra
On context switch, write the the domain's Class of Service(COS) to MSR
IA32_PQR_ASSOC, to notify hardware to use the new COS.
For performance reason, the COS mask for current cpu is also cached in
the local per-CPU variable.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Acked-by: Jan Beulich <jbeulich@suse.com>
---
Changes in v5:
* Remove the need to cache socket.
Changes in v2:
* merge common scheduling changes into scheduling improvement patch.
* use readable expr for psra->cos_mask.
---
xen/arch/x86/psr.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/xen/arch/x86/psr.c b/xen/arch/x86/psr.c
index 97034a9..2a30e3c 100644
--- a/xen/arch/x86/psr.c
+++ b/xen/arch/x86/psr.c
@@ -36,6 +36,7 @@ struct psr_cat_socket_info {
struct psr_assoc {
uint64_t val;
+ uint64_t cos_mask;
};
struct psr_cmt *__read_mostly psr_cmt;
@@ -201,7 +202,16 @@ static inline void psr_assoc_init(void)
{
struct psr_assoc *psra = &this_cpu(psr_assoc);
- if ( psr_cmt_enabled() )
+ if ( cat_socket_info )
+ {
+ unsigned int socket = cpu_to_socket(smp_processor_id());
+
+ if ( test_bit(socket, cat_socket_enable) )
+ psra->cos_mask = ((1ull << get_count_order(
+ cat_socket_info[socket].cos_max)) - 1) << 32;
+ }
+
+ if ( psr_cmt_enabled() || psra->cos_mask )
rdmsrl(MSR_IA32_PSR_ASSOC, psra->val);
}
@@ -210,6 +220,12 @@ static inline void psr_assoc_rmid(uint64_t *reg, unsigned int rmid)
*reg = (*reg & ~rmid_mask) | (rmid & rmid_mask);
}
+static inline void psr_assoc_cos(uint64_t *reg, unsigned int cos,
+ uint64_t cos_mask)
+{
+ *reg = (*reg & ~cos_mask) | (((uint64_t)cos << 32) & cos_mask);
+}
+
void psr_ctxt_switch_to(struct domain *d)
{
struct psr_assoc *psra = &this_cpu(psr_assoc);
@@ -218,6 +234,11 @@ void psr_ctxt_switch_to(struct domain *d)
if ( psr_cmt_enabled() )
psr_assoc_rmid(®, d->arch.psr_rmid);
+ if ( psra->cos_mask )
+ psr_assoc_cos(®, d->arch.psr_cos_ids ?
+ d->arch.psr_cos_ids[cpu_to_socket(smp_processor_id())] :
+ 0, psra->cos_mask);
+
if ( reg != psra->val )
{
wrmsrl(MSR_IA32_PSR_ASSOC, reg);
--
1.9.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v10 08/13] xsm: add CAT related xsm policies
2015-06-26 8:43 [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs Chao Peng
` (6 preceding siblings ...)
2015-06-26 8:43 ` [PATCH v10 07/13] x86: add scheduling support for Intel CAT Chao Peng
@ 2015-06-26 8:43 ` Chao Peng
2015-06-26 8:43 ` [PATCH v10 09/13] tools/libxl: minor name changes for CMT commands Chao Peng
` (5 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Chao Peng @ 2015-06-26 8:43 UTC (permalink / raw)
To: xen-devel
Cc: keir, Ian.Campbell, stefano.stabellini, andrew.cooper3,
dario.faggioli, Ian.Jackson, will.auld, JBeulich, wei.liu2,
dgdegra
Add xsm policies for Cache Allocation Technology(CAT) related hypercalls
to restrict the functions visibility to control domain only.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Acked-by: Daniel De Graaf <dgdegra@tycho.nsa.gov>
---
tools/flask/policy/policy/modules/xen/xen.if | 2 +-
tools/flask/policy/policy/modules/xen/xen.te | 4 +++-
xen/xsm/flask/hooks.c | 6 ++++++
xen/xsm/flask/policy/access_vectors | 4 ++++
4 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/tools/flask/policy/policy/modules/xen/xen.if b/tools/flask/policy/policy/modules/xen/xen.if
index f4cde11..da4c95b 100644
--- a/tools/flask/policy/policy/modules/xen/xen.if
+++ b/tools/flask/policy/policy/modules/xen/xen.if
@@ -52,7 +52,7 @@ define(`create_domain_common', `
getaffinity setaffinity setvcpuextstate };
allow $1 $2:domain2 { set_cpuid settsc setscheduler setclaim
set_max_evtchn set_vnumainfo get_vnumainfo cacheflush
- psr_cmt_op };
+ psr_cmt_op psr_cat_op };
allow $1 $2:security check_context;
allow $1 $2:shadow enable;
allow $1 $2:mmu { map_read map_write adjust memorymap physmap pinpage mmuext_op updatemp };
diff --git a/tools/flask/policy/policy/modules/xen/xen.te b/tools/flask/policy/policy/modules/xen/xen.te
index 51f59c5..50aacfe 100644
--- a/tools/flask/policy/policy/modules/xen/xen.te
+++ b/tools/flask/policy/policy/modules/xen/xen.te
@@ -67,6 +67,7 @@ allow dom0_t xen_t:xen {
allow dom0_t xen_t:xen2 {
resource_op
psr_cmt_op
+ psr_cat_op
};
allow dom0_t xen_t:mmu memorymap;
@@ -80,7 +81,8 @@ allow dom0_t dom0_t:domain {
getpodtarget setpodtarget set_misc_info set_virq_handler
};
allow dom0_t dom0_t:domain2 {
- set_cpuid gettsc settsc setscheduler set_max_evtchn set_vnumainfo get_vnumainfo psr_cmt_op
+ set_cpuid gettsc settsc setscheduler set_max_evtchn set_vnumainfo
+ get_vnumainfo psr_cmt_op psr_cat_op
};
allow dom0_t dom0_t:resource { add remove };
diff --git a/xen/xsm/flask/hooks.c b/xen/xsm/flask/hooks.c
index 6e37d29..317f50f 100644
--- a/xen/xsm/flask/hooks.c
+++ b/xen/xsm/flask/hooks.c
@@ -735,6 +735,9 @@ static int flask_domctl(struct domain *d, int cmd)
case XEN_DOMCTL_psr_cmt_op:
return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__PSR_CMT_OP);
+ case XEN_DOMCTL_psr_cat_op:
+ return current_has_perm(d, SECCLASS_DOMAIN2, DOMAIN2__PSR_CAT_OP);
+
default:
printk("flask_domctl: Unknown op %d\n", cmd);
return -EPERM;
@@ -794,6 +797,9 @@ static int flask_sysctl(int cmd)
case XEN_SYSCTL_psr_cmt_op:
return avc_current_has_perm(SECINITSID_XEN, SECCLASS_XEN2,
XEN2__PSR_CMT_OP, NULL);
+ case XEN_SYSCTL_psr_cat_op:
+ return avc_current_has_perm(SECINITSID_XEN, SECCLASS_XEN2,
+ XEN2__PSR_CAT_OP, NULL);
default:
printk("flask_sysctl: Unknown op %d\n", cmd);
diff --git a/xen/xsm/flask/policy/access_vectors b/xen/xsm/flask/policy/access_vectors
index 68284d5..e1a11b2 100644
--- a/xen/xsm/flask/policy/access_vectors
+++ b/xen/xsm/flask/policy/access_vectors
@@ -85,6 +85,8 @@ class xen2
resource_op
# XEN_SYSCTL_psr_cmt_op
psr_cmt_op
+# XEN_SYSCTL_psr_cat_op
+ psr_cat_op
}
# Classes domain and domain2 consist of operations that a domain performs on
@@ -230,6 +232,8 @@ class domain2
mem_paging
# XENMEM_sharing_op
mem_sharing
+# XEN_DOMCTL_psr_cat_op
+ psr_cat_op
}
# Similar to class domain, but primarily contains domctls related to HVM domains
--
1.9.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v10 09/13] tools/libxl: minor name changes for CMT commands
2015-06-26 8:43 [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs Chao Peng
` (7 preceding siblings ...)
2015-06-26 8:43 ` [PATCH v10 08/13] xsm: add CAT related xsm policies Chao Peng
@ 2015-06-26 8:43 ` Chao Peng
2015-06-26 8:43 ` [PATCH v10 10/13] tools/libxl: add command to show PSR hardware info Chao Peng
` (4 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Chao Peng @ 2015-06-26 8:43 UTC (permalink / raw)
To: xen-devel
Cc: keir, Ian.Campbell, stefano.stabellini, andrew.cooper3,
dario.faggioli, Ian.Jackson, will.auld, JBeulich, wei.liu2,
dgdegra
Use "-" instead of "_" for monitor types.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Reviewed-by: Dario Faggioli <dario.faggioli@citrix.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---
tools/libxl/xl_cmdimpl.c | 6 +++---
tools/libxl/xl_cmdtable.c | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/tools/libxl/xl_cmdimpl.c b/tools/libxl/xl_cmdimpl.c
index c858068..fbc69ab 100644
--- a/tools/libxl/xl_cmdimpl.c
+++ b/tools/libxl/xl_cmdimpl.c
@@ -8286,11 +8286,11 @@ int main_psr_cmt_show(int argc, char **argv)
/* No options */
}
- if (!strcmp(argv[optind], "cache_occupancy"))
+ if (!strcmp(argv[optind], "cache-occupancy"))
type = LIBXL_PSR_CMT_TYPE_CACHE_OCCUPANCY;
- else if (!strcmp(argv[optind], "total_mem_bandwidth"))
+ else if (!strcmp(argv[optind], "total-mem-bandwidth"))
type = LIBXL_PSR_CMT_TYPE_TOTAL_MEM_COUNT;
- else if (!strcmp(argv[optind], "local_mem_bandwidth"))
+ else if (!strcmp(argv[optind], "local-mem-bandwidth"))
type = LIBXL_PSR_CMT_TYPE_LOCAL_MEM_COUNT;
else {
help("psr-cmt-show");
diff --git a/tools/libxl/xl_cmdtable.c b/tools/libxl/xl_cmdtable.c
index 7f4759b..12899d1 100644
--- a/tools/libxl/xl_cmdtable.c
+++ b/tools/libxl/xl_cmdtable.c
@@ -540,9 +540,9 @@ struct cmd_spec cmd_table[] = {
"Show Cache Monitoring Technology information",
"<PSR-CMT-Type> <Domain>",
"Available monitor types:\n"
- "\"cache_occupancy\": Show L3 cache occupancy(KB)\n"
- "\"total_mem_bandwidth\": Show total memory bandwidth(KB/s)\n"
- "\"local_mem_bandwidth\": Show local memory bandwidth(KB/s)\n",
+ "\"cache-occupancy\": Show L3 cache occupancy(KB)\n"
+ "\"total-mem-bandwidth\": Show total memory bandwidth(KB/s)\n"
+ "\"local-mem-bandwidth\": Show local memory bandwidth(KB/s)\n",
},
#endif
};
--
1.9.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v10 10/13] tools/libxl: add command to show PSR hardware info
2015-06-26 8:43 [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs Chao Peng
` (8 preceding siblings ...)
2015-06-26 8:43 ` [PATCH v10 09/13] tools/libxl: minor name changes for CMT commands Chao Peng
@ 2015-06-26 8:43 ` Chao Peng
2015-06-26 8:43 ` [PATCH v10 11/13] tools/libxl: introduce some socket helpers Chao Peng
` (3 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Chao Peng @ 2015-06-26 8:43 UTC (permalink / raw)
To: xen-devel
Cc: keir, Ian.Campbell, stefano.stabellini, andrew.cooper3,
dario.faggioli, Ian.Jackson, will.auld, JBeulich, wei.liu2,
dgdegra
Add dedicated one to show hardware information.
[root@vmm-psr]xl psr-hwinfo
Cache Monitoring Technology (CMT):
Enabled : 1
Total RMID : 63
Supported monitor types:
cache-occupancy
total-mem-bandwidth
local-mem-bandwidth
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Reviewed-by: Dario Faggioli <dario.faggioli@citrix.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---
Changes in v6:
* Add SWITCH_FOREACH_OPT to make '-h' work.
---
docs/man/xl.pod.1 | 4 ++++
tools/libxl/xl.h | 1 +
tools/libxl/xl_cmdimpl.c | 41 +++++++++++++++++++++++++++++++++++++++++
tools/libxl/xl_cmdtable.c | 5 +++++
4 files changed, 51 insertions(+)
diff --git a/docs/man/xl.pod.1 b/docs/man/xl.pod.1
index 4eb929d..cebec46 100644
--- a/docs/man/xl.pod.1
+++ b/docs/man/xl.pod.1
@@ -1502,6 +1502,10 @@ for any of these monitoring types.
=over 4
+=item B<psr-hwinfo>
+
+Show CMT hardware information.
+
=item B<psr-cmt-attach> [I<domain-id>]
attach: Attach the platform shared resource monitoring service to a domain.
diff --git a/tools/libxl/xl.h b/tools/libxl/xl.h
index 5bc138c..7b56449 100644
--- a/tools/libxl/xl.h
+++ b/tools/libxl/xl.h
@@ -113,6 +113,7 @@ int main_remus(int argc, char **argv);
#endif
int main_devd(int argc, char **argv);
#ifdef LIBXL_HAVE_PSR_CMT
+int main_psr_hwinfo(int argc, char **argv);
int main_psr_cmt_attach(int argc, char **argv);
int main_psr_cmt_detach(int argc, char **argv);
int main_psr_cmt_show(int argc, char **argv);
diff --git a/tools/libxl/xl_cmdimpl.c b/tools/libxl/xl_cmdimpl.c
index fbc69ab..e76a154 100644
--- a/tools/libxl/xl_cmdimpl.c
+++ b/tools/libxl/xl_cmdimpl.c
@@ -8080,6 +8080,36 @@ out:
}
#ifdef LIBXL_HAVE_PSR_CMT
+static int psr_cmt_hwinfo(void)
+{
+ int rc;
+ int enabled;
+ uint32_t total_rmid;
+
+ printf("Cache Monitoring Technology (CMT):\n");
+
+ enabled = libxl_psr_cmt_enabled(ctx);
+ printf("%-16s: %s\n", "Enabled", enabled ? "1" : "0");
+ if (!enabled)
+ return 0;
+
+ rc = libxl_psr_cmt_get_total_rmid(ctx, &total_rmid);
+ if (rc) {
+ fprintf(stderr, "Failed to get max RMID value\n");
+ return rc;
+ }
+ printf("%-16s: %u\n", "Total RMID", total_rmid);
+
+ printf("Supported monitor types:\n");
+ if (libxl_psr_cmt_type_supported(ctx, LIBXL_PSR_CMT_TYPE_CACHE_OCCUPANCY))
+ printf("cache-occupancy\n");
+ if (libxl_psr_cmt_type_supported(ctx, LIBXL_PSR_CMT_TYPE_TOTAL_MEM_COUNT))
+ printf("total-mem-bandwidth\n");
+ if (libxl_psr_cmt_type_supported(ctx, LIBXL_PSR_CMT_TYPE_LOCAL_MEM_COUNT))
+ printf("local-mem-bandwidth\n");
+
+ return rc;
+}
#define MBM_SAMPLE_RETRY_MAX 4
static int psr_cmt_get_mem_bandwidth(uint32_t domid,
@@ -8246,6 +8276,17 @@ static int psr_cmt_show(libxl_psr_cmt_type type, uint32_t domid)
return 0;
}
+int main_psr_hwinfo(int argc, char **argv)
+{
+ int opt;
+
+ SWITCH_FOREACH_OPT(opt, "", NULL, "psr-hwinfo", 0) {
+ /* No options */
+ }
+
+ return psr_cmt_hwinfo();
+}
+
int main_psr_cmt_attach(int argc, char **argv)
{
uint32_t domid;
diff --git a/tools/libxl/xl_cmdtable.c b/tools/libxl/xl_cmdtable.c
index 12899d1..77a37c5 100644
--- a/tools/libxl/xl_cmdtable.c
+++ b/tools/libxl/xl_cmdtable.c
@@ -525,6 +525,11 @@ struct cmd_spec cmd_table[] = {
"-F Run in the foreground",
},
#ifdef LIBXL_HAVE_PSR_CMT
+ { "psr-hwinfo",
+ &main_psr_hwinfo, 0, 1,
+ "Show hardware information for Platform Shared Resource",
+ "",
+ },
{ "psr-cmt-attach",
&main_psr_cmt_attach, 0, 1,
"Attach Cache Monitoring Technology service to a domain",
--
1.9.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v10 11/13] tools/libxl: introduce some socket helpers
2015-06-26 8:43 [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs Chao Peng
` (9 preceding siblings ...)
2015-06-26 8:43 ` [PATCH v10 10/13] tools/libxl: add command to show PSR hardware info Chao Peng
@ 2015-06-26 8:43 ` Chao Peng
2015-06-26 8:43 ` [PATCH v10 12/13] tools: add tools support for Intel CAT Chao Peng
` (2 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Chao Peng @ 2015-06-26 8:43 UTC (permalink / raw)
To: xen-devel
Cc: keir, Ian.Campbell, stefano.stabellini, andrew.cooper3,
dario.faggioli, Ian.Jackson, will.auld, JBeulich, wei.liu2,
dgdegra
Add libxl_socket_bitmap_alloc() to allow allocating a socket specific
libxl_bitmap (as it is for cpu/node bitmap).
Internal function libxl__count_physical_sockets() is introduced together
to get the socket count when the size of bitmap is not specified.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---
Changes in v7:
* Broadcast LIBXL_HAVE_SOCKET_BITMAP_ALLOC
---
tools/libxl/libxl.h | 7 +++++++
tools/libxl/libxl_internal.h | 2 ++
tools/libxl/libxl_utils.c | 46 ++++++++++++++++++++++++++++++++++++++++++++
tools/libxl/libxl_utils.h | 2 ++
4 files changed, 57 insertions(+)
diff --git a/tools/libxl/libxl.h b/tools/libxl/libxl.h
index 0a7913b..13e7a8c 100644
--- a/tools/libxl/libxl.h
+++ b/tools/libxl/libxl.h
@@ -775,6 +775,13 @@ void libxl_mac_copy(libxl_ctx *ctx, libxl_mac *dst, libxl_mac *src);
*/
#define LIBXL_HAVE_PCITOPOLOGY 1
+/*
+ * LIBXL_HAVE_SOCKET_BITMAP_ALLOC
+ *
+ * If this is defined, then libxl_socket_bitmap_alloc exists.
+ */
+#define LIBXL_HAVE_SOCKET_BITMAP_ALLOC 1
+
typedef char **libxl_string_list;
void libxl_string_list_dispose(libxl_string_list *sl);
int libxl_string_list_length(const libxl_string_list *sl);
diff --git a/tools/libxl/libxl_internal.h b/tools/libxl/libxl_internal.h
index e96d6b5..250a87e 100644
--- a/tools/libxl/libxl_internal.h
+++ b/tools/libxl/libxl_internal.h
@@ -3703,6 +3703,8 @@ static inline void libxl__update_config_vtpm(libxl__gc *gc,
*/
void libxl__bitmap_copy_best_effort(libxl__gc *gc, libxl_bitmap *dptr,
const libxl_bitmap *sptr);
+
+int libxl__count_physical_sockets(libxl__gc *gc, int *sockets);
#endif
/*
diff --git a/tools/libxl/libxl_utils.c b/tools/libxl/libxl_utils.c
index f6be2d7..bfc9699 100644
--- a/tools/libxl/libxl_utils.c
+++ b/tools/libxl/libxl_utils.c
@@ -840,6 +840,52 @@ int libxl_node_bitmap_alloc(libxl_ctx *ctx, libxl_bitmap *nodemap,
return rc;
}
+int libxl__count_physical_sockets(libxl__gc *gc, int *sockets)
+{
+ int rc;
+ libxl_physinfo info;
+
+ libxl_physinfo_init(&info);
+
+ rc = libxl_get_physinfo(CTX, &info);
+ if (rc)
+ return rc;
+
+ *sockets = info.nr_cpus / info.threads_per_core
+ / info.cores_per_socket;
+
+ libxl_physinfo_dispose(&info);
+ return 0;
+}
+
+int libxl_socket_bitmap_alloc(libxl_ctx *ctx, libxl_bitmap *socketmap,
+ int max_sockets)
+{
+ GC_INIT(ctx);
+ int rc = 0;
+
+ if (max_sockets < 0) {
+ rc = ERROR_INVAL;
+ LOG(ERROR, "invalid number of sockets provided");
+ goto out;
+ }
+
+ if (max_sockets == 0) {
+ rc = libxl__count_physical_sockets(gc, &max_sockets);
+ if (rc) {
+ LOGE(ERROR, "failed to get system socket count");
+ goto out;
+ }
+ }
+ /* This can't fail: no need to check and log */
+ libxl_bitmap_alloc(ctx, socketmap, max_sockets);
+
+ out:
+ GC_FREE;
+ return rc;
+
+}
+
int libxl_nodemap_to_cpumap(libxl_ctx *ctx,
const libxl_bitmap *nodemap,
libxl_bitmap *cpumap)
diff --git a/tools/libxl/libxl_utils.h b/tools/libxl/libxl_utils.h
index 1c1761d..82340ec 100644
--- a/tools/libxl/libxl_utils.h
+++ b/tools/libxl/libxl_utils.h
@@ -141,6 +141,8 @@ static inline int libxl_bitmap_equal(const libxl_bitmap *ba,
int libxl_cpu_bitmap_alloc(libxl_ctx *ctx, libxl_bitmap *cpumap, int max_cpus);
int libxl_node_bitmap_alloc(libxl_ctx *ctx, libxl_bitmap *nodemap,
int max_nodes);
+int libxl_socket_bitmap_alloc(libxl_ctx *ctx, libxl_bitmap *socketmap,
+ int max_sockets);
/* Populate cpumap with the cpus spanned by the nodes in nodemap */
int libxl_nodemap_to_cpumap(libxl_ctx *ctx,
--
1.9.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v10 12/13] tools: add tools support for Intel CAT
2015-06-26 8:43 [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs Chao Peng
` (10 preceding siblings ...)
2015-06-26 8:43 ` [PATCH v10 11/13] tools/libxl: introduce some socket helpers Chao Peng
@ 2015-06-26 8:43 ` Chao Peng
2015-06-26 8:43 ` [PATCH v10 13/13] docs: add xl-psr.markdown Chao Peng
2015-07-07 14:46 ` [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs Ian Campbell
13 siblings, 0 replies; 23+ messages in thread
From: Chao Peng @ 2015-06-26 8:43 UTC (permalink / raw)
To: xen-devel
Cc: keir, Ian.Campbell, stefano.stabellini, andrew.cooper3,
dario.faggioli, Ian.Jackson, will.auld, JBeulich, wei.liu2,
dgdegra
This is the xc/xl changes to support Intel Cache Allocation
Technology(CAT).
'xl psr-hwinfo' is updated to show CAT info and two new commands
for CAT are introduced:
- xl psr-cat-cbm-set [-s socket] <domain> <cbm>
Set cache capacity bitmasks(CBM) for a domain.
- xl psr-cat-show <domain>
Show CAT domain information.
Examples:
[root@vmm-psr vmm]# xl psr-hwinfo --cat
Cache Allocation Technology (CAT):
Socket ID : 0
L3 Cache : 12288KB
Maximum COS : 15
CBM length : 12
Default CBM : 0xfff
[root@vmm-psr vmm]# xl psr-cat-cbm-set 0 0xff
[root@vmm-psr vmm]# xl psr-cat-show
Socket ID : 0
L3 Cache : 12288KB
Default CBM : 0xfff
ID NAME CBM
0 Domain-0 0xff
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Reviewed-by: Dario Faggioli <dario.faggioli@citrix.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---
Changes in v7:
* Add PSR head1 level section and change CMT/CAT as its subsections for xl man page.
* Other minor document changes.
Changes in v6:
* Merge xl psr-cmt/cat-hwinfo => xl psr-hwinfo.
* Add function header to explain the 'target' parameter.
* Use bitmap instead of TARGETS_ALL.
* Remove the need to store the return value form libxc.
* Minor document/commit msg adjustment.
Changes in v5:
* Add psr-cat-hwinfo.
* Add libxl_psr_cat_info_list_free.
* malloc => libxl__malloc
* Other comments from Ian/Wei.
Changes in v4:
* Add example output in commit message.
* Make libxl__count_physical_sockets private to libxl_psr.c.
* Set errno in several error cases.
* Change libxl_psr_cat_get_l3_info to return all sockets information.
* Remove unused libxl_domain_info call.
Changes in v3:
* Add manpage.
* libxl_psr_cat_set/get_domain_data => libxl_psr_cat_set/get_cbm.
* Move libxl_count_physical_sockets into seperate patch.
* Support LIBXL_PSR_TARGET_ALL for libxl_psr_cat_set_cbm.
* Clean up the print codes.
---
docs/man/xl.pod.1 | 75 +++++++++++--
tools/libxc/include/xenctrl.h | 15 +++
tools/libxc/xc_psr.c | 76 ++++++++++++++
tools/libxl/libxl.h | 35 +++++++
tools/libxl/libxl_psr.c | 143 +++++++++++++++++++++++--
tools/libxl/libxl_types.idl | 10 ++
tools/libxl/xl.h | 4 +
tools/libxl/xl_cmdimpl.c | 237 ++++++++++++++++++++++++++++++++++++++++--
tools/libxl/xl_cmdtable.c | 18 +++-
9 files changed, 584 insertions(+), 29 deletions(-)
diff --git a/docs/man/xl.pod.1 b/docs/man/xl.pod.1
index cebec46..d77ce77 100644
--- a/docs/man/xl.pod.1
+++ b/docs/man/xl.pod.1
@@ -1484,28 +1484,52 @@ policy. Loading new security policy will reset runtime changes to device labels.
=back
-=head1 CACHE MONITORING TECHNOLOGY
+=head1 PLATFORM SHARED RESOURCE MONITORING/CONTROL
+
+Intel Haswell and later server platforms offer shared resource monitoring
+and control technologies. The availability of these technologies and the
+hardware capabilities can be shown with B<psr-hwinfo>.
+
+=over 4
+
+=item B<psr-hwinfo> [I<OPTIONS>]
+
+Show Platform Shared Resource (PSR) hardware information.
+
+B<OPTIONS>
+
+=over 4
+
+=item B<-m>, B<--cmt>
+
+Show Cache Monitoring Technology (CMT) hardware information.
+
+=item B<-a>, B<--cat>
+
+Show Cache Allocation Technology (CAT) hardware information.
+
+=back
+
+=back
+
+=head2 CACHE MONITORING TECHNOLOGY
Intel Haswell and later server platforms offer monitoring capability in each
logical processor to measure specific platform shared resource metric, for
-example, L3 cache occupancy. In Xen implementation, the monitoring granularity
-is domain level. To monitor a specific domain, just attach the domain id with
-the monitoring service. When the domain doesn't need to be monitored any more,
-detach the domain id from the monitoring service.
+example, L3 cache occupancy. In the Xen implementation, the monitoring
+granularity is domain level. To monitor a specific domain, just attach the
+domain id with the monitoring service. When the domain doesn't need to be
+monitored any more, detach the domain id from the monitoring service.
Intel Broadwell and later server platforms also offer total/local memory
bandwidth monitoring. Xen supports per-domain monitoring for these two
additional monitoring types. Both memory bandwidth monitoring and L3 cache
occupancy monitoring share the same set of underlying monitoring service. Once
-a domain is attached to the monitoring service, monitoring data can be showed
+a domain is attached to the monitoring service, monitoring data can be shown
for any of these monitoring types.
=over 4
-=item B<psr-hwinfo>
-
-Show CMT hardware information.
-
=item B<psr-cmt-attach> [I<domain-id>]
attach: Attach the platform shared resource monitoring service to a domain.
@@ -1536,6 +1560,37 @@ ignored:
=back
+=head2 CACHE ALLOCATION TECHNOLOGY
+
+Intel Broadwell and later server platforms offer capabilities to configure and
+make use of the Cache Allocation Technology (CAT) mechanisms, which enable more
+cache resources (i.e. L3 cache) to be made available for high priority
+applications. In the Xen implementation, CAT is used to control cache allocation
+on VM basis. To enforce cache on a specific domain, just set capacity bitmasks
+(CBM) for the domain.
+
+=over 4
+
+=item B<psr-cat-cbm-set> [I<OPTIONS>] I<domain-id> I<cbm>
+
+Set cache capacity bitmasks(CBM) for a domain.
+
+B<OPTIONS>
+
+=over 4
+
+=item B<-s SOCKET>, B<--socket=SOCKET>
+
+Specify the socket to process, otherwise all sockets are processed.
+
+=back
+
+=item B<psr-cat-show> [I<domain-id>]
+
+Show CAT settings for a certain domain or all domains.
+
+=back
+
=head1 TO BE DOCUMENTED
We need better documentation for:
diff --git a/tools/libxc/include/xenctrl.h b/tools/libxc/include/xenctrl.h
index d1d2ab3..5ae9fd1 100644
--- a/tools/libxc/include/xenctrl.h
+++ b/tools/libxc/include/xenctrl.h
@@ -2770,6 +2770,12 @@ enum xc_psr_cmt_type {
XC_PSR_CMT_LOCAL_MEM_COUNT,
};
typedef enum xc_psr_cmt_type xc_psr_cmt_type;
+
+enum xc_psr_cat_type {
+ XC_PSR_CAT_L3_CBM = 1,
+};
+typedef enum xc_psr_cat_type xc_psr_cat_type;
+
int xc_psr_cmt_attach(xc_interface *xch, uint32_t domid);
int xc_psr_cmt_detach(xc_interface *xch, uint32_t domid);
int xc_psr_cmt_get_domain_rmid(xc_interface *xch, uint32_t domid,
@@ -2784,6 +2790,15 @@ int xc_psr_cmt_get_data(xc_interface *xch, uint32_t rmid, uint32_t cpu,
uint32_t psr_cmt_type, uint64_t *monitor_data,
uint64_t *tsc);
int xc_psr_cmt_enabled(xc_interface *xch);
+
+int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
+ xc_psr_cat_type type, uint32_t target,
+ uint64_t data);
+int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
+ xc_psr_cat_type type, uint32_t target,
+ uint64_t *data);
+int xc_psr_cat_get_l3_info(xc_interface *xch, uint32_t socket,
+ uint32_t *cos_max, uint32_t *cbm_len);
#endif
#endif /* XENCTRL_H */
diff --git a/tools/libxc/xc_psr.c b/tools/libxc/xc_psr.c
index e367a80..d8b3a51 100644
--- a/tools/libxc/xc_psr.c
+++ b/tools/libxc/xc_psr.c
@@ -248,6 +248,82 @@ int xc_psr_cmt_enabled(xc_interface *xch)
return 0;
}
+int xc_psr_cat_set_domain_data(xc_interface *xch, uint32_t domid,
+ xc_psr_cat_type type, uint32_t target,
+ uint64_t data)
+{
+ DECLARE_DOMCTL;
+ uint32_t cmd;
+
+ switch ( type )
+ {
+ case XC_PSR_CAT_L3_CBM:
+ cmd = XEN_DOMCTL_PSR_CAT_OP_SET_L3_CBM;
+ break;
+ default:
+ errno = EINVAL;
+ return -1;
+ }
+
+ domctl.cmd = XEN_DOMCTL_psr_cat_op;
+ domctl.domain = (domid_t)domid;
+ domctl.u.psr_cat_op.cmd = cmd;
+ domctl.u.psr_cat_op.target = target;
+ domctl.u.psr_cat_op.data = data;
+
+ return do_domctl(xch, &domctl);
+}
+
+int xc_psr_cat_get_domain_data(xc_interface *xch, uint32_t domid,
+ xc_psr_cat_type type, uint32_t target,
+ uint64_t *data)
+{
+ int rc;
+ DECLARE_DOMCTL;
+ uint32_t cmd;
+
+ switch ( type )
+ {
+ case XC_PSR_CAT_L3_CBM:
+ cmd = XEN_DOMCTL_PSR_CAT_OP_GET_L3_CBM;
+ break;
+ default:
+ errno = EINVAL;
+ return -1;
+ }
+
+ domctl.cmd = XEN_DOMCTL_psr_cat_op;
+ domctl.domain = (domid_t)domid;
+ domctl.u.psr_cat_op.cmd = cmd;
+ domctl.u.psr_cat_op.target = target;
+
+ rc = do_domctl(xch, &domctl);
+
+ if ( !rc )
+ *data = domctl.u.psr_cat_op.data;
+
+ return rc;
+}
+
+int xc_psr_cat_get_l3_info(xc_interface *xch, uint32_t socket,
+ uint32_t *cos_max, uint32_t *cbm_len)
+{
+ int rc;
+ DECLARE_SYSCTL;
+
+ sysctl.cmd = XEN_SYSCTL_psr_cat_op;
+ sysctl.u.psr_cat_op.cmd = XEN_SYSCTL_PSR_CAT_get_l3_info;
+ sysctl.u.psr_cat_op.target = socket;
+
+ rc = xc_sysctl(xch, &sysctl);
+ if ( !rc )
+ {
+ *cos_max = sysctl.u.psr_cat_op.u.l3_info.cos_max;
+ *cbm_len = sysctl.u.psr_cat_op.u.l3_info.cbm_len;
+ }
+
+ return rc;
+}
/*
* Local variables:
diff --git a/tools/libxl/libxl.h b/tools/libxl/libxl.h
index 13e7a8c..5aba368 100644
--- a/tools/libxl/libxl.h
+++ b/tools/libxl/libxl.h
@@ -765,6 +765,13 @@ void libxl_mac_copy(libxl_ctx *ctx, libxl_mac *dst, libxl_mac *src);
* If this is defined, the Memory Bandwidth Monitoring feature is supported.
*/
#define LIBXL_HAVE_PSR_MBM 1
+
+/*
+ * LIBXL_HAVE_PSR_CAT
+ *
+ * If this is defined, the Cache Allocation Technology feature is supported.
+ */
+#define LIBXL_HAVE_PSR_CAT 1
#endif
/*
@@ -1585,6 +1592,34 @@ int libxl_psr_cmt_get_sample(libxl_ctx *ctx,
uint64_t *tsc_r);
#endif
+#ifdef LIBXL_HAVE_PSR_CAT
+/*
+ * Function to set a domain's cbm. It operates on a single or multiple
+ * target(s) defined in 'target_map'. The definition of 'target_map' is
+ * related to 'type':
+ * 'L3_CBM': 'target_map' specifies all the sockets to be operated on.
+ */
+int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
+ libxl_psr_cbm_type type, libxl_bitmap *target_map,
+ uint64_t cbm);
+/*
+ * Function to get a domain's cbm. It operates on a single 'target'.
+ * The definition of 'target' is related to 'type':
+ * 'L3_CBM': 'target' specifies which socket to be operated on.
+ */
+int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
+ libxl_psr_cbm_type type, uint32_t target,
+ uint64_t *cbm_r);
+
+/*
+ * On success, the function returns an array of elements in 'info',
+ * and the length in 'nr'.
+ */
+int libxl_psr_cat_get_l3_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
+ int *nr);
+void libxl_psr_cat_info_list_free(libxl_psr_cat_info *list, int nr);
+#endif
+
/* misc */
/* Each of these sets or clears the flag according to whether the
diff --git a/tools/libxl/libxl_psr.c b/tools/libxl/libxl_psr.c
index 3e1c792..313ec86 100644
--- a/tools/libxl/libxl_psr.c
+++ b/tools/libxl/libxl_psr.c
@@ -19,14 +19,37 @@
#define IA32_QM_CTR_ERROR_MASK (0x3ul << 62)
-static void libxl__psr_cmt_log_err_msg(libxl__gc *gc, int err)
+static void libxl__psr_log_err_msg(libxl__gc *gc, int err)
{
char *msg;
switch (err) {
case ENOSYS:
+ case EOPNOTSUPP:
msg = "unsupported operation";
break;
+ case ESRCH:
+ msg = "invalid domain ID";
+ break;
+ case EBADSLT:
+ msg = "socket is not supported";
+ break;
+ case EFAULT:
+ msg = "failed to exchange data with Xen";
+ break;
+ default:
+ msg = "unknown error";
+ break;
+ }
+
+ LOGE(ERROR, "%s", msg);
+}
+
+static void libxl__psr_cmt_log_err_msg(libxl__gc *gc, int err)
+{
+ char *msg;
+
+ switch (err) {
case ENODEV:
msg = "CMT is not supported in this system";
break;
@@ -39,15 +62,35 @@ static void libxl__psr_cmt_log_err_msg(libxl__gc *gc, int err)
case EUSERS:
msg = "no free RMID available";
break;
- case ESRCH:
- msg = "invalid domain ID";
+ default:
+ libxl__psr_log_err_msg(gc, err);
+ return;
+ }
+
+ LOGE(ERROR, "%s", msg);
+}
+
+static void libxl__psr_cat_log_err_msg(libxl__gc *gc, int err)
+{
+ char *msg;
+
+ switch (err) {
+ case ENODEV:
+ msg = "CAT is not supported in this system";
break;
- case EFAULT:
- msg = "failed to exchange data with Xen";
+ case ENOENT:
+ msg = "CAT is not enabled on the socket";
break;
- default:
- msg = "unknown error";
+ case EUSERS:
+ msg = "no free COS available";
break;
+ case EEXIST:
+ msg = "The same CBM is already set to this domain";
+ break;
+
+ default:
+ libxl__psr_log_err_msg(gc, err);
+ return;
}
LOGE(ERROR, "%s", msg);
@@ -247,6 +290,92 @@ out:
return rc;
}
+int libxl_psr_cat_set_cbm(libxl_ctx *ctx, uint32_t domid,
+ libxl_psr_cbm_type type, libxl_bitmap *target_map,
+ uint64_t cbm)
+{
+ GC_INIT(ctx);
+ int rc;
+ int socket, nr_sockets;
+
+ rc = libxl__count_physical_sockets(gc, &nr_sockets);
+ if (rc) {
+ LOGE(ERROR, "failed to get system socket count");
+ goto out;
+ }
+
+ libxl_for_each_set_bit(socket, *target_map) {
+ if (socket >= nr_sockets)
+ break;
+ if (xc_psr_cat_set_domain_data(ctx->xch, domid, type, socket, cbm)) {
+ libxl__psr_cat_log_err_msg(gc, errno);
+ rc = ERROR_FAIL;
+ }
+ }
+
+out:
+ GC_FREE;
+ return rc;
+}
+
+int libxl_psr_cat_get_cbm(libxl_ctx *ctx, uint32_t domid,
+ libxl_psr_cbm_type type, uint32_t target,
+ uint64_t *cbm_r)
+{
+ GC_INIT(ctx);
+ int rc = 0;
+
+ if (xc_psr_cat_get_domain_data(ctx->xch, domid, type, target, cbm_r)) {
+ libxl__psr_cat_log_err_msg(gc, errno);
+ rc = ERROR_FAIL;
+ }
+
+ GC_FREE;
+ return rc;
+}
+
+int libxl_psr_cat_get_l3_info(libxl_ctx *ctx, libxl_psr_cat_info **info,
+ int *nr)
+{
+ GC_INIT(ctx);
+ int rc;
+ int i, nr_sockets;
+ libxl_psr_cat_info *ptr;
+
+ rc = libxl__count_physical_sockets(gc, &nr_sockets);
+ if (rc) {
+ LOGE(ERROR, "failed to get system socket count");
+ goto out;
+ }
+
+ ptr = libxl__malloc(NOGC, nr_sockets * sizeof(libxl_psr_cat_info));
+
+ for (i = 0; i < nr_sockets; i++) {
+ if (xc_psr_cat_get_l3_info(ctx->xch, i, &ptr[i].cos_max,
+ &ptr[i].cbm_len)) {
+ libxl__psr_cat_log_err_msg(gc, errno);
+ rc = ERROR_FAIL;
+ free(ptr);
+ goto out;
+ }
+ }
+
+ *info = ptr;
+ *nr = nr_sockets;
+out:
+ GC_FREE;
+ return rc;
+}
+
+void libxl_psr_cat_info_list_free(libxl_psr_cat_info *list, int nr)
+{
+ int i;
+
+ for (i = 0; i < nr; i++)
+ libxl_psr_cat_info_dispose(&list[i]);
+ free(list);
+}
+
/*
* Local variables:
* mode: C
diff --git a/tools/libxl/libxl_types.idl b/tools/libxl/libxl_types.idl
index 23f27d4..cdf7578 100644
--- a/tools/libxl/libxl_types.idl
+++ b/tools/libxl/libxl_types.idl
@@ -729,3 +729,13 @@ libxl_psr_cmt_type = Enumeration("psr_cmt_type", [
(2, "TOTAL_MEM_COUNT"),
(3, "LOCAL_MEM_COUNT"),
])
+
+libxl_psr_cbm_type = Enumeration("psr_cbm_type", [
+ (0, "UNKNOWN"),
+ (1, "L3_CBM"),
+ ])
+
+libxl_psr_cat_info = Struct("psr_cat_info", [
+ ("cos_max", uint32),
+ ("cbm_len", uint32),
+ ])
diff --git a/tools/libxl/xl.h b/tools/libxl/xl.h
index 7b56449..bef32d7 100644
--- a/tools/libxl/xl.h
+++ b/tools/libxl/xl.h
@@ -118,6 +118,10 @@ int main_psr_cmt_attach(int argc, char **argv);
int main_psr_cmt_detach(int argc, char **argv);
int main_psr_cmt_show(int argc, char **argv);
#endif
+#ifdef LIBXL_HAVE_PSR_CAT
+int main_psr_cat_cbm_set(int argc, char **argv);
+int main_psr_cat_show(int argc, char **argv);
+#endif
void help(const char *command);
diff --git a/tools/libxl/xl_cmdimpl.c b/tools/libxl/xl_cmdimpl.c
index e76a154..78232f3 100644
--- a/tools/libxl/xl_cmdimpl.c
+++ b/tools/libxl/xl_cmdimpl.c
@@ -8276,17 +8276,6 @@ static int psr_cmt_show(libxl_psr_cmt_type type, uint32_t domid)
return 0;
}
-int main_psr_hwinfo(int argc, char **argv)
-{
- int opt;
-
- SWITCH_FOREACH_OPT(opt, "", NULL, "psr-hwinfo", 0) {
- /* No options */
- }
-
- return psr_cmt_hwinfo();
-}
-
int main_psr_cmt_attach(int argc, char **argv)
{
uint32_t domid;
@@ -8353,6 +8342,232 @@ int main_psr_cmt_show(int argc, char **argv)
}
#endif
+#ifdef LIBXL_HAVE_PSR_CAT
+static int psr_cat_hwinfo(void)
+{
+ int rc;
+ int socket, nr_sockets;
+ uint32_t l3_cache_size;
+ libxl_psr_cat_info *info;
+
+ printf("Cache Allocation Technology (CAT):\n");
+
+ rc = libxl_psr_cat_get_l3_info(ctx, &info, &nr_sockets);
+ if (rc) {
+ fprintf(stderr, "Failed to get cat info\n");
+ return rc;
+ }
+
+ for (socket = 0; socket < nr_sockets; socket++) {
+ rc = libxl_psr_cmt_get_l3_cache_size(ctx, socket, &l3_cache_size);
+ if (rc) {
+ fprintf(stderr, "Failed to get l3 cache size for socket:%d\n",
+ socket);
+ goto out;
+ }
+ printf("%-16s: %u\n", "Socket ID", socket);
+ printf("%-16s: %uKB\n", "L3 Cache", l3_cache_size);
+ printf("%-16s: %u\n", "Maximum COS", info->cos_max);
+ printf("%-16s: %u\n", "CBM length", info->cbm_len);
+ printf("%-16s: %#"PRIx64"\n", "Default CBM",
+ (1ul << info->cbm_len) - 1);
+ }
+
+out:
+ libxl_psr_cat_info_list_free(info, nr_sockets);
+ return rc;
+}
+
+static void psr_cat_print_one_domain_cbm(uint32_t domid, uint32_t socket)
+{
+ char *domain_name;
+ uint64_t cbm;
+
+ domain_name = libxl_domid_to_name(ctx, domid);
+ printf("%5d%25s", domid, domain_name);
+ free(domain_name);
+
+ if (!libxl_psr_cat_get_cbm(ctx, domid, LIBXL_PSR_CBM_TYPE_L3_CBM,
+ socket, &cbm))
+ printf("%#16"PRIx64, cbm);
+
+ printf("\n");
+}
+
+static int psr_cat_print_domain_cbm(uint32_t domid, uint32_t socket)
+{
+ int i, nr_domains;
+ libxl_dominfo *list;
+
+ if (domid != INVALID_DOMID) {
+ psr_cat_print_one_domain_cbm(domid, socket);
+ return 0;
+ }
+
+ if (!(list = libxl_list_domain(ctx, &nr_domains))) {
+ fprintf(stderr, "Failed to get domain list for cbm display\n");
+ return -1;
+ }
+
+ for (i = 0; i < nr_domains; i++)
+ psr_cat_print_one_domain_cbm(list[i].domid, socket);
+ libxl_dominfo_list_free(list, nr_domains);
+
+ return 0;
+}
+
+static int psr_cat_print_socket(uint32_t domid, uint32_t socket,
+ libxl_psr_cat_info *info)
+{
+ int rc;
+ uint32_t l3_cache_size;
+
+ rc = libxl_psr_cmt_get_l3_cache_size(ctx, socket, &l3_cache_size);
+ if (rc) {
+ fprintf(stderr, "Failed to get l3 cache size for socket:%d\n", socket);
+ return -1;
+ }
+
+ printf("%-16s: %u\n", "Socket ID", socket);
+ printf("%-16s: %uKB\n", "L3 Cache", l3_cache_size);
+ printf("%-16s: %#"PRIx64"\n", "Default CBM", (1ul << info->cbm_len) - 1);
+ printf("%5s%25s%16s\n", "ID", "NAME", "CBM");
+
+ return psr_cat_print_domain_cbm(domid, socket);
+}
+
+static int psr_cat_show(uint32_t domid)
+{
+ int socket, nr_sockets;
+ int rc;
+ libxl_psr_cat_info *info;
+
+ rc = libxl_psr_cat_get_l3_info(ctx, &info, &nr_sockets);
+ if (rc) {
+ fprintf(stderr, "Failed to get cat info\n");
+ return rc;
+ }
+
+ for (socket = 0; socket < nr_sockets; socket++) {
+ rc = psr_cat_print_socket(domid, socket, info + socket);
+ if (rc)
+ goto out;
+ }
+
+out:
+ libxl_psr_cat_info_list_free(info, nr_sockets);
+ return rc;
+}
+
+int main_psr_cat_cbm_set(int argc, char **argv)
+{
+ uint32_t domid;
+ libxl_psr_cbm_type type = LIBXL_PSR_CBM_TYPE_L3_CBM;
+ uint64_t cbm;
+ int ret, opt = 0;
+ libxl_bitmap target_map;
+ char *value;
+ libxl_string_list socket_list;
+ unsigned long start, end;
+ int i, j, len;
+
+ static struct option opts[] = {
+ {"socket", 0, 0, 's'},
+ COMMON_LONG_OPTS,
+ {0, 0, 0, 0}
+ };
+
+ libxl_socket_bitmap_alloc(ctx, &target_map, 0);
+ libxl_bitmap_set_none(&target_map);
+
+ SWITCH_FOREACH_OPT(opt, "s", opts, "psr-cat-cbm-set", 1) {
+ case 's':
+ trim(isspace, optarg, &value);
+ split_string_into_string_list(value, ",", &socket_list);
+ len = libxl_string_list_length(&socket_list);
+ for (i = 0; i < len; i++) {
+ parse_range(socket_list[i], &start, &end);
+ for (j = start; j < end; j++)
+ libxl_bitmap_set(&target_map, j);
+ }
+
+ libxl_string_list_dispose(&socket_list);
+ free(value);
+ break;
+ }
+
+ if (libxl_bitmap_is_empty(&target_map))
+ libxl_bitmap_set_any(&target_map);
+
+ domid = find_domain(argv[optind]);
+ cbm = strtoll(argv[optind + 1], NULL , 0);
+
+ ret = libxl_psr_cat_set_cbm(ctx, domid, type, &target_map, cbm);
+
+ libxl_bitmap_dispose(&target_map);
+ return ret;
+}
+
+int main_psr_cat_show(int argc, char **argv)
+{
+ int opt;
+ uint32_t domid;
+
+ SWITCH_FOREACH_OPT(opt, "", NULL, "psr-cat-show", 0) {
+ /* No options */
+ }
+
+ if (optind >= argc)
+ domid = INVALID_DOMID;
+ else if (optind == argc - 1)
+ domid = find_domain(argv[optind]);
+ else {
+ help("psr-cat-show");
+ return 2;
+ }
+
+ return psr_cat_show(domid);
+}
+
+int main_psr_hwinfo(int argc, char **argv)
+{
+ int opt, ret;
+ int cmt = 0, cat = 0;
+ static struct option opts[] = {
+ {"cmt", 0, 0, 'm'},
+ {"cat", 0, 0, 'a'},
+ COMMON_LONG_OPTS,
+ {0, 0, 0, 0}
+ };
+
+ SWITCH_FOREACH_OPT(opt, "ma", opts, "psr-hwinfo", 0) {
+ case 'm':
+ cmt = 1;
+ break;
+ case 'a':
+ cat = 1;
+ break;
+ }
+
+ if (!(cmt | cat)) {
+ cmt = 1;
+ cat = 1;
+ }
+
+ if (cmt)
+ ret = psr_cmt_hwinfo();
+
+ if (ret)
+ return ret;
+
+ if (cat)
+ ret = psr_cat_hwinfo();
+
+ return ret;
+}
+
+#endif
+
/*
* Local variables:
* mode: C
diff --git a/tools/libxl/xl_cmdtable.c b/tools/libxl/xl_cmdtable.c
index 77a37c5..51a56fb 100644
--- a/tools/libxl/xl_cmdtable.c
+++ b/tools/libxl/xl_cmdtable.c
@@ -528,7 +528,9 @@ struct cmd_spec cmd_table[] = {
{ "psr-hwinfo",
&main_psr_hwinfo, 0, 1,
"Show hardware information for Platform Shared Resource",
- "",
+ "[options]",
+ "-m, --cmt Show Cache Monitoring Technology (CMT) hardware info\n"
+ "-a, --cat Show Cache Allocation Technology (CAT) hardware info\n"
},
{ "psr-cmt-attach",
&main_psr_cmt_attach, 0, 1,
@@ -550,6 +552,20 @@ struct cmd_spec cmd_table[] = {
"\"local-mem-bandwidth\": Show local memory bandwidth(KB/s)\n",
},
#endif
+#ifdef LIBXL_HAVE_PSR_CAT
+ { "psr-cat-cbm-set",
+ &main_psr_cat_cbm_set, 0, 1,
+ "Set cache capacity bitmasks(CBM) for a domain",
+ "[options] <Domain> <CBM>",
+ "-s <socket> Specify the socket to process, otherwise all sockets are processed\n"
+ },
+ { "psr-cat-show",
+ &main_psr_cat_show, 0, 1,
+ "Show Cache Allocation Technology information",
+ "<Domain>",
+ },
+
+#endif
};
int cmdtable_len = sizeof(cmd_table)/sizeof(struct cmd_spec);
--
1.9.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH v10 13/13] docs: add xl-psr.markdown
2015-06-26 8:43 [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs Chao Peng
` (11 preceding siblings ...)
2015-06-26 8:43 ` [PATCH v10 12/13] tools: add tools support for Intel CAT Chao Peng
@ 2015-06-26 8:43 ` Chao Peng
2015-07-07 14:46 ` [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs Ian Campbell
13 siblings, 0 replies; 23+ messages in thread
From: Chao Peng @ 2015-06-26 8:43 UTC (permalink / raw)
To: xen-devel
Cc: keir, Ian.Campbell, stefano.stabellini, andrew.cooper3,
dario.faggioli, Ian.Jackson, will.auld, JBeulich, wei.liu2,
dgdegra
Add document to introduce basic concepts and terms in PSR family
technologies and the xl interfaces.
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
---
Changes in v7:
* Correct 'xl psr-hwinfo'.
Changes in v6:
* Address comments from Ian.
Changes in v5:
* Address comments from Andrew/Ian.
---
docs/man/xl.pod.1 | 7 ++-
docs/misc/xl-psr.markdown | 133 ++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 139 insertions(+), 1 deletion(-)
create mode 100644 docs/misc/xl-psr.markdown
diff --git a/docs/man/xl.pod.1 b/docs/man/xl.pod.1
index d77ce77..45600e8 100644
--- a/docs/man/xl.pod.1
+++ b/docs/man/xl.pod.1
@@ -1490,6 +1490,9 @@ Intel Haswell and later server platforms offer shared resource monitoring
and control technologies. The availability of these technologies and the
hardware capabilities can be shown with B<psr-hwinfo>.
+See L<http://xenbits.xen.org/docs/unstable/misc/xl-psr.html> for more
+information.
+
=over 4
=item B<psr-hwinfo> [I<OPTIONS>]
@@ -1573,7 +1576,8 @@ on VM basis. To enforce cache on a specific domain, just set capacity bitmasks
=item B<psr-cat-cbm-set> [I<OPTIONS>] I<domain-id> I<cbm>
-Set cache capacity bitmasks(CBM) for a domain.
+Set cache capacity bitmasks(CBM) for a domain. For how to specify I<cbm>
+please refer to L<http://xenbits.xen.org/docs/unstable/misc/xl-psr.html>.
B<OPTIONS>
@@ -1614,6 +1618,7 @@ And the following documents on the xen.org website:
L<http://xenbits.xen.org/docs/unstable/misc/xl-network-configuration.html>
L<http://xenbits.xen.org/docs/unstable/misc/xl-disk-configuration.txt>
L<http://xenbits.xen.org/docs/unstable/misc/xsm-flask.txt>
+L<http://xenbits.xen.org/docs/unstable/misc/xl-psr.html>
For systems that don't automatically bring CPU online:
diff --git a/docs/misc/xl-psr.markdown b/docs/misc/xl-psr.markdown
new file mode 100644
index 0000000..3545912
--- /dev/null
+++ b/docs/misc/xl-psr.markdown
@@ -0,0 +1,133 @@
+# Intel Platform Shared Resource Monitoring/Control in xl
+
+This document introduces Intel Platform Shared Resource Monitoring/Control
+technologies, their basic concepts and the xl interfaces.
+
+## Cache Monitoring Technology (CMT)
+
+Cache Monitoring Technology (CMT) is a new feature available on Intel Haswell
+and later server platforms that allows an OS or Hypervisor/VMM to determine
+the usage of cache (currently only L3 cache supported) by applications running
+on the platform. A Resource Monitoring ID (RMID) is the abstraction of the
+application(s) that will be monitored for its cache usage. The CMT hardware
+tracks cache utilization of memory accesses according to the RMID and reports
+monitored data via a counter register.
+
+For more detailed information please refer to Intel SDM chapter
+"17.14 - Platform Shared Resource Monitoring: Cache Monitoring Technology".
+
+In Xen's implementation, each domain in the system can be assigned a RMID
+independently, while RMID=0 is reserved for monitoring domains that don't
+have CMT service attached. RMID is opaque for xl/libxl and is only used in
+hypervisor.
+
+### xl interfaces
+
+A domain is assigned a RMID implicitly by attaching it to CMT service:
+
+`xl psr-cmt-attach <domid>`
+
+After that, cache usage for the domain can be shown by:
+
+`xl psr-cmt-show cache-occupancy <domid>`
+
+Once monitoring is not needed any more, the domain can be detached from the
+CMT service by:
+
+`xl psr-cmt-detach <domid>`
+
+An attach may fail because of no free RMID available. In such case unused
+RMID(s) can be freed by detaching corresponding domains from CMT service.
+
+Maximum RMID and supported monitor types in the system can be obtained by:
+
+`xl psr-hwinfo --cmt`
+
+## Memory Bandwidth Monitoring (MBM)
+
+Memory Bandwidth Monitoring(MBM) is a new hardware feature available on Intel
+Broadwell and later server platforms which builds on the CMT infrastructure to
+allow monitoring of system memory bandwidth. It introduces two new monitoring
+event type to monitor system total/local memory bandwidth. The same RMID can
+be used to monitor both cache usage and memory bandwidth at the same time.
+
+For more detailed information please refer to Intel SDM chapter
+"17.14 - Platform Shared Resource Monitoring: Cache Monitoring Technology".
+
+In Xen's implementation, MBM shares the same set of underlying monitoring
+service with CMT and can be used to monitor memory bandwidth on a per domain
+basis.
+
+The xl interfaces are the same with that of CMT. The difference is the
+monitor type is corresponding memory monitoring type (local-mem-bandwidth/
+total-mem-bandwidth instead of cache-occupancy). E.g. after a `xl psr-cmt-attach`:
+
+`xl psr-cmt-show local-mem-bandwidth <domid>`
+
+`xl psr-cmt-show total-mem-bandwidth <domid>`
+
+## Cache Allocation Technology (CAT)
+
+Cache Allocation Technology (CAT) is a new feature available on Intel
+Broadwell and later server platforms that allows an OS or Hypervisor/VMM to
+partition cache allocation (i.e. L3 cache) based on application priority or
+Class of Service (COS). Each COS is configured using capacity bitmasks (CBM)
+which represent cache capacity and indicate the degree of overlap and
+isolation between classes. System cache resource is divided into numbers of
+minimum portions which is then made up into subset for cache partition. Each
+portion corresponds to a bit in CBM and the set bit represents the
+corresponding cache portion is available.
+
+For example, assuming a system with 8 portions and 3 domains:
+
+ * A CBM of 0xff for every domain means each domain can access the whole cache.
+ This is the default.
+
+ * Giving one domain a CBM of 0x0f and the other two domain's 0xf0 means that
+ the first domain gets exclusive access to half of the cache (half of the
+ portions) and the other two will share the other half.
+
+ * Giving one domain a CBM of 0x0f, one 0x30 and the last 0xc0 would give the
+ first domain exclusive access to half the cache, and the other two exclusive
+ access to one quarter each.
+
+For more detailed information please refer to Intel SDM chapter
+"17.15 - Platform Shared Resource Control: Cache Allocation Technology".
+
+In Xen's implementation, CBM can be configured with libxl/xl interfaces but
+COS is maintained in hypervisor only. The cache partition granularity is per
+domain, each domain has COS=0 assigned by default, the corresponding CBM is
+all-ones, which means all the cache resource can be used by default.
+
+### xl interfaces
+
+System CAT information such as maximum COS and CBM length can be obtained by:
+
+`xl psr-hwinfo --cat`
+
+The simplest way to change a domain's CBM from its default is running:
+
+`xl psr-cat-cbm-set [OPTIONS] <domid> <cbm>`
+
+where cbm is a number to represent the corresponding cache subset can be used.
+A cbm is valid only when:
+
+ * Set bits only exist in the range of [0, cbm_len), where cbm_len can be
+ obtained with `xl psr-hwinfo --cat`.
+ * All the set bits are contiguous.
+
+In a multi-socket system, the same cbm will be set on each socket by default.
+Per socket cbm can be specified with the `--socket SOCKET` option.
+
+Setting the CBM may not be successful if insufficient COS is available. In
+such case unused COS(es) may be freed by setting CBM of all related domains to
+its default value(all-ones).
+
+Per domain CBM settings can be shown by:
+
+`xl psr-cat-show`
+
+## Reference
+
+[1] Intel SDM
+(http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html).
--
1.9.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs
2015-06-26 8:43 [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs Chao Peng
` (12 preceding siblings ...)
2015-06-26 8:43 ` [PATCH v10 13/13] docs: add xl-psr.markdown Chao Peng
@ 2015-07-07 14:46 ` Ian Campbell
2015-07-08 9:40 ` Chao Peng
13 siblings, 1 reply; 23+ messages in thread
From: Ian Campbell @ 2015-07-07 14:46 UTC (permalink / raw)
To: Chao Peng
Cc: keir, stefano.stabellini, andrew.cooper3, dario.faggioli,
Ian.Jackson, xen-devel, will.auld, JBeulich, wei.liu2, dgdegra
On Fri, 2015-06-26 at 16:43 +0800, Chao Peng wrote:
> Chao Peng (13):
> x86: add socket_cpumask
> x86: detect and initialize Intel CAT feature
> x86: maintain COS to CBM mapping for each socket
> x86: add COS information for each domain
> x86: expose CBM length and COS number information
> x86: dynamically get/set CBM for a domain
> x86: add scheduling support for Intel CAT
> xsm: add CAT related xsm policies
Jan applied to here.
So I was going to apply these 5:
> tools/libxl: minor name changes for CMT commands
> tools/libxl: add command to show PSR hardware info
> tools/libxl: introduce some socket helpers
> tools: add tools support for Intel CAT
> docs: add xl-psr.markdown
But, on i686 I see:
xl_cmdimpl.c: In function ‘psr_cat_hwinfo’:
xl_cmdimpl.c:8390:16: error: format ‘%llx’ expects argument of type ‘long long unsigned int’, but argument 3 has type ‘long unsigned int’ [-Werror=format=]
(1ul << info->cbm_len) - 1);
^
xl_cmdimpl.c: In function ‘psr_cat_print_socket’:
xl_cmdimpl.c:8450:5: error: format ‘%llx’ expects argument of type ‘long long unsigned int’, but argument 3 has type ‘long unsigned int’ [-Werror=format=]
printf("%-16s: %#"PRIx64"\n", "Default CBM", (1ul << info->cbm_len) - 1);
^
cc1: all warnings being treated as errors
It seems there is some mismatch between your types and the printf
formats used.
The appropriate format specifier for an unsigned long (which you have
from the "ul" in the constant) is %#lx and not "%#"PRIxXX which is
associated with uintXX_t types.
If you need a 64 bit type then you might have meant instead to use "ull"
in which case you want "%#llx" as the format specifier.
If you really want/need an exactly 64 bit type then you'll have to do
some nasty casting, something like "((uint64_t)1) << info->cbm_len) - 1"
or something, that's pretty ugly though. If you have to go this route
then please test both builds, in case I've gotten my ()'s wrong.
Ian.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
http://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs
2015-07-07 14:46 ` [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs Ian Campbell
@ 2015-07-08 9:40 ` Chao Peng
2015-07-08 10:02 ` Wei Liu
0 siblings, 1 reply; 23+ messages in thread
From: Chao Peng @ 2015-07-08 9:40 UTC (permalink / raw)
To: Ian Campbell
Cc: keir, stefano.stabellini, andrew.cooper3, dario.faggioli,
Ian.Jackson, xen-devel, will.auld, JBeulich, wei.liu2, dgdegra
On Tue, Jul 07, 2015 at 03:46:21PM +0100, Ian Campbell wrote:
> On Fri, 2015-06-26 at 16:43 +0800, Chao Peng wrote:
> > Chao Peng (13):
> > x86: add socket_cpumask
> > x86: detect and initialize Intel CAT feature
> > x86: maintain COS to CBM mapping for each socket
> > x86: add COS information for each domain
> > x86: expose CBM length and COS number information
> > x86: dynamically get/set CBM for a domain
> > x86: add scheduling support for Intel CAT
> > xsm: add CAT related xsm policies
>
> Jan applied to here.
>
> So I was going to apply these 5:
>
> > tools/libxl: minor name changes for CMT commands
> > tools/libxl: add command to show PSR hardware info
> > tools/libxl: introduce some socket helpers
> > tools: add tools support for Intel CAT
> > docs: add xl-psr.markdown
>
> But, on i686 I see:
>
> xl_cmdimpl.c: In function ‘psr_cat_hwinfo’:
> xl_cmdimpl.c:8390:16: error: format ‘%llx’ expects argument of type ‘long long unsigned int’, but argument 3 has type ‘long unsigned int’ [-Werror=format=]
> (1ul << info->cbm_len) - 1);
> ^
> xl_cmdimpl.c: In function ‘psr_cat_print_socket’:
> xl_cmdimpl.c:8450:5: error: format ‘%llx’ expects argument of type ‘long long unsigned int’, but argument 3 has type ‘long unsigned int’ [-Werror=format=]
> printf("%-16s: %#"PRIx64"\n", "Default CBM", (1ul << info->cbm_len) - 1);
> ^
> cc1: all warnings being treated as errors
>
> It seems there is some mismatch between your types and the printf
> formats used.
>
> The appropriate format specifier for an unsigned long (which you have
> from the "ul" in the constant) is %#lx and not "%#"PRIxXX which is
> associated with uintXX_t types.
>
> If you need a 64 bit type then you might have meant instead to use "ull"
> in which case you want "%#llx" as the format specifier.
This is what I need. Thanks for suggestion.
Chao
>
> If you really want/need an exactly 64 bit type then you'll have to do
> some nasty casting, something like "((uint64_t)1) << info->cbm_len) - 1"
> or something, that's pretty ugly though. If you have to go this route
> then please test both builds, in case I've gotten my ()'s wrong.
>
> Ian.
>
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xen.org
> http://lists.xen.org/xen-devel
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
http://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs
2015-07-08 9:40 ` Chao Peng
@ 2015-07-08 10:02 ` Wei Liu
2015-07-09 1:29 ` Chao Peng
0 siblings, 1 reply; 23+ messages in thread
From: Wei Liu @ 2015-07-08 10:02 UTC (permalink / raw)
To: Chao Peng
Cc: keir, Ian Campbell, stefano.stabellini, andrew.cooper3,
dario.faggioli, Ian.Jackson, xen-devel, will.auld, JBeulich,
wei.liu2, dgdegra
On Wed, Jul 08, 2015 at 05:40:47PM +0800, Chao Peng wrote:
> On Tue, Jul 07, 2015 at 03:46:21PM +0100, Ian Campbell wrote:
> > On Fri, 2015-06-26 at 16:43 +0800, Chao Peng wrote:
> > > Chao Peng (13):
> > > x86: add socket_cpumask
> > > x86: detect and initialize Intel CAT feature
> > > x86: maintain COS to CBM mapping for each socket
> > > x86: add COS information for each domain
> > > x86: expose CBM length and COS number information
> > > x86: dynamically get/set CBM for a domain
> > > x86: add scheduling support for Intel CAT
> > > xsm: add CAT related xsm policies
> >
> > Jan applied to here.
> >
> > So I was going to apply these 5:
> >
> > > tools/libxl: minor name changes for CMT commands
> > > tools/libxl: add command to show PSR hardware info
> > > tools/libxl: introduce some socket helpers
> > > tools: add tools support for Intel CAT
> > > docs: add xl-psr.markdown
> >
> > But, on i686 I see:
> >
> > xl_cmdimpl.c: In function ‘psr_cat_hwinfo’:
> > xl_cmdimpl.c:8390:16: error: format ‘%llx’ expects argument of type ‘long long unsigned int’, but argument 3 has type ‘long unsigned int’ [-Werror=format=]
> > (1ul << info->cbm_len) - 1);
> > ^
> > xl_cmdimpl.c: In function ‘psr_cat_print_socket’:
> > xl_cmdimpl.c:8450:5: error: format ‘%llx’ expects argument of type ‘long long unsigned int’, but argument 3 has type ‘long unsigned int’ [-Werror=format=]
> > printf("%-16s: %#"PRIx64"\n", "Default CBM", (1ul << info->cbm_len) - 1);
> > ^
> > cc1: all warnings being treated as errors
> >
> > It seems there is some mismatch between your types and the printf
> > formats used.
> >
> > The appropriate format specifier for an unsigned long (which you have
> > from the "ul" in the constant) is %#lx and not "%#"PRIxXX which is
> > associated with uintXX_t types.
> >
> > If you need a 64 bit type then you might have meant instead to use "ull"
> > in which case you want "%#llx" as the format specifier.
>
> This is what I need. Thanks for suggestion.
>
Chao, 4.6 freeze is on Friday. Can you fix that minor bug and
repost your series within two days?
Wei.
> Chao
> >
> > If you really want/need an exactly 64 bit type then you'll have to do
> > some nasty casting, something like "((uint64_t)1) << info->cbm_len) - 1"
> > or something, that's pretty ugly though. If you have to go this route
> > then please test both builds, in case I've gotten my ()'s wrong.
> >
> > Ian.
> >
> >
> > _______________________________________________
> > Xen-devel mailing list
> > Xen-devel@lists.xen.org
> > http://lists.xen.org/xen-devel
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
http://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v10 00/13] enable Cache Allocation Technology (CAT) for VMs
2015-07-08 10:02 ` Wei Liu
@ 2015-07-09 1:29 ` Chao Peng
0 siblings, 0 replies; 23+ messages in thread
From: Chao Peng @ 2015-07-09 1:29 UTC (permalink / raw)
To: Wei Liu
Cc: keir, Ian Campbell, stefano.stabellini, andrew.cooper3,
dario.faggioli, Ian.Jackson, xen-devel, will.auld, JBeulich,
dgdegra
On Wed, Jul 08, 2015 at 11:02:10AM +0100, Wei Liu wrote:
>
> Chao, 4.6 freeze is on Friday. Can you fix that minor bug and
> repost your series within two days?
>
Sure, I will post another version later today.
Thanks,
Chao
^ permalink raw reply [flat|nested] 23+ messages in thread