* [PATCH 0/2] Fix min dbuf, 90/270 wm calcs
@ 2015-06-26 13:53 Chandra Konduru
2015-06-26 13:53 ` [PATCH 1/2] drm/i915: Allocate min dbuf blocks per bspec Chandra Konduru
2015-06-26 13:53 ` [PATCH 2/2] drm/i915: In DBUF/WM calcs for 90/270, swap w & h Chandra Konduru
0 siblings, 2 replies; 7+ messages in thread
From: Chandra Konduru @ 2015-06-26 13:53 UTC (permalink / raw)
To: intel-gfx
Resending with correct patches.
This patch series allocates minimum dbuf blocks required for tile-y, tile-yf
buffers correctly as per bspec. Also in WM calculations, for 90/270,
swaps source width and height.
Chandra Konduru (2):
drm/i915: Allocate min dbuf blocks per bspec
drm/i915: In DBUF/WM calcs for 90/270, swap w & h
drivers/gpu/drm/i915/intel_pm.c | 71 +++++++++++++++++++++++++++++++++++----
1 file changed, 65 insertions(+), 6 deletions(-)
--
1.7.9.5
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^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] drm/i915: Allocate min dbuf blocks per bspec
2015-06-26 13:53 [PATCH 0/2] Fix min dbuf, 90/270 wm calcs Chandra Konduru
@ 2015-06-26 13:53 ` Chandra Konduru
2015-06-26 13:53 ` [PATCH 2/2] drm/i915: In DBUF/WM calcs for 90/270, swap w & h Chandra Konduru
1 sibling, 0 replies; 7+ messages in thread
From: Chandra Konduru @ 2015-06-26 13:53 UTC (permalink / raw)
To: intel-gfx
Properly allocate min blocks per hw requirements.
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 39 +++++++++++++++++++++++++++++++++++++--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 32ff034..ea3e435 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2679,6 +2679,41 @@ skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
return total_data_rate;
}
+static uint16_t
+skl_dbuf_min_alloc(const struct intel_plane_wm_parameters *p, int y_plane)
+{
+ uint16_t min_alloc;
+
+ /* For packed formats, no y-plane, return 0 */
+ if (y_plane && !p->y_bytes_per_pixel)
+ return 0;
+
+
+ if (p->tiling == I915_FORMAT_MOD_Y_TILED ||
+ p->tiling == I915_FORMAT_MOD_Yf_TILED) {
+ uint32_t min_scanlines = 8;
+ uint8_t bytes_per_pixel =
+ y_plane ? p->y_bytes_per_pixel : p->bytes_per_pixel;
+
+ switch (bytes_per_pixel) {
+ case 1:
+ min_scanlines = 32;
+ break;
+ case 2:
+ min_scanlines = 16;
+ break;
+ case 8:
+ WARN(1, "Unsupported pixel depth for rotation");
+ }
+ min_alloc = DIV_ROUND_UP((4 * p->horiz_pixels/(y_plane ? 1 : 2) *
+ bytes_per_pixel), 512) * min_scanlines/4 + 3;
+ } else {
+ min_alloc = 8;
+ }
+
+ return min_alloc;
+}
+
static void
skl_allocate_pipe_ddb(struct drm_crtc *crtc,
const struct intel_wm_config *config,
@@ -2719,9 +2754,9 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
if (!p->enabled)
continue;
- minimum[plane] = 8;
+ minimum[plane] = skl_dbuf_min_alloc(p, 0); /* uv-plane/packed */
alloc_size -= minimum[plane];
- y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
+ y_minimum[plane] = skl_dbuf_min_alloc(p, 1); /* y-plane */
alloc_size -= y_minimum[plane];
}
--
1.7.9.5
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] drm/i915: In DBUF/WM calcs for 90/270, swap w & h
2015-06-26 13:53 [PATCH 0/2] Fix min dbuf, 90/270 wm calcs Chandra Konduru
2015-06-26 13:53 ` [PATCH 1/2] drm/i915: Allocate min dbuf blocks per bspec Chandra Konduru
@ 2015-06-26 13:53 ` Chandra Konduru
2015-06-26 17:31 ` Daniel Vetter
2015-06-28 15:23 ` shuang.he
1 sibling, 2 replies; 7+ messages in thread
From: Chandra Konduru @ 2015-06-26 13:53 UTC (permalink / raw)
To: intel-gfx
This patch swaps src width and height for dbuf/wm calculations
when rotation is 90/270 as per hw requirements.
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 32 ++++++++++++++++++++++++++++----
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ea3e435..767313b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2913,6 +2913,8 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
enum pipe pipe = intel_crtc->pipe;
struct drm_plane *plane;
struct drm_framebuffer *fb;
+ struct intel_plane_state *plane_state;
+ int src_w, src_h;
int i = 1; /* Index for sprite planes start */
p->active = intel_crtc->active;
@@ -2921,6 +2923,7 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
fb = crtc->primary->state->fb;
+ plane_state = to_intel_plane_state(crtc->primary->state);
/* For planar: Bpp is for uv plane, y_Bpp is for y plane */
if (fb) {
p->plane[0].enabled = true;
@@ -2935,8 +2938,22 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
p->plane[0].y_bytes_per_pixel = 0;
p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
}
- p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
- p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
+
+ if (drm_rect_width(&plane_state->src)) {
+ src_w = drm_rect_width(&plane_state->src) >> 16;
+ src_h = drm_rect_height(&plane_state->src) >> 16;
+ } else {
+ src_w = intel_crtc->config->pipe_src_w;
+ src_h = intel_crtc->config->pipe_src_h;
+ }
+
+ if (intel_rotation_90_or_270(crtc->primary->state->rotation)) {
+ p->plane[0].horiz_pixels = src_h;
+ p->plane[0].vert_pixels = src_w;
+ } else {
+ p->plane[0].horiz_pixels = src_w;
+ p->plane[0].vert_pixels = src_h;
+ }
p->plane[0].rotation = crtc->primary->state->rotation;
fb = crtc->cursor->state->fb;
@@ -3468,8 +3485,15 @@ skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
intel_plane->wm.enabled = enabled;
intel_plane->wm.scaled = scaled;
- intel_plane->wm.horiz_pixels = sprite_width;
- intel_plane->wm.vert_pixels = sprite_height;
+
+ if (intel_rotation_90_or_270(plane->state->rotation)) {
+ intel_plane->wm.horiz_pixels = sprite_height;
+ intel_plane->wm.vert_pixels = sprite_width;
+ } else {
+ intel_plane->wm.horiz_pixels = sprite_width;
+ intel_plane->wm.vert_pixels = sprite_height;
+ }
+
intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
/* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
--
1.7.9.5
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/i915: In DBUF/WM calcs for 90/270, swap w & h
2015-06-26 13:53 ` [PATCH 2/2] drm/i915: In DBUF/WM calcs for 90/270, swap w & h Chandra Konduru
@ 2015-06-26 17:31 ` Daniel Vetter
2015-06-30 3:42 ` Konduru, Chandra
2015-06-28 15:23 ` shuang.he
1 sibling, 1 reply; 7+ messages in thread
From: Daniel Vetter @ 2015-06-26 17:31 UTC (permalink / raw)
To: Chandra Konduru; +Cc: intel-gfx
On Fri, Jun 26, 2015 at 06:53:49AM -0700, Chandra Konduru wrote:
> This patch swaps src width and height for dbuf/wm calculations
> when rotation is 90/270 as per hw requirements.
>
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Do we have an igt which provokes underruns and hence can test this
automatically? Very tall/narrow buffers should do it I think.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_pm.c | 32 ++++++++++++++++++++++++++++----
> 1 file changed, 28 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ea3e435..767313b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2913,6 +2913,8 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
> enum pipe pipe = intel_crtc->pipe;
> struct drm_plane *plane;
> struct drm_framebuffer *fb;
> + struct intel_plane_state *plane_state;
> + int src_w, src_h;
> int i = 1; /* Index for sprite planes start */
>
> p->active = intel_crtc->active;
> @@ -2921,6 +2923,7 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
> p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
>
> fb = crtc->primary->state->fb;
> + plane_state = to_intel_plane_state(crtc->primary->state);
> /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
> if (fb) {
> p->plane[0].enabled = true;
> @@ -2935,8 +2938,22 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
> p->plane[0].y_bytes_per_pixel = 0;
> p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
> }
> - p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
> - p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
> +
> + if (drm_rect_width(&plane_state->src)) {
> + src_w = drm_rect_width(&plane_state->src) >> 16;
> + src_h = drm_rect_height(&plane_state->src) >> 16;
> + } else {
> + src_w = intel_crtc->config->pipe_src_w;
> + src_h = intel_crtc->config->pipe_src_h;
> + }
> +
> + if (intel_rotation_90_or_270(crtc->primary->state->rotation)) {
> + p->plane[0].horiz_pixels = src_h;
> + p->plane[0].vert_pixels = src_w;
> + } else {
> + p->plane[0].horiz_pixels = src_w;
> + p->plane[0].vert_pixels = src_h;
> + }
> p->plane[0].rotation = crtc->primary->state->rotation;
>
> fb = crtc->cursor->state->fb;
> @@ -3468,8 +3485,15 @@ skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
>
> intel_plane->wm.enabled = enabled;
> intel_plane->wm.scaled = scaled;
> - intel_plane->wm.horiz_pixels = sprite_width;
> - intel_plane->wm.vert_pixels = sprite_height;
> +
> + if (intel_rotation_90_or_270(plane->state->rotation)) {
> + intel_plane->wm.horiz_pixels = sprite_height;
> + intel_plane->wm.vert_pixels = sprite_width;
> + } else {
> + intel_plane->wm.horiz_pixels = sprite_width;
> + intel_plane->wm.vert_pixels = sprite_height;
> + }
> +
> intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
>
> /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
> --
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/i915: In DBUF/WM calcs for 90/270, swap w & h
2015-06-26 13:53 ` [PATCH 2/2] drm/i915: In DBUF/WM calcs for 90/270, swap w & h Chandra Konduru
2015-06-26 17:31 ` Daniel Vetter
@ 2015-06-28 15:23 ` shuang.he
1 sibling, 0 replies; 7+ messages in thread
From: shuang.he @ 2015-06-28 15:23 UTC (permalink / raw)
To: shuang.he, lei.a.liu, intel-gfx, chandra.konduru
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6564
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
ILK 303/303 303/303
SNB 312/312 312/312
IVB 343/343 343/343
BYT 284/284 284/284
HSW 380/380 380/380
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
Note: You need to pay more attention to line start with '*'
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/i915: In DBUF/WM calcs for 90/270, swap w & h
2015-06-26 17:31 ` Daniel Vetter
@ 2015-06-30 3:42 ` Konduru, Chandra
0 siblings, 0 replies; 7+ messages in thread
From: Konduru, Chandra @ 2015-06-30 3:42 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
> This patch swaps src width and height for dbuf/wm calculations
> when rotation is 90/270 as per hw requirements.
>
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Do we have an igt which provokes underruns and hence can test this
automatically? Very tall/narrow buffers should do it I think.
-Daniel
Yes. Right now kms_rotation_crc is the case we have, but I'm also
triggering something via kms_nv12 too.
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 0/2] Fix min dbuf, 90/270 wm calcs
@ 2015-06-26 13:51 Chandra Konduru
0 siblings, 0 replies; 7+ messages in thread
From: Chandra Konduru @ 2015-06-26 13:51 UTC (permalink / raw)
To: intel-gfx
This patch series allocates minimum dbuf blocks required for tile-y, tile-yf
buffers correctly as per bspec. Also in WM calculations, for 90/270,
swaps source width and height.
Chandra Konduru (2):
drm/i915: Allocate min dbuf blocks per bspec
drm/i915: In DBUF/WM calcs for 90/270, swap w & h
drivers/gpu/drm/i915/intel_pm.c | 71 +++++++++++++++++++++++++++++++++++----
1 file changed, 65 insertions(+), 6 deletions(-)
--
1.7.9.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2015-06-30 3:42 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2015-06-26 13:53 [PATCH 0/2] Fix min dbuf, 90/270 wm calcs Chandra Konduru
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2015-06-26 13:53 ` [PATCH 2/2] drm/i915: In DBUF/WM calcs for 90/270, swap w & h Chandra Konduru
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2015-06-30 3:42 ` Konduru, Chandra
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