* [U-Boot] [PATCH v2 0/4] This series implements fastboot on the "bcm28155_ap" boards.
@ 2015-07-06 19:49 Steve Rae
2015-07-06 19:49 ` [U-Boot] [PATCH v2 1/4] g_dnl: add missing declaration Steve Rae
` (3 more replies)
0 siblings, 4 replies; 14+ messages in thread
From: Steve Rae @ 2015-07-06 19:49 UTC (permalink / raw)
To: u-boot
The OTG hardware is a DWC2 controller and this series uses the
existing gadget driver ("s3c_udc_otg.c").
Changes in v2:
- rebased against u-boot-dfu
JD (Jiandong) Zheng and Steve Rae (2):
usb: gadget: bcm_udc_otg files
implement Fastboot via USB OTG on bcm28155_ap boards
Steve Rae (2):
g_dnl: add missing declaration
usb: s3c-otg: support 8-bit interface
arch/arm/include/asm/arch-bcm281xx/sysmap.h | 7 ++++
board/broadcom/bcm28155_ap/bcm28155_ap.c | 40 +++++++++++++++++++++++
drivers/usb/gadget/Makefile | 1 +
drivers/usb/gadget/bcm_udc_otg.h | 17 ++++++++++
drivers/usb/gadget/bcm_udc_otg_phy.c | 50 +++++++++++++++++++++++++++++
drivers/usb/gadget/s3c_udc_otg.c | 4 +++
include/configs/bcm28155_ap.h | 21 ++++++++++++
include/g_dnl.h | 1 +
8 files changed, 141 insertions(+)
create mode 100644 drivers/usb/gadget/bcm_udc_otg.h
create mode 100644 drivers/usb/gadget/bcm_udc_otg_phy.c
--
1.8.5
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v2 1/4] g_dnl: add missing declaration
2015-07-06 19:49 [U-Boot] [PATCH v2 0/4] This series implements fastboot on the "bcm28155_ap" boards Steve Rae
@ 2015-07-06 19:49 ` Steve Rae
2015-07-07 13:19 ` Lukasz Majewski
2015-07-06 19:49 ` [U-Boot] [PATCH v2 2/4] usb: s3c-otg: support 8-bit interface Steve Rae
` (2 subsequent siblings)
3 siblings, 1 reply; 14+ messages in thread
From: Steve Rae @ 2015-07-06 19:49 UTC (permalink / raw)
To: u-boot
Signed-off-by: Steve Rae <srae@broadcom.com>
---
Changes in v2: None
include/g_dnl.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/g_dnl.h b/include/g_dnl.h
index 4eeb5e4..ba49f1f 100644
--- a/include/g_dnl.h
+++ b/include/g_dnl.h
@@ -34,6 +34,7 @@ struct g_dnl_bind_callback {
};
int g_dnl_bind_fixup(struct usb_device_descriptor *, const char *);
+int g_dnl_get_board_bcd_device_number(int gcnum);
int g_dnl_board_usb_cable_connected(void);
int g_dnl_register(const char *s);
void g_dnl_unregister(void);
--
1.8.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v2 2/4] usb: s3c-otg: support 8-bit interface
2015-07-06 19:49 [U-Boot] [PATCH v2 0/4] This series implements fastboot on the "bcm28155_ap" boards Steve Rae
2015-07-06 19:49 ` [U-Boot] [PATCH v2 1/4] g_dnl: add missing declaration Steve Rae
@ 2015-07-06 19:49 ` Steve Rae
2015-07-07 13:27 ` Lukasz Majewski
2015-07-06 19:49 ` [U-Boot] [PATCH v2 3/4] usb: gadget: bcm_udc_otg files Steve Rae
2015-07-06 19:49 ` [U-Boot] [PATCH v2 4/4] implement Fastboot via USB OTG on bcm28155_ap boards Steve Rae
3 siblings, 1 reply; 14+ messages in thread
From: Steve Rae @ 2015-07-06 19:49 UTC (permalink / raw)
To: u-boot
Signed-off-by: Steve Rae <srae@broadcom.com>
---
Changes in v2: None
drivers/usb/gadget/s3c_udc_otg.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/usb/gadget/s3c_udc_otg.c b/drivers/usb/gadget/s3c_udc_otg.c
index 7a2d1e7..2e3b4f7 100644
--- a/drivers/usb/gadget/s3c_udc_otg.c
+++ b/drivers/usb/gadget/s3c_udc_otg.c
@@ -414,7 +414,11 @@ static void reconfig_usbd(struct s3c_udc *dev)
|0<<7 /* Ulpi DDR sel*/
|0<<6 /* 0: high speed utmi+, 1: full speed serial*/
|0<<4 /* 0: utmi+, 1:ulpi*/
+#ifdef CONFIG_USB_GADGET_PHY_8_BIT
+ |0<<3 /* phy i/f 0:8bit, 1:16bit*/
+#else
|1<<3 /* phy i/f 0:8bit, 1:16bit*/
+#endif
|0x7<<0; /* HS/FS Timeout**/
if (dev->pdata->usb_gusbcfg)
--
1.8.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v2 3/4] usb: gadget: bcm_udc_otg files
2015-07-06 19:49 [U-Boot] [PATCH v2 0/4] This series implements fastboot on the "bcm28155_ap" boards Steve Rae
2015-07-06 19:49 ` [U-Boot] [PATCH v2 1/4] g_dnl: add missing declaration Steve Rae
2015-07-06 19:49 ` [U-Boot] [PATCH v2 2/4] usb: s3c-otg: support 8-bit interface Steve Rae
@ 2015-07-06 19:49 ` Steve Rae
2015-07-07 13:33 ` Lukasz Majewski
2015-07-06 19:49 ` [U-Boot] [PATCH v2 4/4] implement Fastboot via USB OTG on bcm28155_ap boards Steve Rae
3 siblings, 1 reply; 14+ messages in thread
From: Steve Rae @ 2015-07-06 19:49 UTC (permalink / raw)
To: u-boot
From: "JD (Jiandong) Zheng" <jdzheng@broadcom.com>
Add the required files for the Broadcom UDC OTG interface.
Signed-off-by: Steve Rae <srae@broadcom.com>
---
Changes in v2: None
arch/arm/include/asm/arch-bcm281xx/sysmap.h | 7 ++++
drivers/usb/gadget/bcm_udc_otg.h | 17 ++++++++++
drivers/usb/gadget/bcm_udc_otg_phy.c | 50 +++++++++++++++++++++++++++++
3 files changed, 74 insertions(+)
create mode 100644 drivers/usb/gadget/bcm_udc_otg.h
create mode 100644 drivers/usb/gadget/bcm_udc_otg_phy.c
diff --git a/arch/arm/include/asm/arch-bcm281xx/sysmap.h b/arch/arm/include/asm/arch-bcm281xx/sysmap.h
index 93ebf34..dbcc88c 100644
--- a/arch/arm/include/asm/arch-bcm281xx/sysmap.h
+++ b/arch/arm/include/asm/arch-bcm281xx/sysmap.h
@@ -27,4 +27,11 @@
#define SECWD2_BASE_ADDR 0x35002f40
#define TIMER_BASE_ADDR 0x3e00d000
+#define HSOTG_DCTL_OFFSET 0x00000804
+#define HSOTG_DCTL_SFTDISCON_MASK 0x00000002
+
+#define HSOTG_CTRL_PHY_P1CTL_OFFSET 0x00000008
+#define HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK 0x00000002
+#define HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001
+
#endif
diff --git a/drivers/usb/gadget/bcm_udc_otg.h b/drivers/usb/gadget/bcm_udc_otg.h
new file mode 100644
index 0000000..81a1fc0
--- /dev/null
+++ b/drivers/usb/gadget/bcm_udc_otg.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2015 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BCM_UDC_OTG_H
+#define __BCM_UDC_OTG_H
+
+#include <linux/types.h>
+
+#define wfld_set(addr, fld_val, fld_mask) \
+ (writel(((readl(addr) & ~(fld_mask)) | (fld_val)), (addr)))
+#define wfld_clear(addr, fld_mask) \
+ (writel((readl(addr) & ~(fld_mask)), (addr)))
+
+#endif
diff --git a/drivers/usb/gadget/bcm_udc_otg_phy.c b/drivers/usb/gadget/bcm_udc_otg_phy.c
new file mode 100644
index 0000000..1aa9f91
--- /dev/null
+++ b/drivers/usb/gadget/bcm_udc_otg_phy.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2015 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sysmap.h>
+
+#include <usb/s3c_udc.h>
+#include "bcm_udc_otg.h"
+
+void otg_phy_init(struct s3c_udc *dev)
+{
+ /* set Phy to driving mode */
+ wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
+ HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
+
+ udelay(100);
+
+ /* clear Soft Disconnect */
+ wfld_clear(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
+ HSOTG_DCTL_SFTDISCON_MASK);
+
+ /* invoke Reset (active low) */
+ wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
+ HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
+
+ udelay(10000);
+
+ /* release Reset */
+ wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
+ HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK,
+ HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
+}
+
+void otg_phy_off(struct s3c_udc *dev)
+{
+ /* Soft Disconnect */
+ wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
+ HSOTG_DCTL_SFTDISCON_MASK,
+ HSOTG_DCTL_SFTDISCON_MASK);
+
+ /* set Phy to non-driving (reset) mode */
+ wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
+ HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK,
+ HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
+}
--
1.8.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v2 4/4] implement Fastboot via USB OTG on bcm28155_ap boards
2015-07-06 19:49 [U-Boot] [PATCH v2 0/4] This series implements fastboot on the "bcm28155_ap" boards Steve Rae
` (2 preceding siblings ...)
2015-07-06 19:49 ` [U-Boot] [PATCH v2 3/4] usb: gadget: bcm_udc_otg files Steve Rae
@ 2015-07-06 19:49 ` Steve Rae
2015-07-07 13:39 ` Lukasz Majewski
3 siblings, 1 reply; 14+ messages in thread
From: Steve Rae @ 2015-07-06 19:49 UTC (permalink / raw)
To: u-boot
From: "JD (Jiandong) Zheng" <jdzheng@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
---
Changes in v2:
- rebased against u-boot-dfu
board/broadcom/bcm28155_ap/bcm28155_ap.c | 40 ++++++++++++++++++++++++++++++++
drivers/usb/gadget/Makefile | 1 +
include/configs/bcm28155_ap.h | 21 +++++++++++++++++
3 files changed, 62 insertions(+)
diff --git a/board/broadcom/bcm28155_ap/bcm28155_ap.c b/board/broadcom/bcm28155_ap/bcm28155_ap.c
index 940a1c2..20eb191 100644
--- a/board/broadcom/bcm28155_ap/bcm28155_ap.c
+++ b/board/broadcom/bcm28155_ap/bcm28155_ap.c
@@ -12,12 +12,20 @@
#include <asm/kona-common/clk.h>
#include <asm/arch/sysmap.h>
+#include <usb.h>
+#include <usb/s3c_udc.h>
+#include <g_dnl.h>
+
#define SECWATCHDOG_SDOGCR_OFFSET 0x00000000
#define SECWATCHDOG_SDOGCR_EN_SHIFT 27
#define SECWATCHDOG_SDOGCR_SRSTEN_SHIFT 26
#define SECWATCHDOG_SDOGCR_CLKS_SHIFT 20
#define SECWATCHDOG_SDOGCR_LD_SHIFT 0
+#ifndef CONFIG_USB_SERIALNO
+#define CONFIG_USB_SERIALNO "1234567890"
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
/*
@@ -85,3 +93,35 @@ int board_mmc_init(bd_t *bis)
return ret;
}
#endif
+
+#ifdef CONFIG_USB_GADGET
+static struct s3c_plat_otg_data bcm_otg_data = {
+ .regs_otg = HSOTG_BASE_ADDR
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ debug("%s: performing s3c_udc_probe\n", __func__);
+ return s3c_udc_probe(&bcm_otg_data);
+}
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+ debug("%s\n", __func__);
+ if (!getenv("serial#"))
+ g_dnl_set_serialnumber(CONFIG_USB_SERIALNO);
+ return 0;
+}
+
+int g_dnl_get_board_bcd_device_number(int gcnum)
+{
+ debug("%s\n", __func__);
+ return 1;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ debug("%s\n", __func__);
+ return 0;
+}
+#endif
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 4e15323..4c11a7e 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o usbstring.o
# new USB gadget layer dependencies
ifdef CONFIG_USB_GADGET
obj-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o
+obj-$(CONFIG_USB_GADGET_BCM_UDC_OTG_PHY) += bcm_udc_otg_phy.o
obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o
obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG_PHY) += s3c_udc_otg_phy.o
obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o
diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h
index 900dc42..46920a1 100644
--- a/include/configs/bcm28155_ap.h
+++ b/include/configs/bcm28155_ap.h
@@ -109,6 +109,7 @@
* for example.
*/
#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
/* version string, parser, etc */
#define CONFIG_VERSION_VARIABLE
@@ -136,4 +137,24 @@
#undef CONFIG_CMD_NFS
+/* Fastboot and USB OTG */
+#define CONFIG_USB_FUNCTION_FASTBOOT
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_FASTBOOT_FLASH
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 0
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_USB_FASTBOOT_BUF_SIZE (CONFIG_SYS_SDRAM_SIZE - (1024 * 1024))
+#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_SDRAM_BASE
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW 0
+#define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_BCM_UDC_OTG_PHY
+#define CONFIG_USB_GADGET_PHY_8_BIT
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_USBID_ADDR 0x34052c46
+#define CONFIG_G_DNL_VENDOR_NUM 0x18d1 /* google */
+#define CONFIG_G_DNL_PRODUCT_NUM 0x0d02 /* nexus one */
+#define CONFIG_G_DNL_MANUFACTURER "Broadcom Corporation"
+
#endif /* __BCM28155_AP_H */
--
1.8.5
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v2 1/4] g_dnl: add missing declaration
2015-07-06 19:49 ` [U-Boot] [PATCH v2 1/4] g_dnl: add missing declaration Steve Rae
@ 2015-07-07 13:19 ` Lukasz Majewski
0 siblings, 0 replies; 14+ messages in thread
From: Lukasz Majewski @ 2015-07-07 13:19 UTC (permalink / raw)
To: u-boot
Hi Steve,
> Signed-off-by: Steve Rae <srae@broadcom.com>
> ---
>
> Changes in v2: None
>
> include/g_dnl.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/g_dnl.h b/include/g_dnl.h
> index 4eeb5e4..ba49f1f 100644
> --- a/include/g_dnl.h
> +++ b/include/g_dnl.h
> @@ -34,6 +34,7 @@ struct g_dnl_bind_callback {
> };
>
> int g_dnl_bind_fixup(struct usb_device_descriptor *, const char *);
> +int g_dnl_get_board_bcd_device_number(int gcnum);
> int g_dnl_board_usb_cable_connected(void);
> int g_dnl_register(const char *s);
> void g_dnl_unregister(void);
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
--
Best regards,
Lukasz Majewski
Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v2 2/4] usb: s3c-otg: support 8-bit interface
2015-07-06 19:49 ` [U-Boot] [PATCH v2 2/4] usb: s3c-otg: support 8-bit interface Steve Rae
@ 2015-07-07 13:27 ` Lukasz Majewski
2015-07-07 19:43 ` Steve Rae
0 siblings, 1 reply; 14+ messages in thread
From: Lukasz Majewski @ 2015-07-07 13:27 UTC (permalink / raw)
To: u-boot
Hi Steve,
> Signed-off-by: Steve Rae <srae@broadcom.com>
> ---
>
> Changes in v2: None
>
> drivers/usb/gadget/s3c_udc_otg.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/usb/gadget/s3c_udc_otg.c
> b/drivers/usb/gadget/s3c_udc_otg.c index 7a2d1e7..2e3b4f7 100644
> --- a/drivers/usb/gadget/s3c_udc_otg.c
> +++ b/drivers/usb/gadget/s3c_udc_otg.c
> @@ -414,7 +414,11 @@ static void reconfig_usbd(struct s3c_udc *dev)
> |0<<7 /* Ulpi DDR sel*/
> |0<<6 /* 0: high speed utmi+, 1: full
> speed serial*/ |0<<4 /* 0: utmi+, 1:ulpi*/
> +#ifdef CONFIG_USB_GADGET_PHY_8_BIT
> + |0<<3 /* phy i/f 0:8bit, 1:16bit*/
> +#else
> |1<<3 /* phy i/f 0:8bit, 1:16bit*/
> +#endif
Is your board using also host phy? As fair as I remember, the upper 8
bits are for host interface.
> |0x7<<0; /* HS/FS Timeout**/
>
> if (dev->pdata->usb_gusbcfg)
Despite my above question:
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
--
Best regards,
Lukasz Majewski
Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v2 3/4] usb: gadget: bcm_udc_otg files
2015-07-06 19:49 ` [U-Boot] [PATCH v2 3/4] usb: gadget: bcm_udc_otg files Steve Rae
@ 2015-07-07 13:33 ` Lukasz Majewski
2015-07-07 20:26 ` Steve Rae
0 siblings, 1 reply; 14+ messages in thread
From: Lukasz Majewski @ 2015-07-07 13:33 UTC (permalink / raw)
To: u-boot
Hi Steve,
> From: "JD (Jiandong) Zheng" <jdzheng@broadcom.com>
>
> Add the required files for the Broadcom UDC OTG interface.
>
> Signed-off-by: Steve Rae <srae@broadcom.com>
> ---
>
> Changes in v2: None
>
> arch/arm/include/asm/arch-bcm281xx/sysmap.h | 7 ++++
> drivers/usb/gadget/bcm_udc_otg.h | 17 ++++++++++
> drivers/usb/gadget/bcm_udc_otg_phy.c | 50
> +++++++++++++++++++++++++++++ 3 files changed, 74 insertions(+)
> create mode 100644 drivers/usb/gadget/bcm_udc_otg.h
> create mode 100644 drivers/usb/gadget/bcm_udc_otg_phy.c
>
> diff --git a/arch/arm/include/asm/arch-bcm281xx/sysmap.h
> b/arch/arm/include/asm/arch-bcm281xx/sysmap.h index 93ebf34..dbcc88c
> 100644 --- a/arch/arm/include/asm/arch-bcm281xx/sysmap.h
> +++ b/arch/arm/include/asm/arch-bcm281xx/sysmap.h
> @@ -27,4 +27,11 @@
> #define SECWD2_BASE_ADDR 0x35002f40
> #define TIMER_BASE_ADDR 0x3e00d000
>
> +#define HSOTG_DCTL_OFFSET
> 0x00000804 +#define
> HSOTG_DCTL_SFTDISCON_MASK 0x00000002 +
> +#define HSOTG_CTRL_PHY_P1CTL_OFFSET
> 0x00000008 +#define
> HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK
> 0x00000002 +#define
> HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001 +
> #endif diff --git a/drivers/usb/gadget/bcm_udc_otg.h
> b/drivers/usb/gadget/bcm_udc_otg.h new file mode 100644
> index 0000000..81a1fc0
> --- /dev/null
> +++ b/drivers/usb/gadget/bcm_udc_otg.h
> @@ -0,0 +1,17 @@
> +/*
> + * Copyright 2015 Broadcom Corporation.
--> Please also add the name of the code author.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __BCM_UDC_OTG_H
> +#define __BCM_UDC_OTG_H
> +
> +#include <linux/types.h>
> +
> +#define wfld_set(addr, fld_val, fld_mask) \
> + (writel(((readl(addr) & ~(fld_mask)) | (fld_val)),
> (addr))) +#define wfld_clear(addr, fld_mask) \
> + (writel((readl(addr) & ~(fld_mask)), (addr)))
Maybe we could replace those preprocessor macros with static inline
functions?
> +
> +#endif
> diff --git a/drivers/usb/gadget/bcm_udc_otg_phy.c
> b/drivers/usb/gadget/bcm_udc_otg_phy.c new file mode 100644
> index 0000000..1aa9f91
> --- /dev/null
> +++ b/drivers/usb/gadget/bcm_udc_otg_phy.c
> @@ -0,0 +1,50 @@
> +/*
> + * Copyright 2015 Broadcom Corporation.
---> The same as above.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <config.h>
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/arch/sysmap.h>
> +
> +#include <usb/s3c_udc.h>
> +#include "bcm_udc_otg.h"
> +
> +void otg_phy_init(struct s3c_udc *dev)
> +{
> + /* set Phy to driving mode */
> + wfld_clear(HSOTG_CTRL_BASE_ADDR +
> HSOTG_CTRL_PHY_P1CTL_OFFSET,
> + HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
> +
> + udelay(100);
> +
> + /* clear Soft Disconnect */
> + wfld_clear(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
> + HSOTG_DCTL_SFTDISCON_MASK);
> +
> + /* invoke Reset (active low) */
> + wfld_clear(HSOTG_CTRL_BASE_ADDR +
> HSOTG_CTRL_PHY_P1CTL_OFFSET,
> + HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
> +
> + udelay(10000);
^^^^^^^^^^^^^^ -- would it be possible to add some comment
regarding for what we are waiting here?
> +
> + /* release Reset */
> + wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
> + HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK,
> + HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
> +}
> +
> +void otg_phy_off(struct s3c_udc *dev)
> +{
> + /* Soft Disconnect */
> + wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
> + HSOTG_DCTL_SFTDISCON_MASK,
> + HSOTG_DCTL_SFTDISCON_MASK);
> +
> + /* set Phy to non-driving (reset) mode */
> + wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
> + HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK,
> + HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
> +}
--
Best regards,
Lukasz Majewski
Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v2 4/4] implement Fastboot via USB OTG on bcm28155_ap boards
2015-07-06 19:49 ` [U-Boot] [PATCH v2 4/4] implement Fastboot via USB OTG on bcm28155_ap boards Steve Rae
@ 2015-07-07 13:39 ` Lukasz Majewski
0 siblings, 0 replies; 14+ messages in thread
From: Lukasz Majewski @ 2015-07-07 13:39 UTC (permalink / raw)
To: u-boot
Hi Steve,
> From: "JD (Jiandong) Zheng" <jdzheng@broadcom.com>
>
> Signed-off-by: Steve Rae <srae@broadcom.com>
> ---
>
> Changes in v2:
> - rebased against u-boot-dfu
>
> board/broadcom/bcm28155_ap/bcm28155_ap.c | 40
> ++++++++++++++++++++++++++++++++
> drivers/usb/gadget/Makefile | 1 +
> include/configs/bcm28155_ap.h | 21 +++++++++++++++++ 3
> files changed, 62 insertions(+)
>
> diff --git a/board/broadcom/bcm28155_ap/bcm28155_ap.c
> b/board/broadcom/bcm28155_ap/bcm28155_ap.c index 940a1c2..20eb191
> 100644 --- a/board/broadcom/bcm28155_ap/bcm28155_ap.c
> +++ b/board/broadcom/bcm28155_ap/bcm28155_ap.c
> @@ -12,12 +12,20 @@
> #include <asm/kona-common/clk.h>
> #include <asm/arch/sysmap.h>
>
> +#include <usb.h>
> +#include <usb/s3c_udc.h>
> +#include <g_dnl.h>
> +
> #define SECWATCHDOG_SDOGCR_OFFSET 0x00000000
> #define SECWATCHDOG_SDOGCR_EN_SHIFT 27
> #define SECWATCHDOG_SDOGCR_SRSTEN_SHIFT 26
> #define SECWATCHDOG_SDOGCR_CLKS_SHIFT 20
> #define SECWATCHDOG_SDOGCR_LD_SHIFT 0
>
> +#ifndef CONFIG_USB_SERIALNO
> +#define CONFIG_USB_SERIALNO "1234567890"
> +#endif
> +
> DECLARE_GLOBAL_DATA_PTR;
>
> /*
> @@ -85,3 +93,35 @@ int board_mmc_init(bd_t *bis)
> return ret;
> }
> #endif
> +
> +#ifdef CONFIG_USB_GADGET
> +static struct s3c_plat_otg_data bcm_otg_data = {
> + .regs_otg = HSOTG_BASE_ADDR
> +};
> +
> +int board_usb_init(int index, enum usb_init_type init)
> +{
> + debug("%s: performing s3c_udc_probe\n", __func__);
> + return s3c_udc_probe(&bcm_otg_data);
> +}
> +
> +int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char
> *name) +{
> + debug("%s\n", __func__);
> + if (!getenv("serial#"))
> + g_dnl_set_serialnumber(CONFIG_USB_SERIALNO);
> + return 0;
> +}
> +
> +int g_dnl_get_board_bcd_device_number(int gcnum)
> +{
> + debug("%s\n", __func__);
> + return 1;
> +}
> +
> +int board_usb_cleanup(int index, enum usb_init_type init)
> +{
> + debug("%s\n", __func__);
> + return 0;
> +}
> +#endif
> diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
> index 4e15323..4c11a7e 100644
> --- a/drivers/usb/gadget/Makefile
> +++ b/drivers/usb/gadget/Makefile
> @@ -11,6 +11,7 @@ obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o
> usbstring.o # new USB gadget layer dependencies
> ifdef CONFIG_USB_GADGET
> obj-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o
> +obj-$(CONFIG_USB_GADGET_BCM_UDC_OTG_PHY) += bcm_udc_otg_phy.o
> obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o
> obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG_PHY) += s3c_udc_otg_phy.o
> obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o
> diff --git a/include/configs/bcm28155_ap.h
> b/include/configs/bcm28155_ap.h index 900dc42..46920a1 100644
> --- a/include/configs/bcm28155_ap.h
> +++ b/include/configs/bcm28155_ap.h
> @@ -109,6 +109,7 @@
> * for example.
> */
> #define CONFIG_DOS_PARTITION
> +#define CONFIG_EFI_PARTITION
>
> /* version string, parser, etc */
> #define CONFIG_VERSION_VARIABLE
> @@ -136,4 +137,24 @@
>
> #undef CONFIG_CMD_NFS
>
> +/* Fastboot and USB OTG */
> +#define CONFIG_USB_FUNCTION_FASTBOOT
> +#define CONFIG_CMD_FASTBOOT
> +#define CONFIG_FASTBOOT_FLASH
> +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 0
> +#define CONFIG_SYS_CACHELINE_SIZE 64
> +#define CONFIG_USB_FASTBOOT_BUF_SIZE (CONFIG_SYS_SDRAM_SIZE -
> (1024 * 1024)) +#define CONFIG_USB_FASTBOOT_BUF_ADDR
^^^^^^^^^^^ Here you can use SZ_1M
> CONFIG_SYS_SDRAM_BASE +#define CONFIG_USB_GADGET
> +#define CONFIG_USB_GADGET_DUALSPEED
> +#define CONFIG_USB_GADGET_VBUS_DRAW 0
> +#define CONFIG_USB_GADGET_S3C_UDC_OTG
> +#define CONFIG_USB_GADGET_BCM_UDC_OTG_PHY
> +#define CONFIG_USB_GADGET_PHY_8_BIT
> +#define CONFIG_USB_GADGET_DOWNLOAD
> +#define CONFIG_USBID_ADDR 0x34052c46
> +#define CONFIG_G_DNL_VENDOR_NUM 0x18d1 /*
> google */ +#define CONFIG_G_DNL_PRODUCT_NUM 0x0d02 /*
> nexus one */ +#define CONFIG_G_DNL_MANUFACTURER "Broadcom
> Corporation" +
> #endif /* __BCM28155_AP_H */
--
Best regards,
Lukasz Majewski
Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v2 2/4] usb: s3c-otg: support 8-bit interface
2015-07-07 13:27 ` Lukasz Majewski
@ 2015-07-07 19:43 ` Steve Rae
2015-07-08 14:14 ` Lukasz Majewski
0 siblings, 1 reply; 14+ messages in thread
From: Steve Rae @ 2015-07-07 19:43 UTC (permalink / raw)
To: u-boot
On 15-07-07 06:27 AM, Lukasz Majewski wrote:
> Hi Steve,
>
>> Signed-off-by: Steve Rae <srae@broadcom.com>
>> ---
>>
>> Changes in v2: None
>>
>> drivers/usb/gadget/s3c_udc_otg.c | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/usb/gadget/s3c_udc_otg.c
>> b/drivers/usb/gadget/s3c_udc_otg.c index 7a2d1e7..2e3b4f7 100644
>> --- a/drivers/usb/gadget/s3c_udc_otg.c
>> +++ b/drivers/usb/gadget/s3c_udc_otg.c
>> @@ -414,7 +414,11 @@ static void reconfig_usbd(struct s3c_udc *dev)
>> |0<<7 /* Ulpi DDR sel*/
>> |0<<6 /* 0: high speed utmi+, 1: full
>> speed serial*/ |0<<4 /* 0: utmi+, 1:ulpi*/
>> +#ifdef CONFIG_USB_GADGET_PHY_8_BIT
>> + |0<<3 /* phy i/f 0:8bit, 1:16bit*/
>> +#else
>> |1<<3 /* phy i/f 0:8bit, 1:16bit*/
>> +#endif
>
> Is your board using also host phy? As fair as I remember, the upper 8
> bits are for host interface.
Hi Lukasz,
Are you suggesting that we define this as a 16-bit interface, and then
only use the upper 8-bits (to achieve the 8-bit interface)?
Please clarify, Thanks Steve
>
>
>> |0x7<<0; /* HS/FS Timeout**/
>>
>> if (dev->pdata->usb_gusbcfg)
>
> Despite my above question:
>
> Acked-by: Lukasz Majewski <l.majewski@samsung.com>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v2 3/4] usb: gadget: bcm_udc_otg files
2015-07-07 13:33 ` Lukasz Majewski
@ 2015-07-07 20:26 ` Steve Rae
2015-07-08 14:22 ` Lukasz Majewski
0 siblings, 1 reply; 14+ messages in thread
From: Steve Rae @ 2015-07-07 20:26 UTC (permalink / raw)
To: u-boot
Hi, Lukasz
On 15-07-07 06:33 AM, Lukasz Majewski wrote:
> Hi Steve,
>
>> From: "JD (Jiandong) Zheng" <jdzheng@broadcom.com>
>>
>> Add the required files for the Broadcom UDC OTG interface.
>>
>> Signed-off-by: Steve Rae <srae@broadcom.com>
>> ---
>>
>> Changes in v2: None
>>
>> arch/arm/include/asm/arch-bcm281xx/sysmap.h | 7 ++++
>> drivers/usb/gadget/bcm_udc_otg.h | 17 ++++++++++
>> drivers/usb/gadget/bcm_udc_otg_phy.c | 50
>> +++++++++++++++++++++++++++++ 3 files changed, 74 insertions(+)
>> create mode 100644 drivers/usb/gadget/bcm_udc_otg.h
>> create mode 100644 drivers/usb/gadget/bcm_udc_otg_phy.c
>>
>> diff --git a/arch/arm/include/asm/arch-bcm281xx/sysmap.h
>> b/arch/arm/include/asm/arch-bcm281xx/sysmap.h index 93ebf34..dbcc88c
>> 100644 --- a/arch/arm/include/asm/arch-bcm281xx/sysmap.h
>> +++ b/arch/arm/include/asm/arch-bcm281xx/sysmap.h
>> @@ -27,4 +27,11 @@
>> #define SECWD2_BASE_ADDR 0x35002f40
>> #define TIMER_BASE_ADDR 0x3e00d000
>>
>> +#define HSOTG_DCTL_OFFSET
>> 0x00000804 +#define
>> HSOTG_DCTL_SFTDISCON_MASK 0x00000002 +
>> +#define HSOTG_CTRL_PHY_P1CTL_OFFSET
>> 0x00000008 +#define
>> HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK
>> 0x00000002 +#define
>> HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001 +
>> #endif diff --git a/drivers/usb/gadget/bcm_udc_otg.h
>> b/drivers/usb/gadget/bcm_udc_otg.h new file mode 100644
>> index 0000000..81a1fc0
>> --- /dev/null
>> +++ b/drivers/usb/gadget/bcm_udc_otg.h
>> @@ -0,0 +1,17 @@
>> +/*
>> + * Copyright 2015 Broadcom Corporation.
>
> --> Please also add the name of the code author.
this is not standard practice at Broadcom....
and it seems that at least five (5) people have contributed to the code
in this commit....
What would you suggest? The most recent author, or ???
>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#ifndef __BCM_UDC_OTG_H
>> +#define __BCM_UDC_OTG_H
>> +
>> +#include <linux/types.h>
>> +
>> +#define wfld_set(addr, fld_val, fld_mask) \
>> + (writel(((readl(addr) & ~(fld_mask)) | (fld_val)),
>> (addr))) +#define wfld_clear(addr, fld_mask) \
>> + (writel((readl(addr) & ~(fld_mask)), (addr)))
>
> Maybe we could replace those preprocessor macros with static inline
> functions?
Hmmm - since writel() and readl() are also macros, it makes it difficult
to make these into functions....
I guess we could use "uintprt_t" and "uint32_t"
Would you agree?
>
>> +
>> +#endif
>> diff --git a/drivers/usb/gadget/bcm_udc_otg_phy.c
>> b/drivers/usb/gadget/bcm_udc_otg_phy.c new file mode 100644
>> index 0000000..1aa9f91
>> --- /dev/null
>> +++ b/drivers/usb/gadget/bcm_udc_otg_phy.c
>> @@ -0,0 +1,50 @@
>> +/*
>> + * Copyright 2015 Broadcom Corporation.
>
> ---> The same as above.
>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <config.h>
>> +#include <common.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/sysmap.h>
>> +
>> +#include <usb/s3c_udc.h>
>> +#include "bcm_udc_otg.h"
>> +
>> +void otg_phy_init(struct s3c_udc *dev)
>> +{
>> + /* set Phy to driving mode */
>> + wfld_clear(HSOTG_CTRL_BASE_ADDR +
>> HSOTG_CTRL_PHY_P1CTL_OFFSET,
>> + HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
>> +
>> + udelay(100);
>> +
>> + /* clear Soft Disconnect */
>> + wfld_clear(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
>> + HSOTG_DCTL_SFTDISCON_MASK);
>> +
>> + /* invoke Reset (active low) */
>> + wfld_clear(HSOTG_CTRL_BASE_ADDR +
>> HSOTG_CTRL_PHY_P1CTL_OFFSET,
>> + HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
>> +
>> + udelay(10000);
> ^^^^^^^^^^^^^^ -- would it be possible to add some comment
> regarding for what we are waiting here?
OK
>> +
>> + /* release Reset */
>> + wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
>> + HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK,
>> + HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
>> +}
>> +
>> +void otg_phy_off(struct s3c_udc *dev)
>> +{
>> + /* Soft Disconnect */
>> + wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
>> + HSOTG_DCTL_SFTDISCON_MASK,
>> + HSOTG_DCTL_SFTDISCON_MASK);
>> +
>> + /* set Phy to non-driving (reset) mode */
>> + wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
>> + HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK,
>> + HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
>> +}
>
>
>
Thanks, Steve
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v2 2/4] usb: s3c-otg: support 8-bit interface
2015-07-07 19:43 ` Steve Rae
@ 2015-07-08 14:14 ` Lukasz Majewski
0 siblings, 0 replies; 14+ messages in thread
From: Lukasz Majewski @ 2015-07-08 14:14 UTC (permalink / raw)
To: u-boot
Hi Steve,
>
>
> On 15-07-07 06:27 AM, Lukasz Majewski wrote:
> > Hi Steve,
> >
> >> Signed-off-by: Steve Rae <srae@broadcom.com>
> >> ---
> >>
> >> Changes in v2: None
> >>
> >> drivers/usb/gadget/s3c_udc_otg.c | 4 ++++
> >> 1 file changed, 4 insertions(+)
> >>
> >> diff --git a/drivers/usb/gadget/s3c_udc_otg.c
> >> b/drivers/usb/gadget/s3c_udc_otg.c index 7a2d1e7..2e3b4f7 100644
> >> --- a/drivers/usb/gadget/s3c_udc_otg.c
> >> +++ b/drivers/usb/gadget/s3c_udc_otg.c
> >> @@ -414,7 +414,11 @@ static void reconfig_usbd(struct s3c_udc *dev)
> >> |0<<7 /* Ulpi DDR sel*/
> >> |0<<6 /* 0: high speed utmi+, 1:
> >> full speed serial*/ |0<<4 /* 0: utmi+, 1:ulpi*/
> >> +#ifdef CONFIG_USB_GADGET_PHY_8_BIT
> >> + |0<<3 /* phy i/f 0:8bit, 1:16bit*/
> >> +#else
> >> |1<<3 /* phy i/f 0:8bit,
> >> 1:16bit*/ +#endif
> >
> > Is your board using also host phy? As fair as I remember, the upper
> > 8 bits are for host interface.
> Hi Lukasz,
> Are you suggesting that we define this as a 16-bit interface, and
> then only use the upper 8-bits (to achieve the 8-bit interface)?
> Please clarify, Thanks Steve
As fair as I remember we use lower 8 bits for device PHY and upper for
host.
Your board (with this Synopsys IP) should work with 16 bits as well.
> >
> >
> >> |0x7<<0; /* HS/FS Timeout**/
> >>
> >> if (dev->pdata->usb_gusbcfg)
> >
> > Despite my above question:
> >
> > Acked-by: Lukasz Majewski <l.majewski@samsung.com>
> >
--
Best regards,
Lukasz Majewski
Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v2 3/4] usb: gadget: bcm_udc_otg files
2015-07-07 20:26 ` Steve Rae
@ 2015-07-08 14:22 ` Lukasz Majewski
2015-07-08 14:35 ` Marek Vasut
0 siblings, 1 reply; 14+ messages in thread
From: Lukasz Majewski @ 2015-07-08 14:22 UTC (permalink / raw)
To: u-boot
Hi Steve,
> Hi, Lukasz
>
> On 15-07-07 06:33 AM, Lukasz Majewski wrote:
> > Hi Steve,
> >
> >> From: "JD (Jiandong) Zheng" <jdzheng@broadcom.com>
> >>
> >> Add the required files for the Broadcom UDC OTG interface.
> >>
> >> Signed-off-by: Steve Rae <srae@broadcom.com>
> >> ---
> >>
> >> Changes in v2: None
> >>
> >> arch/arm/include/asm/arch-bcm281xx/sysmap.h | 7 ++++
> >> drivers/usb/gadget/bcm_udc_otg.h | 17 ++++++++++
> >> drivers/usb/gadget/bcm_udc_otg_phy.c | 50
> >> +++++++++++++++++++++++++++++ 3 files changed, 74 insertions(+)
> >> create mode 100644 drivers/usb/gadget/bcm_udc_otg.h
> >> create mode 100644 drivers/usb/gadget/bcm_udc_otg_phy.c
> >>
> >> diff --git a/arch/arm/include/asm/arch-bcm281xx/sysmap.h
> >> b/arch/arm/include/asm/arch-bcm281xx/sysmap.h index
> >> 93ebf34..dbcc88c 100644 ---
> >> a/arch/arm/include/asm/arch-bcm281xx/sysmap.h +++
> >> b/arch/arm/include/asm/arch-bcm281xx/sysmap.h @@ -27,4 +27,11 @@
> >> #define SECWD2_BASE_ADDR 0x35002f40
> >> #define TIMER_BASE_ADDR 0x3e00d000
> >>
> >> +#define HSOTG_DCTL_OFFSET
> >> 0x00000804 +#define
> >> HSOTG_DCTL_SFTDISCON_MASK
> >> 0x00000002 + +#define HSOTG_CTRL_PHY_P1CTL_OFFSET
> >> 0x00000008 +#define
> >> HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK
> >> 0x00000002 +#define
> >> HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001 +
> >> #endif diff --git a/drivers/usb/gadget/bcm_udc_otg.h
> >> b/drivers/usb/gadget/bcm_udc_otg.h new file mode 100644
> >> index 0000000..81a1fc0
> >> --- /dev/null
> >> +++ b/drivers/usb/gadget/bcm_udc_otg.h
> >> @@ -0,0 +1,17 @@
> >> +/*
> >> + * Copyright 2015 Broadcom Corporation.
> >
> > --> Please also add the name of the code author.
> this is not standard practice at Broadcom....
> and it seems that at least five (5) people have contributed to the
> code in this commit....
> What would you suggest? The most recent author, or ???
I will not push you to add names if it is not mandatory in your company.
I just wanted to stress here that putting ones name is some kind of
reward when working with community.
>
> >
> >> + *
> >> + * SPDX-License-Identifier: GPL-2.0+
> >> + */
> >> +
> >> +#ifndef __BCM_UDC_OTG_H
> >> +#define __BCM_UDC_OTG_H
> >> +
> >> +#include <linux/types.h>
> >> +
> >> +#define wfld_set(addr, fld_val, fld_mask) \
> >> + (writel(((readl(addr) & ~(fld_mask)) | (fld_val)),
> >> (addr))) +#define wfld_clear(addr, fld_mask) \
> >> + (writel((readl(addr) & ~(fld_mask)), (addr)))
> >
> > Maybe we could replace those preprocessor macros with static inline
> > functions?
> Hmmm - since writel() and readl() are also macros, it makes it
> difficult to make these into functions....
I think that it would be doable to embed writel() and readl() in a
static inline function.
> I guess we could use "uintprt_t" and "uint32_t"
> Would you agree?
We can give it a try.
> >
> >> +
> >> +#endif
> >> diff --git a/drivers/usb/gadget/bcm_udc_otg_phy.c
> >> b/drivers/usb/gadget/bcm_udc_otg_phy.c new file mode 100644
> >> index 0000000..1aa9f91
> >> --- /dev/null
> >> +++ b/drivers/usb/gadget/bcm_udc_otg_phy.c
> >> @@ -0,0 +1,50 @@
> >> +/*
> >> + * Copyright 2015 Broadcom Corporation.
> >
> > ---> The same as above.
> >
> >> + *
> >> + * SPDX-License-Identifier: GPL-2.0+
> >> + */
> >> +
> >> +#include <config.h>
> >> +#include <common.h>
> >> +#include <asm/io.h>
> >> +#include <asm/arch/sysmap.h>
> >> +
> >> +#include <usb/s3c_udc.h>
> >> +#include "bcm_udc_otg.h"
> >> +
> >> +void otg_phy_init(struct s3c_udc *dev)
> >> +{
> >> + /* set Phy to driving mode */
> >> + wfld_clear(HSOTG_CTRL_BASE_ADDR +
> >> HSOTG_CTRL_PHY_P1CTL_OFFSET,
> >> + HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
> >> +
> >> + udelay(100);
> >> +
> >> + /* clear Soft Disconnect */
> >> + wfld_clear(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
> >> + HSOTG_DCTL_SFTDISCON_MASK);
> >> +
> >> + /* invoke Reset (active low) */
> >> + wfld_clear(HSOTG_CTRL_BASE_ADDR +
> >> HSOTG_CTRL_PHY_P1CTL_OFFSET,
> >> + HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
> >> +
> >> + udelay(10000);
> > ^^^^^^^^^^^^^^ -- would it be possible to add some comment
> > regarding for what we are waiting here?
> OK
>
> >> +
> >> + /* release Reset */
> >> + wfld_set(HSOTG_CTRL_BASE_ADDR +
> >> HSOTG_CTRL_PHY_P1CTL_OFFSET,
> >> + HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK,
> >> + HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
> >> +}
> >> +
> >> +void otg_phy_off(struct s3c_udc *dev)
> >> +{
> >> + /* Soft Disconnect */
> >> + wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
> >> + HSOTG_DCTL_SFTDISCON_MASK,
> >> + HSOTG_DCTL_SFTDISCON_MASK);
> >> +
> >> + /* set Phy to non-driving (reset) mode */
> >> + wfld_set(HSOTG_CTRL_BASE_ADDR +
> >> HSOTG_CTRL_PHY_P1CTL_OFFSET,
> >> + HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK,
> >> + HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
> >> +}
> >
> >
> >
> Thanks, Steve
--
Best regards,
Lukasz Majewski
Samsung R&D Institute Poland (SRPOL) | Linux Platform Group
^ permalink raw reply [flat|nested] 14+ messages in thread
* [U-Boot] [PATCH v2 3/4] usb: gadget: bcm_udc_otg files
2015-07-08 14:22 ` Lukasz Majewski
@ 2015-07-08 14:35 ` Marek Vasut
0 siblings, 0 replies; 14+ messages in thread
From: Marek Vasut @ 2015-07-08 14:35 UTC (permalink / raw)
To: u-boot
On Wednesday, July 08, 2015 at 04:22:14 PM, Lukasz Majewski wrote:
> Hi Steve,
Hi!
> > >> b/drivers/usb/gadget/bcm_udc_otg.h new file mode 100644
> > >> index 0000000..81a1fc0
> > >> --- /dev/null
> > >> +++ b/drivers/usb/gadget/bcm_udc_otg.h
> > >> @@ -0,0 +1,17 @@
> > >> +/*
> > >> + * Copyright 2015 Broadcom Corporation.
> > >
> > > --> Please also add the name of the code author.
> >
> > this is not standard practice at Broadcom....
> > and it seems that at least five (5) people have contributed to the
> > code in this commit....
> > What would you suggest? The most recent author, or ???
>
> I will not push you to add names if it is not mandatory in your company.
>
> I just wanted to stress here that putting ones name is some kind of
> reward when working with community.
And it's also much easier to point fingers if something goes wrong :-)
(and contact the author, but that's in git log too, so whatever)
[...]
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2015-07-08 14:35 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-07-06 19:49 [U-Boot] [PATCH v2 0/4] This series implements fastboot on the "bcm28155_ap" boards Steve Rae
2015-07-06 19:49 ` [U-Boot] [PATCH v2 1/4] g_dnl: add missing declaration Steve Rae
2015-07-07 13:19 ` Lukasz Majewski
2015-07-06 19:49 ` [U-Boot] [PATCH v2 2/4] usb: s3c-otg: support 8-bit interface Steve Rae
2015-07-07 13:27 ` Lukasz Majewski
2015-07-07 19:43 ` Steve Rae
2015-07-08 14:14 ` Lukasz Majewski
2015-07-06 19:49 ` [U-Boot] [PATCH v2 3/4] usb: gadget: bcm_udc_otg files Steve Rae
2015-07-07 13:33 ` Lukasz Majewski
2015-07-07 20:26 ` Steve Rae
2015-07-08 14:22 ` Lukasz Majewski
2015-07-08 14:35 ` Marek Vasut
2015-07-06 19:49 ` [U-Boot] [PATCH v2 4/4] implement Fastboot via USB OTG on bcm28155_ap boards Steve Rae
2015-07-07 13:39 ` Lukasz Majewski
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.