[BXT MIPI PATCH v2 00/13] MIPI DSI Support for BXT

[BXT MIPI PATCH v2 00/13] MIPI DSI Support for BXT

[Uma Shankar]

This patch series adds support for MIPI DSI for BXT platform.
Support for VBT v3 sequence parsing and programming is needed
for panel, backlight enable and control. The same will be added
as part of a different patch series.

Below is the link for earlier patch series in mailing list:
http://www.spinics.net/lists/intel-gfx/msg67354.html

v2: Addressed the review comments from Jani. Fixed Macros
    definitions as per convention. Adjusted the BXT DSI MACROS to
    get proper offsets for PORT C. DDI/DSI handling in generic
    code has been simplified. Backlight handling for BXT DSI has
    been re-designed.

Shashank Sharma (10):
  drm/i915/bxt: Initialize MIPI for BXT
  drm/i915/bxt: Enable BXT DSI PLL
  drm/i915/bxt: Disable DSI PLL for BXT
  drm/i915/bxt: DSI prepare changes for BXT
  drm/i915/bxt: DSI encoder support in CRTC modeset
  drm/i915/bxt: DSI enable for BXT
  drm/i915/bxt: Program Tx Rx and Dphy clocks
  drm/i915/bxt: DSI disable and post-disable
  drm/i915/bxt: get_hw_state for BXT
  drm/i915/bxt: get DSI pixelclock

Sunil Kamath (1):
  drm/i915/bxt: Modify BXT BLC according to VBT changes

Uma Shankar (2):
  drm/i915/bxt: Remove DSP CLK_GATE programming for BXT
  drm/i915: Added BXT DSI backlight support

 drivers/gpu/drm/i915/i915_drv.h       |    1 +
 drivers/gpu/drm/i915/i915_reg.h       |  123 ++++++++++++-
 drivers/gpu/drm/i915/intel_ddi.c      |   10 +-
 drivers/gpu/drm/i915/intel_display.c  |   22 ++-
 drivers/gpu/drm/i915/intel_drv.h      |    2 +
 drivers/gpu/drm/i915/intel_dsi.c      |  312 ++++++++++++++++++++++++---------
 drivers/gpu/drm/i915/intel_dsi.h      |    7 +-
 drivers/gpu/drm/i915/intel_dsi_pll.c  |  242 ++++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_opregion.c |    3 +-
 drivers/gpu/drm/i915/intel_panel.c    |   94 ++++++++--
 10 files changed, 693 insertions(+), 123 deletions(-)

-- 
1.7.9.5

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[BXT MIPI PATCH v2 01/13] drm/i915/bxt: Initialize MIPI for BXT

[Uma Shankar]

From: Shashank Sharma <shashank.sharma@intel.com>

This patch contains following changes:
1. Add BXT MIPI display address base.
2. Call dsi_init from display_setup function.

v2: Rebased on latest nightly branch

Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |    1 +
 drivers/gpu/drm/i915/intel_display.c |    3 +++
 drivers/gpu/drm/i915/intel_dsi.c     |    2 ++
 3 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e9a95df..de1eea4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1673,6 +1673,7 @@ enum skl_disp_power_wells {
 
 #define VLV_DISPLAY_BASE 0x180000
 #define VLV_MIPI_BASE VLV_DISPLAY_BASE
+#define BXT_MIPI_BASE 0x60000
 
 #define VLV_GU_CTL0	(VLV_DISPLAY_BASE + 0x2030)
 #define VLV_GU_CTL1	(VLV_DISPLAY_BASE + 0x2034)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index af0bcfe..52e21d4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14096,6 +14096,9 @@ static void intel_setup_outputs(struct drm_device *dev)
 		 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
 		 * detect the ports.
 		 */
+		/* Initialize MIPI for BXT */
+		intel_dsi_init(dev);
+
 		intel_ddi_init(dev, PORT_A);
 		intel_ddi_init(dev, PORT_B);
 		intel_ddi_init(dev, PORT_C);
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index f4438eb..d709da3 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -993,6 +993,8 @@ void intel_dsi_init(struct drm_device *dev)
 
 	if (IS_VALLEYVIEW(dev)) {
 		dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
+	} else if (IS_BROXTON(dev)) {
+		dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
 	} else {
 		DRM_ERROR("Unsupported Mipi device to reg base");
 		return;
-- 
1.7.9.5

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[BXT MIPI PATCH v2 02/13] drm/i915/bxt: Enable BXT DSI PLL

[Uma Shankar]

From: Shashank Sharma <shashank.sharma@intel.com>

This patch adds new functions for BXT clock and PLL programming.
They are:
1. configure_dsi_pll for BXT.
   This function does the basic math and generates the divider ratio
   based on requested pixclock, and program clock registers.
2. enable_dsi_pll function.
   This function programs the calculated clock values on the PLL.
3. intel_enable_dsi_pll
   Wrapper function to use same code for multiple platforms. It checks the
   platform and calls appropriate core pll enable function.

v2: Fixed Jani's review comments. Macros are adjusted as per convention.

Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |   25 ++++++++-
 drivers/gpu/drm/i915/intel_dsi.c     |    2 +-
 drivers/gpu/drm/i915/intel_dsi.h     |    2 +-
 drivers/gpu/drm/i915/intel_dsi_pll.c |   95 +++++++++++++++++++++++++++++++++-
 4 files changed, 119 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index de1eea4..0862018 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7443,10 +7443,31 @@ enum skl_disp_power_wells {
 #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
 #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
 
-/* MIPI DSI registers */
-
 #define _MIPI_PORT(port, a, c)	_PORT3(port, a, 0, c)	/* ports A and C only */
 
+/* MIPI DSI registers */
+#define BXT_DSI_PLL_CTL			0x161000
+#define  BXT_DSI_PLL_PVD_RATIO_SHIFT	16
+#define  BXT_DSI_PLL_PVD_RATIO_MASK	(3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
+#define  BXT_DSI_PLL_PVD_RATIO_1	(1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
+#define  BXT_DSIC_16X_BY2		(1 << 10)
+#define  BXT_DSIC_16X_BY3		(2 << 10)
+#define  BXT_DSIC_16X_BY4		(3 << 10)
+#define  BXT_DSIA_16X_BY2		(1 << 8)
+#define  BXT_DSIA_16X_BY3		(2 << 8)
+#define  BXT_DSIA_16X_BY4		(3 << 8)
+#define  BXT_DSI_FREQ_SEL_SHIFT		8
+#define  BXT_DSI_FREQ_SEL_MASK		(0xF << BXT_DSI_FREQ_SEL_SHIFT)
+
+#define BXT_DSI_PLL_RATIO_MAX		0x7D
+#define BXT_DSI_PLL_RATIO_MIN		0x22
+#define BXT_DSI_PLL_RATIO_MASK		0xFF
+#define BXT_REF_CLOCK_KHZ		19500
+
+#define BXT_DSI_PLL_ENABLE		0x46080
+#define  BXT_DSI_PLL_DO_ENABLE		(1 << 31)
+#define  BXT_DSI_PLL_LOCKED		(1 << 30)
+
 #define _MIPIA_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61190)
 #define _MIPIC_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61700)
 #define MIPI_PORT_CTRL(port)	_MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index d709da3..e201c0f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -898,8 +898,8 @@ static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
 	DRM_DEBUG_KMS("\n");
 
 	intel_dsi_prepare(encoder);
+	intel_enable_dsi_pll(encoder);
 
-	vlv_enable_dsi_pll(encoder);
 }
 
 static enum drm_connector_status
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 2784ac4..20cfcf07 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -121,7 +121,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
 	return container_of(encoder, struct intel_dsi, base.base);
 }
 
-extern void vlv_enable_dsi_pll(struct intel_encoder *encoder);
+extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
 extern void vlv_disable_dsi_pll(struct intel_encoder *encoder);
 extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index c6a8975..b07483b 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -246,7 +246,7 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
 	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl);
 }
 
-void vlv_enable_dsi_pll(struct intel_encoder *encoder)
+static void vlv_enable_dsi_pll(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 	u32 tmp;
@@ -363,3 +363,96 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
 
 	return pclk;
 }
+
+static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	u8 dsi_ratio;
+	u32 dsi_clk;
+	u32 val;
+
+	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
+			intel_dsi->lane_count);
+
+	/*
+	 * From clock diagram, to get PLL ratio divider, divide double of DSI
+	 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to
+	 * round 'up' the result
+	 */
+	dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
+	if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
+			dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
+		DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
+		return false;
+	}
+
+	/*
+	 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
+	 * Spec says both have to be programmed, even if one is not getting
+	 * used. Configure MIPI_CLOCK_CTL dividers in modeset
+	 */
+	val = I915_READ(BXT_DSI_PLL_CTL);
+	val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
+	val &= ~BXT_DSI_FREQ_SEL_MASK;
+	val &= ~BXT_DSI_PLL_RATIO_MASK;
+	val |= (dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2);
+
+	/* As per recommendation from hardware team,
+	 * Prog PVD ratio =1 if dsi ratio <= 50
+	 */
+	if (dsi_ratio <= 50) {
+		val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
+		val |= BXT_DSI_PLL_PVD_RATIO_1;
+	}
+
+	I915_WRITE(BXT_DSI_PLL_CTL, val);
+	POSTING_READ(BXT_DSI_PLL_CTL);
+
+	return true;
+}
+
+static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+	u32 val;
+
+	DRM_DEBUG_KMS("\n");
+
+	val = I915_READ(BXT_DSI_PLL_ENABLE);
+
+	if (val & BXT_DSI_PLL_DO_ENABLE) {
+		WARN(1, "DSI PLL already enabled. Disabling it.\n");
+		val &= ~BXT_DSI_PLL_DO_ENABLE;
+		I915_WRITE(BXT_DSI_PLL_ENABLE, val);
+	}
+
+	/* Configure PLL vales */
+	if (!bxt_configure_dsi_pll(encoder)) {
+		DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n");
+		return;
+	}
+
+	/* Enable DSI PLL */
+	val = I915_READ(BXT_DSI_PLL_ENABLE);
+	val |= BXT_DSI_PLL_DO_ENABLE;
+	I915_WRITE(BXT_DSI_PLL_ENABLE, val);
+
+	/* Timeout and fail if PLL not locked */
+	if (wait_for(I915_READ(BXT_DSI_PLL_ENABLE) & BXT_DSI_PLL_LOCKED, 1)) {
+		DRM_ERROR("Timed out waiting for DSI PLL to lock\n");
+		return;
+	}
+
+	DRM_DEBUG_KMS("DSI PLL locked\n");
+}
+
+void intel_enable_dsi_pll(struct intel_encoder *encoder)
+{
+	struct drm_device *dev = encoder->base.dev;
+
+	if (IS_VALLEYVIEW(dev))
+		vlv_enable_dsi_pll(encoder);
+	else if (IS_BROXTON(dev))
+		bxt_enable_dsi_pll(encoder);
+}
-- 
1.7.9.5

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[BXT MIPI PATCH v2 03/13] drm/i915/bxt: Disable DSI PLL for BXT

[Uma Shankar]

From: Shashank Sharma <shashank.sharma@intel.com>

This patch adds two new functions:
- disable_dsi_pll.
  BXT DSI disable sequence and registers are
  different from previous platforms.
- intel_disable_dsi_pll
  wrapper function to re-use the same code for
  multiple platforms. It checks platform type and
  calls appropriate core pll disable function.

v2: Fixed Jani's review comments.

Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c     |    2 +-
 drivers/gpu/drm/i915/intel_dsi.h     |    2 +-
 drivers/gpu/drm/i915/intel_dsi_pll.c |   32 +++++++++++++++++++++++++++++++-
 3 files changed, 33 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index e201c0f..544166f 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -548,7 +548,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 		usleep_range(2000, 2500);
 	}
 
-	vlv_disable_dsi_pll(encoder);
+	intel_disable_dsi_pll(encoder);
 }
 
 static void intel_dsi_post_disable(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 20cfcf07..759983e 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -122,7 +122,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
 }
 
 extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
-extern void vlv_disable_dsi_pll(struct intel_encoder *encoder);
+extern void intel_disable_dsi_pll(struct intel_encoder *encoder);
 extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
 
 struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index b07483b..f335e6c 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -276,7 +276,7 @@ static void vlv_enable_dsi_pll(struct intel_encoder *encoder)
 	DRM_DEBUG_KMS("DSI PLL locked\n");
 }
 
-void vlv_disable_dsi_pll(struct intel_encoder *encoder)
+static void vlv_disable_dsi_pll(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 	u32 tmp;
@@ -293,6 +293,26 @@ void vlv_disable_dsi_pll(struct intel_encoder *encoder)
 	mutex_unlock(&dev_priv->sb_lock);
 }
 
+static void bxt_disable_dsi_pll(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+	u32 val;
+
+	DRM_DEBUG_KMS("\n");
+
+	val = I915_READ(BXT_DSI_PLL_ENABLE);
+	val &= ~BXT_DSI_PLL_DO_ENABLE;
+	I915_WRITE(BXT_DSI_PLL_ENABLE, val);
+
+	/*
+	 * PLL lock should deassert within 200us.
+	 * Wait up to 1ms before timing out.
+	 */
+	if (wait_for((I915_READ(BXT_DSI_PLL_ENABLE)
+					& BXT_DSI_PLL_LOCKED) == 0, 1))
+		DRM_ERROR("Timeout waiting for PLL lock deassertion\n");
+}
+
 static void assert_bpp_mismatch(int pixel_format, int pipe_bpp)
 {
 	int bpp = dsi_pixel_format_bpp(pixel_format);
@@ -456,3 +476,13 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder)
 	else if (IS_BROXTON(dev))
 		bxt_enable_dsi_pll(encoder);
 }
+
+void intel_disable_dsi_pll(struct intel_encoder *encoder)
+{
+	struct drm_device *dev = encoder->base.dev;
+
+	if (IS_VALLEYVIEW(dev))
+		vlv_disable_dsi_pll(encoder);
+	else if (IS_BROXTON(dev))
+		bxt_disable_dsi_pll(encoder);
+}
-- 
1.7.9.5

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[BXT MIPI PATCH v2 04/13] drm/i915/bxt: DSI prepare changes for BXT

[Uma Shankar]

From: Shashank Sharma <shashank.sharma@intel.com>

This patch modifies dsi_prepare() function to support the same
modeset prepare sequence for BXT also. Main changes are:
1. BXT port control register is different than VLV.
2. BXT modeset sequence needs vdisplay and hdisplay programmed
   for transcoder.
3. BXT can select PIPE for MIPI transcoders.
4. BXT needs to program register MIPI_INIT_COUNT for both the ports,
   even if only one is being used.

v2: Fixed Jani's review comments. Rectified the DSI Macros to get
    proper register offsets using _MIPI_PORT instead of _TRANSCODER

Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |   21 ++++++++++++
 drivers/gpu/drm/i915/intel_dsi.c |   67 ++++++++++++++++++++++++++++++++------
 2 files changed, 78 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0862018..8796b25 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7445,6 +7445,22 @@ enum skl_disp_power_wells {
 
 #define _MIPI_PORT(port, a, c)	_PORT3(port, a, 0, c)	/* ports A and C only */
 
+/* BXT MIPI mode configure */
+#define  _BXT_MIPIA_TRANS_HACTIVE			0x6B0F8
+#define  _BXT_MIPIC_TRANS_HACTIVE			0x6B8F8
+#define  BXT_MIPI_TRANS_HACTIVE(tc)	_MIPI_PORT(tc, \
+		_BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
+
+#define  _BXT_MIPIA_TRANS_VACTIVE			0x6B0FC
+#define  _BXT_MIPIC_TRANS_VACTIVE			0x6B8FC
+#define  BXT_MIPI_TRANS_VACTIVE(tc)	_MIPI_PORT(tc, \
+		_BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
+
+#define  _BXT_MIPIA_TRANS_VTOTAL			0x6B100
+#define  _BXT_MIPIC_TRANS_VTOTAL			0x6B900
+#define  BXT_MIPI_TRANS_VTOTAL(tc)	_MIPI_PORT(tc, \
+		_BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
+
 /* MIPI DSI registers */
 #define BXT_DSI_PLL_CTL			0x161000
 #define  BXT_DSI_PLL_PVD_RATIO_SHIFT	16
@@ -7881,6 +7897,11 @@ enum skl_disp_power_wells {
 #define  READ_REQUEST_PRIORITY_HIGH			(3 << 3)
 #define  RGB_FLIP_TO_BGR				(1 << 2)
 
+#define  BXT_PIPE_SELECT_MASK				(7 << 7)
+#define  BXT_PIPE_SELECT_C				(2 << 7)
+#define  BXT_PIPE_SELECT_B				(1 << 7)
+#define  BXT_PIPE_SELECT_A				(0 << 7)
+
 #define _MIPIA_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb108)
 #define _MIPIC_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)
 #define MIPI_DATA_ADDRESS(port)		_MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 544166f..0b20534 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -721,6 +721,21 @@ static void set_dsi_timings(struct drm_encoder *encoder,
 	hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
 
 	for_each_dsi_port(port, intel_dsi->ports) {
+		if (IS_BROXTON(dev)) {
+			/*
+			 * Program hdisplay and vdisplay on MIPI transcoder.
+			 * This is different from calculated hactive and
+			 * vactive, as they are calculated per channel basis,
+			 * whereas these values should be based on resolution.
+			 */
+			I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
+					mode->hdisplay);
+			I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
+					mode->vdisplay);
+			I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
+					mode->vtotal);
+		}
+
 		I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
 		I915_WRITE(MIPI_HFP_COUNT(port), hfp);
 
@@ -761,16 +776,35 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 	}
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-		/* escape clock divider, 20MHz, shared for A and C.
-		 * device ready must be off when doing this! txclkesc? */
-		tmp = I915_READ(MIPI_CTRL(PORT_A));
-		tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
-		I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
-
-		/* read request priority is per pipe */
-		tmp = I915_READ(MIPI_CTRL(port));
-		tmp &= ~READ_REQUEST_PRIORITY_MASK;
-		I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
+		if (IS_VALLEYVIEW(dev)) {
+			/*
+			 * escape clock divider, 20MHz, shared for A and C.
+			 * device ready must be off when doing this! txclkesc?
+			 */
+			tmp = I915_READ(MIPI_CTRL(PORT_A));
+			tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
+			I915_WRITE(MIPI_CTRL(PORT_A), tmp |
+					ESCAPE_CLOCK_DIVIDER_1);
+
+			/* read request priority is per pipe */
+			tmp = I915_READ(MIPI_CTRL(port));
+			tmp &= ~READ_REQUEST_PRIORITY_MASK;
+			I915_WRITE(MIPI_CTRL(port), tmp |
+					READ_REQUEST_PRIORITY_HIGH);
+		} else if (IS_BROXTON(dev)) {
+			/*
+			 * FIXME:
+			 * BXT can connect any PIPE to any MIPI port.
+			 * Select the pipe based on the MIPI port read from
+			 * VBT for now. Pick PIPE A for MIPI port A and C
+			 * for port C.
+			 */
+			tmp = I915_READ(MIPI_CTRL(port));
+			tmp &= ~BXT_PIPE_SELECT_MASK;
+			(port == PORT_C) ? (tmp |= BXT_PIPE_SELECT_C) :
+				(tmp |= BXT_PIPE_SELECT_A);
+			I915_WRITE(MIPI_CTRL(port), tmp);
+		}
 
 		/* XXX: why here, why like this? handling in irq handler?! */
 		I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
@@ -847,6 +881,19 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
 		I915_WRITE(MIPI_INIT_COUNT(port),
 				txclkesc(intel_dsi->escape_clk_div, 100));
 
+		if (IS_BROXTON(dev)) {
+			if (!intel_dsi->dual_link) {
+				/*
+				 * BXT spec says write MIPI_INIT_COUNT for
+				 * both the ports, even if only one is
+				 * getting used. So write the other port
+				 * if not in dual link mode.
+				 */
+				I915_WRITE(MIPI_INIT_COUNT(port ==
+						PORT_A ? PORT_C : PORT_A),
+							intel_dsi->init_count);
+			}
+		}
 
 		/* recovery disables */
 		I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
-- 
1.7.9.5

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[BXT MIPI PATCH v2 05/13] drm/i915/bxt: DSI encoder support in CRTC modeset

[Uma Shankar]

From: Shashank Sharma <shashank.sharma@intel.com>

SKL and BXT qualifies the HAS_DDI() check, and hence haswell
modeset functions are re-used for modeset sequence. But DDI
interface doesn't include support for DSI.
This patch adds:
1. cases for DSI encoder, in those modeset functions and allows
   a CRTC modeset
2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
   needs to be done as such in CRTC for DSI encoder, as PLL, clock
   and and transcoder programming will be taken care in encoder's
   pre_enable and pre_pll_enable function.

v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
    encoder like DSI for platforms having HAS_DDI as true.

Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |    1 +
 drivers/gpu/drm/i915/intel_ddi.c      |   10 +++++++++-
 drivers/gpu/drm/i915/intel_display.c  |   19 ++++++++++++++-----
 drivers/gpu/drm/i915/intel_opregion.c |    3 ++-
 4 files changed, 26 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 23ce125e..04f746d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -142,6 +142,7 @@ enum plane {
 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
 
 enum port {
+	PORT_INVALID = -1,
 	PORT_A = 0,
 	PORT_B,
 	PORT_C,
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9a40bfb..2bad86e 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -310,6 +310,10 @@ static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
 	} else if (type == INTEL_OUTPUT_ANALOG) {
 		*dig_port = NULL;
 		*port = PORT_E;
+	} else if (type == INTEL_OUTPUT_DSI) {
+		*dig_port = NULL;
+		*port = PORT_INVALID;
+		DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
 	} else {
 		DRM_ERROR("Invalid DDI encoder type %d\n", type);
 		BUG();
@@ -565,6 +569,9 @@ void intel_prepare_ddi(struct drm_device *dev)
 
 		ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
 
+		if (port == PORT_INVALID)
+			continue;
+
 		if (visited[port])
 			continue;
 
@@ -2052,7 +2059,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
 {
 	struct drm_crtc *crtc = &intel_crtc->base;
-	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
 	enum port port = intel_ddi_get_encoder_port(intel_encoder);
 	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 52e21d4..db27995 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4904,6 +4904,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
 	int pipe = intel_crtc->pipe, hsw_workaround_pipe;
+	bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
 	struct intel_crtc_state *pipe_config =
 		to_intel_crtc_state(crtc->state);
 
@@ -4945,7 +4946,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 		dev_priv->display.fdi_link_train(crtc);
 	}
 
-	intel_ddi_enable_pipe_clock(intel_crtc);
+	if (!is_dsi)
+		intel_ddi_enable_pipe_clock(intel_crtc);
 
 	if (INTEL_INFO(dev)->gen == 9)
 		skylake_pfit_enable(intel_crtc);
@@ -4961,7 +4963,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	intel_crtc_load_lut(crtc);
 
 	intel_ddi_set_pipe_settings(crtc);
-	intel_ddi_enable_transcoder_func(crtc);
+	if (!is_dsi)
+		intel_ddi_enable_transcoder_func(crtc);
 
 	intel_update_watermarks(crtc);
 	intel_enable_pipe(intel_crtc);
@@ -4969,13 +4972,16 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
 	if (intel_crtc->config->has_pch_encoder)
 		lpt_pch_enable(crtc);
 
-	if (intel_crtc->config->dp_encoder_is_mst)
+	if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
 		intel_ddi_set_vc_payload_alloc(crtc, true);
 
 	assert_vblank_disabled(crtc);
 	drm_crtc_vblank_on(crtc);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder) {
+		if (encoder->pre_pll_enable)
+			encoder->pre_pll_enable(encoder);
+
 		encoder->enable(encoder);
 		intel_opregion_notify_encoder(encoder, true);
 	}
@@ -5065,6 +5071,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	struct intel_encoder *encoder;
 	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
+	bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
 
 	for_each_encoder_on_crtc(dev, crtc, encoder) {
 		intel_opregion_notify_encoder(encoder, false);
@@ -5082,7 +5089,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 	if (intel_crtc->config->dp_encoder_is_mst)
 		intel_ddi_set_vc_payload_alloc(crtc, false);
 
-	intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
+	if (!is_dsi)
+		intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
 
 	if (INTEL_INFO(dev)->gen == 9)
 		skylake_scaler_disable(intel_crtc);
@@ -5091,7 +5099,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
 	else
 		MISSING_CASE(INTEL_INFO(dev)->gen);
 
-	intel_ddi_disable_pipe_clock(intel_crtc);
+	if (!is_dsi)
+		intel_ddi_disable_pipe_clock(intel_crtc);
 
 	if (intel_crtc->config->has_pch_encoder) {
 		lpt_disable_pch_transcoder(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
index cb1c657..8182f67 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -342,7 +342,7 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
 		return 0;
 
 	port = intel_ddi_get_encoder_port(intel_encoder);
-	if (port == PORT_E) {
+	if ((port == PORT_E) || (port == PORT_INVALID)) {
 		port = 0;
 	} else {
 		parm |= 1 << port;
@@ -363,6 +363,7 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
 		type = DISPLAY_TYPE_EXTERNAL_FLAT_PANEL;
 		break;
 	case INTEL_OUTPUT_EDP:
+	case INTEL_OUTPUT_DSI:
 		type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL;
 		break;
 	default:
-- 
1.7.9.5

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[BXT MIPI PATCH v2 06/13] drm/i915/bxt: DSI enable for BXT

[Uma Shankar]

From: Shashank Sharma <shashank.sharma@intel.com>

This patch contains following changes:
1. MIPI device ready changes to support dsi_pre_enable. Changes
   are specific to BXT device ready sequence. Added check for
   ULPS mode(No effects on VLV).
2. Changes in dsi_enable to pick BXT port control register.
3. Changes in dsi_pre_enable to restrict DPIO programming for VLV

v2: Fixed Jani's review comments. Removed the changes in VLV/CHV
    code. Fixed the macros to get proper port offsets.

Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |    9 +++
 drivers/gpu/drm/i915/intel_dsi.c |  156 ++++++++++++++++++++++++++------------
 2 files changed, 115 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8796b25..7559062 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7487,6 +7487,15 @@ enum skl_disp_power_wells {
 #define _MIPIA_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61190)
 #define _MIPIC_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61700)
 #define MIPI_PORT_CTRL(port)	_MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
+
+ /* BXT port control */
+#define _BXT_MIPIA_PORT_CTRL				0x6B0C0
+#define _BXT_MIPIC_PORT_CTRL				0x6B8C0
+#define BXT_MIPI_PORT_CTRL(tc)	_MIPI_PORT(tc, _BXT_MIPIA_PORT_CTRL, \
+						_BXT_MIPIC_PORT_CTRL)
+#define GET_DSI_PORT_CTRL(dev) (IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) : \
+						MIPI_PORT_CTRL(port))
+
 #define  DPI_ENABLE					(1 << 31) /* A + C */
 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
 #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 0b20534..c5889c4 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -281,6 +281,85 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
 	return true;
 }
 
+static void bxt_dsi_device_ready(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 val;
+
+	DRM_DEBUG_KMS("\n");
+
+	/* Exit Low power state in 4 steps*/
+	for_each_dsi_port(port, intel_dsi->ports) {
+
+		/* 1. Enable MIPI PHY transparent latch */
+		val = I915_READ(BXT_MIPI_PORT_CTRL(port));
+		I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
+		usleep_range(2000, 2500);
+
+		/* 2. Enter ULPS */
+		val = I915_READ(MIPI_DEVICE_READY(port));
+		val &= ~ULPS_STATE_MASK;
+		val |= (ULPS_STATE_ENTER | DEVICE_READY);
+		I915_WRITE(MIPI_DEVICE_READY(port), val);
+		usleep_range(2, 3);
+
+		/* 3. Exit ULPS */
+		val = I915_READ(MIPI_DEVICE_READY(port));
+		val &= ~ULPS_STATE_MASK;
+		val |= (ULPS_STATE_EXIT | DEVICE_READY);
+		I915_WRITE(MIPI_DEVICE_READY(port), val);
+		usleep_range(1000, 1500);
+
+		/* Clear ULPS and set device ready */
+		val = I915_READ(MIPI_DEVICE_READY(port));
+		val &= ~ULPS_STATE_MASK;
+		val |= DEVICE_READY;
+		I915_WRITE(MIPI_DEVICE_READY(port), val);
+	}
+}
+
+static void vlv_dsi_device_ready(struct intel_encoder *encoder)
+{
+	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
+	u32 val;
+
+	DRM_DEBUG_KMS("\n");
+
+	mutex_lock(&dev_priv->sb_lock);
+	/* program rcomp for compliance, reduce from 50 ohms to 45 ohms
+	 * needed everytime after power gate */
+	vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
+	mutex_unlock(&dev_priv->sb_lock);
+
+	/* bandgap reset is needed after everytime we do power gate */
+	band_gap_reset(dev_priv);
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+
+		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
+		usleep_range(2500, 3000);
+
+		/* Enable MIPI PHY transparent latch
+		 * Common bit for both MIPI Port A & MIPI Port C
+		 * No similar bit in MIPI Port C reg
+		 */
+		val = I915_READ(MIPI_PORT_CTRL(PORT_A));
+		I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
+		usleep_range(1000, 1500);
+
+		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
+		usleep_range(2500, 3000);
+
+		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
+		usleep_range(2500, 3000);
+	}
+}
+
+
 static void intel_dsi_port_enable(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
@@ -289,6 +368,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	enum port port;
 	u32 temp;
+	u32 port_ctrl;
 
 	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 		temp = I915_READ(VLV_CHICKEN_3);
@@ -299,7 +379,9 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
 	}
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-		temp = I915_READ(MIPI_PORT_CTRL(port));
+		port_ctrl = GET_DSI_PORT_CTRL(dev);
+		temp = I915_READ(port_ctrl);
+
 		temp &= ~LANE_CONFIGURATION_MASK;
 		temp &= ~DUAL_LINK_MODE_MASK;
 
@@ -311,8 +393,8 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
 					LANE_CONFIGURATION_DUAL_LINK_A;
 		}
 		/* assert ip_tg_enable signal */
-		I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
-		POSTING_READ(MIPI_PORT_CTRL(port));
+		I915_WRITE(port_ctrl, temp | DPI_ENABLE);
+		POSTING_READ(port_ctrl);
 	}
 }
 
@@ -334,41 +416,12 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
 
 static void intel_dsi_device_ready(struct intel_encoder *encoder)
 {
-	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
-	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
-	enum port port;
-	u32 val;
-
-	DRM_DEBUG_KMS("\n");
-
-	mutex_lock(&dev_priv->sb_lock);
-	/* program rcomp for compliance, reduce from 50 ohms to 45 ohms
-	 * needed everytime after power gate */
-	vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
-	mutex_unlock(&dev_priv->sb_lock);
-
-	/* bandgap reset is needed after everytime we do power gate */
-	band_gap_reset(dev_priv);
-
-	for_each_dsi_port(port, intel_dsi->ports) {
-
-		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
-		usleep_range(2500, 3000);
-
-		/* Enable MIPI PHY transparent latch
-		 * Common bit for both MIPI Port A & MIPI Port C
-		 * No similar bit in MIPI Port C reg
-		 */
-		val = I915_READ(MIPI_PORT_CTRL(PORT_A));
-		I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
-		usleep_range(1000, 1500);
-
-		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
-		usleep_range(2500, 3000);
+	struct drm_device *dev = encoder->base.dev;
 
-		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
-		usleep_range(2500, 3000);
-	}
+	if (IS_VALLEYVIEW(dev))
+		vlv_dsi_device_ready(encoder);
+	else if (IS_BROXTON(dev))
+		bxt_dsi_device_ready(encoder);
 }
 
 static void intel_dsi_enable(struct intel_encoder *encoder)
@@ -410,19 +463,22 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
 
 	DRM_DEBUG_KMS("\n");
 
-	/* Disable DPOunit clock gating, can stall pipe
-	 * and we need DPLL REFA always enabled */
-	tmp = I915_READ(DPLL(pipe));
-	tmp |= DPLL_REF_CLK_ENABLE_VLV;
-	I915_WRITE(DPLL(pipe), tmp);
-
-	/* update the hw state for DPLL */
-	intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
-		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
-
-	tmp = I915_READ(DSPCLK_GATE_D);
-	tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
-	I915_WRITE(DSPCLK_GATE_D, tmp);
+	if (IS_VALLEYVIEW(dev)) {
+		/* Disable DPOunit clock gating, can stall pipe
+		 * and we need DPLL REFA always enabled */
+		tmp = I915_READ(DPLL(pipe));
+		tmp |= DPLL_REF_CLK_ENABLE_VLV;
+		I915_WRITE(DPLL(pipe), tmp);
+
+		/* update the hw state for DPLL */
+		intel_crtc->config->dpll_hw_state.dpll =
+			DPLL_INTEGRATED_REF_CLK_VLV |
+			DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
+
+		tmp = I915_READ(DSPCLK_GATE_D);
+		tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
+		I915_WRITE(DSPCLK_GATE_D, tmp);
+	}
 
 	/* put device in ready state */
 	intel_dsi_device_ready(encoder);
-- 
1.7.9.5

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[BXT MIPI PATCH v2 07/13] drm/i915/bxt: Program Tx Rx and Dphy clocks

[Uma Shankar]

From: Shashank Sharma <shashank.sharma@intel.com>

BXT DSI clocks are different than previous platforms. So adding a
new function to program following clocks and dividers:
1. Program variable divider to generate input to Tx clock divider
   (Output value must be < 39.5Mhz)
2. Select divide by 2 option to get < 20Mhz for Tx clock
3. Program 8by3 divider to generate Rx clock

v2: Fixed Jani's review comments. Adjusted the Macro defintion as
    per convention. Simplified the logic for bit definitions for
    MIPI PORT A and PORT C in same registers.

Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |   40 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_dsi_pll.c |   41 ++++++++++++++++++++++++++++++++++
 2 files changed, 81 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7559062..310afd4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7445,6 +7445,46 @@ enum skl_disp_power_wells {
 
 #define _MIPI_PORT(port, a, c)	_PORT3(port, a, 0, c)	/* ports A and C only */
 
+/* BXT MIPI clock controls */
+#define BXT_MAX_VAR_OUTPUT_KHZ			39500
+
+#define BXT_MIPI_CLOCK_CTL			0x46090
+#define  BXT_MIPI_DIV_SHIFT			16
+/* Var clock divider to generate TX source. Result must be < 39.5 M */
+#define  BXT_MIPI1_ESCLK_VAR_DIV_MASK		(0x3F << 26)
+#define  BXT_MIPI2_ESCLK_VAR_DIV_MASK		(0x3F << 10)
+#define  BXT_MIPI_ESCLK_VAR_DIV_MASK(port)	\
+		(0x3F << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 10))
+#define  BXT_MIPI_ESCLK_VAR_DIV(port, val)            \
+		(val << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 10))
+/* TX control divider to select actual TX clock output from (8x/var) */
+#define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK		(3 << 21)
+#define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK		(3 << 5)
+#define  BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)	\
+		(3 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 5))
+#define  BXT_MIPI_TX_ESCLK_8XDIV_BY2(port)	\
+		(0x0 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 5))
+#define  BXT_MIPI_TX_ESCLK_8XDIV_BY4(port)	\
+		(0x1 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 5))
+#define  BXT_MIPI_TX_ESCLK_8XDIV_BY8(port)	\
+		(0x2 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 5))
+/* RX control divider to select actual RX clock output from 8x*/
+#define  BXT_MIPI1_RX_ESCLK_FIXDIV_MASK		(3 << 19)
+#define  BXT_MIPI2_RX_ESCLK_FIXDIV_MASK		(3 << 3)
+#define  BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port)	\
+		(3 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 3))
+#define  BXT_MIPI_RX_ESCLK_8X_BY2(port)	\
+		(1 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 3))
+#define  BXT_MIPI_RX_ESCLK_8X_BY3(port)	\
+		(2 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 3))
+#define  BXT_MIPI_RX_ESCLK_8X_BY4(port)	\
+		(3 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 3))
+/* BXT: Always prog DPHY dividers to 00 */
+#define  BXT_MIPI_1_DPHY_DIVIDER_MASK		(3 << 16)
+#define  BXT_MIPI_2_DPHY_DIVIDER_MASK		(3 << 0)
+#define  BXT_MIPI_DPHY_DIVIDER_MASK(port)	\
+		(3 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT))
+
 /* BXT MIPI mode configure */
 #define  _BXT_MIPIA_TRANS_HACTIVE			0x6B0F8
 #define  _BXT_MIPIC_TRANS_HACTIVE			0x6B8F8
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index f335e6c..0b74399 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -384,6 +384,41 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
 	return pclk;
 }
 
+/* Program BXT Mipi clocks and dividers */
+static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
+{
+	u32 tmp;
+	u32 divider;
+	u32 dsi_rate;
+	u32 pll_ratio;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/* Clear old configurations */
+	tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
+	tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
+	tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
+	tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
+	tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
+
+	/* Get the current DSI rate(actual) */
+	pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
+				BXT_DSI_PLL_RATIO_MASK;
+	dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
+
+	/* Max possible output of clock is 39.5 MHz, program value -1 */
+	divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
+	tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
+
+	/* Tx escape clock should be >=20MHz, so select divide by 2 */
+	tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
+
+	/* Rx escape clock, select fix divide by 3 clock */
+	tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
+
+	/* Do the honors */
+	I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
+}
+
 static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
@@ -435,6 +470,8 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
 static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	enum port port;
 	u32 val;
 
 	DRM_DEBUG_KMS("\n");
@@ -453,6 +490,10 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
 		return;
 	}
 
+	/* Now program TX, RX, Dphy clocks */
+	for_each_dsi_port(port, intel_dsi->ports)
+		bxt_dsi_program_clocks(encoder->base.dev, port);
+
 	/* Enable DSI PLL */
 	val = I915_READ(BXT_DSI_PLL_ENABLE);
 	val |= BXT_DSI_PLL_DO_ENABLE;
-- 
1.7.9.5

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[BXT MIPI PATCH v2 08/13] drm/i915/bxt: DSI disable and post-disable

[Uma Shankar]

From: Shashank Sharma <shashank.sharma@intel.com>

This patch contains changes to support DSI disble sequence in BXT.
The changes are:
1. BXT specific changes in clear_device_ready function.
2. BXT specific changes in DSI disable and post-disable functions.
3. Add a new function to reset BXT Dphy clock and dividers
   (bxt_dsi_reset_clocks).
4. Moved some part of the vlv clock reset code, in a new function
   (vlv_dsi_reset_clocks) maintaining the exact same sequence.
5. Wrapper function to call corresponding reset clock function.

v2: Fixed Jani's review comments.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c     |   35 ++++++++++++++++--------------
 drivers/gpu/drm/i915/intel_dsi.h     |    2 ++
 drivers/gpu/drm/i915/intel_dsi_pll.c |   39 ++++++++++++++++++++++++++++++++++
 3 files changed, 60 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index c5889c4..5b8af80 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -405,12 +405,14 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	enum port port;
 	u32 temp;
+	u32 port_ctrl;
 
 	for_each_dsi_port(port, intel_dsi->ports) {
 		/* de-assert ip_tg_enable signal */
-		temp = I915_READ(MIPI_PORT_CTRL(port));
-		I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
-		POSTING_READ(MIPI_PORT_CTRL(port));
+		port_ctrl = GET_DSI_PORT_CTRL(dev);
+		temp = I915_READ(port_ctrl);
+		I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
+		POSTING_READ(port_ctrl);
 	}
 }
 
@@ -542,12 +544,7 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 		/* Panel commands can be sent when clock is in LP11 */
 		I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
 
-		temp = I915_READ(MIPI_CTRL(port));
-		temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
-		I915_WRITE(MIPI_CTRL(port), temp |
-			   intel_dsi->escape_clk_div <<
-			   ESCAPE_CLOCK_DIVIDER_SHIFT);
-
+		intel_dsi_reset_clocks(encoder, port);
 		I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
 
 		temp = I915_READ(MIPI_DSI_FUNC_PRG(port));
@@ -566,10 +563,12 @@ static void intel_dsi_disable(struct intel_encoder *encoder)
 
 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 {
+	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	enum port port;
 	u32 val;
+	u32 port_ctrl = 0;
 
 	DRM_DEBUG_KMS("\n");
 	for_each_dsi_port(port, intel_dsi->ports) {
@@ -586,18 +585,22 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 							ULPS_STATE_ENTER);
 		usleep_range(2000, 2500);
 
+		if (IS_BROXTON(dev))
+			port_ctrl = BXT_MIPI_PORT_CTRL(port);
+		else if (IS_VALLEYVIEW(dev))
+			/* Common bit for both MIPI Port A & MIPI Port C */
+			port_ctrl = MIPI_PORT_CTRL(PORT_A);
+
 		/* Wait till Clock lanes are in LP-00 state for MIPI Port A
 		 * only. MIPI Port C has no similar bit for checking
 		 */
-		if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT)
-							== 0x00000), 30))
+		if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT)
+						== 0x00000), 30))
 			DRM_ERROR("DSI LP not going Low\n");
 
-		/* Disable MIPI PHY transparent latch
-		 * Common bit for both MIPI Port A & MIPI Port C
-		 */
-		val = I915_READ(MIPI_PORT_CTRL(PORT_A));
-		I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD);
+		/* Disable MIPI PHY transparent latch */
+		val = I915_READ(port_ctrl);
+		I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
 		usleep_range(1000, 1500);
 
 		I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 759983e..078ea1b 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -124,6 +124,8 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
 extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
 extern void intel_disable_dsi_pll(struct intel_encoder *encoder);
 extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
+extern void intel_dsi_reset_clocks(struct intel_encoder *encoder,
+							enum port port);
 
 struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index 0b74399..cdf9c9b 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -384,6 +384,19 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
 	return pclk;
 }
 
+void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
+{
+	u32 temp;
+	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+
+	temp = I915_READ(MIPI_CTRL(port));
+	temp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
+	I915_WRITE(MIPI_CTRL(port), temp |
+			intel_dsi->escape_clk_div <<
+			ESCAPE_CLOCK_DIVIDER_SHIFT);
+}
+
 /* Program BXT Mipi clocks and dividers */
 static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
 {
@@ -527,3 +540,29 @@ void intel_disable_dsi_pll(struct intel_encoder *encoder)
 	else if (IS_BROXTON(dev))
 		bxt_disable_dsi_pll(encoder);
 }
+
+void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
+{
+	u32 tmp;
+	struct drm_device *dev = encoder->base.dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+
+	/* Clear old configurations */
+	tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
+	tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
+	tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
+	tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
+	tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
+	I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
+	I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
+}
+
+void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
+{
+	struct drm_device *dev = encoder->base.dev;
+
+	if (IS_BROXTON(dev))
+		bxt_dsi_reset_clocks(encoder, port);
+	else if (IS_VALLEYVIEW(dev))
+		vlv_dsi_reset_clocks(encoder, port);
+}
-- 
1.7.9.5

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[BXT MIPI PATCH v2 09/13] drm/i915/bxt: get_hw_state for BXT

[Uma Shankar]

From: Shashank Sharma <shashank.sharma@intel.com>

Pick appropriate port control register (BXT or VLV), based on device.
Get the current hw state wrt Mipi port.

v2: Rebased on latest drm nightly branch.

Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 5b8af80..aadd669 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -639,7 +639,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	struct drm_device *dev = encoder->base.dev;
 	enum intel_display_power_domain power_domain;
-	u32 dpi_enabled, func;
+	u32 dpi_enabled, func, ctrl_reg;
 	enum port port;
 
 	DRM_DEBUG_KMS("\n");
@@ -651,8 +651,8 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 	/* XXX: this only works for one DSI output */
 	for_each_dsi_port(port, intel_dsi->ports) {
 		func = I915_READ(MIPI_DSI_FUNC_PRG(port));
-		dpi_enabled = I915_READ(MIPI_PORT_CTRL(port)) &
-							DPI_ENABLE;
+		ctrl_reg = GET_DSI_PORT_CTRL(dev);
+		dpi_enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
 
 		/* Due to some hardware limitations on BYT, MIPI Port C DPI
 		 * Enable bit does not get set. To check whether DSI Port C
-- 
1.7.9.5

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[BXT MIPI PATCH v2 10/13] drm/i915/bxt: get DSI pixelclock

[Uma Shankar]

From: Shashank Sharma <shashank.sharma@intel.com>

BXT's DSI PLL is different from that of VLV. So this patch
adds a new function to get the current DSI pixel clock based
on the PLL divider ratio and lane count.

This function is required for intel_dsi_get_config() function.

v2: Fixed Jani's review comments.

Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c     |    8 ++++++--
 drivers/gpu/drm/i915/intel_dsi.h     |    1 +
 drivers/gpu/drm/i915/intel_dsi_pll.c |   35 ++++++++++++++++++++++++++++++++++
 3 files changed, 42 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index aadd669..350e10a 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -677,7 +677,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 static void intel_dsi_get_config(struct intel_encoder *encoder,
 				 struct intel_crtc_state *pipe_config)
 {
-	u32 pclk;
+	u32 pclk = 0;
 	DRM_DEBUG_KMS("\n");
 
 	/*
@@ -686,7 +686,11 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
 	 */
 	pipe_config->dpll_hw_state.dpll_md = 0;
 
-	pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
+	if (IS_BROXTON(encoder->base.dev))
+		pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
+	else if (IS_VALLEYVIEW(encoder->base.dev))
+		pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp);
+
 	if (!pclk)
 		return;
 
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 078ea1b..24fc550 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -124,6 +124,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
 extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
 extern void intel_disable_dsi_pll(struct intel_encoder *encoder);
 extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
+extern u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
 extern void intel_dsi_reset_clocks(struct intel_encoder *encoder,
 							enum port port);
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
index cdf9c9b..b647f13 100644
--- a/drivers/gpu/drm/i915/intel_dsi_pll.c
+++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -384,6 +384,41 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
 	return pclk;
 }
 
+u32 bxt_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
+{
+	u32 pclk;
+	u32 dsi_clk;
+	u32 dsi_ratio;
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
+
+	/* Divide by zero */
+	if (!pipe_bpp) {
+		DRM_ERROR("Invalid BPP(0)\n");
+		return 0;
+	}
+
+	dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) &
+				BXT_DSI_PLL_RATIO_MASK;
+
+	/* Invalid DSI ratio ? */
+	if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
+			dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
+		DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio);
+		return 0;
+	}
+
+	dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2;
+
+	/* pixel_format and pipe_bpp should agree */
+	assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp);
+
+	pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp);
+
+	DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk);
+	return pclk;
+}
+
 void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port)
 {
 	u32 temp;
-- 
1.7.9.5

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[BXT MIPI PATCH v2 11/13] drm/i915/bxt: Modify BXT BLC according to VBT changes

[Uma Shankar]

From: Sunil Kamath <sunil.kamath@intel.com>

Latest VBT mentions which set of registers will be used for BLC,
as controller number field. Making use of this field in BXT
BLC implementation. Also, the registers are used in case control
pin indicates display DDI. Adding a check for this.
According to Bspec, BLC_PWM_*_2 uses the display utility pin for output.
To use backlight 2, enable the utility pin with mode = PWM
   v2: Jani's review comments
   addressed
       - Add a prefix _ to BXT BLC registers definitions.
       - Add "bxt only" comment for u8 controller
       - Remove control_pin check for DDI controller
       - Check for valid controller values
       - Set pipe bits in UTIL_PIN_CTL
       - Enable/Disable UTIL_PIN_CTL in enable/disable_backlight()
       - If BLC 2 is used, read active_low_pwm from UTIL_PIN polarity
   Satheesh's review comment addressed
       - If UTIL PIN is already enabled, BIOS would have programmed it. No
       need to disable and enable again.
   v3: Jani's review comments
       - add UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK
       - Disable UTIL_PIN if controller 1 is used
       - Mask out UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK before enabling
       UTIL_PIN
       - check valid controller value in intel_bios.c
       - add backlight.util_pin_active_low
       - disable util pin before enabling
   v4: Change for BXT-PO branch:
   Stubbed unwanted definition which was existing before
   because of DC6 patch.
   UTIL_PIN_MODE_PWM     (0x1b << 24)

v2: Fixed Jani's review comment.

Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Sunil Kamath <sunil.kamath@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h    |   27 ++++++++---
 drivers/gpu/drm/i915/intel_drv.h   |    2 +
 drivers/gpu/drm/i915/intel_panel.c |   94 +++++++++++++++++++++++++++++-------
 3 files changed, 100 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 310afd4..0b1d7ff 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3553,17 +3553,29 @@ enum skl_disp_power_wells {
 #define UTIL_PIN_CTL		0x48400
 #define   UTIL_PIN_ENABLE	(1 << 31)
 
+#define   UTIL_PIN_PIPE(x)     ((x) << 29)
+#define   UTIL_PIN_PIPE_MASK   (3 << 29)
+#define   UTIL_PIN_MODE_PWM    (1 << 24)
+#define   UTIL_PIN_MODE_MASK   (0xf << 24)
+#define   UTIL_PIN_POLARITY    (1 << 22)
+
 /* BXT backlight register definition. */
-#define BXT_BLC_PWM_CTL1			0xC8250
+#define _BXT_BLC_PWM_CTL1			0xC8250
 #define   BXT_BLC_PWM_ENABLE			(1 << 31)
 #define   BXT_BLC_PWM_POLARITY			(1 << 29)
-#define BXT_BLC_PWM_FREQ1			0xC8254
-#define BXT_BLC_PWM_DUTY1			0xC8258
+#define _BXT_BLC_PWM_FREQ1			0xC8254
+#define _BXT_BLC_PWM_DUTY1			0xC8258
 
-#define BXT_BLC_PWM_CTL2			0xC8350
-#define BXT_BLC_PWM_FREQ2			0xC8354
-#define BXT_BLC_PWM_DUTY2			0xC8358
+#define _BXT_BLC_PWM_CTL2			0xC8350
+#define _BXT_BLC_PWM_FREQ2			0xC8354
+#define _BXT_BLC_PWM_DUTY2			0xC8358
 
+#define BXT_BLC_PWM_CTL(controller)    _PIPE(controller, \
+					_BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
+#define BXT_BLC_PWM_FREQ(controller)   _PIPE(controller, \
+					_BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
+#define BXT_BLC_PWM_DUTY(controller)   _PIPE(controller, \
+					_BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
 
 #define PCH_GTC_CTL		0xe7000
 #define   PCH_GTC_ENABLE	(1 << 31)
@@ -7280,6 +7292,9 @@ enum skl_disp_power_wells {
 #define  BXT_CDCLK_CD2X_DIV_SEL_4	(3<<22)
 #define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1<<16)
 
+/* Max CDCLK freq for BXT in HZ */
+#define BXT_CDCLK_MAX			624000000
+
 /* LCPLL_CTL */
 #define LCPLL1_CTL		0x46010
 #define LCPLL2_CTL		0x46014
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 3b00d00..8111a21 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -177,7 +177,9 @@ struct intel_panel {
 		bool enabled;
 		bool combination_mode;	/* gen 2/4 only */
 		bool active_low_pwm;
+		bool util_pin_active_low;	/* bxt+ */
 		struct backlight_device *device;
+		u8 controller;		/* bxt+ only */
 	} backlight;
 
 	void (*backlight_power)(struct intel_connector *, bool enable);
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 55aad23..2a97e5c 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -539,9 +539,10 @@ static u32 vlv_get_backlight(struct intel_connector *connector)
 static u32 bxt_get_backlight(struct intel_connector *connector)
 {
 	struct drm_device *dev = connector->base.dev;
+	struct intel_panel *panel = &connector->panel;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	return I915_READ(BXT_BLC_PWM_DUTY1);
+	return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller));
 }
 
 static u32 intel_panel_get_backlight(struct intel_connector *connector)
@@ -628,8 +629,9 @@ static void bxt_set_backlight(struct intel_connector *connector, u32 level)
 {
 	struct drm_device *dev = connector->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_panel *panel = &connector->panel;
 
-	I915_WRITE(BXT_BLC_PWM_DUTY1, level);
+	I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller), level);
 }
 
 static void
@@ -761,12 +763,20 @@ static void bxt_disable_backlight(struct intel_connector *connector)
 {
 	struct drm_device *dev = connector->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 tmp;
+	struct intel_panel *panel = &connector->panel;
+	u32 tmp, val;
 
 	intel_panel_actually_set_backlight(connector, 0);
 
-	tmp = I915_READ(BXT_BLC_PWM_CTL1);
-	I915_WRITE(BXT_BLC_PWM_CTL1, tmp & ~BXT_BLC_PWM_ENABLE);
+	tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+			tmp & ~BXT_BLC_PWM_ENABLE);
+
+	if (panel->backlight.controller == 1) {
+		val = I915_READ(UTIL_PIN_CTL);
+		val &= ~UTIL_PIN_ENABLE;
+		I915_WRITE(UTIL_PIN_CTL, val);
+	}
 }
 
 void intel_panel_disable_backlight(struct intel_connector *connector)
@@ -988,16 +998,39 @@ static void bxt_enable_backlight(struct intel_connector *connector)
 	struct drm_device *dev = connector->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_panel *panel = &connector->panel;
-	u32 pwm_ctl;
+	enum pipe pipe = intel_get_pipe_from_connector(connector);
+	u32 pwm_ctl, val;
+
+	/* To use 2nd set of backlight registers, utility pin has to be
+	 * enabled with PWM mode.
+	 * The field should only be changed when the utility pin is disabled
+	 */
+	if (panel->backlight.controller == 1) {
+		val = I915_READ(UTIL_PIN_CTL);
+		if (val & UTIL_PIN_ENABLE) {
+			DRM_DEBUG_KMS("util pin already enabled\n");
+			val &= ~UTIL_PIN_ENABLE;
+			I915_WRITE(UTIL_PIN_CTL, val);
+		}
+		/* mask out UTIL_PIN_PIPE and UTIL_PIN_MODE */
+		val &= ~(UTIL_PIN_PIPE_MASK | UTIL_PIN_MODE_MASK);
+		I915_WRITE(UTIL_PIN_CTL, val);
+		if (panel->backlight.util_pin_active_low)
+			val |= UTIL_PIN_POLARITY;
+		I915_WRITE(UTIL_PIN_CTL, val | UTIL_PIN_PIPE(pipe) |
+				UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE);
+	}
 
-	pwm_ctl = I915_READ(BXT_BLC_PWM_CTL1);
+	pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
 	if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
 		DRM_DEBUG_KMS("backlight already enabled\n");
 		pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
-		I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl);
+		I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+				pwm_ctl);
 	}
 
-	I915_WRITE(BXT_BLC_PWM_FREQ1, panel->backlight.max);
+	I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
+			panel->backlight.max);
 
 	intel_panel_actually_set_backlight(connector, panel->backlight.level);
 
@@ -1005,9 +1038,10 @@ static void bxt_enable_backlight(struct intel_connector *connector)
 	if (panel->backlight.active_low_pwm)
 		pwm_ctl |= BXT_BLC_PWM_POLARITY;
 
-	I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl);
-	POSTING_READ(BXT_BLC_PWM_CTL1);
-	I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl | BXT_BLC_PWM_ENABLE);
+	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
+	POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
+			pwm_ctl | BXT_BLC_PWM_ENABLE);
 }
 
 void intel_panel_enable_backlight(struct intel_connector *connector)
@@ -1370,12 +1404,38 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
 	struct intel_panel *panel = &connector->panel;
 	u32 pwm_ctl, val;
 
-	pwm_ctl = I915_READ(BXT_BLC_PWM_CTL1);
-	panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
+	/* For BXT hard coding the Backlight controller to 0.
+	 * TODO : Read the controller value from VBT and generalize
+	 */
+	panel->backlight.controller = 0;
 
-	panel->backlight.max = I915_READ(BXT_BLC_PWM_FREQ1);
-	if (!panel->backlight.max)
-		return -ENODEV;
+	pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
+
+	/* Keeping the check if controller 1 is to be programmed.
+	 * This will come into affect once the VBT parsing
+	 * is fixed for controller selection, and controller 1 is used
+	 * for a prticular display configuration.
+	 */
+	if (panel->backlight.controller == 1) {
+		val = I915_READ(UTIL_PIN_CTL);
+		panel->backlight.util_pin_active_low =
+					val & UTIL_PIN_POLARITY;
+	}
+
+	panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
+	panel->backlight.max = I915_READ(
+			BXT_BLC_PWM_FREQ(panel->backlight.controller));
+
+	if (!panel->backlight.max) {
+		DRM_DEBUG_KMS("PWM freq not programmed by BIOS\n");
+		DRM_DEBUG_KMS("Programming PWM freq\n");
+
+		/* Max Backlight = Max CD Clock / pwm freq) */
+		panel->backlight.max = (BXT_CDCLK_MAX /
+				dev_priv->vbt.backlight.pwm_freq_hz);
+		I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
+				panel->backlight.max);
+	}
 
 	val = bxt_get_backlight(connector);
 	panel->backlight.level = intel_panel_compute_brightness(connector, val);
-- 
1.7.9.5

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[BXT MIPI PATCH v2 12/13] drm/i915/bxt: Remove DSP CLK_GATE programming for BXT

[Uma Shankar]

DSP CLK_GATE registers are specific to BYT and CHT.
Avoid programming the same for BXT platform.

v2: Rebased on latest drm nightly branch.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |    9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 350e10a..d0b26c8 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -612,6 +612,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 
 static void intel_dsi_post_disable(struct intel_encoder *encoder)
 {
+	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	u32 val;
@@ -622,9 +623,11 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder)
 
 	intel_dsi_clear_device_ready(encoder);
 
-	val = I915_READ(DSPCLK_GATE_D);
-	val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
-	I915_WRITE(DSPCLK_GATE_D, val);
+	if (!IS_BROXTON(dev)) {
+		val = I915_READ(DSPCLK_GATE_D);
+		val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
+		I915_WRITE(DSPCLK_GATE_D, val);
+	}
 
 	drm_panel_unprepare(intel_dsi->panel);
 
-- 
1.7.9.5

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[BXT MIPI PATCH v2 13/13] drm/i915: Added BXT DSI backlight support

[Uma Shankar]

DSI backlight support for bxt is added.

TODO: There is no support for backlight control in drm panel
      framework. This will be added as part of VBT version patches
      fixing the backlight sequence.

v2: Fixed Jani's review comments from previous patch. Added the
    BXT DSI backlight code in this patch. Backlight setup and
    enable/disable code for backlight is added in intel_dsi.c.

Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/intel_dsi.c |   25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index d0b26c8..36fcb86 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -431,6 +431,7 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	struct intel_connector *intel_connector = intel_dsi->attached_connector;
 	enum port port;
 
 	DRM_DEBUG_KMS("\n");
@@ -451,6 +452,16 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
 
 		intel_dsi_port_enable(encoder);
 	}
+
+	if (IS_BROXTON(dev)) {
+		if (intel_dsi->backlight_on_delay >= 20)
+			msleep(intel_dsi->backlight_on_delay);
+		else
+			usleep_range(intel_dsi->backlight_on_delay * 1000,
+					(intel_dsi->backlight_on_delay * 1000) + 500);
+
+		intel_panel_enable_backlight(intel_connector);
+	}
 }
 
 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
@@ -615,10 +626,20 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder)
 	struct drm_device *dev = encoder->base.dev;
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	struct intel_connector *intel_connector = intel_dsi->attached_connector;
 	u32 val;
 
 	DRM_DEBUG_KMS("\n");
 
+	if (IS_BROXTON(dev)) {
+		intel_panel_disable_backlight(intel_connector);
+		if (intel_dsi->backlight_off_delay >= 20)
+			msleep(intel_dsi->backlight_off_delay);
+		else
+			usleep_range(intel_dsi->backlight_off_delay * 1000,
+				(intel_dsi->backlight_off_delay * 1000) + 500);
+	}
+
 	intel_dsi_disable(encoder);
 
 	intel_dsi_clear_device_ready(encoder);
@@ -1213,9 +1234,11 @@ void intel_dsi_init(struct drm_device *dev)
 	}
 
 	intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
+	if (IS_BROXTON(dev))
+		intel_panel_setup_backlight(connector,
+			intel_encoder->crtc_mask == (1 << PIPE_A) ? PIPE_A : PIPE_B);
 
 	return;
-
 err:
 	drm_encoder_cleanup(&intel_encoder->base);
 	kfree(intel_dsi);
-- 
1.7.9.5

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Re: [BXT MIPI PATCH v2 03/13] drm/i915/bxt: Disable DSI PLL for BXT

[Daniel Vetter]

On Sun, Jul 26, 2015 at 02:07:10PM +0530, Uma Shankar wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
> 
> This patch adds two new functions:
> - disable_dsi_pll.
>   BXT DSI disable sequence and registers are
>   different from previous platforms.
> - intel_disable_dsi_pll
>   wrapper function to re-use the same code for
>   multiple platforms. It checks platform type and
>   calls appropriate core pll disable function.
> 
> v2: Fixed Jani's review comments.
> 
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.c     |    2 +-
>  drivers/gpu/drm/i915/intel_dsi.h     |    2 +-
>  drivers/gpu/drm/i915/intel_dsi_pll.c |   32 +++++++++++++++++++++++++++++++-
>  3 files changed, 33 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index e201c0f..544166f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -548,7 +548,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
>  		usleep_range(2000, 2500);
>  	}
>  
> -	vlv_disable_dsi_pll(encoder);
> +	intel_disable_dsi_pll(encoder);
>  }
>  
>  static void intel_dsi_post_disable(struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 20cfcf07..759983e 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -122,7 +122,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
>  }
>  
>  extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
> -extern void vlv_disable_dsi_pll(struct intel_encoder *encoder);
> +extern void intel_disable_dsi_pll(struct intel_encoder *encoder);

Kerneldoc for the entire dsi subsystem would be awesome ... are you
working on that too?
-Daniel

>  extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
>  
>  struct drm_panel *vbt_panel_init(struct intel_dsi *intel_dsi, u16 panel_id);
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index b07483b..f335e6c 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -276,7 +276,7 @@ static void vlv_enable_dsi_pll(struct intel_encoder *encoder)
>  	DRM_DEBUG_KMS("DSI PLL locked\n");
>  }
>  
> -void vlv_disable_dsi_pll(struct intel_encoder *encoder)
> +static void vlv_disable_dsi_pll(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
>  	u32 tmp;
> @@ -293,6 +293,26 @@ void vlv_disable_dsi_pll(struct intel_encoder *encoder)
>  	mutex_unlock(&dev_priv->sb_lock);
>  }
>  
> +static void bxt_disable_dsi_pll(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> +	u32 val;
> +
> +	DRM_DEBUG_KMS("\n");
> +
> +	val = I915_READ(BXT_DSI_PLL_ENABLE);
> +	val &= ~BXT_DSI_PLL_DO_ENABLE;
> +	I915_WRITE(BXT_DSI_PLL_ENABLE, val);
> +
> +	/*
> +	 * PLL lock should deassert within 200us.
> +	 * Wait up to 1ms before timing out.
> +	 */
> +	if (wait_for((I915_READ(BXT_DSI_PLL_ENABLE)
> +					& BXT_DSI_PLL_LOCKED) == 0, 1))
> +		DRM_ERROR("Timeout waiting for PLL lock deassertion\n");
> +}
> +
>  static void assert_bpp_mismatch(int pixel_format, int pipe_bpp)
>  {
>  	int bpp = dsi_pixel_format_bpp(pixel_format);
> @@ -456,3 +476,13 @@ void intel_enable_dsi_pll(struct intel_encoder *encoder)
>  	else if (IS_BROXTON(dev))
>  		bxt_enable_dsi_pll(encoder);
>  }
> +
> +void intel_disable_dsi_pll(struct intel_encoder *encoder)
> +{
> +	struct drm_device *dev = encoder->base.dev;
> +
> +	if (IS_VALLEYVIEW(dev))
> +		vlv_disable_dsi_pll(encoder);
> +	else if (IS_BROXTON(dev))
> +		bxt_disable_dsi_pll(encoder);
> +}
> -- 
> 1.7.9.5
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [BXT MIPI PATCH v2 03/13] drm/i915/bxt: Disable DSI PLL for BXT

[Shankar, Uma]

On 7/27/2015 2:58 PM, Daniel Vetter wrote:
> On Sun, Jul 26, 2015 at 02:07:10PM +0530, Uma Shankar wrote:
>> From: Shashank Sharma <shashank.sharma@intel.com>
>>
>> This patch adds two new functions:
>> - disable_dsi_pll.
>>    BXT DSI disable sequence and registers are
>>    different from previous platforms.
>> - intel_disable_dsi_pll
>>    wrapper function to re-use the same code for
>>    multiple platforms. It checks platform type and
>>    calls appropriate core pll disable function.
>>
>> v2: Fixed Jani's review comments.
>>
>> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_dsi.c     |    2 +-
>>   drivers/gpu/drm/i915/intel_dsi.h     |    2 +-
>>   drivers/gpu/drm/i915/intel_dsi_pll.c |   32 +++++++++++++++++++++++++++++++-
>>   3 files changed, 33 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>> index e201c0f..544166f 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -548,7 +548,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
>>   		usleep_range(2000, 2500);
>>   	}
>>   
>> -	vlv_disable_dsi_pll(encoder);
>> +	intel_disable_dsi_pll(encoder);
>>   }
>>   
>>   
>>   extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
>> -extern void vlv_disable_dsi_pll(struct intel_encoder *encoder);
>> +extern void intel_disable_dsi_pll(struct intel_encoder *encoder);
> Kerneldoc for the entire dsi subsystem would be awesome ... are you
> working on that too?
> -Daniel
Hi Daniel,
Yes that would be really good document to have. Currently not working on 
that, but will take this up and create a documentation for DSI subsystem 
along with generic mipi sequence parsing from VBT and backlight control.

Regards,
Uma Shankar
> -void vlv_disable_dsi_pll(struct intel_encoder *encoder)
> +static void vlv_disable_dsi_pll(struct intel_encoder *encoder)
>   {
>   	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
>   	u32 tmp;
> @@ -293,6 +293,26 @@ void vlv_disable_dsi_pll(struct intel_encoder *encoder)
>   	mutex_unlock(&dev_priv->sb_lock);
>   }
>
> 1.7.9.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [BXT MIPI PATCH v2 02/13] drm/i915/bxt: Enable BXT DSI PLL

[Jani Nikula]

On Sun, 26 Jul 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> This patch adds new functions for BXT clock and PLL programming.
> They are:
> 1. configure_dsi_pll for BXT.
>    This function does the basic math and generates the divider ratio
>    based on requested pixclock, and program clock registers.
> 2. enable_dsi_pll function.
>    This function programs the calculated clock values on the PLL.
> 3. intel_enable_dsi_pll
>    Wrapper function to use same code for multiple platforms. It checks the
>    platform and calls appropriate core pll enable function.
>
> v2: Fixed Jani's review comments. Macros are adjusted as per convention.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |   25 ++++++++-
>  drivers/gpu/drm/i915/intel_dsi.c     |    2 +-
>  drivers/gpu/drm/i915/intel_dsi.h     |    2 +-
>  drivers/gpu/drm/i915/intel_dsi_pll.c |   95 +++++++++++++++++++++++++++++++++-
>  4 files changed, 119 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index de1eea4..0862018 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7443,10 +7443,31 @@ enum skl_disp_power_wells {
>  #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
>  #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
>  
> -/* MIPI DSI registers */
> -
>  #define _MIPI_PORT(port, a, c)	_PORT3(port, a, 0, c)	/* ports A and C only */
>  
> +/* MIPI DSI registers */

Why are you moving this comment?

BR,
Jani.

> +#define BXT_DSI_PLL_CTL			0x161000
> +#define  BXT_DSI_PLL_PVD_RATIO_SHIFT	16
> +#define  BXT_DSI_PLL_PVD_RATIO_MASK	(3 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
> +#define  BXT_DSI_PLL_PVD_RATIO_1	(1 << BXT_DSI_PLL_PVD_RATIO_SHIFT)
> +#define  BXT_DSIC_16X_BY2		(1 << 10)
> +#define  BXT_DSIC_16X_BY3		(2 << 10)
> +#define  BXT_DSIC_16X_BY4		(3 << 10)
> +#define  BXT_DSIA_16X_BY2		(1 << 8)
> +#define  BXT_DSIA_16X_BY3		(2 << 8)
> +#define  BXT_DSIA_16X_BY4		(3 << 8)
> +#define  BXT_DSI_FREQ_SEL_SHIFT		8
> +#define  BXT_DSI_FREQ_SEL_MASK		(0xF << BXT_DSI_FREQ_SEL_SHIFT)
> +
> +#define BXT_DSI_PLL_RATIO_MAX		0x7D
> +#define BXT_DSI_PLL_RATIO_MIN		0x22
> +#define BXT_DSI_PLL_RATIO_MASK		0xFF
> +#define BXT_REF_CLOCK_KHZ		19500
> +
> +#define BXT_DSI_PLL_ENABLE		0x46080
> +#define  BXT_DSI_PLL_DO_ENABLE		(1 << 31)
> +#define  BXT_DSI_PLL_LOCKED		(1 << 30)
> +
>  #define _MIPIA_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61190)
>  #define _MIPIC_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61700)
>  #define MIPI_PORT_CTRL(port)	_MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index d709da3..e201c0f 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -898,8 +898,8 @@ static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
>  	DRM_DEBUG_KMS("\n");
>  
>  	intel_dsi_prepare(encoder);
> +	intel_enable_dsi_pll(encoder);
>  
> -	vlv_enable_dsi_pll(encoder);
>  }
>  
>  static enum drm_connector_status
> diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
> index 2784ac4..20cfcf07 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.h
> +++ b/drivers/gpu/drm/i915/intel_dsi.h
> @@ -121,7 +121,7 @@ static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
>  	return container_of(encoder, struct intel_dsi, base.base);
>  }
>  
> -extern void vlv_enable_dsi_pll(struct intel_encoder *encoder);
> +extern void intel_enable_dsi_pll(struct intel_encoder *encoder);
>  extern void vlv_disable_dsi_pll(struct intel_encoder *encoder);
>  extern u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp);
>  
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index c6a8975..b07483b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -246,7 +246,7 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder)
>  	vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl);
>  }
>  
> -void vlv_enable_dsi_pll(struct intel_encoder *encoder)
> +static void vlv_enable_dsi_pll(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
>  	u32 tmp;
> @@ -363,3 +363,96 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
>  
>  	return pclk;
>  }
> +
> +static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	u8 dsi_ratio;
> +	u32 dsi_clk;
> +	u32 val;
> +
> +	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
> +			intel_dsi->lane_count);
> +
> +	/*
> +	 * From clock diagram, to get PLL ratio divider, divide double of DSI
> +	 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to
> +	 * round 'up' the result
> +	 */
> +	dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ);
> +	if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN ||
> +			dsi_ratio > BXT_DSI_PLL_RATIO_MAX) {
> +		DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n");
> +		return false;
> +	}
> +
> +	/*
> +	 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x
> +	 * Spec says both have to be programmed, even if one is not getting
> +	 * used. Configure MIPI_CLOCK_CTL dividers in modeset
> +	 */
> +	val = I915_READ(BXT_DSI_PLL_CTL);
> +	val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
> +	val &= ~BXT_DSI_FREQ_SEL_MASK;
> +	val &= ~BXT_DSI_PLL_RATIO_MASK;
> +	val |= (dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2);
> +
> +	/* As per recommendation from hardware team,
> +	 * Prog PVD ratio =1 if dsi ratio <= 50
> +	 */
> +	if (dsi_ratio <= 50) {
> +		val &= ~BXT_DSI_PLL_PVD_RATIO_MASK;
> +		val |= BXT_DSI_PLL_PVD_RATIO_1;
> +	}
> +
> +	I915_WRITE(BXT_DSI_PLL_CTL, val);
> +	POSTING_READ(BXT_DSI_PLL_CTL);
> +
> +	return true;
> +}
> +
> +static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> +	u32 val;
> +
> +	DRM_DEBUG_KMS("\n");
> +
> +	val = I915_READ(BXT_DSI_PLL_ENABLE);
> +
> +	if (val & BXT_DSI_PLL_DO_ENABLE) {
> +		WARN(1, "DSI PLL already enabled. Disabling it.\n");
> +		val &= ~BXT_DSI_PLL_DO_ENABLE;
> +		I915_WRITE(BXT_DSI_PLL_ENABLE, val);
> +	}
> +
> +	/* Configure PLL vales */
> +	if (!bxt_configure_dsi_pll(encoder)) {
> +		DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n");
> +		return;
> +	}
> +
> +	/* Enable DSI PLL */
> +	val = I915_READ(BXT_DSI_PLL_ENABLE);
> +	val |= BXT_DSI_PLL_DO_ENABLE;
> +	I915_WRITE(BXT_DSI_PLL_ENABLE, val);
> +
> +	/* Timeout and fail if PLL not locked */
> +	if (wait_for(I915_READ(BXT_DSI_PLL_ENABLE) & BXT_DSI_PLL_LOCKED, 1)) {
> +		DRM_ERROR("Timed out waiting for DSI PLL to lock\n");
> +		return;
> +	}
> +
> +	DRM_DEBUG_KMS("DSI PLL locked\n");
> +}
> +
> +void intel_enable_dsi_pll(struct intel_encoder *encoder)
> +{
> +	struct drm_device *dev = encoder->base.dev;
> +
> +	if (IS_VALLEYVIEW(dev))
> +		vlv_enable_dsi_pll(encoder);
> +	else if (IS_BROXTON(dev))
> +		bxt_enable_dsi_pll(encoder);
> +}
> -- 
> 1.7.9.5
>

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [BXT MIPI PATCH v2 04/13] drm/i915/bxt: DSI prepare changes for BXT

[Jani Nikula]

On Sun, 26 Jul 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> This patch modifies dsi_prepare() function to support the same
> modeset prepare sequence for BXT also. Main changes are:
> 1. BXT port control register is different than VLV.
> 2. BXT modeset sequence needs vdisplay and hdisplay programmed
>    for transcoder.
> 3. BXT can select PIPE for MIPI transcoders.
> 4. BXT needs to program register MIPI_INIT_COUNT for both the ports,
>    even if only one is being used.
>
> v2: Fixed Jani's review comments. Rectified the DSI Macros to get
>     proper register offsets using _MIPI_PORT instead of _TRANSCODER
>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |   21 ++++++++++++
>  drivers/gpu/drm/i915/intel_dsi.c |   67 ++++++++++++++++++++++++++++++++------
>  2 files changed, 78 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0862018..8796b25 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7445,6 +7445,22 @@ enum skl_disp_power_wells {
>  
>  #define _MIPI_PORT(port, a, c)	_PORT3(port, a, 0, c)	/* ports A and C only */
>  
> +/* BXT MIPI mode configure */
> +#define  _BXT_MIPIA_TRANS_HACTIVE			0x6B0F8
> +#define  _BXT_MIPIC_TRANS_HACTIVE			0x6B8F8
> +#define  BXT_MIPI_TRANS_HACTIVE(tc)	_MIPI_PORT(tc, \
> +		_BXT_MIPIA_TRANS_HACTIVE, _BXT_MIPIC_TRANS_HACTIVE)
> +
> +#define  _BXT_MIPIA_TRANS_VACTIVE			0x6B0FC
> +#define  _BXT_MIPIC_TRANS_VACTIVE			0x6B8FC
> +#define  BXT_MIPI_TRANS_VACTIVE(tc)	_MIPI_PORT(tc, \
> +		_BXT_MIPIA_TRANS_VACTIVE, _BXT_MIPIC_TRANS_VACTIVE)
> +
> +#define  _BXT_MIPIA_TRANS_VTOTAL			0x6B100
> +#define  _BXT_MIPIC_TRANS_VTOTAL			0x6B900
> +#define  BXT_MIPI_TRANS_VTOTAL(tc)	_MIPI_PORT(tc, \
> +		_BXT_MIPIA_TRANS_VTOTAL, _BXT_MIPIC_TRANS_VTOTAL)
> +
>  /* MIPI DSI registers */

This should be the topmost comment for DSI.

>  #define BXT_DSI_PLL_CTL			0x161000
>  #define  BXT_DSI_PLL_PVD_RATIO_SHIFT	16
> @@ -7881,6 +7897,11 @@ enum skl_disp_power_wells {
>  #define  READ_REQUEST_PRIORITY_HIGH			(3 << 3)
>  #define  RGB_FLIP_TO_BGR				(1 << 2)
>  
> +#define  BXT_PIPE_SELECT_MASK				(7 << 7)
> +#define  BXT_PIPE_SELECT_C				(2 << 7)
> +#define  BXT_PIPE_SELECT_B				(1 << 7)
> +#define  BXT_PIPE_SELECT_A				(0 << 7)
> +
>  #define _MIPIA_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb108)
>  #define _MIPIC_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)
>  #define MIPI_DATA_ADDRESS(port)		_MIPI_PORT(port, _MIPIA_DATA_ADDRESS, \
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 544166f..0b20534 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -721,6 +721,21 @@ static void set_dsi_timings(struct drm_encoder *encoder,
>  	hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
>  
>  	for_each_dsi_port(port, intel_dsi->ports) {
> +		if (IS_BROXTON(dev)) {
> +			/*
> +			 * Program hdisplay and vdisplay on MIPI transcoder.
> +			 * This is different from calculated hactive and
> +			 * vactive, as they are calculated per channel basis,
> +			 * whereas these values should be based on resolution.
> +			 */
> +			I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
> +					mode->hdisplay);
> +			I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
> +					mode->vdisplay);
> +			I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
> +					mode->vtotal);
> +		}
> +
>  		I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
>  		I915_WRITE(MIPI_HFP_COUNT(port), hfp);
>  
> @@ -761,16 +776,35 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
>  	}
>  
>  	for_each_dsi_port(port, intel_dsi->ports) {
> -		/* escape clock divider, 20MHz, shared for A and C.
> -		 * device ready must be off when doing this! txclkesc? */
> -		tmp = I915_READ(MIPI_CTRL(PORT_A));
> -		tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
> -		I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
> -
> -		/* read request priority is per pipe */
> -		tmp = I915_READ(MIPI_CTRL(port));
> -		tmp &= ~READ_REQUEST_PRIORITY_MASK;
> -		I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
> +		if (IS_VALLEYVIEW(dev)) {
> +			/*
> +			 * escape clock divider, 20MHz, shared for A and C.
> +			 * device ready must be off when doing this! txclkesc?
> +			 */
> +			tmp = I915_READ(MIPI_CTRL(PORT_A));
> +			tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
> +			I915_WRITE(MIPI_CTRL(PORT_A), tmp |
> +					ESCAPE_CLOCK_DIVIDER_1);
> +
> +			/* read request priority is per pipe */
> +			tmp = I915_READ(MIPI_CTRL(port));
> +			tmp &= ~READ_REQUEST_PRIORITY_MASK;
> +			I915_WRITE(MIPI_CTRL(port), tmp |
> +					READ_REQUEST_PRIORITY_HIGH);
> +		} else if (IS_BROXTON(dev)) {
> +			/*
> +			 * FIXME:
> +			 * BXT can connect any PIPE to any MIPI port.
> +			 * Select the pipe based on the MIPI port read from
> +			 * VBT for now. Pick PIPE A for MIPI port A and C
> +			 * for port C.
> +			 */
> +			tmp = I915_READ(MIPI_CTRL(port));
> +			tmp &= ~BXT_PIPE_SELECT_MASK;
> +			(port == PORT_C) ? (tmp |= BXT_PIPE_SELECT_C) :
> +				(tmp |= BXT_PIPE_SELECT_A);

if (port == PORT_A)
	...
else
	...

seems clearer.


> +			I915_WRITE(MIPI_CTRL(port), tmp);
> +		}
>  
>  		/* XXX: why here, why like this? handling in irq handler?! */
>  		I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
> @@ -847,6 +881,19 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder)
>  		I915_WRITE(MIPI_INIT_COUNT(port),
>  				txclkesc(intel_dsi->escape_clk_div, 100));
>  
> +		if (IS_BROXTON(dev)) {
> +			if (!intel_dsi->dual_link) {

Those could be combined into one if condition to reduce indent.

> +				/*
> +				 * BXT spec says write MIPI_INIT_COUNT for
> +				 * both the ports, even if only one is
> +				 * getting used. So write the other port
> +				 * if not in dual link mode.
> +				 */
> +				I915_WRITE(MIPI_INIT_COUNT(port ==
> +						PORT_A ? PORT_C : PORT_A),
> +							intel_dsi->init_count);
> +			}
> +		}
>  
>  		/* recovery disables */
>  		I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
> -- 
> 1.7.9.5
>

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [BXT MIPI PATCH v2 05/13] drm/i915/bxt: DSI encoder support in CRTC modeset

[Jani Nikula]

On Sun, 26 Jul 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> SKL and BXT qualifies the HAS_DDI() check, and hence haswell
> modeset functions are re-used for modeset sequence. But DDI
> interface doesn't include support for DSI.
> This patch adds:
> 1. cases for DSI encoder, in those modeset functions and allows
>    a CRTC modeset
> 2. Adds call to pre_pll enabled from CRTC modeset function. Nothing
>    needs to be done as such in CRTC for DSI encoder, as PLL, clock
>    and and transcoder programming will be taken care in encoder's
>    pre_enable and pre_pll_enable function.
>
> v2: Fixed Jani's review comments. Added INVALID_PORT for non DDI
>     encoder like DSI for platforms having HAS_DDI as true.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h       |    1 +
>  drivers/gpu/drm/i915/intel_ddi.c      |   10 +++++++++-
>  drivers/gpu/drm/i915/intel_display.c  |   19 ++++++++++++++-----
>  drivers/gpu/drm/i915/intel_opregion.c |    3 ++-
>  4 files changed, 26 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 23ce125e..04f746d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -142,6 +142,7 @@ enum plane {
>  #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
>  
>  enum port {
> +	PORT_INVALID = -1,
>  	PORT_A = 0,
>  	PORT_B,
>  	PORT_C,
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 9a40bfb..2bad86e 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -310,6 +310,10 @@ static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
>  	} else if (type == INTEL_OUTPUT_ANALOG) {
>  		*dig_port = NULL;
>  		*port = PORT_E;
> +	} else if (type == INTEL_OUTPUT_DSI) {
> +		*dig_port = NULL;
> +		*port = PORT_INVALID;
> +		DRM_DEBUG_KMS("Encoder type: DSI. Returning...\n");
>  	} else {
>  		DRM_ERROR("Invalid DDI encoder type %d\n", type);
>  		BUG();
> @@ -565,6 +569,9 @@ void intel_prepare_ddi(struct drm_device *dev)
>  
>  		ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
>  
> +		if (port == PORT_INVALID)
> +			continue;
> +

I think you should add WARN_ON(port == PORT_INVALID) wherever you call
(intel_)ddi_get_encoder_port and you feel you don't need to check the
port.


>  		if (visited[port])
>  			continue;
>  
> @@ -2052,7 +2059,8 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
>  void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
>  {
>  	struct drm_crtc *crtc = &intel_crtc->base;
> -	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
> +	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
>  	enum port port = intel_ddi_get_encoder_port(intel_encoder);
>  	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 52e21d4..db27995 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4904,6 +4904,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_encoder *encoder;
>  	int pipe = intel_crtc->pipe, hsw_workaround_pipe;
> +	bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>  	struct intel_crtc_state *pipe_config =
>  		to_intel_crtc_state(crtc->state);
>  
> @@ -4945,7 +4946,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  		dev_priv->display.fdi_link_train(crtc);
>  	}
>  
> -	intel_ddi_enable_pipe_clock(intel_crtc);
> +	if (!is_dsi)
> +		intel_ddi_enable_pipe_clock(intel_crtc);
>  
>  	if (INTEL_INFO(dev)->gen == 9)
>  		skylake_pfit_enable(intel_crtc);
> @@ -4961,7 +4963,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  	intel_crtc_load_lut(crtc);
>  
>  	intel_ddi_set_pipe_settings(crtc);
> -	intel_ddi_enable_transcoder_func(crtc);
> +	if (!is_dsi)
> +		intel_ddi_enable_transcoder_func(crtc);
>  
>  	intel_update_watermarks(crtc);
>  	intel_enable_pipe(intel_crtc);
> @@ -4969,13 +4972,16 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
>  	if (intel_crtc->config->has_pch_encoder)
>  		lpt_pch_enable(crtc);
>  
> -	if (intel_crtc->config->dp_encoder_is_mst)
> +	if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
>  		intel_ddi_set_vc_payload_alloc(crtc, true);
>  
>  	assert_vblank_disabled(crtc);
>  	drm_crtc_vblank_on(crtc);
>  
>  	for_each_encoder_on_crtc(dev, crtc, encoder) {
> +		if (encoder->pre_pll_enable)
> +			encoder->pre_pll_enable(encoder);
> +
>  		encoder->enable(encoder);
>  		intel_opregion_notify_encoder(encoder, true);
>  	}
> @@ -5065,6 +5071,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>  	struct intel_encoder *encoder;
>  	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
> +	bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
>  
>  	for_each_encoder_on_crtc(dev, crtc, encoder) {
>  		intel_opregion_notify_encoder(encoder, false);
> @@ -5082,7 +5089,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
>  	if (intel_crtc->config->dp_encoder_is_mst)
>  		intel_ddi_set_vc_payload_alloc(crtc, false);
>  
> -	intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
> +	if (!is_dsi)
> +		intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
>  
>  	if (INTEL_INFO(dev)->gen == 9)
>  		skylake_scaler_disable(intel_crtc);
> @@ -5091,7 +5099,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
>  	else
>  		MISSING_CASE(INTEL_INFO(dev)->gen);
>  
> -	intel_ddi_disable_pipe_clock(intel_crtc);
> +	if (!is_dsi)
> +		intel_ddi_disable_pipe_clock(intel_crtc);
>  
>  	if (intel_crtc->config->has_pch_encoder) {
>  		lpt_disable_pch_transcoder(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
> index cb1c657..8182f67 100644
> --- a/drivers/gpu/drm/i915/intel_opregion.c
> +++ b/drivers/gpu/drm/i915/intel_opregion.c
> @@ -342,7 +342,7 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
>  		return 0;
>  
>  	port = intel_ddi_get_encoder_port(intel_encoder);
> -	if (port == PORT_E) {
> +	if ((port == PORT_E) || (port == PORT_INVALID)) {
>  		port = 0;
>  	} else {
>  		parm |= 1 << port;
> @@ -363,6 +363,7 @@ int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
>  		type = DISPLAY_TYPE_EXTERNAL_FLAT_PANEL;
>  		break;
>  	case INTEL_OUTPUT_EDP:
> +	case INTEL_OUTPUT_DSI:
>  		type = DISPLAY_TYPE_INTERNAL_FLAT_PANEL;
>  		break;
>  	default:
> -- 
> 1.7.9.5
>

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [BXT MIPI PATCH v2 06/13] drm/i915/bxt: DSI enable for BXT

[Jani Nikula]

On Sun, 26 Jul 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> This patch contains following changes:
> 1. MIPI device ready changes to support dsi_pre_enable. Changes
>    are specific to BXT device ready sequence. Added check for
>    ULPS mode(No effects on VLV).
> 2. Changes in dsi_enable to pick BXT port control register.
> 3. Changes in dsi_pre_enable to restrict DPIO programming for VLV
>
> v2: Fixed Jani's review comments. Removed the changes in VLV/CHV
>     code. Fixed the macros to get proper port offsets.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |    9 +++
>  drivers/gpu/drm/i915/intel_dsi.c |  156 ++++++++++++++++++++++++++------------
>  2 files changed, 115 insertions(+), 50 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8796b25..7559062 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7487,6 +7487,15 @@ enum skl_disp_power_wells {
>  #define _MIPIA_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61190)
>  #define _MIPIC_PORT_CTRL			(VLV_DISPLAY_BASE + 0x61700)
>  #define MIPI_PORT_CTRL(port)	_MIPI_PORT(port, _MIPIA_PORT_CTRL, _MIPIC_PORT_CTRL)
> +
> + /* BXT port control */
> +#define _BXT_MIPIA_PORT_CTRL				0x6B0C0
> +#define _BXT_MIPIC_PORT_CTRL				0x6B8C0
> +#define BXT_MIPI_PORT_CTRL(tc)	_MIPI_PORT(tc, _BXT_MIPIA_PORT_CTRL, \
> +						_BXT_MIPIC_PORT_CTRL)
> +#define GET_DSI_PORT_CTRL(dev) (IS_BROXTON(dev) ? BXT_MIPI_PORT_CTRL(port) : \
> +						MIPI_PORT_CTRL(port))

I think you should just leave that IS_BROXTON check in the code, and
drop the GET_DSI_PORT_CTRL macro. We haven't really done this sort of
thing, and part of the reason (AFAICS) is that it's more obvious to read
the code when you know which register will be used.

> +
>  #define  DPI_ENABLE					(1 << 31) /* A + C */
>  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT		27
>  #define  MIPIA_MIPI4DPHY_DELAY_COUNT_MASK		(0xf << 27)
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 0b20534..c5889c4 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -281,6 +281,85 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder,
>  	return true;
>  }
>  
> +static void bxt_dsi_device_ready(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
> +	u32 val;
> +
> +	DRM_DEBUG_KMS("\n");
> +
> +	/* Exit Low power state in 4 steps*/
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +
> +		/* 1. Enable MIPI PHY transparent latch */
> +		val = I915_READ(BXT_MIPI_PORT_CTRL(port));
> +		I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
> +		usleep_range(2000, 2500);
> +
> +		/* 2. Enter ULPS */
> +		val = I915_READ(MIPI_DEVICE_READY(port));
> +		val &= ~ULPS_STATE_MASK;
> +		val |= (ULPS_STATE_ENTER | DEVICE_READY);
> +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> +		usleep_range(2, 3);
> +
> +		/* 3. Exit ULPS */
> +		val = I915_READ(MIPI_DEVICE_READY(port));
> +		val &= ~ULPS_STATE_MASK;
> +		val |= (ULPS_STATE_EXIT | DEVICE_READY);
> +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> +		usleep_range(1000, 1500);
> +
> +		/* Clear ULPS and set device ready */
> +		val = I915_READ(MIPI_DEVICE_READY(port));
> +		val &= ~ULPS_STATE_MASK;
> +		val |= DEVICE_READY;
> +		I915_WRITE(MIPI_DEVICE_READY(port), val);
> +	}
> +}
> +
> +static void vlv_dsi_device_ready(struct intel_encoder *encoder)
> +{
> +	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
> +	u32 val;
> +
> +	DRM_DEBUG_KMS("\n");
> +
> +	mutex_lock(&dev_priv->sb_lock);
> +	/* program rcomp for compliance, reduce from 50 ohms to 45 ohms
> +	 * needed everytime after power gate */
> +	vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
> +	mutex_unlock(&dev_priv->sb_lock);
> +
> +	/* bandgap reset is needed after everytime we do power gate */
> +	band_gap_reset(dev_priv);
> +
> +	for_each_dsi_port(port, intel_dsi->ports) {
> +
> +		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
> +		usleep_range(2500, 3000);
> +
> +		/* Enable MIPI PHY transparent latch
> +		 * Common bit for both MIPI Port A & MIPI Port C
> +		 * No similar bit in MIPI Port C reg
> +		 */
> +		val = I915_READ(MIPI_PORT_CTRL(PORT_A));
> +		I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
> +		usleep_range(1000, 1500);
> +
> +		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
> +		usleep_range(2500, 3000);
> +
> +		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
> +		usleep_range(2500, 3000);
> +	}
> +}

I'd prefer you put these functions where the intel_dsi_device_ready
function is now instead of separating these from it. You'll also get a
nice diff where you see that things are not changed for vlv.

> +
> +
>  static void intel_dsi_port_enable(struct intel_encoder *encoder)
>  {
>  	struct drm_device *dev = encoder->base.dev;
> @@ -289,6 +368,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	enum port port;
>  	u32 temp;
> +	u32 port_ctrl;
>  
>  	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
>  		temp = I915_READ(VLV_CHICKEN_3);
> @@ -299,7 +379,9 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>  	}
>  
>  	for_each_dsi_port(port, intel_dsi->ports) {
> -		temp = I915_READ(MIPI_PORT_CTRL(port));
> +		port_ctrl = GET_DSI_PORT_CTRL(dev);
> +		temp = I915_READ(port_ctrl);
> +
>  		temp &= ~LANE_CONFIGURATION_MASK;
>  		temp &= ~DUAL_LINK_MODE_MASK;
>  
> @@ -311,8 +393,8 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>  					LANE_CONFIGURATION_DUAL_LINK_A;
>  		}
>  		/* assert ip_tg_enable signal */
> -		I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
> -		POSTING_READ(MIPI_PORT_CTRL(port));
> +		I915_WRITE(port_ctrl, temp | DPI_ENABLE);
> +		POSTING_READ(port_ctrl);
>  	}
>  }
>  
> @@ -334,41 +416,12 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder)
>  
>  static void intel_dsi_device_ready(struct intel_encoder *encoder)
>  {
> -	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> -	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> -	enum port port;
> -	u32 val;
> -
> -	DRM_DEBUG_KMS("\n");
> -
> -	mutex_lock(&dev_priv->sb_lock);
> -	/* program rcomp for compliance, reduce from 50 ohms to 45 ohms
> -	 * needed everytime after power gate */
> -	vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
> -	mutex_unlock(&dev_priv->sb_lock);
> -
> -	/* bandgap reset is needed after everytime we do power gate */
> -	band_gap_reset(dev_priv);
> -
> -	for_each_dsi_port(port, intel_dsi->ports) {
> -
> -		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
> -		usleep_range(2500, 3000);
> -
> -		/* Enable MIPI PHY transparent latch
> -		 * Common bit for both MIPI Port A & MIPI Port C
> -		 * No similar bit in MIPI Port C reg
> -		 */
> -		val = I915_READ(MIPI_PORT_CTRL(PORT_A));
> -		I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
> -		usleep_range(1000, 1500);
> -
> -		I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
> -		usleep_range(2500, 3000);
> +	struct drm_device *dev = encoder->base.dev;
>  
> -		I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
> -		usleep_range(2500, 3000);
> -	}
> +	if (IS_VALLEYVIEW(dev))
> +		vlv_dsi_device_ready(encoder);
> +	else if (IS_BROXTON(dev))
> +		bxt_dsi_device_ready(encoder);
>  }
>  
>  static void intel_dsi_enable(struct intel_encoder *encoder)
> @@ -410,19 +463,22 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder)
>  
>  	DRM_DEBUG_KMS("\n");
>  
> -	/* Disable DPOunit clock gating, can stall pipe
> -	 * and we need DPLL REFA always enabled */
> -	tmp = I915_READ(DPLL(pipe));
> -	tmp |= DPLL_REF_CLK_ENABLE_VLV;
> -	I915_WRITE(DPLL(pipe), tmp);
> -
> -	/* update the hw state for DPLL */
> -	intel_crtc->config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
> -		DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> -
> -	tmp = I915_READ(DSPCLK_GATE_D);
> -	tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
> -	I915_WRITE(DSPCLK_GATE_D, tmp);
> +	if (IS_VALLEYVIEW(dev)) {
> +		/* Disable DPOunit clock gating, can stall pipe
> +		 * and we need DPLL REFA always enabled */
> +		tmp = I915_READ(DPLL(pipe));
> +		tmp |= DPLL_REF_CLK_ENABLE_VLV;
> +		I915_WRITE(DPLL(pipe), tmp);
> +
> +		/* update the hw state for DPLL */
> +		intel_crtc->config->dpll_hw_state.dpll =
> +			DPLL_INTEGRATED_REF_CLK_VLV |
> +			DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> +
> +		tmp = I915_READ(DSPCLK_GATE_D);
> +		tmp |= DPOUNIT_CLOCK_GATE_DISABLE;
> +		I915_WRITE(DSPCLK_GATE_D, tmp);
> +	}
>  
>  	/* put device in ready state */
>  	intel_dsi_device_ready(encoder);
> -- 
> 1.7.9.5
>

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [BXT MIPI PATCH v2 07/13] drm/i915/bxt: Program Tx Rx and Dphy clocks

[Jani Nikula]

On Sun, 26 Jul 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Shashank Sharma <shashank.sharma@intel.com>
>
> BXT DSI clocks are different than previous platforms. So adding a
> new function to program following clocks and dividers:
> 1. Program variable divider to generate input to Tx clock divider
>    (Output value must be < 39.5Mhz)
> 2. Select divide by 2 option to get < 20Mhz for Tx clock
> 3. Program 8by3 divider to generate Rx clock
>
> v2: Fixed Jani's review comments. Adjusted the Macro defintion as
>     per convention. Simplified the logic for bit definitions for
>     MIPI PORT A and PORT C in same registers.
>
> Signed-off-by: Shashank Sharma <shashank.sharma@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |   40 +++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_dsi_pll.c |   41 ++++++++++++++++++++++++++++++++++
>  2 files changed, 81 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7559062..310afd4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7445,6 +7445,46 @@ enum skl_disp_power_wells {
>  
>  #define _MIPI_PORT(port, a, c)	_PORT3(port, a, 0, c)	/* ports A and C only */
>  
> +/* BXT MIPI clock controls */
> +#define BXT_MAX_VAR_OUTPUT_KHZ			39500
> +
> +#define BXT_MIPI_CLOCK_CTL			0x46090
> +#define  BXT_MIPI_DIV_SHIFT			16
> +/* Var clock divider to generate TX source. Result must be < 39.5 M */
> +#define  BXT_MIPI1_ESCLK_VAR_DIV_MASK		(0x3F << 26)
> +#define  BXT_MIPI2_ESCLK_VAR_DIV_MASK		(0x3F << 10)
> +#define  BXT_MIPI_ESCLK_VAR_DIV_MASK(port)	\
> +		(0x3F << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 10))
> +#define  BXT_MIPI_ESCLK_VAR_DIV(port, val)            \
> +		(val << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 10))
> +/* TX control divider to select actual TX clock output from (8x/var) */
> +#define  BXT_MIPI1_TX_ESCLK_FIXDIV_MASK		(3 << 21)
> +#define  BXT_MIPI2_TX_ESCLK_FIXDIV_MASK		(3 << 5)
> +#define  BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)	\
> +		(3 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 5))
> +#define  BXT_MIPI_TX_ESCLK_8XDIV_BY2(port)	\
> +		(0x0 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 5))
> +#define  BXT_MIPI_TX_ESCLK_8XDIV_BY4(port)	\
> +		(0x1 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 5))
> +#define  BXT_MIPI_TX_ESCLK_8XDIV_BY8(port)	\
> +		(0x2 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 5))
> +/* RX control divider to select actual RX clock output from 8x*/
> +#define  BXT_MIPI1_RX_ESCLK_FIXDIV_MASK		(3 << 19)
> +#define  BXT_MIPI2_RX_ESCLK_FIXDIV_MASK		(3 << 3)
> +#define  BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port)	\
> +		(3 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 3))
> +#define  BXT_MIPI_RX_ESCLK_8X_BY2(port)	\
> +		(1 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 3))
> +#define  BXT_MIPI_RX_ESCLK_8X_BY3(port)	\
> +		(2 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 3))
> +#define  BXT_MIPI_RX_ESCLK_8X_BY4(port)	\
> +		(3 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT + 3))
> +/* BXT: Always prog DPHY dividers to 00 */
> +#define  BXT_MIPI_1_DPHY_DIVIDER_MASK		(3 << 16)
> +#define  BXT_MIPI_2_DPHY_DIVIDER_MASK		(3 << 0)
> +#define  BXT_MIPI_DPHY_DIVIDER_MASK(port)	\
> +		(3 << ((port == PORT_A) * BXT_MIPI_DIV_SHIFT))

Meh. Please define the shifts and masks for all fields, and if you want
to have macros with port argument, please use _MIPI_PORT for defining
them.

For example,

#define  _BXT_MIPI1_TX_ESCLK_FIXDIV_MASK		(3 << 21)
#define  _BXT_MIPI2_TX_ESCLK_FIXDIV_MASK		(3 << 5)
#define  BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port) \
	_MIPI_PORT(port, _BXT_MIPI1_TX_ESCLK_FIXDIV_MASK, _BXT_MIPI2_TX_ESCLK_FIXDIV_MASK)


> +
>  /* BXT MIPI mode configure */
>  #define  _BXT_MIPIA_TRANS_HACTIVE			0x6B0F8
>  #define  _BXT_MIPIC_TRANS_HACTIVE			0x6B8F8
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index f335e6c..0b74399 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -384,6 +384,41 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
>  	return pclk;
>  }
>  
> +/* Program BXT Mipi clocks and dividers */
> +static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
> +{
> +	u32 tmp;
> +	u32 divider;
> +	u32 dsi_rate;
> +	u32 pll_ratio;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +
> +	/* Clear old configurations */
> +	tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
> +	tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port));
> +	tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port));
> +	tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port));
> +	tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port));
> +
> +	/* Get the current DSI rate(actual) */
> +	pll_ratio = I915_READ(BXT_DSI_PLL_CTL) &
> +				BXT_DSI_PLL_RATIO_MASK;

Please do not use registers as temp storage. Pass the information into
this function instead.

> +	dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2;
> +
> +	/* Max possible output of clock is 39.5 MHz, program value -1 */
> +	divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1;
> +	tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider);
> +
> +	/* Tx escape clock should be >=20MHz, so select divide by 2 */

Here the comment is useful as it contains rationale...

> +	tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port);
> +
> +	/* Rx escape clock, select fix divide by 3 clock */

...however this just describes what should be obvious from the code.

> +	tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port);
> +
> +	/* Do the honors */

Useless comment.

> +	I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp);
> +}
> +
>  static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> @@ -435,6 +470,8 @@ static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
>  static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> +	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	enum port port;
>  	u32 val;
>  
>  	DRM_DEBUG_KMS("\n");
> @@ -453,6 +490,10 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder)
>  		return;
>  	}
>  
> +	/* Now program TX, RX, Dphy clocks */
> +	for_each_dsi_port(port, intel_dsi->ports)
> +		bxt_dsi_program_clocks(encoder->base.dev, port);
> +
>  	/* Enable DSI PLL */
>  	val = I915_READ(BXT_DSI_PLL_ENABLE);
>  	val |= BXT_DSI_PLL_DO_ENABLE;
> -- 
> 1.7.9.5
>

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [BXT MIPI PATCH v2 11/13] drm/i915/bxt: Modify BXT BLC according to VBT changes

[Jani Nikula]

On Sun, 26 Jul 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> From: Sunil Kamath <sunil.kamath@intel.com>
>
> Latest VBT mentions which set of registers will be used for BLC,
> as controller number field. Making use of this field in BXT
> BLC implementation. Also, the registers are used in case control
> pin indicates display DDI. Adding a check for this.
> According to Bspec, BLC_PWM_*_2 uses the display utility pin for output.
> To use backlight 2, enable the utility pin with mode = PWM
>    v2: Jani's review comments
>    addressed
>        - Add a prefix _ to BXT BLC registers definitions.
>        - Add "bxt only" comment for u8 controller
>        - Remove control_pin check for DDI controller
>        - Check for valid controller values
>        - Set pipe bits in UTIL_PIN_CTL
>        - Enable/Disable UTIL_PIN_CTL in enable/disable_backlight()
>        - If BLC 2 is used, read active_low_pwm from UTIL_PIN polarity
>    Satheesh's review comment addressed
>        - If UTIL PIN is already enabled, BIOS would have programmed it. No
>        need to disable and enable again.
>    v3: Jani's review comments
>        - add UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK
>        - Disable UTIL_PIN if controller 1 is used
>        - Mask out UTIL_PIN_PIPE_MASK and UTIL_PIN_MODE_MASK before enabling
>        UTIL_PIN
>        - check valid controller value in intel_bios.c
>        - add backlight.util_pin_active_low
>        - disable util pin before enabling
>    v4: Change for BXT-PO branch:
>    Stubbed unwanted definition which was existing before
>    because of DC6 patch.
>    UTIL_PIN_MODE_PWM     (0x1b << 24)
>
> v2: Fixed Jani's review comment.
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Signed-off-by: Sunil Kamath <sunil.kamath@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h    |   27 ++++++++---
>  drivers/gpu/drm/i915/intel_drv.h   |    2 +
>  drivers/gpu/drm/i915/intel_panel.c |   94 +++++++++++++++++++++++++++++-------
>  3 files changed, 100 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 310afd4..0b1d7ff 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3553,17 +3553,29 @@ enum skl_disp_power_wells {
>  #define UTIL_PIN_CTL		0x48400
>  #define   UTIL_PIN_ENABLE	(1 << 31)
>  
> +#define   UTIL_PIN_PIPE(x)     ((x) << 29)
> +#define   UTIL_PIN_PIPE_MASK   (3 << 29)
> +#define   UTIL_PIN_MODE_PWM    (1 << 24)
> +#define   UTIL_PIN_MODE_MASK   (0xf << 24)
> +#define   UTIL_PIN_POLARITY    (1 << 22)
> +
>  /* BXT backlight register definition. */
> -#define BXT_BLC_PWM_CTL1			0xC8250
> +#define _BXT_BLC_PWM_CTL1			0xC8250
>  #define   BXT_BLC_PWM_ENABLE			(1 << 31)
>  #define   BXT_BLC_PWM_POLARITY			(1 << 29)
> -#define BXT_BLC_PWM_FREQ1			0xC8254
> -#define BXT_BLC_PWM_DUTY1			0xC8258
> +#define _BXT_BLC_PWM_FREQ1			0xC8254
> +#define _BXT_BLC_PWM_DUTY1			0xC8258
>  
> -#define BXT_BLC_PWM_CTL2			0xC8350
> -#define BXT_BLC_PWM_FREQ2			0xC8354
> -#define BXT_BLC_PWM_DUTY2			0xC8358
> +#define _BXT_BLC_PWM_CTL2			0xC8350
> +#define _BXT_BLC_PWM_FREQ2			0xC8354
> +#define _BXT_BLC_PWM_DUTY2			0xC8358
>  
> +#define BXT_BLC_PWM_CTL(controller)    _PIPE(controller, \
> +					_BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
> +#define BXT_BLC_PWM_FREQ(controller)   _PIPE(controller, \
> +					_BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
> +#define BXT_BLC_PWM_DUTY(controller)   _PIPE(controller, \
> +					_BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)
>  
>  #define PCH_GTC_CTL		0xe7000
>  #define   PCH_GTC_ENABLE	(1 << 31)
> @@ -7280,6 +7292,9 @@ enum skl_disp_power_wells {
>  #define  BXT_CDCLK_CD2X_DIV_SEL_4	(3<<22)
>  #define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1<<16)
>  
> +/* Max CDCLK freq for BXT in HZ */
> +#define BXT_CDCLK_MAX			624000000
> +
>  /* LCPLL_CTL */
>  #define LCPLL1_CTL		0x46010
>  #define LCPLL2_CTL		0x46014
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 3b00d00..8111a21 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -177,7 +177,9 @@ struct intel_panel {
>  		bool enabled;
>  		bool combination_mode;	/* gen 2/4 only */
>  		bool active_low_pwm;
> +		bool util_pin_active_low;	/* bxt+ */
>  		struct backlight_device *device;
> +		u8 controller;		/* bxt+ only */
>  	} backlight;
>  
>  	void (*backlight_power)(struct intel_connector *, bool enable);
> diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> index 55aad23..2a97e5c 100644
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -539,9 +539,10 @@ static u32 vlv_get_backlight(struct intel_connector *connector)
>  static u32 bxt_get_backlight(struct intel_connector *connector)
>  {
>  	struct drm_device *dev = connector->base.dev;
> +	struct intel_panel *panel = &connector->panel;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	return I915_READ(BXT_BLC_PWM_DUTY1);
> +	return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller));
>  }
>  
>  static u32 intel_panel_get_backlight(struct intel_connector *connector)
> @@ -628,8 +629,9 @@ static void bxt_set_backlight(struct intel_connector *connector, u32 level)
>  {
>  	struct drm_device *dev = connector->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> +	struct intel_panel *panel = &connector->panel;
>  
> -	I915_WRITE(BXT_BLC_PWM_DUTY1, level);
> +	I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller), level);
>  }
>  
>  static void
> @@ -761,12 +763,20 @@ static void bxt_disable_backlight(struct intel_connector *connector)
>  {
>  	struct drm_device *dev = connector->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	u32 tmp;
> +	struct intel_panel *panel = &connector->panel;
> +	u32 tmp, val;
>  
>  	intel_panel_actually_set_backlight(connector, 0);
>  
> -	tmp = I915_READ(BXT_BLC_PWM_CTL1);
> -	I915_WRITE(BXT_BLC_PWM_CTL1, tmp & ~BXT_BLC_PWM_ENABLE);
> +	tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> +	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> +			tmp & ~BXT_BLC_PWM_ENABLE);
> +
> +	if (panel->backlight.controller == 1) {
> +		val = I915_READ(UTIL_PIN_CTL);
> +		val &= ~UTIL_PIN_ENABLE;
> +		I915_WRITE(UTIL_PIN_CTL, val);
> +	}
>  }
>  
>  void intel_panel_disable_backlight(struct intel_connector *connector)
> @@ -988,16 +998,39 @@ static void bxt_enable_backlight(struct intel_connector *connector)
>  	struct drm_device *dev = connector->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_panel *panel = &connector->panel;
> -	u32 pwm_ctl;
> +	enum pipe pipe = intel_get_pipe_from_connector(connector);
> +	u32 pwm_ctl, val;
> +
> +	/* To use 2nd set of backlight registers, utility pin has to be
> +	 * enabled with PWM mode.
> +	 * The field should only be changed when the utility pin is disabled
> +	 */
> +	if (panel->backlight.controller == 1) {
> +		val = I915_READ(UTIL_PIN_CTL);
> +		if (val & UTIL_PIN_ENABLE) {
> +			DRM_DEBUG_KMS("util pin already enabled\n");
> +			val &= ~UTIL_PIN_ENABLE;
> +			I915_WRITE(UTIL_PIN_CTL, val);
> +		}
> +		/* mask out UTIL_PIN_PIPE and UTIL_PIN_MODE */
> +		val &= ~(UTIL_PIN_PIPE_MASK | UTIL_PIN_MODE_MASK);
> +		I915_WRITE(UTIL_PIN_CTL, val);
> +		if (panel->backlight.util_pin_active_low)
> +			val |= UTIL_PIN_POLARITY;
> +		I915_WRITE(UTIL_PIN_CTL, val | UTIL_PIN_PIPE(pipe) |
> +				UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE);
> +	}
>  
> -	pwm_ctl = I915_READ(BXT_BLC_PWM_CTL1);
> +	pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
>  	if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
>  		DRM_DEBUG_KMS("backlight already enabled\n");
>  		pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
> -		I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl);
> +		I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> +				pwm_ctl);
>  	}
>  
> -	I915_WRITE(BXT_BLC_PWM_FREQ1, panel->backlight.max);
> +	I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
> +			panel->backlight.max);
>  
>  	intel_panel_actually_set_backlight(connector, panel->backlight.level);
>  
> @@ -1005,9 +1038,10 @@ static void bxt_enable_backlight(struct intel_connector *connector)
>  	if (panel->backlight.active_low_pwm)
>  		pwm_ctl |= BXT_BLC_PWM_POLARITY;
>  
> -	I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl);
> -	POSTING_READ(BXT_BLC_PWM_CTL1);
> -	I915_WRITE(BXT_BLC_PWM_CTL1, pwm_ctl | BXT_BLC_PWM_ENABLE);
> +	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
> +	POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> +	I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
> +			pwm_ctl | BXT_BLC_PWM_ENABLE);
>  }
>  
>  void intel_panel_enable_backlight(struct intel_connector *connector)
> @@ -1370,12 +1404,38 @@ bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
>  	struct intel_panel *panel = &connector->panel;
>  	u32 pwm_ctl, val;
>  
> -	pwm_ctl = I915_READ(BXT_BLC_PWM_CTL1);
> -	panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
> +	/* For BXT hard coding the Backlight controller to 0.
> +	 * TODO : Read the controller value from VBT and generalize
> +	 */
> +	panel->backlight.controller = 0;
>  
> -	panel->backlight.max = I915_READ(BXT_BLC_PWM_FREQ1);
> -	if (!panel->backlight.max)
> -		return -ENODEV;
> +	pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
> +
> +	/* Keeping the check if controller 1 is to be programmed.
> +	 * This will come into affect once the VBT parsing
> +	 * is fixed for controller selection, and controller 1 is used
> +	 * for a prticular display configuration.
> +	 */
> +	if (panel->backlight.controller == 1) {
> +		val = I915_READ(UTIL_PIN_CTL);
> +		panel->backlight.util_pin_active_low =
> +					val & UTIL_PIN_POLARITY;
> +	}
> +
> +	panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
> +	panel->backlight.max = I915_READ(
> +			BXT_BLC_PWM_FREQ(panel->backlight.controller));
> +
> +	if (!panel->backlight.max) {
> +		DRM_DEBUG_KMS("PWM freq not programmed by BIOS\n");
> +		DRM_DEBUG_KMS("Programming PWM freq\n");
> +
> +		/* Max Backlight = Max CD Clock / pwm freq) */
> +		panel->backlight.max = (BXT_CDCLK_MAX /
> +				dev_priv->vbt.backlight.pwm_freq_hz);
> +		I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
> +				panel->backlight.max);
> +	}

Handling (!panel->backlight.max) should probably be a separate patch.

>  
>  	val = bxt_get_backlight(connector);
>  	panel->backlight.level = intel_panel_compute_brightness(connector, val);
> -- 
> 1.7.9.5
>

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [BXT MIPI PATCH v2 12/13] drm/i915/bxt: Remove DSP CLK_GATE programming for BXT

[Jani Nikula]

On Sun, 26 Jul 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> DSP CLK_GATE registers are specific to BYT and CHT.
> Avoid programming the same for BXT platform.
>
> v2: Rebased on latest drm nightly branch.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.c |    9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 350e10a..d0b26c8 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -612,6 +612,7 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
>  
>  static void intel_dsi_post_disable(struct intel_encoder *encoder)
>  {
> +	struct drm_device *dev = encoder->base.dev;
>  	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	u32 val;
> @@ -622,9 +623,11 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder)
>  
>  	intel_dsi_clear_device_ready(encoder);
>  
> -	val = I915_READ(DSPCLK_GATE_D);
> -	val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
> -	I915_WRITE(DSPCLK_GATE_D, val);
> +	if (!IS_BROXTON(dev)) {

You can use dev_priv for IS_BROXTON.

> +		val = I915_READ(DSPCLK_GATE_D);
> +		val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
> +		I915_WRITE(DSPCLK_GATE_D, val);
> +	}
>  
>  	drm_panel_unprepare(intel_dsi->panel);
>  
> -- 
> 1.7.9.5
>

-- 
Jani Nikula, Intel Open Source Technology Center
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Re: [BXT MIPI PATCH v2 13/13] drm/i915: Added BXT DSI backlight support

[Jani Nikula]

On Sun, 26 Jul 2015, Uma Shankar <uma.shankar@intel.com> wrote:
> DSI backlight support for bxt is added.
>
> TODO: There is no support for backlight control in drm panel
>       framework. This will be added as part of VBT version patches
>       fixing the backlight sequence.
>
> v2: Fixed Jani's review comments from previous patch. Added the
>     BXT DSI backlight code in this patch. Backlight setup and
>     enable/disable code for backlight is added in intel_dsi.c.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi.c |   25 ++++++++++++++++++++++++-
>  1 file changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index d0b26c8..36fcb86 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -431,6 +431,7 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
>  	struct drm_device *dev = encoder->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	struct intel_connector *intel_connector = intel_dsi->attached_connector;
>  	enum port port;
>  
>  	DRM_DEBUG_KMS("\n");
> @@ -451,6 +452,16 @@ static void intel_dsi_enable(struct intel_encoder *encoder)
>  
>  		intel_dsi_port_enable(encoder);
>  	}
> +
> +	if (IS_BROXTON(dev)) {
> +		if (intel_dsi->backlight_on_delay >= 20)
> +			msleep(intel_dsi->backlight_on_delay);
> +		else
> +			usleep_range(intel_dsi->backlight_on_delay * 1000,
> +					(intel_dsi->backlight_on_delay * 1000) + 500);

Please just use msleep, let's optimize (possibly with sensible wrappers)
later.

> +
> +		intel_panel_enable_backlight(intel_connector);
> +	}
>  }
>  
>  static void intel_dsi_pre_enable(struct intel_encoder *encoder)
> @@ -615,10 +626,20 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder)
>  	struct drm_device *dev = encoder->base.dev;
>  	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> +	struct intel_connector *intel_connector = intel_dsi->attached_connector;
>  	u32 val;
>  
>  	DRM_DEBUG_KMS("\n");
>  
> +	if (IS_BROXTON(dev)) {
> +		intel_panel_disable_backlight(intel_connector);
> +		if (intel_dsi->backlight_off_delay >= 20)
> +			msleep(intel_dsi->backlight_off_delay);
> +		else
> +			usleep_range(intel_dsi->backlight_off_delay * 1000,
> +				(intel_dsi->backlight_off_delay * 1000) + 500);
> +	}
> +
>  	intel_dsi_disable(encoder);
>  
>  	intel_dsi_clear_device_ready(encoder);
> @@ -1213,9 +1234,11 @@ void intel_dsi_init(struct drm_device *dev)
>  	}
>  
>  	intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
> +	if (IS_BROXTON(dev))
> +		intel_panel_setup_backlight(connector,
> +			intel_encoder->crtc_mask == (1 << PIPE_A) ? PIPE_A : PIPE_B);

The pipe parameter is not used for broxton, you can just pass
INVALID_PIPE.

>  
>  	return;
> -
>  err:
>  	drm_encoder_cleanup(&intel_encoder->base);
>  	kfree(intel_dsi);
> -- 
> 1.7.9.5
>

-- 
Jani Nikula, Intel Open Source Technology Center
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