* [PATCH 0/7] ARM: sunxi: Switch to clock indices
@ 2015-07-26 21:14 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-26 21:14 UTC (permalink / raw)
To: Mike Turquette, Stephen Boyd
Cc: Maxime Ripard, Chen-Yu Tsai, linux-clk, linux-arm-kernel
Hi,
We currently have in our clock driver a logic very similar to the one
that clock-indices is supposed to cover.
Using this property, we can create a new driver generic for all gates
that will get the valid indices directly from the device tree, instead
of storing that in the driver itself.
While we're at it, we also move to using CLK_OF_DECLARE for that new
driver, which should ease the orphan clocks breakage we saw.
Let me know what you think,
Maxime
Maxime Ripard (7):
ARM: sun4i: Add clock indices
ARM: sun5i: Add clock indices
ARM: sun6i: Add clock indices
ARM: sun7i: Add clock indices
ARM: sun8i: Add clock indices
ARM: sun9i: Add clock indices
clk: sunxi: Add a simple gates driver
arch/arm/boot/dts/sun4i-a10.dtsi | 69 ++++++++++----
arch/arm/boot/dts/sun5i-a10s.dtsi | 23 ++++-
arch/arm/boot/dts/sun5i-a13.dtsi | 18 +++-
arch/arm/boot/dts/sun5i.dtsi | 1 +
arch/arm/boot/dts/sun6i-a31.dtsi | 24 +++++
arch/arm/boot/dts/sun7i-a20.dtsi | 23 +++++
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++
arch/arm/boot/dts/sun9i-a80.dtsi | 32 +++++--
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk-simple-gates.c | 159 +++++++++++++++++++++++++++++++
drivers/clk/sunxi/clk-sunxi.c | 177 -----------------------------------
11 files changed, 335 insertions(+), 207 deletions(-)
create mode 100644 drivers/clk/sunxi/clk-simple-gates.c
--
2.4.6
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 0/7] ARM: sunxi: Switch to clock indices
@ 2015-07-26 21:14 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-26 21:14 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
We currently have in our clock driver a logic very similar to the one
that clock-indices is supposed to cover.
Using this property, we can create a new driver generic for all gates
that will get the valid indices directly from the device tree, instead
of storing that in the driver itself.
While we're at it, we also move to using CLK_OF_DECLARE for that new
driver, which should ease the orphan clocks breakage we saw.
Let me know what you think,
Maxime
Maxime Ripard (7):
ARM: sun4i: Add clock indices
ARM: sun5i: Add clock indices
ARM: sun6i: Add clock indices
ARM: sun7i: Add clock indices
ARM: sun8i: Add clock indices
ARM: sun9i: Add clock indices
clk: sunxi: Add a simple gates driver
arch/arm/boot/dts/sun4i-a10.dtsi | 69 ++++++++++----
arch/arm/boot/dts/sun5i-a10s.dtsi | 23 ++++-
arch/arm/boot/dts/sun5i-a13.dtsi | 18 +++-
arch/arm/boot/dts/sun5i.dtsi | 1 +
arch/arm/boot/dts/sun6i-a31.dtsi | 24 +++++
arch/arm/boot/dts/sun7i-a20.dtsi | 23 +++++
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++
arch/arm/boot/dts/sun9i-a80.dtsi | 32 +++++--
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk-simple-gates.c | 159 +++++++++++++++++++++++++++++++
drivers/clk/sunxi/clk-sunxi.c | 177 -----------------------------------
11 files changed, 335 insertions(+), 207 deletions(-)
create mode 100644 drivers/clk/sunxi/clk-simple-gates.c
--
2.4.6
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 1/7] ARM: sun4i: Add clock indices
2015-07-26 21:14 ` Maxime Ripard
@ 2015-07-26 21:14 ` Maxime Ripard
-1 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-26 21:14 UTC (permalink / raw)
To: Mike Turquette, Stephen Boyd
Cc: Maxime Ripard, Chen-Yu Tsai, linux-clk, linux-arm-kernel
The A10 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun4i-a10.dtsi | 69 ++++++++++++++++++++++++++++++----------
1 file changed, 52 insertions(+), 17 deletions(-)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 61c03d1fe530..ab0e131587bb 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -241,6 +241,7 @@
compatible = "allwinner,sun4i-a10-axi-gates-clk";
reg = <0x01c2005c 0x4>;
clocks = <&axi>;
+ clock-indices = <0>;
clock-output-names = "axi_dram";
};
@@ -257,17 +258,36 @@
compatible = "allwinner,sun4i-a10-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+ <2>, <3>,
+ <4>, <5>, <6>,
+ <7>, <8>, <9>,
+ <10>, <11>, <12>,
+ <13>, <14>, <16>,
+ <17>, <18>, <20>,
+ <21>, <22>, <23>,
+ <24>, <25>, <26>,
+ <32>, <33>, <34>,
+ <35>, <36>, <37>,
+ <40>, <41>, <43>,
+ <44>, <45>,
+ <46>, <47>,
+ <50>, <52>;
clock-output-names = "ahb_usb0", "ahb_ehci0",
- "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
- "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
- "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
- "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
- "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
- "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
- "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
- "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
- "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
- "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+ "ahb_ohci0", "ahb_ehci1",
+ "ahb_ohci1", "ahb_ss", "ahb_dma",
+ "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+ "ahb_mmc2", "ahb_mmc3", "ahb_ms",
+ "ahb_nand", "ahb_sdram", "ahb_ace",
+ "ahb_emac", "ahb_ts", "ahb_spi0",
+ "ahb_spi1", "ahb_spi2", "ahb_spi3",
+ "ahb_pata", "ahb_sata", "ahb_gps",
+ "ahb_ve", "ahb_tvd", "ahb_tve0",
+ "ahb_tve1", "ahb_lcd0", "ahb_lcd1",
+ "ahb_csi0", "ahb_csi1", "ahb_hdmi",
+ "ahb_de_be0", "ahb_de_be1",
+ "ahb_de_fe0", "ahb_de_fe1",
+ "ahb_mp", "ahb_mali400";
};
apb0: apb0@01c20054 {
@@ -283,9 +303,14 @@
compatible = "allwinner,sun4i-a10-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
+ clock-indices = <0>, <1>,
+ <2>, <3>,
+ <5>, <6>,
+ <7>, <10>;
clock-output-names = "apb0_codec", "apb0_spdif",
- "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
- "apb0_ir1", "apb0_keypad";
+ "apb0_ac97", "apb0_iis",
+ "apb0_pio", "apb0_ir0",
+ "apb0_ir1", "apb0_keypad";
};
apb1: clk@01c20058 {
@@ -301,12 +326,22 @@
compatible = "allwinner,sun4i-a10-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <1>,
+ <2>, <4>,
+ <5>, <6>,
+ <7>, <16>,
+ <17>, <18>,
+ <19>, <20>,
+ <21>, <22>,
+ <23>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_can", "apb1_scr",
- "apb1_ps20", "apb1_ps21", "apb1_uart0",
- "apb1_uart1", "apb1_uart2", "apb1_uart3",
- "apb1_uart4", "apb1_uart5", "apb1_uart6",
- "apb1_uart7";
+ "apb1_i2c2", "apb1_can",
+ "apb1_scr", "apb1_ps20",
+ "apb1_ps21", "apb1_uart0",
+ "apb1_uart1", "apb1_uart2",
+ "apb1_uart3", "apb1_uart4",
+ "apb1_uart5", "apb1_uart6",
+ "apb1_uart7";
};
nand_clk: clk@01c20080 {
--
2.4.6
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 1/7] ARM: sun4i: Add clock indices
@ 2015-07-26 21:14 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-26 21:14 UTC (permalink / raw)
To: linux-arm-kernel
The A10 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun4i-a10.dtsi | 69 ++++++++++++++++++++++++++++++----------
1 file changed, 52 insertions(+), 17 deletions(-)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 61c03d1fe530..ab0e131587bb 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -241,6 +241,7 @@
compatible = "allwinner,sun4i-a10-axi-gates-clk";
reg = <0x01c2005c 0x4>;
clocks = <&axi>;
+ clock-indices = <0>;
clock-output-names = "axi_dram";
};
@@ -257,17 +258,36 @@
compatible = "allwinner,sun4i-a10-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+ <2>, <3>,
+ <4>, <5>, <6>,
+ <7>, <8>, <9>,
+ <10>, <11>, <12>,
+ <13>, <14>, <16>,
+ <17>, <18>, <20>,
+ <21>, <22>, <23>,
+ <24>, <25>, <26>,
+ <32>, <33>, <34>,
+ <35>, <36>, <37>,
+ <40>, <41>, <43>,
+ <44>, <45>,
+ <46>, <47>,
+ <50>, <52>;
clock-output-names = "ahb_usb0", "ahb_ehci0",
- "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
- "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
- "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
- "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
- "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
- "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
- "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
- "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
- "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
- "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+ "ahb_ohci0", "ahb_ehci1",
+ "ahb_ohci1", "ahb_ss", "ahb_dma",
+ "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+ "ahb_mmc2", "ahb_mmc3", "ahb_ms",
+ "ahb_nand", "ahb_sdram", "ahb_ace",
+ "ahb_emac", "ahb_ts", "ahb_spi0",
+ "ahb_spi1", "ahb_spi2", "ahb_spi3",
+ "ahb_pata", "ahb_sata", "ahb_gps",
+ "ahb_ve", "ahb_tvd", "ahb_tve0",
+ "ahb_tve1", "ahb_lcd0", "ahb_lcd1",
+ "ahb_csi0", "ahb_csi1", "ahb_hdmi",
+ "ahb_de_be0", "ahb_de_be1",
+ "ahb_de_fe0", "ahb_de_fe1",
+ "ahb_mp", "ahb_mali400";
};
apb0: apb0 at 01c20054 {
@@ -283,9 +303,14 @@
compatible = "allwinner,sun4i-a10-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
+ clock-indices = <0>, <1>,
+ <2>, <3>,
+ <5>, <6>,
+ <7>, <10>;
clock-output-names = "apb0_codec", "apb0_spdif",
- "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
- "apb0_ir1", "apb0_keypad";
+ "apb0_ac97", "apb0_iis",
+ "apb0_pio", "apb0_ir0",
+ "apb0_ir1", "apb0_keypad";
};
apb1: clk at 01c20058 {
@@ -301,12 +326,22 @@
compatible = "allwinner,sun4i-a10-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <1>,
+ <2>, <4>,
+ <5>, <6>,
+ <7>, <16>,
+ <17>, <18>,
+ <19>, <20>,
+ <21>, <22>,
+ <23>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_can", "apb1_scr",
- "apb1_ps20", "apb1_ps21", "apb1_uart0",
- "apb1_uart1", "apb1_uart2", "apb1_uart3",
- "apb1_uart4", "apb1_uart5", "apb1_uart6",
- "apb1_uart7";
+ "apb1_i2c2", "apb1_can",
+ "apb1_scr", "apb1_ps20",
+ "apb1_ps21", "apb1_uart0",
+ "apb1_uart1", "apb1_uart2",
+ "apb1_uart3", "apb1_uart4",
+ "apb1_uart5", "apb1_uart6",
+ "apb1_uart7";
};
nand_clk: clk at 01c20080 {
--
2.4.6
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 2/7] ARM: sun5i: Add clock indices
2015-07-26 21:14 ` Maxime Ripard
@ 2015-07-26 21:14 ` Maxime Ripard
-1 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-26 21:14 UTC (permalink / raw)
To: Mike Turquette, Stephen Boyd
Cc: linux-clk, Chen-Yu Tsai, linux-arm-kernel, Maxime Ripard
The A10s and A13 gates have a non continuous set of clock IDs that are
valid. Add the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 23 +++++++++++++++++++++--
arch/arm/boot/dts/sun5i-a13.dtsi | 18 +++++++++++++++++-
arch/arm/boot/dts/sun5i.dtsi | 1 +
3 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index f11efb722bbb..a513b416a807 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -85,6 +85,17 @@
compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+ <2>, <5>, <6>,
+ <7>, <8>, <9>,
+ <10>, <13>,
+ <14>, <17>, <18>,
+ <20>, <21>, <22>,
+ <26>, <28>, <32>,
+ <34>, <36>, <40>,
+ <43>, <44>,
+ <46>, <51>,
+ <52>;
clock-output-names = "ahb_usbotg", "ahb_ehci",
"ahb_ohci", "ahb_ss", "ahb_dma",
"ahb_bist", "ahb_mmc0", "ahb_mmc1",
@@ -103,6 +114,9 @@
compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
+ clock-indices = <0>, <3>,
+ <5>, <6>,
+ <10>;
clock-output-names = "apb0_codec", "apb0_iis",
"apb0_pio", "apb0_ir",
"apb0_keypad";
@@ -113,9 +127,14 @@
compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <1>,
+ <2>, <16>,
+ <17>, <18>,
+ <19>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_uart0", "apb1_uart1",
- "apb1_uart2", "apb1_uart3";
+ "apb1_i2c2", "apb1_uart0",
+ "apb1_uart1", "apb1_uart2",
+ "apb1_uart3";
};
};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 976d4faa2179..f3631c9c6fa2 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -104,6 +104,16 @@
compatible = "allwinner,sun5i-a13-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+ <2>, <5>, <6>,
+ <7>, <8>, <9>,
+ <10>, <13>,
+ <14>, <20>,
+ <21>, <22>,
+ <28>, <32>, <36>,
+ <40>, <44>,
+ <46>, <51>,
+ <52>;
clock-output-names = "ahb_usbotg", "ahb_ehci",
"ahb_ohci", "ahb_ss", "ahb_dma",
"ahb_bist", "ahb_mmc0", "ahb_mmc1",
@@ -121,6 +131,8 @@
compatible = "allwinner,sun5i-a13-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
+ clock-indices = <0>, <5>,
+ <6>;
clock-output-names = "apb0_codec", "apb0_pio",
"apb0_ir";
};
@@ -130,8 +142,12 @@
compatible = "allwinner,sun5i-a13-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <1>,
+ <2>, <17>,
+ <19>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_uart1", "apb1_uart3";
+ "apb1_i2c2", "apb1_uart1",
+ "apb1_uart3";
};
};
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 54b097830434..427c0e7289fa 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -178,6 +178,7 @@
compatible = "allwinner,sun4i-a10-axi-gates-clk";
reg = <0x01c2005c 0x4>;
clocks = <&axi>;
+ clock-indices = <0>;
clock-output-names = "axi_dram";
};
--
2.4.6
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 2/7] ARM: sun5i: Add clock indices
@ 2015-07-26 21:14 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-26 21:14 UTC (permalink / raw)
To: linux-arm-kernel
The A10s and A13 gates have a non continuous set of clock IDs that are
valid. Add the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun5i-a10s.dtsi | 23 +++++++++++++++++++++--
arch/arm/boot/dts/sun5i-a13.dtsi | 18 +++++++++++++++++-
arch/arm/boot/dts/sun5i.dtsi | 1 +
3 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index f11efb722bbb..a513b416a807 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -85,6 +85,17 @@
compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+ <2>, <5>, <6>,
+ <7>, <8>, <9>,
+ <10>, <13>,
+ <14>, <17>, <18>,
+ <20>, <21>, <22>,
+ <26>, <28>, <32>,
+ <34>, <36>, <40>,
+ <43>, <44>,
+ <46>, <51>,
+ <52>;
clock-output-names = "ahb_usbotg", "ahb_ehci",
"ahb_ohci", "ahb_ss", "ahb_dma",
"ahb_bist", "ahb_mmc0", "ahb_mmc1",
@@ -103,6 +114,9 @@
compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
+ clock-indices = <0>, <3>,
+ <5>, <6>,
+ <10>;
clock-output-names = "apb0_codec", "apb0_iis",
"apb0_pio", "apb0_ir",
"apb0_keypad";
@@ -113,9 +127,14 @@
compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <1>,
+ <2>, <16>,
+ <17>, <18>,
+ <19>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_uart0", "apb1_uart1",
- "apb1_uart2", "apb1_uart3";
+ "apb1_i2c2", "apb1_uart0",
+ "apb1_uart1", "apb1_uart2",
+ "apb1_uart3";
};
};
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 976d4faa2179..f3631c9c6fa2 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -104,6 +104,16 @@
compatible = "allwinner,sun5i-a13-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+ <2>, <5>, <6>,
+ <7>, <8>, <9>,
+ <10>, <13>,
+ <14>, <20>,
+ <21>, <22>,
+ <28>, <32>, <36>,
+ <40>, <44>,
+ <46>, <51>,
+ <52>;
clock-output-names = "ahb_usbotg", "ahb_ehci",
"ahb_ohci", "ahb_ss", "ahb_dma",
"ahb_bist", "ahb_mmc0", "ahb_mmc1",
@@ -121,6 +131,8 @@
compatible = "allwinner,sun5i-a13-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
+ clock-indices = <0>, <5>,
+ <6>;
clock-output-names = "apb0_codec", "apb0_pio",
"apb0_ir";
};
@@ -130,8 +142,12 @@
compatible = "allwinner,sun5i-a13-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <1>,
+ <2>, <17>,
+ <19>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
- "apb1_i2c2", "apb1_uart1", "apb1_uart3";
+ "apb1_i2c2", "apb1_uart1",
+ "apb1_uart3";
};
};
};
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 54b097830434..427c0e7289fa 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -178,6 +178,7 @@
compatible = "allwinner,sun4i-a10-axi-gates-clk";
reg = <0x01c2005c 0x4>;
clocks = <&axi>;
+ clock-indices = <0>;
clock-output-names = "axi_dram";
};
--
2.4.6
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 3/7] ARM: sun6i: Add clock indices
2015-07-26 21:14 ` Maxime Ripard
@ 2015-07-26 21:14 ` Maxime Ripard
-1 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-26 21:14 UTC (permalink / raw)
To: Mike Turquette, Stephen Boyd
Cc: Maxime Ripard, Chen-Yu Tsai, linux-clk, linux-arm-kernel
The A31 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 008047a018cf..3ec456fa03a4 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -252,6 +252,20 @@
compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb1>;
+ clock-indices = <1>, <5>,
+ <6>, <8>, <9>,
+ <10>, <11>, <12>,
+ <13>, <14>,
+ <17>, <18>, <19>,
+ <20>, <21>, <22>,
+ <23>, <24>, <26>,
+ <27>, <29>,
+ <30>, <31>, <32>,
+ <36>, <37>, <40>,
+ <43>, <44>, <45>,
+ <46>, <47>, <50>,
+ <52>, <55>, <56>,
+ <57>, <58>;
clock-output-names = "ahb1_mipidsi", "ahb1_ss",
"ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
"ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
@@ -281,6 +295,9 @@
compatible = "allwinner,sun6i-a31-apb1-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <4>,
+ <5>, <12>,
+ <13>;
clock-output-names = "apb1_codec", "apb1_digital_mic",
"apb1_pio", "apb1_daudio0",
"apb1_daudio1";
@@ -299,6 +316,10 @@
compatible = "allwinner,sun6i-a31-apb2-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb2>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <16>,
+ <17>, <18>, <19>,
+ <20>, <21>;
clock-output-names = "apb2_i2c0", "apb2_i2c1",
"apb2_i2c2", "apb2_i2c3",
"apb2_uart0", "apb2_uart1",
@@ -384,6 +405,9 @@
compatible = "allwinner,sun6i-a31-usb-clk";
reg = <0x01c200cc 0x4>;
clocks = <&osc24M>;
+ clock-indices = <8>, <9>, <10>,
+ <16>, <17>,
+ <18>;
clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
"usb_ohci0", "usb_ohci1",
"usb_ohci2";
--
2.4.6
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 3/7] ARM: sun6i: Add clock indices
@ 2015-07-26 21:14 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-26 21:14 UTC (permalink / raw)
To: linux-arm-kernel
The A31 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 008047a018cf..3ec456fa03a4 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -252,6 +252,20 @@
compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb1>;
+ clock-indices = <1>, <5>,
+ <6>, <8>, <9>,
+ <10>, <11>, <12>,
+ <13>, <14>,
+ <17>, <18>, <19>,
+ <20>, <21>, <22>,
+ <23>, <24>, <26>,
+ <27>, <29>,
+ <30>, <31>, <32>,
+ <36>, <37>, <40>,
+ <43>, <44>, <45>,
+ <46>, <47>, <50>,
+ <52>, <55>, <56>,
+ <57>, <58>;
clock-output-names = "ahb1_mipidsi", "ahb1_ss",
"ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
"ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
@@ -281,6 +295,9 @@
compatible = "allwinner,sun6i-a31-apb1-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <4>,
+ <5>, <12>,
+ <13>;
clock-output-names = "apb1_codec", "apb1_digital_mic",
"apb1_pio", "apb1_daudio0",
"apb1_daudio1";
@@ -299,6 +316,10 @@
compatible = "allwinner,sun6i-a31-apb2-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb2>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <16>,
+ <17>, <18>, <19>,
+ <20>, <21>;
clock-output-names = "apb2_i2c0", "apb2_i2c1",
"apb2_i2c2", "apb2_i2c3",
"apb2_uart0", "apb2_uart1",
@@ -384,6 +405,9 @@
compatible = "allwinner,sun6i-a31-usb-clk";
reg = <0x01c200cc 0x4>;
clocks = <&osc24M>;
+ clock-indices = <8>, <9>, <10>,
+ <16>, <17>,
+ <18>;
clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
"usb_ohci0", "usb_ohci1",
"usb_ohci2";
--
2.4.6
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 4/7] ARM: sun7i: Add clock indices
2015-07-26 21:14 ` Maxime Ripard
@ 2015-07-26 21:14 ` Maxime Ripard
-1 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-26 21:14 UTC (permalink / raw)
To: Mike Turquette, Stephen Boyd
Cc: linux-clk, Chen-Yu Tsai, linux-arm-kernel, Maxime Ripard
The A20 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun7i-a20.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 6a63f30c9a69..ca0b01a96c52 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -267,6 +267,19 @@
compatible = "allwinner,sun7i-a20-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <4>,
+ <5>, <6>, <7>, <8>,
+ <9>, <10>, <11>, <12>,
+ <13>, <14>, <16>,
+ <17>, <18>, <20>, <21>,
+ <22>, <23>, <25>,
+ <28>, <32>, <33>, <34>,
+ <35>, <36>, <37>, <40>,
+ <41>, <42>, <43>,
+ <44>, <45>, <46>,
+ <47>, <49>, <50>,
+ <52>;
clock-output-names = "ahb_usb0", "ahb_ehci0",
"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
@@ -295,6 +308,10 @@
compatible = "allwinner,sun7i-a20-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <4>,
+ <5>, <6>, <7>,
+ <8>, <10>;
clock-output-names = "apb0_codec", "apb0_spdif",
"apb0_ac97", "apb0_iis0", "apb0_iis1",
"apb0_pio", "apb0_ir0", "apb0_ir1",
@@ -314,6 +331,12 @@
compatible = "allwinner,sun7i-a20-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <4>,
+ <5>, <6>, <7>,
+ <15>, <16>, <17>,
+ <18>, <19>, <20>,
+ <21>, <22>, <23>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
"apb1_i2c2", "apb1_i2c3", "apb1_can",
"apb1_scr", "apb1_ps20", "apb1_ps21",
--
2.4.6
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 4/7] ARM: sun7i: Add clock indices
@ 2015-07-26 21:14 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-26 21:14 UTC (permalink / raw)
To: linux-arm-kernel
The A20 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun7i-a20.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 6a63f30c9a69..ca0b01a96c52 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -267,6 +267,19 @@
compatible = "allwinner,sun7i-a20-ahb-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <4>,
+ <5>, <6>, <7>, <8>,
+ <9>, <10>, <11>, <12>,
+ <13>, <14>, <16>,
+ <17>, <18>, <20>, <21>,
+ <22>, <23>, <25>,
+ <28>, <32>, <33>, <34>,
+ <35>, <36>, <37>, <40>,
+ <41>, <42>, <43>,
+ <44>, <45>, <46>,
+ <47>, <49>, <50>,
+ <52>;
clock-output-names = "ahb_usb0", "ahb_ehci0",
"ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
@@ -295,6 +308,10 @@
compatible = "allwinner,sun7i-a20-apb0-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb0>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <4>,
+ <5>, <6>, <7>,
+ <8>, <10>;
clock-output-names = "apb0_codec", "apb0_spdif",
"apb0_ac97", "apb0_iis0", "apb0_iis1",
"apb0_pio", "apb0_ir0", "apb0_ir1",
@@ -314,6 +331,12 @@
compatible = "allwinner,sun7i-a20-apb1-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <4>,
+ <5>, <6>, <7>,
+ <15>, <16>, <17>,
+ <18>, <19>, <20>,
+ <21>, <22>, <23>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
"apb1_i2c2", "apb1_i2c3", "apb1_can",
"apb1_scr", "apb1_ps20", "apb1_ps21",
--
2.4.6
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 5/7] ARM: sun8i: Add clock indices
2015-07-26 21:14 ` Maxime Ripard
@ 2015-07-26 21:14 ` Maxime Ripard
-1 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-26 21:14 UTC (permalink / raw)
To: Mike Turquette, Stephen Boyd
Cc: Maxime Ripard, Chen-Yu Tsai, linux-clk, linux-arm-kernel
The A23 and A33 gates have a non continuous set of clock IDs that are
valid. Add the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 7abd0ae3143d..c318c770b6c1 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -180,6 +180,15 @@
compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb1>;
+ clock-indices = <1>, <6>,
+ <8>, <9>, <10>,
+ <13>, <14>,
+ <19>, <20>,
+ <21>, <24>, <26>,
+ <29>, <32>, <36>,
+ <40>, <44>, <46>,
+ <52>, <54>,
+ <57>;
clock-output-names = "ahb1_mipidsi", "ahb1_dma",
"ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
"ahb1_nand", "ahb1_sdram",
@@ -196,6 +205,8 @@
compatible = "allwinner,sun8i-a23-apb1-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <5>,
+ <12>, <13>;
clock-output-names = "apb1_codec", "apb1_pio",
"apb1_daudio0", "apb1_daudio1";
};
@@ -213,6 +224,10 @@
compatible = "allwinner,sun8i-a23-apb2-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb2>;
+ clock-indices = <0>, <1>,
+ <2>, <16>,
+ <17>, <18>,
+ <19>, <20>;
clock-output-names = "apb2_i2c0", "apb2_i2c1",
"apb2_i2c2", "apb2_uart0",
"apb2_uart1", "apb2_uart2",
--
2.4.6
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 5/7] ARM: sun8i: Add clock indices
@ 2015-07-26 21:14 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-26 21:14 UTC (permalink / raw)
To: linux-arm-kernel
The A23 and A33 gates have a non continuous set of clock IDs that are
valid. Add the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 7abd0ae3143d..c318c770b6c1 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -180,6 +180,15 @@
compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
reg = <0x01c20060 0x8>;
clocks = <&ahb1>;
+ clock-indices = <1>, <6>,
+ <8>, <9>, <10>,
+ <13>, <14>,
+ <19>, <20>,
+ <21>, <24>, <26>,
+ <29>, <32>, <36>,
+ <40>, <44>, <46>,
+ <52>, <54>,
+ <57>;
clock-output-names = "ahb1_mipidsi", "ahb1_dma",
"ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
"ahb1_nand", "ahb1_sdram",
@@ -196,6 +205,8 @@
compatible = "allwinner,sun8i-a23-apb1-gates-clk";
reg = <0x01c20068 0x4>;
clocks = <&apb1>;
+ clock-indices = <0>, <5>,
+ <12>, <13>;
clock-output-names = "apb1_codec", "apb1_pio",
"apb1_daudio0", "apb1_daudio1";
};
@@ -213,6 +224,10 @@
compatible = "allwinner,sun8i-a23-apb2-gates-clk";
reg = <0x01c2006c 0x4>;
clocks = <&apb2>;
+ clock-indices = <0>, <1>,
+ <2>, <16>,
+ <17>, <18>,
+ <19>, <20>;
clock-output-names = "apb2_i2c0", "apb2_i2c1",
"apb2_i2c2", "apb2_uart0",
"apb2_uart1", "apb2_uart2",
--
2.4.6
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 6/7] ARM: sun9i: Add clock indices
2015-07-26 21:14 ` Maxime Ripard
@ 2015-07-26 21:14 ` Maxime Ripard
-1 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-26 21:14 UTC (permalink / raw)
To: Mike Turquette, Stephen Boyd
Cc: Maxime Ripard, Chen-Yu Tsai, linux-clk, linux-arm-kernel
The A80 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun9i-a80.dtsi | 32 ++++++++++++++++++++++----------
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index a43ad779ee2f..5908e3dcf965 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -277,9 +277,12 @@
compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
reg = <0x06000580 0x4>;
clocks = <&ahb0>;
- clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>,
- <14>, <15>, <16>, <18>, <20>, <21>,
- <22>, <23>;
+ clock-indices = <0>, <1>, <3>,
+ <5>, <8>, <12>,
+ <13>, <14>,
+ <15>, <16>, <18>,
+ <20>, <21>, <22>,
+ <23>;
clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
"ahb0_ss", "ahb0_sd", "ahb0_nand1",
"ahb0_nand0", "ahb0_sdram",
@@ -293,7 +296,10 @@
compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
reg = <0x06000584 0x4>;
clocks = <&ahb1>;
- clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>;
+ clock-indices = <0>, <1>,
+ <17>, <21>,
+ <22>, <23>,
+ <24>;
clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
"ahb1_gmac", "ahb1_msgbox",
"ahb1_spinlock", "ahb1_hstimer",
@@ -305,8 +311,9 @@
compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
reg = <0x06000588 0x4>;
clocks = <&ahb2>;
- clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>,
- <11>;
+ clock-indices = <0>, <1>,
+ <2>, <4>, <5>,
+ <7>, <8>, <11>;
clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
"ahb2_edp", "ahb2_csi", "ahb2_hdmi",
"ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
@@ -317,8 +324,10 @@
compatible = "allwinner,sun9i-a80-apb0-gates-clk";
reg = <0x06000590 0x4>;
clocks = <&apb0>;
- clock-indices = <1>, <5>, <11>, <12>, <13>, <15>,
- <17>, <18>, <19>;
+ clock-indices = <1>, <5>,
+ <11>, <12>, <13>,
+ <15>, <17>, <18>,
+ <19>;
clock-output-names = "apb0_spdif", "apb0_pio",
"apb0_ac97", "apb0_i2s0", "apb0_i2s1",
"apb0_lradc", "apb0_gpadc", "apb0_twd",
@@ -330,8 +339,11 @@
compatible = "allwinner,sun9i-a80-apb1-gates-clk";
reg = <0x06000594 0x4>;
clocks = <&apb1>;
- clock-indices = <0>, <1>, <2>, <3>, <4>,
- <16>, <17>, <18>, <19>, <20>, <21>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <4>,
+ <16>, <17>,
+ <18>, <19>,
+ <20>, <21>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
"apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
"apb1_uart0", "apb1_uart1",
--
2.4.6
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 6/7] ARM: sun9i: Add clock indices
@ 2015-07-26 21:14 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-26 21:14 UTC (permalink / raw)
To: linux-arm-kernel
The A80 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
arch/arm/boot/dts/sun9i-a80.dtsi | 32 ++++++++++++++++++++++----------
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index a43ad779ee2f..5908e3dcf965 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -277,9 +277,12 @@
compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
reg = <0x06000580 0x4>;
clocks = <&ahb0>;
- clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>,
- <14>, <15>, <16>, <18>, <20>, <21>,
- <22>, <23>;
+ clock-indices = <0>, <1>, <3>,
+ <5>, <8>, <12>,
+ <13>, <14>,
+ <15>, <16>, <18>,
+ <20>, <21>, <22>,
+ <23>;
clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
"ahb0_ss", "ahb0_sd", "ahb0_nand1",
"ahb0_nand0", "ahb0_sdram",
@@ -293,7 +296,10 @@
compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
reg = <0x06000584 0x4>;
clocks = <&ahb1>;
- clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>;
+ clock-indices = <0>, <1>,
+ <17>, <21>,
+ <22>, <23>,
+ <24>;
clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
"ahb1_gmac", "ahb1_msgbox",
"ahb1_spinlock", "ahb1_hstimer",
@@ -305,8 +311,9 @@
compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
reg = <0x06000588 0x4>;
clocks = <&ahb2>;
- clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>,
- <11>;
+ clock-indices = <0>, <1>,
+ <2>, <4>, <5>,
+ <7>, <8>, <11>;
clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
"ahb2_edp", "ahb2_csi", "ahb2_hdmi",
"ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
@@ -317,8 +324,10 @@
compatible = "allwinner,sun9i-a80-apb0-gates-clk";
reg = <0x06000590 0x4>;
clocks = <&apb0>;
- clock-indices = <1>, <5>, <11>, <12>, <13>, <15>,
- <17>, <18>, <19>;
+ clock-indices = <1>, <5>,
+ <11>, <12>, <13>,
+ <15>, <17>, <18>,
+ <19>;
clock-output-names = "apb0_spdif", "apb0_pio",
"apb0_ac97", "apb0_i2s0", "apb0_i2s1",
"apb0_lradc", "apb0_gpadc", "apb0_twd",
@@ -330,8 +339,11 @@
compatible = "allwinner,sun9i-a80-apb1-gates-clk";
reg = <0x06000594 0x4>;
clocks = <&apb1>;
- clock-indices = <0>, <1>, <2>, <3>, <4>,
- <16>, <17>, <18>, <19>, <20>, <21>;
+ clock-indices = <0>, <1>,
+ <2>, <3>, <4>,
+ <16>, <17>,
+ <18>, <19>,
+ <20>, <21>;
clock-output-names = "apb1_i2c0", "apb1_i2c1",
"apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
"apb1_uart0", "apb1_uart1",
--
2.4.6
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 7/7] clk: sunxi: Add a simple gates driver
2015-07-26 21:14 ` Maxime Ripard
@ 2015-07-26 21:14 ` Maxime Ripard
-1 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-26 21:14 UTC (permalink / raw)
To: Mike Turquette, Stephen Boyd
Cc: Maxime Ripard, Chen-Yu Tsai, linux-clk, linux-arm-kernel
The gates were handled with a common piece of framework that was
registering all gates array, that was not using the CLK_OF_DECLARE logic,
and was not using clock-indices but some private masks that were pretty
much equivalent.
Move this code in a new driver that handles all the gates array and solves
both these issues.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk-simple-gates.c | 159 +++++++++++++++++++++++++++++++
drivers/clk/sunxi/clk-sunxi.c | 177 -----------------------------------
3 files changed, 160 insertions(+), 177 deletions(-)
create mode 100644 drivers/clk/sunxi/clk-simple-gates.c
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 058f273d6154..f5a35b82cc1a 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -6,6 +6,7 @@ obj-y += clk-sunxi.o clk-factors.o
obj-y += clk-a10-hosc.o
obj-y += clk-a20-gmac.o
obj-y += clk-mod0.o
+obj-y += clk-simple-gates.o
obj-y += clk-sun8i-mbus.o
obj-y += clk-sun9i-core.o
obj-y += clk-sun9i-mmc.o
diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
new file mode 100644
index 000000000000..1a3963a8a686
--- /dev/null
+++ b/drivers/clk/sunxi/clk-simple-gates.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/reset-controller.h>
+#include <linux/spinlock.h>
+#include <linux/log2.h>
+
+static DEFINE_SPINLOCK(gates_lock);
+
+static void __init sunxi_simple_gates_setup(struct device_node *node,
+ const int protected[],
+ int nprotected)
+{
+ struct clk_onecell_data *clk_data;
+ const char *clk_parent, *clk_name;
+ struct property *prop;
+ struct resource res;
+ void __iomem *clk_reg;
+ void __iomem *reg;
+ const __be32 *p;
+ int number, i = 0, j;
+ u8 clk_bit;
+ u32 index;
+
+ reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+ if (IS_ERR(reg))
+ return;
+
+ clk_parent = of_clk_get_parent_name(node, 0);
+
+ clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
+ if (!clk_data)
+ goto err_unmap;
+
+ number = of_property_count_u32_elems(node, "clock-indices");
+ of_property_read_u32_index(node, "clock-indices", number - 1, &number);
+
+ clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
+ if (!clk_data->clks)
+ goto err_free_data;
+
+ of_property_for_each_u32(node, "clock-indices", prop, p, index) {
+ of_property_read_string_index(node, "clock-output-names",
+ i, &clk_name);
+
+ clk_reg = reg + 4 * (index / 32);
+ clk_bit = index % 32;
+
+ clk_data->clks[index] = clk_register_gate(NULL, clk_name,
+ clk_parent, 0,
+ clk_reg,
+ clk_bit,
+ 0, &gates_lock);
+ i++;
+
+ if (IS_ERR(clk_data->clks[index])) {
+ WARN_ON(true);
+ continue;
+ }
+
+ for (j = 0; j < nprotected; j++)
+ if (protected[j] == index)
+ clk_prepare_enable(clk_data->clks[index]);
+
+ }
+
+ clk_data->clk_num = number + 1;
+ of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ return;
+
+err_free_data:
+ kfree(clk_data);
+err_unmap:
+ iounmap(reg);
+ of_address_to_resource(node, 0, &res);
+ release_mem_region(res.start, resource_size(&res));
+}
+
+static void __init sunxi_simple_gates_init(struct device_node *node)
+{
+ sunxi_simple_gates_setup(node, NULL, 0);
+}
+
+CLK_OF_DECLARE(sun4i_a10_apb0, "allwinner,sun4i-a10-apb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun4i_a10_apb1, "allwinner,sun4i-a10-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun4i_a10_axi, "allwinner,sun4i-a10-axi-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a10s_apb0, "allwinner,sun5i-a10s-apb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a10s_apb1, "allwinner,sun5i-a10s-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a13_apb0, "allwinner,sun5i-a13-apb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a13_apb1, "allwinner,sun5i-a13-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun6i_a31_apb1, "allwinner,sun6i-a31-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun6i_a31_apb2, "allwinner,sun6i-a31-apb2-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun7i_a20_apb0, "allwinner,sun7i-a20-apb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun7i_a20_apb1, "allwinner,sun7i-a20-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun8i_a23_ahb1, "allwinner,sun8i-a23-ahb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun8i_a23_apb1, "allwinner,sun8i-a23-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_ahb2, "allwinner,sun9i-a80-ahb2-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-gates-clk",
+ sunxi_simple_gates_init);
+
+static const int sun4i_a10_ahb_critical_clocks[] __initdata = {
+ 14, /* ahb_sdram */
+};
+
+static void __init sun4i_a10_ahb_init(struct device_node *node)
+{
+ sunxi_simple_gates_setup(node, sun4i_a10_ahb_critical_clocks,
+ ARRAY_SIZE(sun4i_a10_ahb_critical_clocks));
+}
+CLK_OF_DECLARE(sun4i_a10_ahb, "allwinner,sun4i-a10-ahb-gates-clk",
+ sun4i_a10_ahb_init);
+CLK_OF_DECLARE(sun5i_a10s_ahb, "allwinner,sun5i-a10s-ahb-gates-clk",
+ sun4i_a10_ahb_init);
+CLK_OF_DECLARE(sun5i_a13_ahb, "allwinner,sun5i-a13-ahb-gates-clk",
+ sun4i_a10_ahb_init);
+CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk",
+ sun4i_a10_ahb_init);
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index abf7b37faf73..1fec91093fcd 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -900,150 +900,6 @@ struct gates_data {
DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
};
-static const struct gates_data sun4i_axi_gates_data __initconst = {
- .mask = {1},
-};
-
-static const struct gates_data sun4i_ahb_gates_data __initconst = {
- .mask = {0x7F77FFF, 0x14FB3F},
-};
-
-static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
- .mask = {0x147667e7, 0x185915},
-};
-
-static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
- .mask = {0x107067e7, 0x185111},
-};
-
-static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
- .mask = {0xEDFE7F62, 0x794F931},
-};
-
-static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
- .mask = { 0x12f77fff, 0x16ff3f },
-};
-
-static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
- .mask = {0x25386742, 0x2505111},
-};
-
-static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
- .mask = {0xF5F12B},
-};
-
-static const struct gates_data sun9i_a80_ahb1_gates_data __initconst = {
- .mask = {0x1E20003},
-};
-
-static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
- .mask = {0x9B7},
-};
-
-static const struct gates_data sun4i_apb0_gates_data __initconst = {
- .mask = {0x4EF},
-};
-
-static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
- .mask = {0x469},
-};
-
-static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
- .mask = {0x61},
-};
-
-static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
- .mask = { 0x4ff },
-};
-
-static const struct gates_data sun9i_a80_apb0_gates_data __initconst = {
- .mask = {0xEB822},
-};
-
-static const struct gates_data sun4i_apb1_gates_data __initconst = {
- .mask = {0xFF00F7},
-};
-
-static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
- .mask = {0xf0007},
-};
-
-static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
- .mask = {0xa0007},
-};
-
-static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
- .mask = {0x3031},
-};
-
-static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
- .mask = {0x3021},
-};
-
-static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
- .mask = {0x3F000F},
-};
-
-static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
- .mask = { 0xff80ff },
-};
-
-static const struct gates_data sun9i_a80_apb1_gates_data __initconst = {
- .mask = {0x3F001F},
-};
-
-static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
- .mask = {0x1F0007},
-};
-
-static void __init sunxi_gates_clk_setup(struct device_node *node,
- struct gates_data *data)
-{
- struct clk_onecell_data *clk_data;
- const char *clk_parent;
- const char *clk_name;
- void __iomem *reg;
- int qty;
- int i = 0;
- int j = 0;
-
- reg = of_iomap(node, 0);
-
- clk_parent = of_clk_get_parent_name(node, 0);
-
- /* Worst-case size approximation and memory allocation */
- qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
- clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
- if (!clk_data)
- return;
- clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
- if (!clk_data->clks) {
- kfree(clk_data);
- return;
- }
-
- for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
- of_property_read_string_index(node, "clock-output-names",
- j, &clk_name);
-
- clk_data->clks[i] = clk_register_gate(NULL, clk_name,
- clk_parent, 0,
- reg + 4 * (i/32), i % 32,
- 0, &clk_lock);
- WARN_ON(IS_ERR(clk_data->clks[i]));
- clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
-
- j++;
- }
-
- /* Adjust to the real max */
- clk_data->clk_num = i;
-
- of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-}
-
-
-
/**
* sunxi_divs_clk_setup() helper data
*/
@@ -1281,34 +1137,6 @@ static const struct of_device_id clk_mux_match[] __initconst = {
{}
};
-/* Matches for gate clocks */
-static const struct of_device_id clk_gates_match[] __initconst = {
- {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
- {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
- {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
- {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
- {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
- {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
- {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
- {.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
- {.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
- {.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
- {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
- {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
- {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
- {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
- {.compatible = "allwinner,sun9i-a80-apb0-gates-clk", .data = &sun9i_a80_apb0_gates_data,},
- {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
- {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
- {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
- {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
- {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
- {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
- {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
- {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
- {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
- {}
-};
static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
void *function)
@@ -1340,9 +1168,6 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
/* Register mux clocks */
of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
- /* Register gate clocks */
- of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
-
/* Protect the clocks that needs to stay on */
for (i = 0; i < nclocks; i++) {
struct clk *clk = clk_get(NULL, clocks[i]);
@@ -1354,7 +1179,6 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
static const char *sun4i_a10_critical_clocks[] __initdata = {
"pll5_ddr",
- "ahb_sdram",
};
static void __init sun4i_a10_init_clocks(struct device_node *node)
@@ -1367,7 +1191,6 @@ CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks)
static const char *sun5i_critical_clocks[] __initdata = {
"cpu",
"pll5_ddr",
- "ahb_sdram",
};
static void __init sun5i_init_clocks(struct device_node *node)
--
2.4.6
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 7/7] clk: sunxi: Add a simple gates driver
@ 2015-07-26 21:14 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-26 21:14 UTC (permalink / raw)
To: linux-arm-kernel
The gates were handled with a common piece of framework that was
registering all gates array, that was not using the CLK_OF_DECLARE logic,
and was not using clock-indices but some private masks that were pretty
much equivalent.
Move this code in a new driver that handles all the gates array and solves
both these issues.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk-simple-gates.c | 159 +++++++++++++++++++++++++++++++
drivers/clk/sunxi/clk-sunxi.c | 177 -----------------------------------
3 files changed, 160 insertions(+), 177 deletions(-)
create mode 100644 drivers/clk/sunxi/clk-simple-gates.c
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 058f273d6154..f5a35b82cc1a 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -6,6 +6,7 @@ obj-y += clk-sunxi.o clk-factors.o
obj-y += clk-a10-hosc.o
obj-y += clk-a20-gmac.o
obj-y += clk-mod0.o
+obj-y += clk-simple-gates.o
obj-y += clk-sun8i-mbus.o
obj-y += clk-sun9i-core.o
obj-y += clk-sun9i-mmc.o
diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
new file mode 100644
index 000000000000..1a3963a8a686
--- /dev/null
+++ b/drivers/clk/sunxi/clk-simple-gates.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright 2015 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/reset-controller.h>
+#include <linux/spinlock.h>
+#include <linux/log2.h>
+
+static DEFINE_SPINLOCK(gates_lock);
+
+static void __init sunxi_simple_gates_setup(struct device_node *node,
+ const int protected[],
+ int nprotected)
+{
+ struct clk_onecell_data *clk_data;
+ const char *clk_parent, *clk_name;
+ struct property *prop;
+ struct resource res;
+ void __iomem *clk_reg;
+ void __iomem *reg;
+ const __be32 *p;
+ int number, i = 0, j;
+ u8 clk_bit;
+ u32 index;
+
+ reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+ if (IS_ERR(reg))
+ return;
+
+ clk_parent = of_clk_get_parent_name(node, 0);
+
+ clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
+ if (!clk_data)
+ goto err_unmap;
+
+ number = of_property_count_u32_elems(node, "clock-indices");
+ of_property_read_u32_index(node, "clock-indices", number - 1, &number);
+
+ clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
+ if (!clk_data->clks)
+ goto err_free_data;
+
+ of_property_for_each_u32(node, "clock-indices", prop, p, index) {
+ of_property_read_string_index(node, "clock-output-names",
+ i, &clk_name);
+
+ clk_reg = reg + 4 * (index / 32);
+ clk_bit = index % 32;
+
+ clk_data->clks[index] = clk_register_gate(NULL, clk_name,
+ clk_parent, 0,
+ clk_reg,
+ clk_bit,
+ 0, &gates_lock);
+ i++;
+
+ if (IS_ERR(clk_data->clks[index])) {
+ WARN_ON(true);
+ continue;
+ }
+
+ for (j = 0; j < nprotected; j++)
+ if (protected[j] == index)
+ clk_prepare_enable(clk_data->clks[index]);
+
+ }
+
+ clk_data->clk_num = number + 1;
+ of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+
+ return;
+
+err_free_data:
+ kfree(clk_data);
+err_unmap:
+ iounmap(reg);
+ of_address_to_resource(node, 0, &res);
+ release_mem_region(res.start, resource_size(&res));
+}
+
+static void __init sunxi_simple_gates_init(struct device_node *node)
+{
+ sunxi_simple_gates_setup(node, NULL, 0);
+}
+
+CLK_OF_DECLARE(sun4i_a10_apb0, "allwinner,sun4i-a10-apb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun4i_a10_apb1, "allwinner,sun4i-a10-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun4i_a10_axi, "allwinner,sun4i-a10-axi-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a10s_apb0, "allwinner,sun5i-a10s-apb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a10s_apb1, "allwinner,sun5i-a10s-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a13_apb0, "allwinner,sun5i-a13-apb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun5i_a13_apb1, "allwinner,sun5i-a13-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun6i_a31_apb1, "allwinner,sun6i-a31-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun6i_a31_apb2, "allwinner,sun6i-a31-apb2-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun7i_a20_apb0, "allwinner,sun7i-a20-apb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun7i_a20_apb1, "allwinner,sun7i-a20-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun8i_a23_ahb1, "allwinner,sun8i-a23-ahb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun8i_a23_apb1, "allwinner,sun8i-a23-apb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_ahb2, "allwinner,sun9i-a80-ahb2-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-gates-clk",
+ sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-gates-clk",
+ sunxi_simple_gates_init);
+
+static const int sun4i_a10_ahb_critical_clocks[] __initdata = {
+ 14, /* ahb_sdram */
+};
+
+static void __init sun4i_a10_ahb_init(struct device_node *node)
+{
+ sunxi_simple_gates_setup(node, sun4i_a10_ahb_critical_clocks,
+ ARRAY_SIZE(sun4i_a10_ahb_critical_clocks));
+}
+CLK_OF_DECLARE(sun4i_a10_ahb, "allwinner,sun4i-a10-ahb-gates-clk",
+ sun4i_a10_ahb_init);
+CLK_OF_DECLARE(sun5i_a10s_ahb, "allwinner,sun5i-a10s-ahb-gates-clk",
+ sun4i_a10_ahb_init);
+CLK_OF_DECLARE(sun5i_a13_ahb, "allwinner,sun5i-a13-ahb-gates-clk",
+ sun4i_a10_ahb_init);
+CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk",
+ sun4i_a10_ahb_init);
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index abf7b37faf73..1fec91093fcd 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -900,150 +900,6 @@ struct gates_data {
DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
};
-static const struct gates_data sun4i_axi_gates_data __initconst = {
- .mask = {1},
-};
-
-static const struct gates_data sun4i_ahb_gates_data __initconst = {
- .mask = {0x7F77FFF, 0x14FB3F},
-};
-
-static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
- .mask = {0x147667e7, 0x185915},
-};
-
-static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
- .mask = {0x107067e7, 0x185111},
-};
-
-static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
- .mask = {0xEDFE7F62, 0x794F931},
-};
-
-static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
- .mask = { 0x12f77fff, 0x16ff3f },
-};
-
-static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
- .mask = {0x25386742, 0x2505111},
-};
-
-static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
- .mask = {0xF5F12B},
-};
-
-static const struct gates_data sun9i_a80_ahb1_gates_data __initconst = {
- .mask = {0x1E20003},
-};
-
-static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
- .mask = {0x9B7},
-};
-
-static const struct gates_data sun4i_apb0_gates_data __initconst = {
- .mask = {0x4EF},
-};
-
-static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
- .mask = {0x469},
-};
-
-static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
- .mask = {0x61},
-};
-
-static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
- .mask = { 0x4ff },
-};
-
-static const struct gates_data sun9i_a80_apb0_gates_data __initconst = {
- .mask = {0xEB822},
-};
-
-static const struct gates_data sun4i_apb1_gates_data __initconst = {
- .mask = {0xFF00F7},
-};
-
-static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
- .mask = {0xf0007},
-};
-
-static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
- .mask = {0xa0007},
-};
-
-static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
- .mask = {0x3031},
-};
-
-static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
- .mask = {0x3021},
-};
-
-static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
- .mask = {0x3F000F},
-};
-
-static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
- .mask = { 0xff80ff },
-};
-
-static const struct gates_data sun9i_a80_apb1_gates_data __initconst = {
- .mask = {0x3F001F},
-};
-
-static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
- .mask = {0x1F0007},
-};
-
-static void __init sunxi_gates_clk_setup(struct device_node *node,
- struct gates_data *data)
-{
- struct clk_onecell_data *clk_data;
- const char *clk_parent;
- const char *clk_name;
- void __iomem *reg;
- int qty;
- int i = 0;
- int j = 0;
-
- reg = of_iomap(node, 0);
-
- clk_parent = of_clk_get_parent_name(node, 0);
-
- /* Worst-case size approximation and memory allocation */
- qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
- clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
- if (!clk_data)
- return;
- clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
- if (!clk_data->clks) {
- kfree(clk_data);
- return;
- }
-
- for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
- of_property_read_string_index(node, "clock-output-names",
- j, &clk_name);
-
- clk_data->clks[i] = clk_register_gate(NULL, clk_name,
- clk_parent, 0,
- reg + 4 * (i/32), i % 32,
- 0, &clk_lock);
- WARN_ON(IS_ERR(clk_data->clks[i]));
- clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
-
- j++;
- }
-
- /* Adjust to the real max */
- clk_data->clk_num = i;
-
- of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-}
-
-
-
/**
* sunxi_divs_clk_setup() helper data
*/
@@ -1281,34 +1137,6 @@ static const struct of_device_id clk_mux_match[] __initconst = {
{}
};
-/* Matches for gate clocks */
-static const struct of_device_id clk_gates_match[] __initconst = {
- {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
- {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
- {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
- {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
- {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
- {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
- {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
- {.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
- {.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
- {.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
- {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
- {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
- {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
- {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
- {.compatible = "allwinner,sun9i-a80-apb0-gates-clk", .data = &sun9i_a80_apb0_gates_data,},
- {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
- {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
- {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
- {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
- {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
- {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
- {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
- {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
- {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
- {}
-};
static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
void *function)
@@ -1340,9 +1168,6 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
/* Register mux clocks */
of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
- /* Register gate clocks */
- of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
-
/* Protect the clocks that needs to stay on */
for (i = 0; i < nclocks; i++) {
struct clk *clk = clk_get(NULL, clocks[i]);
@@ -1354,7 +1179,6 @@ static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
static const char *sun4i_a10_critical_clocks[] __initdata = {
"pll5_ddr",
- "ahb_sdram",
};
static void __init sun4i_a10_init_clocks(struct device_node *node)
@@ -1367,7 +1191,6 @@ CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks)
static const char *sun5i_critical_clocks[] __initdata = {
"cpu",
"pll5_ddr",
- "ahb_sdram",
};
static void __init sun5i_init_clocks(struct device_node *node)
--
2.4.6
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH 7/7] clk: sunxi: Add a simple gates driver
2015-07-26 21:14 ` Maxime Ripard
@ 2015-07-27 20:26 ` Stephen Boyd
-1 siblings, 0 replies; 28+ messages in thread
From: Stephen Boyd @ 2015-07-27 20:26 UTC (permalink / raw)
To: Maxime Ripard; +Cc: Mike Turquette, Chen-Yu Tsai, linux-clk, linux-arm-kernel
On 07/26, Maxime Ripard wrote:
> diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
> new file mode 100644
> index 000000000000..1a3963a8a686
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk-simple-gates.c
> @@ -0,0 +1,159 @@
> +/*
> + * Copyright 2015 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
Is this used?
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/reset-controller.h>
Is this used?
> +#include <linux/spinlock.h>
> +#include <linux/log2.h>
Is this used?
> +
> +static DEFINE_SPINLOCK(gates_lock);
> +
[...]
> +
> +static const int sun4i_a10_ahb_critical_clocks[] __initdata = {
Shouldn't it be __initconst ?
> + 14, /* ahb_sdram */
> +};
> +
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 7/7] clk: sunxi: Add a simple gates driver
@ 2015-07-27 20:26 ` Stephen Boyd
0 siblings, 0 replies; 28+ messages in thread
From: Stephen Boyd @ 2015-07-27 20:26 UTC (permalink / raw)
To: linux-arm-kernel
On 07/26, Maxime Ripard wrote:
> diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
> new file mode 100644
> index 000000000000..1a3963a8a686
> --- /dev/null
> +++ b/drivers/clk/sunxi/clk-simple-gates.c
> @@ -0,0 +1,159 @@
> +/*
> + * Copyright 2015 Maxime Ripard
> + *
> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/clkdev.h>
Is this used?
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/reset-controller.h>
Is this used?
> +#include <linux/spinlock.h>
> +#include <linux/log2.h>
Is this used?
> +
> +static DEFINE_SPINLOCK(gates_lock);
> +
[...]
> +
> +static const int sun4i_a10_ahb_critical_clocks[] __initdata = {
Shouldn't it be __initconst ?
> + 14, /* ahb_sdram */
> +};
> +
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 6/7] ARM: sun9i: Add clock indices
2015-07-26 21:14 ` Maxime Ripard
@ 2015-07-30 7:44 ` Chen-Yu Tsai
-1 siblings, 0 replies; 28+ messages in thread
From: Chen-Yu Tsai @ 2015-07-30 7:44 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mike Turquette, Chen-Yu Tsai, Stephen Boyd, linux-clk, linux-arm-kernel
On Mon, Jul 27, 2015 at 5:14 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The A80 gates have a non continuous set of clock IDs that are valid. Add
> the clock-indices property to the DT to express this.
The commit message does not match the patch, which is just a reformatting of
existing clock-indices properties.
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> arch/arm/boot/dts/sun9i-a80.dtsi | 32 ++++++++++++++++++++++----------
> 1 file changed, 22 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
> index a43ad779ee2f..5908e3dcf965 100644
> --- a/arch/arm/boot/dts/sun9i-a80.dtsi
> +++ b/arch/arm/boot/dts/sun9i-a80.dtsi
> @@ -277,9 +277,12 @@
> compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
> reg = <0x06000580 0x4>;
> clocks = <&ahb0>;
> - clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>,
> - <14>, <15>, <16>, <18>, <20>, <21>,
> - <22>, <23>;
> + clock-indices = <0>, <1>, <3>,
> + <5>, <8>, <12>,
> + <13>, <14>,
> + <15>, <16>, <18>,
> + <20>, <21>, <22>,
> + <23>;
> clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
> "ahb0_ss", "ahb0_sd", "ahb0_nand1",
> "ahb0_nand0", "ahb0_sdram",
> @@ -293,7 +296,10 @@
> compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
> reg = <0x06000584 0x4>;
> clocks = <&ahb1>;
> - clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>;
> + clock-indices = <0>, <1>,
> + <17>, <21>,
> + <22>, <23>,
> + <24>;
> clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
> "ahb1_gmac", "ahb1_msgbox",
> "ahb1_spinlock", "ahb1_hstimer",
> @@ -305,8 +311,9 @@
> compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
> reg = <0x06000588 0x4>;
> clocks = <&ahb2>;
> - clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>,
> - <11>;
> + clock-indices = <0>, <1>,
> + <2>, <4>, <5>,
> + <7>, <8>, <11>;
> clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
> "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
> "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
> @@ -317,8 +324,10 @@
> compatible = "allwinner,sun9i-a80-apb0-gates-clk";
> reg = <0x06000590 0x4>;
> clocks = <&apb0>;
> - clock-indices = <1>, <5>, <11>, <12>, <13>, <15>,
> - <17>, <18>, <19>;
> + clock-indices = <1>, <5>,
> + <11>, <12>, <13>,
> + <15>, <17>, <18>,
> + <19>;
> clock-output-names = "apb0_spdif", "apb0_pio",
> "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
> "apb0_lradc", "apb0_gpadc", "apb0_twd",
> @@ -330,8 +339,11 @@
> compatible = "allwinner,sun9i-a80-apb1-gates-clk";
> reg = <0x06000594 0x4>;
> clocks = <&apb1>;
> - clock-indices = <0>, <1>, <2>, <3>, <4>,
> - <16>, <17>, <18>, <19>, <20>, <21>;
> + clock-indices = <0>, <1>,
> + <2>, <3>, <4>,
> + <16>, <17>,
> + <18>, <19>,
> + <20>, <21>;
> clock-output-names = "apb1_i2c0", "apb1_i2c1",
> "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
> "apb1_uart0", "apb1_uart1",
> --
> 2.4.6
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 6/7] ARM: sun9i: Add clock indices
@ 2015-07-30 7:44 ` Chen-Yu Tsai
0 siblings, 0 replies; 28+ messages in thread
From: Chen-Yu Tsai @ 2015-07-30 7:44 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 27, 2015 at 5:14 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> The A80 gates have a non continuous set of clock IDs that are valid. Add
> the clock-indices property to the DT to express this.
The commit message does not match the patch, which is just a reformatting of
existing clock-indices properties.
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> arch/arm/boot/dts/sun9i-a80.dtsi | 32 ++++++++++++++++++++++----------
> 1 file changed, 22 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
> index a43ad779ee2f..5908e3dcf965 100644
> --- a/arch/arm/boot/dts/sun9i-a80.dtsi
> +++ b/arch/arm/boot/dts/sun9i-a80.dtsi
> @@ -277,9 +277,12 @@
> compatible = "allwinner,sun9i-a80-ahb0-gates-clk";
> reg = <0x06000580 0x4>;
> clocks = <&ahb0>;
> - clock-indices = <0>, <1>, <3>, <5>, <8>, <12>, <13>,
> - <14>, <15>, <16>, <18>, <20>, <21>,
> - <22>, <23>;
> + clock-indices = <0>, <1>, <3>,
> + <5>, <8>, <12>,
> + <13>, <14>,
> + <15>, <16>, <18>,
> + <20>, <21>, <22>,
> + <23>;
> clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu",
> "ahb0_ss", "ahb0_sd", "ahb0_nand1",
> "ahb0_nand0", "ahb0_sdram",
> @@ -293,7 +296,10 @@
> compatible = "allwinner,sun9i-a80-ahb1-gates-clk";
> reg = <0x06000584 0x4>;
> clocks = <&ahb1>;
> - clock-indices = <0>, <1>, <17>, <21>, <22>, <23>, <24>;
> + clock-indices = <0>, <1>,
> + <17>, <21>,
> + <22>, <23>,
> + <24>;
> clock-output-names = "ahb1_usbotg", "ahb1_usbhci",
> "ahb1_gmac", "ahb1_msgbox",
> "ahb1_spinlock", "ahb1_hstimer",
> @@ -305,8 +311,9 @@
> compatible = "allwinner,sun9i-a80-ahb2-gates-clk";
> reg = <0x06000588 0x4>;
> clocks = <&ahb2>;
> - clock-indices = <0>, <1>, <2>, <4>, <5>, <7>, <8>,
> - <11>;
> + clock-indices = <0>, <1>,
> + <2>, <4>, <5>,
> + <7>, <8>, <11>;
> clock-output-names = "ahb2_lcd0", "ahb2_lcd1",
> "ahb2_edp", "ahb2_csi", "ahb2_hdmi",
> "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi";
> @@ -317,8 +324,10 @@
> compatible = "allwinner,sun9i-a80-apb0-gates-clk";
> reg = <0x06000590 0x4>;
> clocks = <&apb0>;
> - clock-indices = <1>, <5>, <11>, <12>, <13>, <15>,
> - <17>, <18>, <19>;
> + clock-indices = <1>, <5>,
> + <11>, <12>, <13>,
> + <15>, <17>, <18>,
> + <19>;
> clock-output-names = "apb0_spdif", "apb0_pio",
> "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
> "apb0_lradc", "apb0_gpadc", "apb0_twd",
> @@ -330,8 +339,11 @@
> compatible = "allwinner,sun9i-a80-apb1-gates-clk";
> reg = <0x06000594 0x4>;
> clocks = <&apb1>;
> - clock-indices = <0>, <1>, <2>, <3>, <4>,
> - <16>, <17>, <18>, <19>, <20>, <21>;
> + clock-indices = <0>, <1>,
> + <2>, <3>, <4>,
> + <16>, <17>,
> + <18>, <19>,
> + <20>, <21>;
> clock-output-names = "apb1_i2c0", "apb1_i2c1",
> "apb1_i2c2", "apb1_i2c3", "apb1_i2c4",
> "apb1_uart0", "apb1_uart1",
> --
> 2.4.6
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 7/7] clk: sunxi: Add a simple gates driver
2015-07-27 20:26 ` Stephen Boyd
@ 2015-07-30 7:55 ` Chen-Yu Tsai
-1 siblings, 0 replies; 28+ messages in thread
From: Chen-Yu Tsai @ 2015-07-30 7:55 UTC (permalink / raw)
To: Stephen Boyd
Cc: Maxime Ripard, Chen-Yu Tsai, Mike Turquette, linux-arm-kernel, linux-clk
On Tue, Jul 28, 2015 at 4:26 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> On 07/26, Maxime Ripard wrote:
>> diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
>> new file mode 100644
>> index 000000000000..1a3963a8a686
>> --- /dev/null
>> +++ b/drivers/clk/sunxi/clk-simple-gates.c
>> @@ -0,0 +1,159 @@
>> +/*
>> + * Copyright 2015 Maxime Ripard
>> + *
>> + * Maxime Ripard <maxime.ripard@free-electrons.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
I'm guessing the following were copied from clk-sunxi.c.
>> +#include <linux/clk-provider.h>
>> +#include <linux/clkdev.h>
>
> Is this used?
clk_register_clkdev() is not used in this file, so not needed.
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/reset-controller.h>
>
> Is this used?
A remnant of the USB clocks, which has been moved to clk-usb.c.
Not needed here nor in clk-sunxi.c.
>> +#include <linux/spinlock.h>
>> +#include <linux/log2.h>
>
> Is this used?
This is only used for clock factor calculation. Not applicable in
clk-simple-gates.c, so no.
>> +
>> +static DEFINE_SPINLOCK(gates_lock);
>> +
> [...]
>> +
>> +static const int sun4i_a10_ahb_critical_clocks[] __initdata = {
>
> Shouldn't it be __initconst ?
Not sure why our critical clocks lists are __initdata...
>> + 14, /* ahb_sdram */
>> +};
>> +
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
> --
> To unsubscribe from this list: send the line "unsubscribe linux-clk" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 7/7] clk: sunxi: Add a simple gates driver
@ 2015-07-30 7:55 ` Chen-Yu Tsai
0 siblings, 0 replies; 28+ messages in thread
From: Chen-Yu Tsai @ 2015-07-30 7:55 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jul 28, 2015 at 4:26 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> On 07/26, Maxime Ripard wrote:
>> diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
>> new file mode 100644
>> index 000000000000..1a3963a8a686
>> --- /dev/null
>> +++ b/drivers/clk/sunxi/clk-simple-gates.c
>> @@ -0,0 +1,159 @@
>> +/*
>> + * Copyright 2015 Maxime Ripard
>> + *
>> + * Maxime Ripard <maxime.ripard@free-electrons.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
I'm guessing the following were copied from clk-sunxi.c.
>> +#include <linux/clk-provider.h>
>> +#include <linux/clkdev.h>
>
> Is this used?
clk_register_clkdev() is not used in this file, so not needed.
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/reset-controller.h>
>
> Is this used?
A remnant of the USB clocks, which has been moved to clk-usb.c.
Not needed here nor in clk-sunxi.c.
>> +#include <linux/spinlock.h>
>> +#include <linux/log2.h>
>
> Is this used?
This is only used for clock factor calculation. Not applicable in
clk-simple-gates.c, so no.
>> +
>> +static DEFINE_SPINLOCK(gates_lock);
>> +
> [...]
>> +
>> +static const int sun4i_a10_ahb_critical_clocks[] __initdata = {
>
> Shouldn't it be __initconst ?
Not sure why our critical clocks lists are __initdata...
>> + 14, /* ahb_sdram */
>> +};
>> +
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
> --
> To unsubscribe from this list: send the line "unsubscribe linux-clk" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 6/7] ARM: sun9i: Add clock indices
2015-07-30 7:44 ` Chen-Yu Tsai
@ 2015-07-30 10:12 ` Maxime Ripard
-1 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-30 10:12 UTC (permalink / raw)
To: Chen-Yu Tsai; +Cc: Mike Turquette, Stephen Boyd, linux-clk, linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 621 bytes --]
On Thu, Jul 30, 2015 at 03:44:59PM +0800, Chen-Yu Tsai wrote:
> On Mon, Jul 27, 2015 at 5:14 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The A80 gates have a non continuous set of clock IDs that are valid. Add
> > the clock-indices property to the DT to express this.
>
> The commit message does not match the patch, which is just a reformatting of
> existing clock-indices properties.
Indeed... That's what happens when you automate too much things.. :)
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
[-- Attachment #2: Digital signature --]
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 6/7] ARM: sun9i: Add clock indices
@ 2015-07-30 10:12 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-30 10:12 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jul 30, 2015 at 03:44:59PM +0800, Chen-Yu Tsai wrote:
> On Mon, Jul 27, 2015 at 5:14 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > The A80 gates have a non continuous set of clock IDs that are valid. Add
> > the clock-indices property to the DT to express this.
>
> The commit message does not match the patch, which is just a reformatting of
> existing clock-indices properties.
Indeed... That's what happens when you automate too much things.. :)
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 7/7] clk: sunxi: Add a simple gates driver
2015-07-30 7:55 ` Chen-Yu Tsai
@ 2015-07-30 10:17 ` Maxime Ripard
-1 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-30 10:17 UTC (permalink / raw)
To: Chen-Yu Tsai; +Cc: Stephen Boyd, Mike Turquette, linux-clk, linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 2375 bytes --]
On Thu, Jul 30, 2015 at 03:55:17PM +0800, Chen-Yu Tsai wrote:
> On Tue, Jul 28, 2015 at 4:26 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> > On 07/26, Maxime Ripard wrote:
> >> diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
> >> new file mode 100644
> >> index 000000000000..1a3963a8a686
> >> --- /dev/null
> >> +++ b/drivers/clk/sunxi/clk-simple-gates.c
> >> @@ -0,0 +1,159 @@
> >> +/*
> >> + * Copyright 2015 Maxime Ripard
> >> + *
> >> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License as published by
> >> + * the Free Software Foundation; either version 2 of the License, or
> >> + * (at your option) any later version.
> >> + *
> >> + * This program is distributed in the hope that it will be useful,
> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> >> + * GNU General Public License for more details.
> >> + */
> >> +
>
> I'm guessing the following were copied from clk-sunxi.c.
>
> >> +#include <linux/clk-provider.h>
> >> +#include <linux/clkdev.h>
> >
> > Is this used?
>
> clk_register_clkdev() is not used in this file, so not needed.
>
> >> +#include <linux/of.h>
> >> +#include <linux/of_address.h>
> >> +#include <linux/reset-controller.h>
> >
> > Is this used?
>
> A remnant of the USB clocks, which has been moved to clk-usb.c.
>
> Not needed here nor in clk-sunxi.c.
>
> >> +#include <linux/spinlock.h>
> >> +#include <linux/log2.h>
> >
> > Is this used?
>
> This is only used for clock factor calculation. Not applicable in
> clk-simple-gates.c, so no.
You're right, we don't need any of these...
> >> +static DEFINE_SPINLOCK(gates_lock);
> >> +
> > [...]
> >> +
> >> +static const int sun4i_a10_ahb_critical_clocks[] __initdata = {
> >
> > Shouldn't it be __initconst ?
>
> Not sure why our critical clocks lists are __initdata...
Why shouldn't it be?
CLK_OF_DECLARE callbacks only run at of_clk_init time, which is way
before the init memory is discarded.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 7/7] clk: sunxi: Add a simple gates driver
@ 2015-07-30 10:17 ` Maxime Ripard
0 siblings, 0 replies; 28+ messages in thread
From: Maxime Ripard @ 2015-07-30 10:17 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jul 30, 2015 at 03:55:17PM +0800, Chen-Yu Tsai wrote:
> On Tue, Jul 28, 2015 at 4:26 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
> > On 07/26, Maxime Ripard wrote:
> >> diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
> >> new file mode 100644
> >> index 000000000000..1a3963a8a686
> >> --- /dev/null
> >> +++ b/drivers/clk/sunxi/clk-simple-gates.c
> >> @@ -0,0 +1,159 @@
> >> +/*
> >> + * Copyright 2015 Maxime Ripard
> >> + *
> >> + * Maxime Ripard <maxime.ripard@free-electrons.com>
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License as published by
> >> + * the Free Software Foundation; either version 2 of the License, or
> >> + * (at your option) any later version.
> >> + *
> >> + * This program is distributed in the hope that it will be useful,
> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> >> + * GNU General Public License for more details.
> >> + */
> >> +
>
> I'm guessing the following were copied from clk-sunxi.c.
>
> >> +#include <linux/clk-provider.h>
> >> +#include <linux/clkdev.h>
> >
> > Is this used?
>
> clk_register_clkdev() is not used in this file, so not needed.
>
> >> +#include <linux/of.h>
> >> +#include <linux/of_address.h>
> >> +#include <linux/reset-controller.h>
> >
> > Is this used?
>
> A remnant of the USB clocks, which has been moved to clk-usb.c.
>
> Not needed here nor in clk-sunxi.c.
>
> >> +#include <linux/spinlock.h>
> >> +#include <linux/log2.h>
> >
> > Is this used?
>
> This is only used for clock factor calculation. Not applicable in
> clk-simple-gates.c, so no.
You're right, we don't need any of these...
> >> +static DEFINE_SPINLOCK(gates_lock);
> >> +
> > [...]
> >> +
> >> +static const int sun4i_a10_ahb_critical_clocks[] __initdata = {
> >
> > Shouldn't it be __initconst ?
>
> Not sure why our critical clocks lists are __initdata...
Why shouldn't it be?
CLK_OF_DECLARE callbacks only run at of_clk_init time, which is way
before the init memory is discarded.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 7/7] clk: sunxi: Add a simple gates driver
2015-07-30 10:17 ` Maxime Ripard
@ 2015-07-30 14:34 ` Chen-Yu Tsai
-1 siblings, 0 replies; 28+ messages in thread
From: Chen-Yu Tsai @ 2015-07-30 14:34 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, Stephen Boyd, Mike Turquette, linux-arm-kernel, linux-clk
On Thu, Jul 30, 2015 at 6:17 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Thu, Jul 30, 2015 at 03:55:17PM +0800, Chen-Yu Tsai wrote:
>> On Tue, Jul 28, 2015 at 4:26 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
>> > On 07/26, Maxime Ripard wrote:
>> >> diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
>> >> new file mode 100644
>> >> index 000000000000..1a3963a8a686
>> >> --- /dev/null
>> >> +++ b/drivers/clk/sunxi/clk-simple-gates.c
>> >> @@ -0,0 +1,159 @@
>> >> +/*
>> >> + * Copyright 2015 Maxime Ripard
>> >> + *
>> >> + * Maxime Ripard <maxime.ripard@free-electrons.com>
>> >> + *
>> >> + * This program is free software; you can redistribute it and/or modify
>> >> + * it under the terms of the GNU General Public License as published by
>> >> + * the Free Software Foundation; either version 2 of the License, or
>> >> + * (at your option) any later version.
>> >> + *
>> >> + * This program is distributed in the hope that it will be useful,
>> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> >> + * GNU General Public License for more details.
>> >> + */
>> >> +
>>
>> I'm guessing the following were copied from clk-sunxi.c.
>>
>> >> +#include <linux/clk-provider.h>
>> >> +#include <linux/clkdev.h>
>> >
>> > Is this used?
>>
>> clk_register_clkdev() is not used in this file, so not needed.
>>
>> >> +#include <linux/of.h>
>> >> +#include <linux/of_address.h>
>> >> +#include <linux/reset-controller.h>
>> >
>> > Is this used?
>>
>> A remnant of the USB clocks, which has been moved to clk-usb.c.
>>
>> Not needed here nor in clk-sunxi.c.
>>
>> >> +#include <linux/spinlock.h>
>> >> +#include <linux/log2.h>
>> >
>> > Is this used?
>>
>> This is only used for clock factor calculation. Not applicable in
>> clk-simple-gates.c, so no.
>
> You're right, we don't need any of these...
>
>> >> +static DEFINE_SPINLOCK(gates_lock);
>> >> +
>> > [...]
>> >> +
>> >> +static const int sun4i_a10_ahb_critical_clocks[] __initdata = {
>> >
>> > Shouldn't it be __initconst ?
>>
>> Not sure why our critical clocks lists are __initdata...
>
> Why shouldn't it be?
>
> CLK_OF_DECLARE callbacks only run at of_clk_init time, which is way
> before the init memory is discarded.
Sorry, I meant why __initdata and not __initconst.
ChenYu
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 7/7] clk: sunxi: Add a simple gates driver
@ 2015-07-30 14:34 ` Chen-Yu Tsai
0 siblings, 0 replies; 28+ messages in thread
From: Chen-Yu Tsai @ 2015-07-30 14:34 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jul 30, 2015 at 6:17 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Thu, Jul 30, 2015 at 03:55:17PM +0800, Chen-Yu Tsai wrote:
>> On Tue, Jul 28, 2015 at 4:26 AM, Stephen Boyd <sboyd@codeaurora.org> wrote:
>> > On 07/26, Maxime Ripard wrote:
>> >> diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
>> >> new file mode 100644
>> >> index 000000000000..1a3963a8a686
>> >> --- /dev/null
>> >> +++ b/drivers/clk/sunxi/clk-simple-gates.c
>> >> @@ -0,0 +1,159 @@
>> >> +/*
>> >> + * Copyright 2015 Maxime Ripard
>> >> + *
>> >> + * Maxime Ripard <maxime.ripard@free-electrons.com>
>> >> + *
>> >> + * This program is free software; you can redistribute it and/or modify
>> >> + * it under the terms of the GNU General Public License as published by
>> >> + * the Free Software Foundation; either version 2 of the License, or
>> >> + * (at your option) any later version.
>> >> + *
>> >> + * This program is distributed in the hope that it will be useful,
>> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> >> + * GNU General Public License for more details.
>> >> + */
>> >> +
>>
>> I'm guessing the following were copied from clk-sunxi.c.
>>
>> >> +#include <linux/clk-provider.h>
>> >> +#include <linux/clkdev.h>
>> >
>> > Is this used?
>>
>> clk_register_clkdev() is not used in this file, so not needed.
>>
>> >> +#include <linux/of.h>
>> >> +#include <linux/of_address.h>
>> >> +#include <linux/reset-controller.h>
>> >
>> > Is this used?
>>
>> A remnant of the USB clocks, which has been moved to clk-usb.c.
>>
>> Not needed here nor in clk-sunxi.c.
>>
>> >> +#include <linux/spinlock.h>
>> >> +#include <linux/log2.h>
>> >
>> > Is this used?
>>
>> This is only used for clock factor calculation. Not applicable in
>> clk-simple-gates.c, so no.
>
> You're right, we don't need any of these...
>
>> >> +static DEFINE_SPINLOCK(gates_lock);
>> >> +
>> > [...]
>> >> +
>> >> +static const int sun4i_a10_ahb_critical_clocks[] __initdata = {
>> >
>> > Shouldn't it be __initconst ?
>>
>> Not sure why our critical clocks lists are __initdata...
>
> Why shouldn't it be?
>
> CLK_OF_DECLARE callbacks only run at of_clk_init time, which is way
> before the init memory is discarded.
Sorry, I meant why __initdata and not __initconst.
ChenYu
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2015-07-30 14:34 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-07-26 21:14 [PATCH 0/7] ARM: sunxi: Switch to clock indices Maxime Ripard
2015-07-26 21:14 ` Maxime Ripard
2015-07-26 21:14 ` [PATCH 1/7] ARM: sun4i: Add " Maxime Ripard
2015-07-26 21:14 ` Maxime Ripard
2015-07-26 21:14 ` [PATCH 2/7] ARM: sun5i: " Maxime Ripard
2015-07-26 21:14 ` Maxime Ripard
2015-07-26 21:14 ` [PATCH 3/7] ARM: sun6i: " Maxime Ripard
2015-07-26 21:14 ` Maxime Ripard
2015-07-26 21:14 ` [PATCH 4/7] ARM: sun7i: " Maxime Ripard
2015-07-26 21:14 ` Maxime Ripard
2015-07-26 21:14 ` [PATCH 5/7] ARM: sun8i: " Maxime Ripard
2015-07-26 21:14 ` Maxime Ripard
2015-07-26 21:14 ` [PATCH 6/7] ARM: sun9i: " Maxime Ripard
2015-07-26 21:14 ` Maxime Ripard
2015-07-30 7:44 ` Chen-Yu Tsai
2015-07-30 7:44 ` Chen-Yu Tsai
2015-07-30 10:12 ` Maxime Ripard
2015-07-30 10:12 ` Maxime Ripard
2015-07-26 21:14 ` [PATCH 7/7] clk: sunxi: Add a simple gates driver Maxime Ripard
2015-07-26 21:14 ` Maxime Ripard
2015-07-27 20:26 ` Stephen Boyd
2015-07-27 20:26 ` Stephen Boyd
2015-07-30 7:55 ` Chen-Yu Tsai
2015-07-30 7:55 ` Chen-Yu Tsai
2015-07-30 10:17 ` Maxime Ripard
2015-07-30 10:17 ` Maxime Ripard
2015-07-30 14:34 ` Chen-Yu Tsai
2015-07-30 14:34 ` Chen-Yu Tsai
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