* [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init
@ 2015-07-27 20:49 Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 001/172] driver/ddr/altera: Add DDR driver for Altera's SDRAM controller Marek Vasut
` (173 more replies)
0 siblings, 174 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
This series fixes the SPL support on SoCFPGA and cleans up the DDR
init code such that it is becoming remotely mainlinable. After this
series, the SPL is capable of booting from both SD/MMC and QSPI NOR.
There is still work to be done, but I'd like to start picking it up
so it can land in 2015.10 . Reviews and comments are welcome.
Dinh Nguyen (3):
driver/ddr/altera: Add DDR driver for Altera's SDRAM controller
driver/ddr/altera: Add the sdram calibration portion
arm: socfpga: enable the Altera SDRAM controller driver
Marek Vasut (169):
arm: socfpga: Move sdram_config.h to board dir
ddr: altera: Move struct sdram_prot_rule prototype
ddr: altera: Fix typo in mp_threshold1 programming
ddr: altera: Fix debug message format in sequencer
arm: socfpga: reset: Add missing reset manager regs
arm: socfpga: reset: Start reworking the SoCFPGA reset manager
arm: socfpga: reset: Implement unified function to toggle reset
arm: socfpga: reset: Replace ad-hoc reset functions
arm: socfpga: reset: Repair bridge reset handling
arm: socfpga: reset: Add function to reset add peripherals
arm: socfpga: reset: Add SDMMC, QSPI and DMA defines
arm: socfpga: clock: Get rid of cm_config_t typedef
arm: socfpga: clock: Clean up pll_config.h
arm: socfpga: scan: Staticize scan_mgr_io_scan_chain_prg()
arm: socfpga: scan: Zap redundant params in
scan_mgr_io_scan_chain_prg()
arm: socfpga: scan: Zap iocsr_scan_chain*_table()
arm: socfpga: system: Rework sysmgr_enable_warmrstcfgio()
arm: socfpga: system: Clean up pinmux_config.c
arm: socfpga: spl: Toggle warm reset config I/O bit
arm: socfpga: spl: Configure SCU and NIC-301 early
arm: socfpga: spl: Add missing reset logic
arm: socfpga: spl: Merge spl_board_init() into board_init_f()
arm: socfpga: spl: Remove custom linker script
arm: socfpga: spl: Add support for booting from SD/MMC
arm: socfpga: spl: Add support for booting from QSPI
arm: socfpga: spl: Add support for selecting boot device from BSEL
arm: socfpga: misc: Fix warm reset
arm: socfpga: misc: Add support for printing boot mode
arm: socfpga: misc: Export bootmode into environment variable
arm: socfpga: misc: Probe ethernet GMAC from OF
arm: socfpga: misc: Reset ethernet from OF
arm: socfpga: config: Move SPL GD and malloc to RAM
arm: socfpga: config: Zap incorrect config options
arm: socfpga: config: Exclude CONFIG_SPI_FLASH_MTD from SPL build
arm: socfpga: config: Enable CONFIG_SPI_FLASH_BAR
arm: socfpga: config: Fix LOADADDR
arm: socfpga: config: Make CONFIG_SPI_FLASH_MTD useful
Makefile: Add target for building bootable SPL image for SoCFPGA
ddr: altera: Minor indent fix in set_rank_and_odt_mask()
ddr: altera: Clean up ugly casts in sdram_calibration_full()
ddr: altera: Zap invocation of sdr_get_addr((u32 *)BASE_RW_MGR)"
ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_reg_file->.*)
ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_scc_mgr->.*)
ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_rw_load.*->.*)
ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_mgr_.*->.*)
ddr: altera: Pluck out remaining sdr_get_addr() calls
ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESS
ddr: altera: Stop using SDR_CTRLGRP_ADDRESS directly
ddr: altera: Massage addr into I/O accessors
ddr: altera: Clean up hc_initialize_rom_data()
ddr: altera: Clean up initialize_reg_file()
ddr: altera: Clean up initialize_hps_phy()
ddr: altera: Clean up reg_file_set*()
ddr: altera: Clean up scc manager function args
ddr: altera: Reorder scc manager functions
ddr: altera: Implement universal scc manager config function
ddr: altera: Clean up scc_mgr_initialize()
ddr: altera: Shuffle around scc_mgr_set_*all_ranks()
ddr: altera: Implement universal scc_mgr_set_all_ranks()
ddr: altera: Clean up scc_mgr_load_dqs_for_write_group()
ddr: altera: Clean up scc_set_bypass_mode()
ddr: altera: Clean up scc_mgr_set_oct_out1_delay()
ddr: altera: Clean up scc_mgr_apply_group_dq_out1_delay()
ddr: altera: Clean up scc_mgr_*_delay() args
ddr: altera: Clean up scc_mgr_set_hhp_extras()
ddr: altera: Extract scc_mgr_set_hhp_extras()
ddr: altera: Clean up scc_mgr_zero_all()
ddr: altera: Clean up scc_mgr_zero_group()
FIXME: ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add()
cleanup part 1
ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add() cleanup
part 2
ddr: altera: Clean up
scc_mgr_apply_group_all_out_delay_add_all_ranks()
ddr: altera: Factor out instruction loading from
rw_mgr_mem_initialize()
ddr: altera: Factor out common code
ddr: altera: Minor clean up of set_jump_as_return()
ddr: altera: Fix ad-hoc iterative division implementation
ddr: altera: Rework initialize_tracking()
ddr: altera: Init my_param and my_gbl
ddr: altera: Rename initialize() to phy_mgr_initialize()
ddr: altera: Clean up run_mem_calibrate()
ddr: altera: Clean up phy_mgr_initialize()
ddr: altera: Clean up mem_config()
ddr: altera: Clean up mem_precharge_and_activate()
ddr: altera: Clean up set_rank_and_odt_mask() part 1
ddr: altera: Clean up set_rank_and_odt_mask() part 2
ddr: altera: Clean up set_rank_and_odt_mask() part 3
ddr: altera: Minor clean up of mem_skip_calibrate()
ddr: altera: Trivial mem_calibrate() indent cleanup
ddr: altera: Internal mem_calibrate() cleanup part 1
ddr: altera: Internal mem_calibrate() cleanup part 2
ddr: altera: Internal mem_calibrate() cleanup part 3
ddr: altera: Internal mem_calibrate() cleanup part 4
ddr: altera: Internal mem_calibrate() cleanup part 5
ddr: altera: Internal mem_calibrate() cleanup part 6
ddr: altera: Minor clean up of rw_mgr_mem_initialize()
ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 1
ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 2
ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 3
ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 4
ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 5
ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 6
ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 7
ddr: altera: Extract guaranteed write from
rw_mgr_mem_calibrate_vfifo()
ddr: altera: Extract DQS enable calibration from
rw_mgr_mem_calibrate_vfifo()
ddr: altera: Extract Centering DQ/DQS from
rw_mgr_mem_calibrate_vfifo()
ddr: altera: Minor rw_mgr_mem_calibrate_read_load_patterns() cleanup
ddr: altera: Zap rw_mgr_mem_calibrate_read_test_patterns_all_ranks()
ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_patterns()
ddr: altera: Clean up
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay()
part 1
ddr: altera: Clean up
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay()
part 2
ddr: altera: Clean up
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay()
part 3
ddr: altera: Clean up
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay()
part 4
ddr: altera: Clean up sdr_find_window_centre() part 1
ddr: altera: Clean up sdr_find_window_centre() part 2
ddr: altera: Clean up sdr_find_window_centre() part 3
ddr: altera: Clean up sdr_*_phase() part 1
ddr: altera: Clean up sdr_*_phase() part 2
ddr: altera: Clean up sdr_*_phase() part 3
ddr: altera: Clean up sdr_*_phase() part 4
ddr: altera: Clean up sdr_*_phase() part 5
ddr: altera: Clean up sdr_*_phase() part 6
ddr: altera: Clean up sdr_*_phase() part 7
ddr: altera: Clean up sdr_*_phase() part 8
ddr: altera: Clean up sdr_*_phase() part 9
ddr: altera: Clean up sdr_*_phase() part 10
ddr: altera: Clean up rw_mgr_*_vfifo() part 1
ddr: altera: Clean up rw_mgr_*_vfifo() part 2
ddr: altera: Clean up find_vfifo_read()
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
part 1
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
part 2
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
part 3
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
part 4
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
part 5
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
part 6
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
part 7
ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_all_ranks()
ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 1
ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 2
ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 3
ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 4
ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 5
ddr: altera: Clean up rw_mgr_mem_calibrate_writes()
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 1
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 2
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 3
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 4
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 5
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 6
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 7
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 8
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 9
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 10
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 11
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 2
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 4
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 5
ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 1
ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 2
ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 3
ddr: altera: Clean up rw_mgr_mem_calibrate_write_test_issue()
ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_end()
ddr: altera: Clean up rw_mgr_mem_calibrate_lfifo()
ddr: altera: Minor clean up of rw_mgr_mem_handoff()
ddr: altera: Clean up of delay_for_n_mem_clocks() part 1
ddr: altera: Clean up of delay_for_n_mem_clocks() part 2
ddr: altera: Clean up of delay_for_n_mem_clocks() part 3
ddr: altera: Clean up of delay_for_n_mem_clocks() part 4
ddr: altera: Clean up of delay_for_n_mem_clocks() part 5
Makefile | 13 +
arch/arm/mach-socfpga/clock_manager.c | 28 +-
arch/arm/mach-socfpga/include/mach/clock_manager.h | 12 +-
arch/arm/mach-socfpga/include/mach/reset_manager.h | 60 +-
arch/arm/mach-socfpga/include/mach/scan_manager.h | 23 +-
arch/arm/mach-socfpga/include/mach/sdram.h | 298 +-
.../arm/mach-socfpga/include/mach/system_manager.h | 7 +-
arch/arm/mach-socfpga/misc.c | 115 +-
arch/arm/mach-socfpga/reset_manager.c | 99 +-
arch/arm/mach-socfpga/scan_manager.c | 31 +-
arch/arm/mach-socfpga/spl.c | 220 +-
arch/arm/mach-socfpga/system_manager.c | 16 +-
arch/arm/mach-socfpga/u-boot-spl.lds | 45 -
board/altera/socfpga/Makefile | 4 +-
board/altera/socfpga/qts/Makefile | 7 -
board/altera/socfpga/qts/sdram_config.h | 100 +
board/altera/socfpga/wrap_iocsr_config.c | 41 +
board/altera/socfpga/wrap_pinmux_config.c | 35 +
board/altera/socfpga/wrap_pll_config.c | 144 +
configs/socfpga_arria5_defconfig | 9 +
configs/socfpga_cyclone5_defconfig | 10 +
configs/socfpga_socrates_defconfig | 11 +-
drivers/ddr/altera/Makefile | 11 +
drivers/ddr/altera/sdram.c | 817 +++++
drivers/ddr/altera/sequencer.c | 3806 ++++++++++++++++++++
drivers/ddr/altera/sequencer.h | 299 ++
drivers/ddr/altera/sequencer_auto.h | 128 +
drivers/ddr/altera/sequencer_auto_ac_init.h | 84 +
drivers/ddr/altera/sequencer_auto_inst_init.h | 268 ++
drivers/ddr/altera/sequencer_defines.h | 121 +
include/configs/socfpga_arria5.h | 7 +-
include/configs/socfpga_common.h | 63 +-
include/configs/socfpga_cyclone5.h | 7 +-
include/fdtdec.h | 1 +
lib/fdtdec.c | 1 +
scripts/Makefile.spl | 11 +
36 files changed, 6566 insertions(+), 386 deletions(-)
delete mode 100644 arch/arm/mach-socfpga/u-boot-spl.lds
delete mode 100644 board/altera/socfpga/qts/Makefile
create mode 100644 board/altera/socfpga/qts/sdram_config.h
create mode 100644 board/altera/socfpga/wrap_iocsr_config.c
create mode 100644 board/altera/socfpga/wrap_pinmux_config.c
create mode 100644 board/altera/socfpga/wrap_pll_config.c
create mode 100644 drivers/ddr/altera/Makefile
create mode 100644 drivers/ddr/altera/sdram.c
create mode 100644 drivers/ddr/altera/sequencer.c
create mode 100644 drivers/ddr/altera/sequencer.h
create mode 100644 drivers/ddr/altera/sequencer_auto.h
create mode 100644 drivers/ddr/altera/sequencer_auto_ac_init.h
create mode 100644 drivers/ddr/altera/sequencer_auto_inst_init.h
create mode 100644 drivers/ddr/altera/sequencer_defines.h
--
2.1.4
^ permalink raw reply [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 001/172] driver/ddr/altera: Add DDR driver for Altera's SDRAM controller
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 002/172] driver/ddr/altera: Add the sdram calibration portion Marek Vasut
` (172 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
From: Dinh Nguyen <dinguyen@opensource.altera.com>
This patch enables the SDRAM controller that is used on Altera's SoCFPGA
family. This patch configures the SDRAM controller based on a configuration
file that is generated from the Quartus tool, sdram_config.h.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
Makefile | 1 +
arch/arm/mach-socfpga/include/mach/sdram.h | 311 ++++++++-
arch/arm/mach-socfpga/include/mach/sdram_config.h | 100 +++
drivers/ddr/altera/sdram.c | 799 ++++++++++++++++++++++
scripts/Makefile.spl | 1 +
5 files changed, 1200 insertions(+), 12 deletions(-)
create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_config.h
create mode 100644 drivers/ddr/altera/sdram.c
diff --git a/Makefile b/Makefile
index 54ef2cd..041dea7 100644
--- a/Makefile
+++ b/Makefile
@@ -651,6 +651,7 @@ libs-y += drivers/power/ \
libs-y += drivers/spi/
libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/
libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/
+libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
libs-y += drivers/serial/
libs-y += drivers/usb/dwc3/
libs-y += drivers/usb/emul/
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index 4f6489d..b4c1a2f 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -1,19 +1,306 @@
/*
- * Copyright (C) 2015 Marek Vasut <marex@denx.de>
- *
- * FIXME: This file contains temporary stub functions and is here
- * only until these functions are properly merged into
- * mainline.
+ * Copyright Altera Corporation (C) 2014-2015
*
* SPDX-License-Identifier: GPL-2.0+
*/
+#ifndef _SDRAM_H_
+#define _SDRAM_H_
+
+#ifndef __ASSEMBLY__
+
+unsigned long sdram_calculate_size(void);
+unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg);
+int sdram_calibration_full(void);
+
+extern int sdram_calibration(void);
+
+#define SDR_CTRLGRP_ADDRESS 0x5000
+
+struct socfpga_sdr_ctrl {
+ u32 ctrl_cfg;
+ u32 dram_timing1;
+ u32 dram_timing2;
+ u32 dram_timing3;
+ u32 dram_timing4; /* 0x10 */
+ u32 lowpwr_timing;
+ u32 dram_odt;
+ u32 __padding0[4];
+ u32 dram_addrw; /* 0x2c */
+ u32 dram_if_width; /* 0x30 */
+ u32 dram_dev_width;
+ u32 dram_sts;
+ u32 dram_intr;
+ u32 sbe_count; /* 0x40 */
+ u32 dbe_count;
+ u32 err_addr;
+ u32 drop_count;
+ u32 drop_addr; /* 0x50 */
+ u32 lowpwr_eq;
+ u32 lowpwr_ack;
+ u32 static_cfg;
+ u32 ctrl_width; /* 0x60 */
+ u32 cport_width;
+ u32 cport_wmap;
+ u32 cport_rmap;
+ u32 rfifo_cmap; /* 0x70 */
+ u32 wfifo_cmap;
+ u32 cport_rdwr;
+ u32 port_cfg;
+ u32 fpgaport_rst; /* 0x80 */
+ u32 __padding1;
+ u32 fifo_cfg;
+ u32 protport_default;
+ u32 prot_rule_addr; /* 0x90 */
+ u32 prot_rule_id;
+ u32 prot_rule_data;
+ u32 prot_rule_rdwr;
+ u32 __padding2[3];
+ u32 mp_priority; /* 0xac */
+ u32 mp_weight0; /* 0xb0 */
+ u32 mp_weight1;
+ u32 mp_weight2;
+ u32 mp_weight3;
+ u32 mp_pacing0; /* 0xc0 */
+ u32 mp_pacing1;
+ u32 mp_pacing2;
+ u32 mp_pacing3;
+ u32 mp_threshold0; /* 0xd0 */
+ u32 mp_threshold1;
+ u32 mp_threshold2;
+ u32 __padding3[29];
+ u32 phy_ctrl0; /* 0x150 */
+ u32 phy_ctrl1;
+ u32 phy_ctrl2;
+};
+
+struct sdram_prot_rule {
+ uint64_t sdram_start; /* SDRAM start address */
+ uint64_t sdram_end; /* SDRAM end address */
+ uint32_t rule; /* SDRAM protection rule number: 0-19 */
+ int valid; /* Rule valid or not? 1 - valid, 0 not*/
+
+ uint32_t security;
+ uint32_t portmask;
+ uint32_t result;
+ uint32_t lo_prot_id;
+ uint32_t hi_prot_id;
+};
-#ifndef __ARCH_SDRAM_H__
-#define __ARCH_SDRAM_H__
+#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
+#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
+#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
+#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000
+#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16
+#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000
+#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15
+#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000
+#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11
+#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800
+#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10
+#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400
+#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8
+#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300
+#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3
+#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8
+#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0
+#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007
+/* Register template: sdr::ctrlgrp::dramtiming1 */
+#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24
+#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000
+#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18
+#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000
+#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14
+#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000
+#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9
+#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00
+#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4
+#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0
+#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f
+/* Register template: sdr::ctrlgrp::dramtiming2 */
+#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25
+#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000
+#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21
+#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000
+#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17
+#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000
+#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13
+#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000
+#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff
+/* Register template: sdr::ctrlgrp::dramtiming3 */
+#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19
+#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000
+#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15
+#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000
+#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9
+#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00
+#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4
+#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0
+#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f
+/* Register template: sdr::ctrlgrp::dramtiming4 */
+#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
+#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000
+#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10
+#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00
+#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0
+#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff
+/* Register template: sdr::ctrlgrp::lowpwrtiming */
+#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16
+#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000
+#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
+#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff
+/* Register template: sdr::ctrlgrp::dramaddrw */
+#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13
+#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000
+#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10
+#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00
+#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5
+#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0
+#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0
+#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f
+/* Register template: sdr::ctrlgrp::dramifwidth */
+#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0
+#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff
+/* Register template: sdr::ctrlgrp::dramdevwidth */
+#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0
+#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f
+/* Register template: sdr::ctrlgrp::dramintr */
+#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0
+#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001
+#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4
+#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030
+/* Register template: sdr::ctrlgrp::staticcfg */
+#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3
+#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008
+#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2
+#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004
+#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0
+#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003
+/* Register template: sdr::ctrlgrp::ctrlwidth */
+#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0
+#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003
+/* Register template: sdr::ctrlgrp::cportwidth */
+#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0
+#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff
+/* Register template: sdr::ctrlgrp::cportwmap */
+#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0
+#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff
+/* Register template: sdr::ctrlgrp::cportrmap */
+#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0
+#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff
+/* Register template: sdr::ctrlgrp::rfifocmap */
+#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0
+#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff
+/* Register template: sdr::ctrlgrp::wfifocmap */
+#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0
+#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff
+/* Register template: sdr::ctrlgrp::cportrdwr */
+#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0
+#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff
+/* Register template: sdr::ctrlgrp::portcfg */
+#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10
+#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00
+#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0
+#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff
+/* Register template: sdr::ctrlgrp::fifocfg */
+#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10
+#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400
+#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0
+#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff
+/* Register template: sdr::ctrlgrp::mppriority */
+#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0
+#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0
+#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */
+#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */
+#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff
+/* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */
+#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0
+#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff
+/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \
+0xffffffff
+/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \
+0xffffffff
+/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0
+#define \
+SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
+0x0000ffff
+/* Register template: sdr::ctrlgrp::remappriority */
+#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0
+#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff
+/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(x) \
+ (((x) << 12) & 0xfffff000)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(x) \
+ (((x) << 10) & 0x00000c00)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(x) \
+ (((x) << 6) & 0x000000c0)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(x) \
+ (((x) << 8) & 0x00000100)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(x) \
+ (((x) << 9) & 0x00000200)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(x) \
+ (((x) << 4) & 0x00000030)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(x) \
+ (((x) << 2) & 0x0000000c)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(x) \
+ (((x) << 0) & 0x00000003)
+/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x) \
+ (((x) << 12) & 0xfffff000)
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(x) \
+ (((x) << 0) & 0x00000fff)
+/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x) \
+ (((x) << 0) & 0x00000fff)
+/* Register template: sdr::ctrlgrp::dramodt */
+#define SDR_CTRLGRP_DRAMODT_READ_LSB 4
+#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0
+#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0
+#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f
+/* Field instance: sdr::ctrlgrp::dramsts */
+#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
+#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
-/* function declaration */
-inline unsigned long sdram_calculate_size(void) { return 0; }
-inline unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) { return 0; }
-inline int sdram_calibration_full(void) { return 0; }
+/* SDRAM width macro for configuration with ECC */
+#define SDRAM_WIDTH_32BIT_WITH_ECC 40
+#define SDRAM_WIDTH_16BIT_WITH_ECC 24
-#endif /* __ARCH_SDRAM_H__ */
+#endif
+#endif /* _SDRAM_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_config.h b/arch/arm/mach-socfpga/include/mach/sdram_config.h
new file mode 100644
index 0000000..f6d51ca
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/sdram_config.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright Altera Corporation (C) 2012-2015
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* This file is autogenerated from tools provided by Altera.*/
+#ifndef __SDRAM_CONFIG_H
+#define __SDRAM_CONFIG_H
+
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
+#ifdef CONFIG_SOCFPGA_ARRIA5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26
+#else
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#endif /* CONFIG_SOCFPGA_ARRIA5 */
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \
+0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \
+0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \
+0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
+
+#endif /*#ifndef__SDRAM_CONFIG_H*/
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c
new file mode 100644
index 0000000..5d8fed3
--- /dev/null
+++ b/drivers/ddr/altera/sdram.c
@@ -0,0 +1,799 @@
+/*
+ * Copyright Altera Corporation (C) 2014-2015
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <div64.h>
+#include <watchdog.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/sdram_config.h>
+#include <asm/arch/system_manager.h>
+#include <asm/io.h>
+
+/* define constant for 4G memory - used for SDRAM errata workaround */
+#define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+static struct socfpga_sdr_ctrl *sdr_ctrl =
+ (struct socfpga_sdr_ctrl *)(SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_ADDRESS);
+
+static int compute_errata_rows(unsigned long long memsize, int cs, int width,
+ int rows, int banks, int cols)
+{
+ unsigned long long newrows;
+ int inewrowslog2;
+ int bits;
+
+ debug("workaround rows - memsize %lld\n", memsize);
+ debug("workaround rows - cs %d\n", cs);
+ debug("workaround rows - width %d\n", width);
+ debug("workaround rows - rows %d\n", rows);
+ debug("workaround rows - banks %d\n", banks);
+ debug("workaround rows - cols %d\n", cols);
+
+ newrows = lldiv(memsize, (cs * (width / 8)));
+ debug("rows workaround - term1 %lld\n", newrows);
+
+ newrows = lldiv(newrows, ((1 << banks) * (1 << cols)));
+ debug("rows workaround - term2 %lld\n", newrows);
+
+ /* Compute the hamming weight - same as number of bits set.
+ * Need to see if result is ordinal power of 2 before
+ * attempting log2 of result.
+ */
+ bits = hweight32(newrows);
+
+ debug("rows workaround - bits %d\n", bits);
+
+ if (bits != 1) {
+ printf("SDRAM workaround failed, bits set %d\n", bits);
+ return rows;
+ }
+
+ if (newrows > UINT_MAX) {
+ printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
+ return rows;
+ }
+
+ inewrowslog2 = __ilog2((unsigned int)newrows);
+
+ debug("rows workaround - ilog2 %d, %d\n", inewrowslog2,
+ (int)newrows);
+
+ if (inewrowslog2 == -1) {
+ printf("SDRAM workaround failed, newrows %d\n", (int)newrows);
+ return rows;
+ }
+
+ return inewrowslog2;
+}
+
+/* SDRAM protection rules vary from 0-19, a total of 20 rules. */
+static void sdram_set_rule(struct sdram_prot_rule *prule)
+{
+ uint32_t lo_addr_bits;
+ uint32_t hi_addr_bits;
+ int ruleno = prule->rule;
+
+ /* Select the rule */
+ writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
+
+ /* Obtain the address bits */
+ lo_addr_bits = (uint32_t)(((prule->sdram_start) >> 20ULL) & 0xFFF);
+ hi_addr_bits = (uint32_t)((((prule->sdram_end-1) >> 20ULL)) & 0xFFF);
+
+ debug("sdram set rule start %x, %lld\n", lo_addr_bits,
+ prule->sdram_start);
+ debug("sdram set rule end %x, %lld\n", hi_addr_bits,
+ prule->sdram_end);
+
+ /* Set rule addresses */
+ writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
+
+ /* Set rule protection ids */
+ writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
+ &sdr_ctrl->prot_rule_id);
+
+ /* Set the rule data */
+ writel(prule->security | (prule->valid << 2) |
+ (prule->portmask << 3) | (prule->result << 13),
+ &sdr_ctrl->prot_rule_data);
+
+ /* write the rule */
+ writel(ruleno | (1L << 5), &sdr_ctrl->prot_rule_rdwr);
+
+ /* Set rule number to 0 by default */
+ writel(0, &sdr_ctrl->prot_rule_rdwr);
+}
+
+static void sdram_get_rule(struct sdram_prot_rule *prule)
+{
+ uint32_t addr;
+ uint32_t id;
+ uint32_t data;
+ int ruleno = prule->rule;
+
+ /* Read the rule */
+ writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
+ writel(ruleno | (1L << 6), &sdr_ctrl->prot_rule_rdwr);
+
+ /* Get the addresses */
+ addr = readl(&sdr_ctrl->prot_rule_addr);
+ prule->sdram_start = (addr & 0xFFF) << 20;
+ prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
+
+ /* Get the configured protection IDs */
+ id = readl(&sdr_ctrl->prot_rule_id);
+ prule->lo_prot_id = id & 0xFFF;
+ prule->hi_prot_id = (id >> 12) & 0xFFF;
+
+ /* Get protection data */
+ data = readl(&sdr_ctrl->prot_rule_data);
+
+ prule->security = data & 0x3;
+ prule->valid = (data >> 2) & 0x1;
+ prule->portmask = (data >> 3) & 0x3FF;
+ prule->result = (data >> 13) & 0x1;
+}
+
+static void sdram_set_protection_config(uint64_t sdram_start, uint64_t sdram_end)
+{
+ struct sdram_prot_rule rule;
+ int rules;
+
+ /* Start with accepting all SDRAM transaction */
+ writel(0x0, &sdr_ctrl->protport_default);
+
+ /* Clear all protection rules for warm boot case */
+ memset(&rule, 0, sizeof(struct sdram_prot_rule));
+
+ for (rules = 0; rules < 20; rules++) {
+ rule.rule = rules;
+ sdram_set_rule(&rule);
+ }
+
+ /* new rule: accept SDRAM */
+ rule.sdram_start = sdram_start;
+ rule.sdram_end = sdram_end;
+ rule.lo_prot_id = 0x0;
+ rule.hi_prot_id = 0xFFF;
+ rule.portmask = 0x3FF;
+ rule.security = 0x3;
+ rule.result = 0;
+ rule.valid = 1;
+ rule.rule = 0;
+
+ /* set new rule */
+ sdram_set_rule(&rule);
+
+ /* default rule: reject everything */
+ writel(0x3ff, &sdr_ctrl->protport_default);
+}
+
+static void sdram_dump_protection_config(void)
+{
+ struct sdram_prot_rule rule;
+ int rules;
+
+ debug("SDRAM Prot rule, default %x\n",
+ readl(&sdr_ctrl->protport_default));
+
+ for (rules = 0; rules < 20; rules++) {
+ sdram_get_rule(&rule);
+ debug("Rule %d, rules ...\n", rules);
+ debug(" sdram start %llx\n", rule.sdram_start);
+ debug(" sdram end %llx\n", rule.sdram_end);
+ debug(" low prot id %d, hi prot id %d\n",
+ rule.lo_prot_id,
+ rule.hi_prot_id);
+ debug(" portmask %x\n", rule.portmask);
+ debug(" security %d\n", rule.security);
+ debug(" result %d\n", rule.result);
+ debug(" valid %d\n", rule.valid);
+ }
+}
+
+/* Function to write to register and verify the write */
+static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value)
+{
+#ifndef SDRAM_MMR_SKIP_VERIFY
+ unsigned reg_value1;
+#endif
+ debug(" Write - Address ");
+ debug("0x%08x Data 0x%08x\n", (u32)addr, reg_value);
+ /* Write to register */
+ writel(reg_value, addr);
+#ifndef SDRAM_MMR_SKIP_VERIFY
+ debug(" Read and verify...");
+ /* Read back the wrote value */
+ reg_value1 = readl(addr);
+ /* Indicate failure if value not matched */
+ if (reg_value1 != reg_value) {
+ debug("FAIL - Address 0x%08x Expected 0x%08x Data 0x%08x\n",
+ (u32)addr, reg_value, reg_value1);
+ return 1;
+ }
+ debug("correct!\n");
+#endif /* SDRAM_MMR_SKIP_VERIFY */
+ return 0;
+}
+
+static void set_sdr_ctrlcfg(void)
+{
+ int addrorder;
+
+ debug("\nConfiguring CTRLCFG\n");
+ clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
+ SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB);
+ clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_MEMBL_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
+ SDR_CTRLGRP_CTRLCFG_MEMBL_LSB);
+
+
+ /* SDRAM Failure When Accessing Non-Existent Memory
+ * Set the addrorder field of the SDRAM control register
+ * based on the CSBITs setting.
+ */
+ switch (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) {
+ case 1:
+ addrorder = 0; /* chip, row, bank, column */
+ if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 0)
+ debug("INFO: Changing address order to 0 (chip, row, \
+ bank, column)\n");
+ break;
+ case 2:
+ addrorder = 2; /* row, chip, bank, column */
+ if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 2)
+ debug("INFO: Changing address order to 2 (row, chip, \
+ bank, column)\n");
+ break;
+ default:
+ addrorder = CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER;
+ break;
+ }
+
+ clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK,
+ addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ECCEN_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
+ SDR_CTRLGRP_CTRLCFG_ECCEN_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
+ SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
+ SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
+ SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
+ SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
+ SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB);
+}
+
+static void set_sdr_dram_timing1(void)
+{
+ debug("Configuring DRAMTIMING1\n");
+ clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
+ SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TAL_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
+ SDR_CTRLGRP_DRAMTIMING1_TAL_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TCL_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
+ SDR_CTRLGRP_DRAMTIMING1_TCL_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
+ SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
+ SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
+ SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB);
+}
+
+static void set_sdr_dram_timing2(void)
+{
+ debug("Configuring DRAMTIMING2\n");
+ clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
+ SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
+ SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TRP_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
+ SDR_CTRLGRP_DRAMTIMING2_TRP_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TWR_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
+ SDR_CTRLGRP_DRAMTIMING2_TWR_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
+ SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB);
+}
+
+static void set_sdr_dram_timing3(void)
+{
+ debug("Configuring DRAMTIMING3\n");
+ clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
+ SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
+ SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRC_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
+ SDR_CTRLGRP_DRAMTIMING3_TRC_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
+ SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
+ SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB);
+}
+
+static void set_sdr_dram_timing4(void)
+{
+ debug("Configuring DRAMTIMING4\n");
+ clrsetbits_le32(&sdr_ctrl->dram_timing4,
+ SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
+ SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->dram_timing4,
+ SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
+ SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB);
+}
+
+static void set_sdr_dram_lowpwr_timing(void)
+{
+ debug("Configuring LOWPWRTIMING\n");
+ clrsetbits_le32(&sdr_ctrl->lowpwr_timing,
+ SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
+ SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->lowpwr_timing,
+ SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
+ SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB);
+}
+
+static void set_sdr_addr_rw(void)
+{
+ int cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
+ int width = 8;
+ int rows = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
+ int banks = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS;
+ int cols = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS;
+ unsigned long long workaround_memsize = MEMSIZE_4G;
+
+ debug("Configuring DRAMADDRW\n");
+ clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
+ SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB);
+ /*
+ * SDRAM Failure When Accessing Non-Existent Memory
+ * Update Preloader to artificially increase the number of rows so
+ * that the memory thinks it has 4GB of RAM.
+ */
+ rows = compute_errata_rows(workaround_memsize, cs, width, rows, banks,
+ cols);
+
+ clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK,
+ rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
+ SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB);
+ /* SDRAM Failure When Accessing Non-Existent Memory
+ * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
+ * log2(number of chip select bits). Since there's only
+ * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
+ * which is the same as "chip selects" - 1.
+ */
+ clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK,
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
+ SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB);
+}
+
+static void set_sdr_static_cfg(void)
+{
+ debug("Configuring STATICCFG\n");
+ clrsetbits_le32(&sdr_ctrl->static_cfg, SDR_CTRLGRP_STATICCFG_MEMBL_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
+ SDR_CTRLGRP_STATICCFG_MEMBL_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->static_cfg,
+ SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
+ SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB);
+}
+
+static void set_sdr_fifo_cfg(void)
+{
+ debug("Configuring FIFOCFG\n");
+ clrsetbits_le32(&sdr_ctrl->fifo_cfg, SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
+ SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->fifo_cfg, SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
+ SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB);
+}
+
+static void set_sdr_mp_weight(void)
+{
+ debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
+ clrsetbits_le32(&sdr_ctrl->mp_weight0,
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->mp_weight1,
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->mp_weight1,
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->mp_weight2,
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->mp_weight3,
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB);
+}
+
+static void set_sdr_mp_pacing(void)
+{
+ debug("Configuring MPPACING_MPPACING_0\n");
+ clrsetbits_le32(&sdr_ctrl->mp_pacing0,
+ SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
+ SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->mp_pacing1,
+ SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
+ SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->mp_pacing1,
+ SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
+ SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->mp_pacing2,
+ SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
+ SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->mp_pacing3,
+ SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
+ SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB);
+}
+
+static void set_sdr_mp_threshold(void)
+{
+ debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
+ clrsetbits_le32(&sdr_ctrl->mp_threshold0,
+ SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
+ SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->mp_threshold1,
+ SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK,
+ SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK <<
+ SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->mp_threshold2,
+ SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
+ SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB);
+}
+
+
+/* Function to initialize SDRAM MMR */
+unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
+{
+ unsigned long reg_value;
+ unsigned long status = 0;
+
+#if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) && \
+defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) && \
+defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS) && \
+defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS) && \
+defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS)
+
+ writel(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS,
+ &sysmgr_regs->iswgrp_handoff[4]);
+#endif
+ set_sdr_ctrlcfg();
+ set_sdr_dram_timing1();
+ set_sdr_dram_timing2();
+ set_sdr_dram_timing3();
+ set_sdr_dram_timing4();
+ set_sdr_dram_lowpwr_timing();
+ set_sdr_addr_rw();
+
+ debug("Configuring DRAMIFWIDTH\n");
+ clrsetbits_le32(&sdr_ctrl->dram_if_width,
+ SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
+ SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB);
+
+ debug("Configuring DRAMDEVWIDTH\n");
+ clrsetbits_le32(&sdr_ctrl->dram_dev_width,
+ SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
+ SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB);
+
+ debug("Configuring LOWPWREQ\n");
+ clrsetbits_le32(&sdr_ctrl->lowpwr_eq,
+ SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
+ SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB);
+
+ debug("Configuring DRAMINTR\n");
+ clrsetbits_le32(&sdr_ctrl->dram_intr, SDR_CTRLGRP_DRAMINTR_INTREN_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
+ SDR_CTRLGRP_DRAMINTR_INTREN_LSB);
+
+ set_sdr_static_cfg();
+
+ debug("Configuring CTRLWIDTH\n");
+ clrsetbits_le32(&sdr_ctrl->ctrl_width,
+ SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
+ SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB);
+
+ debug("Configuring PORTCFG\n");
+ clrsetbits_le32(&sdr_ctrl->port_cfg, SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
+ SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB);
+
+ set_sdr_fifo_cfg();
+
+ debug("Configuring MPPRIORITY\n");
+ clrsetbits_le32(&sdr_ctrl->mp_priority,
+ SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
+ SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB);
+
+ set_sdr_mp_weight();
+ set_sdr_mp_pacing();
+ set_sdr_mp_threshold();
+
+ debug("Configuring PHYCTRL_PHYCTRL_0\n");
+ setbits_le32(&sdr_ctrl->phy_ctrl0,
+ CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0);
+
+ debug("Configuring CPORTWIDTH\n");
+ clrsetbits_le32(&sdr_ctrl->cport_width,
+ SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
+ SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB);
+ debug(" Write - Address ");
+ debug("0x%08x Data 0x%08x\n",
+ (unsigned)(&sdr_ctrl->cport_width),
+ (unsigned)reg_value);
+ reg_value = readl(&sdr_ctrl->cport_width);
+ debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
+
+ debug("Configuring CPORTWMAP\n");
+ clrsetbits_le32(&sdr_ctrl->cport_wmap,
+ SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
+ SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB);
+ debug(" Write - Address ");
+ debug("0x%08x Data 0x%08x\n",
+ (unsigned)(&sdr_ctrl->cport_wmap),
+ (unsigned)reg_value);
+ reg_value = readl(&sdr_ctrl->cport_wmap);
+ debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
+
+ debug("Configuring CPORTRMAP\n");
+ clrsetbits_le32(&sdr_ctrl->cport_rmap,
+ SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
+ SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB);
+ debug(" Write - Address ");
+ debug("0x%08x Data 0x%08x\n",
+ (unsigned)(&sdr_ctrl->cport_rmap),
+ (unsigned)reg_value);
+ reg_value = readl(&sdr_ctrl->cport_rmap);
+ debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
+
+ debug("Configuring RFIFOCMAP\n");
+ clrsetbits_le32(&sdr_ctrl->rfifo_cmap,
+ SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
+ SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB);
+ debug(" Write - Address ");
+ debug("0x%08x Data 0x%08x\n",
+ (unsigned)(&sdr_ctrl->rfifo_cmap),
+ (unsigned)reg_value);
+ reg_value = readl(&sdr_ctrl->rfifo_cmap);
+ debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
+
+ debug("Configuring WFIFOCMAP\n");
+ reg_value = readl(&sdr_ctrl->wfifo_cmap);
+ clrsetbits_le32(&sdr_ctrl->wfifo_cmap,
+ SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
+ SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB);
+ debug(" Write - Address ");
+ debug("0x%08x Data 0x%08x\n",
+ (unsigned)(&sdr_ctrl->wfifo_cmap),
+ (unsigned)reg_value);
+ reg_value = readl(&sdr_ctrl->wfifo_cmap);
+ debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
+
+ debug("Configuring CPORTRDWR\n");
+ clrsetbits_le32(&sdr_ctrl->cport_rdwr,
+ SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
+ SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB);
+ debug(" Write - Address ");
+ debug("0x%08x Data 0x%08x\n",
+ (unsigned)(&sdr_ctrl->cport_rdwr),
+ (unsigned)reg_value);
+ reg_value = readl(&sdr_ctrl->cport_rdwr);
+ debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
+
+ debug("Configuring DRAMODT\n");
+ clrsetbits_le32(&sdr_ctrl->dram_odt,
+ SDR_CTRLGRP_DRAMODT_READ_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
+ SDR_CTRLGRP_DRAMODT_READ_LSB);
+
+ clrsetbits_le32(&sdr_ctrl->dram_odt,
+ SDR_CTRLGRP_DRAMODT_WRITE_MASK,
+ CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
+ SDR_CTRLGRP_DRAMODT_WRITE_LSB);
+
+ /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
+ writel(CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
+ &sysmgr_regs->iswgrp_handoff[3]);
+
+ /* only enable if the FPGA is programmed */
+ if (fpgamgr_test_fpga_ready()) {
+ if (sdram_write_verify(&sdr_ctrl->fpgaport_rst,
+ CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST) == 1) {
+ status = 1;
+ return 1;
+ }
+ }
+
+ /* Restore the SDR PHY Register if valid */
+ if (sdr_phy_reg != 0xffffffff)
+ writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
+
+/***** Final step - apply configuration changes *****/
+ debug("Configuring STATICCFG_\n");
+ clrsetbits_le32(&sdr_ctrl->static_cfg, SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
+ 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
+ debug(" Write - Address ");
+ debug("0x%08x Data 0x%08x\n",
+ (unsigned)(&sdr_ctrl->static_cfg),
+ (unsigned)reg_value);
+ reg_value = readl(&sdr_ctrl->static_cfg);
+ debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
+
+ sdram_set_protection_config(0, sdram_calculate_size());
+
+ sdram_dump_protection_config();
+
+ return status;
+}
+
+/*
+ * To calculate SDRAM device size based on SDRAM controller parameters.
+ * Size is specified in bytes.
+ *
+ * NOTE:
+ * This function is compiled and linked into the preloader and
+ * Uboot (there may be others). So if this function changes, the Preloader
+ * and UBoot must be updated simultaneously.
+ */
+unsigned long sdram_calculate_size(void)
+{
+ unsigned long temp;
+ unsigned long row, bank, col, cs, width;
+
+ temp = readl(&sdr_ctrl->dram_addrw);
+ col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
+
+ /* SDRAM Failure When Accessing Non-Existent Memory
+ * Use ROWBITS from Quartus/QSys to calculate SDRAM size
+ * since the FB specifies we modify ROWBITs to work around SDRAM
+ * controller issue.
+ *
+ * If the stored handoff value for rows is 0, it probably means
+ * the preloader is older than UBoot. Use the
+ * #define from the SOCEDS Tools per Crucible review
+ * uboot-socfpga-204. Note that this is not a supported
+ * configuration and is not tested. The customer
+ * should be using preloader and uboot built from the
+ * same tag.
+ */
+ row = readl(&sysmgr_regs->iswgrp_handoff[4]);
+ if (row == 0)
+ row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
+ /* If the stored handoff value for rows is greater than
+ * the field width in the sdr.dramaddrw register then
+ * something is very wrong. Revert to using the the #define
+ * value handed off by the SOCEDS tool chain instead of
+ * using a broken value.
+ */
+ if (row > 31)
+ row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
+
+ bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
+
+ /* SDRAM Failure When Accessing Non-Existent Memory
+ * Use CSBITs from Quartus/QSys to calculate SDRAM size
+ * since the FB specifies we modify CSBITs to work around SDRAM
+ * controller issue.
+ */
+ cs = (temp & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB;
+ cs += 1;
+
+ cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
+
+ width = readl(&sdr_ctrl->dram_if_width);
+ /* ECC would not be calculated as its not addressible */
+ if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
+ width = 32;
+ if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
+ width = 16;
+
+ /* calculate the SDRAM size base on this info */
+ temp = 1 << (row + bank + col);
+ temp = temp * cs * (width / 8);
+
+ debug("sdram_calculate_memory returns %ld\n", temp);
+
+ return temp;
+}
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index b1047b5..4879d0a 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -62,6 +62,7 @@ libs-$(CONFIG_SPL_MMC_SUPPORT) += drivers/mmc/
libs-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += drivers/ddr/fsl/
libs-$(CONFIG_SYS_MVEBU_DDR_A38X) += drivers/ddr/marvell/a38x/
libs-$(CONFIG_SYS_MVEBU_DDR_AXP) += drivers/ddr/marvell/axp/
+libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/
libs-$(CONFIG_SPL_SERIAL_SUPPORT) += drivers/serial/
libs-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += drivers/mtd/spi/
libs-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 002/172] driver/ddr/altera: Add the sdram calibration portion
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 001/172] driver/ddr/altera: Add DDR driver for Altera's SDRAM controller Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 003/172] arm: socfpga: enable the Altera SDRAM controller driver Marek Vasut
` (171 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
From: Dinh Nguyen <dinguyen@opensource.altera.com>
This patch adds the DDR calibration portion of the Altera SDRAM driver.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
drivers/ddr/altera/Makefile | 11 +
drivers/ddr/altera/sequencer.c | 4051 +++++++++++++++++++++++++
drivers/ddr/altera/sequencer.h | 322 ++
drivers/ddr/altera/sequencer_auto.h | 128 +
drivers/ddr/altera/sequencer_auto_ac_init.h | 84 +
drivers/ddr/altera/sequencer_auto_inst_init.h | 268 ++
drivers/ddr/altera/sequencer_defines.h | 121 +
7 files changed, 4985 insertions(+)
create mode 100644 drivers/ddr/altera/Makefile
create mode 100644 drivers/ddr/altera/sequencer.c
create mode 100644 drivers/ddr/altera/sequencer.h
create mode 100644 drivers/ddr/altera/sequencer_auto.h
create mode 100644 drivers/ddr/altera/sequencer_auto_ac_init.h
create mode 100644 drivers/ddr/altera/sequencer_auto_inst_init.h
create mode 100644 drivers/ddr/altera/sequencer_defines.h
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
new file mode 100644
index 0000000..1ca7058
--- /dev/null
+++ b/drivers/ddr/altera/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
+# Copyright (C) 2014 Altera Corporation <www.altera.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_ALTERA_SDRAM) += sdram.o sequencer.o
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
new file mode 100644
index 0000000..6340859
--- /dev/null
+++ b/drivers/ddr/altera/sequencer.c
@@ -0,0 +1,4051 @@
+/*
+ * Copyright Altera Corporation (C) 2012-2015
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sdram.h>
+#include "sequencer.h"
+#include "sequencer_auto.h"
+#include "sequencer_auto_ac_init.h"
+#include "sequencer_auto_inst_init.h"
+#include "sequencer_defines.h"
+
+static void scc_mgr_load_dqs_for_write_group(uint32_t write_group);
+
+static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
+ (struct socfpga_sdr_rw_load_manager *)(BASE_RW_MGR + 0x800);
+
+static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
+ (struct socfpga_sdr_rw_load_jump_manager *)(BASE_RW_MGR + 0xC00);
+
+static struct socfpga_sdr_reg_file *sdr_reg_file =
+ (struct socfpga_sdr_reg_file *)(BASE_REG_FILE);
+
+static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
+ (struct socfpga_sdr_scc_mgr *)(BASE_SCC_MGR + 0x0E00);
+
+static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
+ (struct socfpga_phy_mgr_cmd *)(BASE_PHY_MGR);
+
+static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
+ (struct socfpga_phy_mgr_cfg *)(BASE_PHY_MGR + 0x4000);
+
+static struct socfpga_data_mgr *data_mgr =
+ (struct socfpga_data_mgr *)(BASE_DATA_MGR);
+
+#define DELTA_D 1
+#define MGR_SELECT_MASK 0xf8000
+
+/*
+ * In order to reduce ROM size, most of the selectable calibration steps are
+ * decided at compile time based on the user's calibration mode selection,
+ * as captured by the STATIC_CALIB_STEPS selection below.
+ *
+ * However, to support simulation-time selection of fast simulation mode, where
+ * we skip everything except the bare minimum, we need a few of the steps to
+ * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
+ * check, which is based on the rtl-supplied value, or we dynamically compute
+ * the value to use based on the dynamically-chosen calibration mode
+ */
+
+#define DLEVEL 0
+#define STATIC_IN_RTL_SIM 0
+#define STATIC_SKIP_DELAY_LOOPS 0
+
+#define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
+ STATIC_SKIP_DELAY_LOOPS)
+
+/* calibration steps requested by the rtl */
+uint16_t dyn_calib_steps;
+
+/*
+ * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
+ * instead of static, we use boolean logic to select between
+ * non-skip and skip values
+ *
+ * The mask is set to include all bits when not-skipping, but is
+ * zero when skipping
+ */
+
+uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
+
+#define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
+ ((non_skip_value) & skip_delay_mask)
+
+struct gbl_type *gbl;
+struct param_type *param;
+uint32_t curr_shadow_reg;
+
+static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
+ uint32_t write_group, uint32_t use_dm,
+ uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
+
+static u32 sdr_get_addr(u32 *base)
+{
+ u32 addr = (u32)base & MGR_SELECT_MASK;
+
+ switch (addr) {
+ case BASE_PHY_MGR:
+ addr = (((u32)base >> 8) & (1 << 6)) | ((u32)base & 0x3f) |
+ SDR_PHYGRP_PHYMGRGRP_ADDRESS;
+ break;
+ case BASE_RW_MGR:
+ addr = ((u32)base & 0x1fff) | SDR_PHYGRP_RWMGRGRP_ADDRESS;
+ break;
+ case BASE_DATA_MGR:
+ addr = ((u32)base & 0x7ff) | SDR_PHYGRP_DATAMGRGRP_ADDRESS;
+ break;
+ case BASE_SCC_MGR:
+ addr = ((u32)base & 0xfff) | SDR_PHYGRP_SCCGRP_ADDRESS;
+ break;
+ case BASE_REG_FILE:
+ addr = ((u32)base & 0x7ff) | SDR_PHYGRP_REGFILEGRP_ADDRESS;
+ break;
+ case BASE_MMR:
+ addr = ((u32)base & 0xfff) | SDR_CTRLGRP_ADDRESS;
+ break;
+ default:
+ return -1;
+ }
+
+ return addr;
+}
+
+static void set_failing_group_stage(uint32_t group, uint32_t stage,
+ uint32_t substage)
+{
+ /*
+ * Only set the global stage if there was not been any other
+ * failing group
+ */
+ if (gbl->error_stage == CAL_STAGE_NIL) {
+ gbl->error_substage = substage;
+ gbl->error_stage = stage;
+ gbl->error_group = group;
+ }
+}
+
+static void reg_file_set_group(uint32_t set_group)
+{
+ u32 addr = sdr_get_addr(&sdr_reg_file->cur_stage);
+
+ /* Read the current group and stage */
+ uint32_t cur_stage_group = readl(SOCFPGA_SDR_ADDRESS + addr);
+
+ /* Clear the group */
+ cur_stage_group &= 0x0000FFFF;
+
+ /* Set the group */
+ cur_stage_group |= (set_group << 16);
+
+ /* Write the data back */
+ writel(cur_stage_group, SOCFPGA_SDR_ADDRESS + addr);
+}
+
+static void reg_file_set_stage(uint32_t set_stage)
+{
+ u32 addr = sdr_get_addr(&sdr_reg_file->cur_stage);
+ /* Read the current group and stage */
+ uint32_t cur_stage_group = readl(SOCFPGA_SDR_ADDRESS + addr);
+
+ /* Clear the stage and substage */
+ cur_stage_group &= 0xFFFF0000;
+
+ /* Set the stage */
+ cur_stage_group |= (set_stage & 0x000000FF);
+
+ /* Write the data back */
+ writel(cur_stage_group, SOCFPGA_SDR_ADDRESS + addr);
+}
+
+static void reg_file_set_sub_stage(uint32_t set_sub_stage)
+{
+ u32 addr = sdr_get_addr(&sdr_reg_file->cur_stage);
+ /* Read the current group and stage */
+ uint32_t cur_stage_group = readl(SOCFPGA_SDR_ADDRESS + addr);
+
+ /* Clear the substage */
+ cur_stage_group &= 0xFFFF00FF;
+
+ /* Set the sub stage */
+ cur_stage_group |= ((set_sub_stage << 8) & 0x0000FF00);
+
+ /* Write the data back */
+ writel(cur_stage_group, SOCFPGA_SDR_ADDRESS + addr);
+}
+
+static void initialize(void)
+{
+ u32 addr = sdr_get_addr(&phy_mgr_cfg->mux_sel);
+
+ debug("%s:%d\n", __func__, __LINE__);
+ /* USER calibration has control over path to memory */
+ /*
+ * In Hard PHY this is a 2-bit control:
+ * 0: AFI Mux Select
+ * 1: DDIO Mux Select
+ */
+ writel(0x3, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* USER memory clock is not stable we begin initialization */
+ addr = sdr_get_addr(&phy_mgr_cfg->reset_mem_stbl);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* USER calibration status all set to zero */
+ addr = sdr_get_addr(&phy_mgr_cfg->cal_status);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&phy_mgr_cfg->cal_debug_info);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ if ((dyn_calib_steps & CALIB_SKIP_ALL) != CALIB_SKIP_ALL) {
+ param->read_correct_mask_vg = ((uint32_t)1 <<
+ (RW_MGR_MEM_DQ_PER_READ_DQS /
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
+ param->write_correct_mask_vg = ((uint32_t)1 <<
+ (RW_MGR_MEM_DQ_PER_READ_DQS /
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
+ param->read_correct_mask = ((uint32_t)1 <<
+ RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
+ param->write_correct_mask = ((uint32_t)1 <<
+ RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
+ param->dm_correct_mask = ((uint32_t)1 <<
+ (RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH))
+ - 1;
+ }
+}
+
+static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
+{
+ uint32_t odt_mask_0 = 0;
+ uint32_t odt_mask_1 = 0;
+ uint32_t cs_and_odt_mask;
+ uint32_t addr;
+
+ if (odt_mode == RW_MGR_ODT_MODE_READ_WRITE) {
+ if (RW_MGR_MEM_NUMBER_OF_RANKS == 1) {
+ /*
+ * 1 Rank
+ * Read: ODT = 0
+ * Write: ODT = 1
+ */
+ odt_mask_0 = 0x0;
+ odt_mask_1 = 0x1;
+ } else if (RW_MGR_MEM_NUMBER_OF_RANKS == 2) {
+ /* 2 Ranks */
+ if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
+ /* - Dual-Slot , Single-Rank
+ * (1 chip-select per DIMM)
+ * OR
+ * - RDIMM, 4 total CS (2 CS per DIMM)
+ * means 2 DIMM
+ * Since MEM_NUMBER_OF_RANKS is 2 they are
+ * both single rank
+ * with 2 CS each (special for RDIMM)
+ * Read: Turn on ODT on the opposite rank
+ * Write: Turn on ODT on all ranks
+ */
+ odt_mask_0 = 0x3 & ~(1 << rank);
+ odt_mask_1 = 0x3;
+ } else {
+ /*
+ * USER - Single-Slot , Dual-rank DIMMs
+ * (2 chip-selects per DIMM)
+ * USER Read: Turn on ODT off on all ranks
+ * USER Write: Turn on ODT on active rank
+ */
+ odt_mask_0 = 0x0;
+ odt_mask_1 = 0x3 & (1 << rank);
+ }
+ } else {
+ /* 4 Ranks
+ * Read:
+ * ----------+-----------------------+
+ * | |
+ * | ODT |
+ * Read From +-----------------------+
+ * Rank | 3 | 2 | 1 | 0 |
+ * ----------+-----+-----+-----+-----+
+ * 0 | 0 | 1 | 0 | 0 |
+ * 1 | 1 | 0 | 0 | 0 |
+ * 2 | 0 | 0 | 0 | 1 |
+ * 3 | 0 | 0 | 1 | 0 |
+ * ----------+-----+-----+-----+-----+
+ *
+ * Write:
+ * ----------+-----------------------+
+ * | |
+ * | ODT |
+ * Write To +-----------------------+
+ * Rank | 3 | 2 | 1 | 0 |
+ * ----------+-----+-----+-----+-----+
+ * 0 | 0 | 1 | 0 | 1 |
+ * 1 | 1 | 0 | 1 | 0 |
+ * 2 | 0 | 1 | 0 | 1 |
+ * 3 | 1 | 0 | 1 | 0 |
+ * ----------+-----+-----+-----+-----+
+ */
+ switch (rank) {
+ case 0:
+ odt_mask_0 = 0x4;
+ odt_mask_1 = 0x5;
+ break;
+ case 1:
+ odt_mask_0 = 0x8;
+ odt_mask_1 = 0xA;
+ break;
+ case 2:
+ odt_mask_0 = 0x1;
+ odt_mask_1 = 0x5;
+ break;
+ case 3:
+ odt_mask_0 = 0x2;
+ odt_mask_1 = 0xA;
+ break;
+ }
+ }
+ } else {
+ odt_mask_0 = 0x0;
+ odt_mask_1 = 0x0;
+ }
+
+ cs_and_odt_mask =
+ (0xFF & ~(1 << rank)) |
+ ((0xFF & odt_mask_0) << 8) |
+ ((0xFF & odt_mask_1) << 16);
+ addr = sdr_get_addr((u32 *)RW_MGR_SET_CS_AND_ODT_MASK);
+ writel(cs_and_odt_mask, SOCFPGA_SDR_ADDRESS + addr);
+}
+
+static void scc_mgr_initialize(void)
+{
+ u32 addr = sdr_get_addr((u32 *)SCC_MGR_HHP_RFILE);
+
+ /*
+ * Clear register file for HPS
+ * 16 (2^4) is the size of the full register file in the scc mgr:
+ * RFILE_DEPTH = log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
+ * MEM_IF_READ_DQS_WIDTH - 1) + 1;
+ */
+ uint32_t i;
+ for (i = 0; i < 16; i++) {
+ debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u",
+ __func__, __LINE__, i);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr + (i << 2));
+ }
+}
+
+static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group,
+ uint32_t delay)
+{
+ u32 addr = sdr_get_addr((u32 *)SCC_MGR_DQS_IN_DELAY);
+
+ /* Load the setting in the SCC manager */
+ writel(delay, SOCFPGA_SDR_ADDRESS + addr + (read_group << 2));
+}
+
+static void scc_mgr_set_dqs_io_in_delay(uint32_t write_group,
+ uint32_t delay)
+{
+ u32 addr = sdr_get_addr((u32 *)SCC_MGR_IO_IN_DELAY);
+
+ writel(delay, SOCFPGA_SDR_ADDRESS + addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
+}
+
+static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
+{
+ u32 addr = sdr_get_addr((u32 *)SCC_MGR_DQS_EN_PHASE);
+
+ /* Load the setting in the SCC manager */
+ writel(phase, SOCFPGA_SDR_ADDRESS + addr + (read_group << 2));
+}
+
+static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,
+ uint32_t phase)
+{
+ uint32_t r;
+ uint32_t update_scan_chains;
+ uint32_t addr;
+
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ r += NUM_RANKS_PER_SHADOW_REG) {
+ /*
+ * USER although the h/w doesn't support different phases per
+ * shadow register, for simplicity our scc manager modeling
+ * keeps different phase settings per shadow reg, and it's
+ * important for us to keep them in sync to match h/w.
+ * for efficiency, the scan chain update should occur only
+ * once to sr0.
+ */
+ update_scan_chains = (r == 0) ? 1 : 0;
+
+ scc_mgr_set_dqs_en_phase(read_group, phase);
+
+ if (update_scan_chains) {
+ addr = sdr_get_addr(&sdr_scc_mgr->dqs_ena);
+ writel(read_group, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ }
+ }
+}
+
+static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group,
+ uint32_t phase)
+{
+ u32 addr = sdr_get_addr((u32 *)SCC_MGR_DQDQS_OUT_PHASE);
+
+ /* Load the setting in the SCC manager */
+ writel(phase, SOCFPGA_SDR_ADDRESS + addr + (write_group << 2));
+}
+
+static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
+ uint32_t phase)
+{
+ uint32_t r;
+ uint32_t update_scan_chains;
+ uint32_t addr;
+
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ r += NUM_RANKS_PER_SHADOW_REG) {
+ /*
+ * USER although the h/w doesn't support different phases per
+ * shadow register, for simplicity our scc manager modeling
+ * keeps different phase settings per shadow reg, and it's
+ * important for us to keep them in sync to match h/w.
+ * for efficiency, the scan chain update should occur only
+ * once to sr0.
+ */
+ update_scan_chains = (r == 0) ? 1 : 0;
+
+ scc_mgr_set_dqdqs_output_phase(write_group, phase);
+
+ if (update_scan_chains) {
+ addr = sdr_get_addr(&sdr_scc_mgr->dqs_ena);
+ writel(write_group, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ }
+ }
+}
+
+static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
+{
+ uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_DQS_EN_DELAY);
+
+ /* Load the setting in the SCC manager */
+ writel(delay + IO_DQS_EN_DELAY_OFFSET, SOCFPGA_SDR_ADDRESS + addr +
+ (read_group << 2));
+}
+
+static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
+ uint32_t delay)
+{
+ uint32_t r;
+ uint32_t addr;
+
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ r += NUM_RANKS_PER_SHADOW_REG) {
+ scc_mgr_set_dqs_en_delay(read_group, delay);
+
+ addr = sdr_get_addr(&sdr_scc_mgr->dqs_ena);
+ writel(read_group, SOCFPGA_SDR_ADDRESS + addr);
+ /*
+ * In shadow register mode, the T11 settings are stored in
+ * registers in the core, which are updated by the DQS_ENA
+ * signals. Not issuing the SCC_MGR_UPD command allows us to
+ * save lots of rank switching overhead, by calling
+ * select_shadow_regs_for_update with update_scan_chains
+ * set to 0.
+ */
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ }
+ /*
+ * In shadow register mode, the T11 settings are stored in
+ * registers in the core, which are updated by the DQS_ENA
+ * signals. Not issuing the SCC_MGR_UPD command allows us to
+ * save lots of rank switching overhead, by calling
+ * select_shadow_regs_for_update with update_scan_chains
+ * set to 0.
+ */
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+}
+
+static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)
+{
+ uint32_t read_group;
+ uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_OCT_OUT1_DELAY);
+
+ /*
+ * Load the setting in the SCC manager
+ * Although OCT affects only write data, the OCT delay is controlled
+ * by the DQS logic block which is instantiated once per read group.
+ * For protocols where a write group consists of multiple read groups,
+ * the setting must be set multiple times.
+ */
+ for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
+ read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
+ writel(delay, SOCFPGA_SDR_ADDRESS + addr + (read_group << 2));
+}
+
+static void scc_mgr_set_dq_out1_delay(uint32_t write_group,
+ uint32_t dq_in_group, uint32_t delay)
+{
+ uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_IO_OUT1_DELAY);
+
+ /* Load the setting in the SCC manager */
+ writel(delay, SOCFPGA_SDR_ADDRESS + addr + (dq_in_group << 2));
+}
+
+static void scc_mgr_set_dq_in_delay(uint32_t write_group,
+ uint32_t dq_in_group, uint32_t delay)
+{
+ uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_IO_IN_DELAY);
+
+ /* Load the setting in the SCC manager */
+ writel(delay, SOCFPGA_SDR_ADDRESS + addr + (dq_in_group << 2));
+}
+
+static void scc_mgr_set_hhp_extras(void)
+{
+ /*
+ * Load the fixed setting in the SCC manager
+ * bits: 0:0 = 1'b1 - dqs bypass
+ * bits: 1:1 = 1'b1 - dq bypass
+ * bits: 4:2 = 3'b001 - rfifo_mode
+ * bits: 6:5 = 2'b01 - rfifo clock_select
+ * bits: 7:7 = 1'b0 - separate gating from ungating setting
+ * bits: 8:8 = 1'b0 - separate OE from Output delay setting
+ */
+ uint32_t value = (0<<8) | (0<<7) | (1<<5) | (1<<2) | (1<<1) | (1<<0);
+ uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_HHP_GLOBALS);
+
+ writel(value, SOCFPGA_SDR_ADDRESS + addr + SCC_MGR_HHP_EXTRAS_OFFSET);
+}
+
+static void scc_mgr_set_dqs_out1_delay(uint32_t write_group,
+ uint32_t delay)
+{
+ uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_IO_OUT1_DELAY);
+
+ /* Load the setting in the SCC manager */
+ writel(delay, SOCFPGA_SDR_ADDRESS + addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
+}
+
+static void scc_mgr_set_dm_out1_delay(uint32_t write_group,
+ uint32_t dm, uint32_t delay)
+{
+ uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_IO_OUT1_DELAY);
+
+ /* Load the setting in the SCC manager */
+ writel(delay, SOCFPGA_SDR_ADDRESS + addr +
+ ((RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm) << 2));
+}
+
+/*
+ * USER Zero all DQS config
+ * TODO: maybe rename to scc_mgr_zero_dqs_config (or something)
+ */
+static void scc_mgr_zero_all(void)
+{
+ uint32_t i, r;
+ uint32_t addr;
+
+ /*
+ * USER Zero all DQS config settings, across all groups and all
+ * shadow registers
+ */
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
+ NUM_RANKS_PER_SHADOW_REG) {
+ for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
+ /*
+ * The phases actually don't exist on a per-rank basis,
+ * but there's no harm updating them several times, so
+ * let's keep the code simple.
+ */
+ scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
+ scc_mgr_set_dqs_en_phase(i, 0);
+ scc_mgr_set_dqs_en_delay(i, 0);
+ }
+
+ for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
+ scc_mgr_set_dqdqs_output_phase(i, 0);
+ /* av/cv don't have out2 */
+ scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
+ }
+ }
+
+ /* multicast to all DQS group enables */
+ addr = sdr_get_addr(&sdr_scc_mgr->dqs_ena);
+ writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+}
+
+static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)
+{
+ uint32_t addr;
+ /* mode = 0 : Do NOT bypass - Half Rate Mode */
+ /* mode = 1 : Bypass - Full Rate Mode */
+
+ /* only need to set once for all groups, pins, dq, dqs, dm */
+ if (write_group == 0) {
+ debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n", __func__,
+ __LINE__);
+ scc_mgr_set_hhp_extras();
+ debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
+ __func__, __LINE__);
+ }
+ /* multicast to all DQ enables */
+ addr = sdr_get_addr(&sdr_scc_mgr->dq_ena);
+ writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_scc_mgr->dm_ena);
+ writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* update current DQS IO enable */
+ addr = sdr_get_addr(&sdr_scc_mgr->dqs_io_ena);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* update the DQS logic */
+ addr = sdr_get_addr(&sdr_scc_mgr->dqs_ena);
+ writel(write_group, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* hit update */
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+}
+
+static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
+ int32_t out_only)
+{
+ uint32_t i, r;
+ uint32_t addr;
+
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
+ NUM_RANKS_PER_SHADOW_REG) {
+ /* Zero all DQ config settings */
+ for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
+ scc_mgr_set_dq_out1_delay(write_group, i, 0);
+ if (!out_only)
+ scc_mgr_set_dq_in_delay(write_group, i, 0);
+ }
+
+ /* multicast to all DQ enables */
+ addr = sdr_get_addr(&sdr_scc_mgr->dq_ena);
+ writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* Zero all DM config settings */
+ for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
+ scc_mgr_set_dm_out1_delay(write_group, i, 0);
+ }
+
+ /* multicast to all DM enables */
+ addr = sdr_get_addr(&sdr_scc_mgr->dm_ena);
+ writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* zero all DQS io settings */
+ if (!out_only)
+ scc_mgr_set_dqs_io_in_delay(write_group, 0);
+ /* av/cv don't have out2 */
+ scc_mgr_set_dqs_out1_delay(write_group, IO_DQS_OUT_RESERVE);
+ scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
+ scc_mgr_load_dqs_for_write_group(write_group);
+
+ /* multicast to all DQS IO enables (only 1) */
+ addr = sdr_get_addr(&sdr_scc_mgr->dqs_io_ena);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* hit update to zero everything */
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ }
+}
+
+/* load up dqs config settings */
+static void scc_mgr_load_dqs(uint32_t dqs)
+{
+ uint32_t addr = sdr_get_addr(&sdr_scc_mgr->dqs_ena);
+
+ writel(dqs, SOCFPGA_SDR_ADDRESS + addr);
+}
+
+static void scc_mgr_load_dqs_for_write_group(uint32_t write_group)
+{
+ uint32_t read_group;
+ uint32_t addr = sdr_get_addr(&sdr_scc_mgr->dqs_ena);
+ /*
+ * Although OCT affects only write data, the OCT delay is controlled
+ * by the DQS logic block which is instantiated once per read group.
+ * For protocols where a write group consists of multiple read groups,
+ * the setting must be scanned multiple times.
+ */
+ for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
+ read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
+ writel(read_group, SOCFPGA_SDR_ADDRESS + addr);
+}
+
+/* load up dqs io config settings */
+static void scc_mgr_load_dqs_io(void)
+{
+ uint32_t addr = sdr_get_addr(&sdr_scc_mgr->dqs_io_ena);
+
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+}
+
+/* load up dq config settings */
+static void scc_mgr_load_dq(uint32_t dq_in_group)
+{
+ uint32_t addr = sdr_get_addr(&sdr_scc_mgr->dq_ena);
+
+ writel(dq_in_group, SOCFPGA_SDR_ADDRESS + addr);
+}
+
+/* load up dm config settings */
+static void scc_mgr_load_dm(uint32_t dm)
+{
+ uint32_t addr = sdr_get_addr(&sdr_scc_mgr->dm_ena);
+
+ writel(dm, SOCFPGA_SDR_ADDRESS + addr);
+}
+
+/*
+ * apply and load a particular input delay for the DQ pins in a group
+ * group_bgn is the index of the first dq pin (in the write group)
+ */
+static void scc_mgr_apply_group_dq_in_delay(uint32_t write_group,
+ uint32_t group_bgn, uint32_t delay)
+{
+ uint32_t i, p;
+
+ for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
+ scc_mgr_set_dq_in_delay(write_group, p, delay);
+ scc_mgr_load_dq(p);
+ }
+}
+
+/* apply and load a particular output delay for the DQ pins in a group */
+static void scc_mgr_apply_group_dq_out1_delay(uint32_t write_group,
+ uint32_t group_bgn,
+ uint32_t delay1)
+{
+ uint32_t i, p;
+
+ for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
+ scc_mgr_set_dq_out1_delay(write_group, i, delay1);
+ scc_mgr_load_dq(i);
+ }
+}
+
+/* apply and load a particular output delay for the DM pins in a group */
+static void scc_mgr_apply_group_dm_out1_delay(uint32_t write_group,
+ uint32_t delay1)
+{
+ uint32_t i;
+
+ for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
+ scc_mgr_set_dm_out1_delay(write_group, i, delay1);
+ scc_mgr_load_dm(i);
+ }
+}
+
+
+/* apply and load delay on both DQS and OCT out1 */
+static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
+ uint32_t delay)
+{
+ scc_mgr_set_dqs_out1_delay(write_group, delay);
+ scc_mgr_load_dqs_io();
+
+ scc_mgr_set_oct_out1_delay(write_group, delay);
+ scc_mgr_load_dqs_for_write_group(write_group);
+}
+
+/* apply a delay to the entire output side: DQ, DM, DQS, OCT */
+static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group,
+ uint32_t group_bgn,
+ uint32_t delay)
+{
+ uint32_t i, p, new_delay;
+
+ /* dq shift */
+ for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
+ new_delay = READ_SCC_DQ_OUT2_DELAY;
+ new_delay += delay;
+
+ if (new_delay > IO_IO_OUT2_DELAY_MAX) {
+ debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQ[%u,%u]:\
+ %u > %lu => %lu", __func__, __LINE__,
+ write_group, group_bgn, delay, i, p, new_delay,
+ (long unsigned int)IO_IO_OUT2_DELAY_MAX,
+ (long unsigned int)IO_IO_OUT2_DELAY_MAX);
+ new_delay = IO_IO_OUT2_DELAY_MAX;
+ }
+
+ scc_mgr_load_dq(i);
+ }
+
+ /* dm shift */
+ for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
+ new_delay = READ_SCC_DM_IO_OUT2_DELAY;
+ new_delay += delay;
+
+ if (new_delay > IO_IO_OUT2_DELAY_MAX) {
+ debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DM[%u]:\
+ %u > %lu => %lu\n", __func__, __LINE__,
+ write_group, group_bgn, delay, i, new_delay,
+ (long unsigned int)IO_IO_OUT2_DELAY_MAX,
+ (long unsigned int)IO_IO_OUT2_DELAY_MAX);
+ new_delay = IO_IO_OUT2_DELAY_MAX;
+ }
+
+ scc_mgr_load_dm(i);
+ }
+
+ /* dqs shift */
+ new_delay = READ_SCC_DQS_IO_OUT2_DELAY;
+ new_delay += delay;
+
+ if (new_delay > IO_IO_OUT2_DELAY_MAX) {
+ debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQS: %u > %d => %d;"
+ " adding %u to OUT1\n", __func__, __LINE__,
+ write_group, group_bgn, delay, new_delay,
+ IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
+ new_delay - IO_IO_OUT2_DELAY_MAX);
+ scc_mgr_set_dqs_out1_delay(write_group, new_delay -
+ IO_IO_OUT2_DELAY_MAX);
+ new_delay = IO_IO_OUT2_DELAY_MAX;
+ }
+
+ scc_mgr_load_dqs_io();
+
+ /* oct shift */
+ new_delay = READ_SCC_OCT_OUT2_DELAY;
+ new_delay += delay;
+
+ if (new_delay > IO_IO_OUT2_DELAY_MAX) {
+ debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQS: %u > %d => %d;"
+ " adding %u to OUT1\n", __func__, __LINE__,
+ write_group, group_bgn, delay, new_delay,
+ IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
+ new_delay - IO_IO_OUT2_DELAY_MAX);
+ scc_mgr_set_oct_out1_delay(write_group, new_delay -
+ IO_IO_OUT2_DELAY_MAX);
+ new_delay = IO_IO_OUT2_DELAY_MAX;
+ }
+
+ scc_mgr_load_dqs_for_write_group(write_group);
+}
+
+/*
+ * USER apply a delay to the entire output side (DQ, DM, DQS, OCT)
+ * and to all ranks
+ */
+static void scc_mgr_apply_group_all_out_delay_add_all_ranks(
+ uint32_t write_group, uint32_t group_bgn, uint32_t delay)
+{
+ uint32_t r;
+ uint32_t addr = sdr_get_addr(&sdr_scc_mgr->update);
+
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ r += NUM_RANKS_PER_SHADOW_REG) {
+ scc_mgr_apply_group_all_out_delay_add(write_group,
+ group_bgn, delay);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ }
+}
+
+/* optimization used to recover some slots in ddr3 inst_rom */
+/* could be applied to other protocols if we wanted to */
+static void set_jump_as_return(void)
+{
+ uint32_t addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
+
+ /*
+ * to save space, we replace return with jump to special shared
+ * RETURN instruction so we set the counter to large value so that
+ * we always jump
+ */
+ writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ writel(RW_MGR_RETURN, SOCFPGA_SDR_ADDRESS + addr);
+}
+
+/*
+ * should always use constants as argument to ensure all computations are
+ * performed at compile time
+ */
+static void delay_for_n_mem_clocks(const uint32_t clocks)
+{
+ uint32_t afi_clocks;
+ uint8_t inner = 0;
+ uint8_t outer = 0;
+ uint16_t c_loop = 0;
+ uint32_t addr;
+
+ debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
+
+
+ afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
+ /* scale (rounding up) to get afi clocks */
+
+ /*
+ * Note, we don't bother accounting for being off a little bit
+ * because of a few extra instructions in outer loops
+ * Note, the loops have a test at the end, and do the test before
+ * the decrement, and so always perform the loop
+ * 1 time more than the counter value
+ */
+ if (afi_clocks == 0) {
+ ;
+ } else if (afi_clocks <= 0x100) {
+ inner = afi_clocks-1;
+ outer = 0;
+ c_loop = 0;
+ } else if (afi_clocks <= 0x10000) {
+ inner = 0xff;
+ outer = (afi_clocks-1) >> 8;
+ c_loop = 0;
+ } else {
+ inner = 0xff;
+ outer = 0xff;
+ c_loop = (afi_clocks-1) >> 16;
+ }
+
+ /*
+ * rom instructions are structured as follows:
+ *
+ * IDLE_LOOP2: jnz cntr0, TARGET_A
+ * IDLE_LOOP1: jnz cntr1, TARGET_B
+ * return
+ *
+ * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
+ * TARGET_B is set to IDLE_LOOP2 as well
+ *
+ * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
+ * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
+ *
+ * a little confusing, but it helps save precious space in the inst_rom
+ * and sequencer rom and keeps the delays more accurate and reduces
+ * overhead
+ */
+ if (afi_clocks <= 0x100) {
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ writel(RW_MGR_IDLE_LOOP1, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ writel(RW_MGR_IDLE_LOOP1, SOCFPGA_SDR_ADDRESS + addr);
+ } else {
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer), SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ writel(RW_MGR_IDLE_LOOP2, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ writel(RW_MGR_IDLE_LOOP2, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* hack to get around compiler not being smart enough */
+ if (afi_clocks <= 0x10000) {
+ /* only need to run once */
+ addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ writel(RW_MGR_IDLE_LOOP2, SOCFPGA_SDR_ADDRESS + addr);
+ } else {
+ do {
+ addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ writel(RW_MGR_IDLE_LOOP2, SOCFPGA_SDR_ADDRESS + addr);
+ } while (c_loop-- != 0);
+ }
+ }
+ debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
+}
+
+static void rw_mgr_mem_initialize(void)
+{
+ uint32_t r;
+ uint32_t addr;
+
+ debug("%s:%d\n", __func__, __LINE__);
+
+ /* The reset / cke part of initialization is broadcasted to all ranks */
+ addr = sdr_get_addr((u32 *)RW_MGR_SET_CS_AND_ODT_MASK);
+ writel(RW_MGR_RANK_ALL, SOCFPGA_SDR_ADDRESS + addr);
+
+ /*
+ * Here's how you load register for a loop
+ * Counters are located @ 0x800
+ * Jump address are located @ 0xC00
+ * For both, registers 0 to 3 are selected using bits 3 and 2, like
+ * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
+ * I know this ain't pretty, but Avalon bus throws away the 2 least
+ * significant bits
+ */
+
+ /* start with memory RESET activated */
+
+ /* tINIT = 200us */
+
+ /*
+ * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
+ * If a and b are the number of iteration in 2 nested loops
+ * it takes the following number of cycles to complete the operation:
+ * number_of_cycles = ((2 + n) * a + 2) * b
+ * where n is the number of instruction in the inner loop
+ * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
+ * b = 6A
+ */
+
+ /* Load counters */
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL),
+ SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL),
+ SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL),
+ SOCFPGA_SDR_ADDRESS + addr);
+
+ /* Load jump address */
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* Execute count instruction */
+ addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* indicate that memory is stable */
+ addr = sdr_get_addr(&phy_mgr_cfg->reset_mem_stbl);
+ writel(1, SOCFPGA_SDR_ADDRESS + addr);
+
+ /*
+ * transition the RESET to high
+ * Wait for 500us
+ */
+
+ /*
+ * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
+ * If a and b are the number of iteration in 2 nested loops
+ * it takes the following number of cycles to complete the operation
+ * number_of_cycles = ((2 + n) * a + 2) * b
+ * where n is the number of instruction in the inner loop
+ * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
+ * b = FF
+ */
+
+ /* Load counters */
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR0_VAL),
+ SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR1_VAL),
+ SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR2_VAL),
+ SOCFPGA_SDR_ADDRESS + addr);
+
+ /* Load jump address */
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* bring up clock enable */
+
+ /* tXRP < 250 ck cycles */
+ delay_for_n_mem_clocks(250);
+
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
+ if (param->skip_ranks[r]) {
+ /* request to skip the rank */
+ continue;
+ }
+
+ /* set rank */
+ set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
+
+ /*
+ * USER Use Mirror-ed commands for odd ranks if address
+ * mirrorring is on
+ */
+ if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
+ set_jump_as_return();
+ addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ writel(RW_MGR_MRS2_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(RW_MGR_MRS3_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(RW_MGR_MRS1_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(RW_MGR_MRS0_DLL_RESET_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ } else {
+ set_jump_as_return();
+ addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ writel(RW_MGR_MRS2, SOCFPGA_SDR_ADDRESS + addr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(RW_MGR_MRS3, SOCFPGA_SDR_ADDRESS + addr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(RW_MGR_MRS1, SOCFPGA_SDR_ADDRESS + addr);
+ set_jump_as_return();
+ writel(RW_MGR_MRS0_DLL_RESET, SOCFPGA_SDR_ADDRESS + addr);
+ }
+ set_jump_as_return();
+ addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ writel(RW_MGR_ZQCL, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* tZQinit = tDLLK = 512 ck cycles */
+ delay_for_n_mem_clocks(512);
+ }
+}
+
+/*
+ * At the end of calibration we have to program the user settings in, and
+ * USER hand off the memory to the user.
+ */
+static void rw_mgr_mem_handoff(void)
+{
+ uint32_t r;
+ uint32_t addr;
+
+ debug("%s:%d\n", __func__, __LINE__);
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
+ if (param->skip_ranks[r])
+ /* request to skip the rank */
+ continue;
+ /* set rank */
+ set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
+
+ /* precharge all banks ... */
+ addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ writel(RW_MGR_PRECHARGE_ALL, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* load up MR settings specified by user */
+
+ /*
+ * Use Mirror-ed commands for odd ranks if address
+ * mirrorring is on
+ */
+ addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
+ set_jump_as_return();
+ writel(RW_MGR_MRS2_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(RW_MGR_MRS3_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(RW_MGR_MRS1_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(RW_MGR_MRS0_USER_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ } else {
+ set_jump_as_return();
+ writel(RW_MGR_MRS2, SOCFPGA_SDR_ADDRESS + addr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(RW_MGR_MRS3, SOCFPGA_SDR_ADDRESS + addr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(RW_MGR_MRS1, SOCFPGA_SDR_ADDRESS + addr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(RW_MGR_MRS0_USER, SOCFPGA_SDR_ADDRESS + addr);
+ }
+ /*
+ * USER need to wait tMOD (12CK or 15ns) time before issuing
+ * other commands, but we will have plenty of NIOS cycles before
+ * actual handoff so its okay.
+ */
+ }
+}
+
+/*
+ * performs a guaranteed read on the patterns we are going to use during a
+ * read test to ensure memory works
+ */
+static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
+ uint32_t group, uint32_t num_tries, uint32_t *bit_chk,
+ uint32_t all_ranks)
+{
+ uint32_t r, vg;
+ uint32_t correct_mask_vg;
+ uint32_t tmp_bit_chk;
+ uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
+ (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
+ uint32_t addr;
+ uint32_t base_rw_mgr;
+
+ *bit_chk = param->read_correct_mask;
+ correct_mask_vg = param->read_correct_mask_vg;
+
+ for (r = rank_bgn; r < rank_end; r++) {
+ if (param->skip_ranks[r])
+ /* request to skip the rank */
+ continue;
+
+ /* set rank */
+ set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
+
+ /* Load up a constant bursts of read commands */
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
+ writel(0x20, SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ writel(RW_MGR_GUARANTEED_READ, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
+ writel(0x20, SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ writel(RW_MGR_GUARANTEED_READ_CONT, SOCFPGA_SDR_ADDRESS + addr);
+
+ tmp_bit_chk = 0;
+ for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
+ /* reset the fifos to get pointers to known state */
+
+ addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr((u32 *)RW_MGR_RESET_READ_DATAPATH);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
+ / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
+
+ addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ writel(RW_MGR_GUARANTEED_READ, SOCFPGA_SDR_ADDRESS + addr +
+ ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
+ vg) << 2));
+
+ addr = sdr_get_addr((u32 *)BASE_RW_MGR);
+ base_rw_mgr = readl(SOCFPGA_SDR_ADDRESS + addr);
+ tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
+
+ if (vg == 0)
+ break;
+ }
+ *bit_chk &= tmp_bit_chk;
+ }
+
+ addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ writel(RW_MGR_CLEAR_DQS_ENABLE, SOCFPGA_SDR_ADDRESS + addr + (group << 2));
+
+ set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
+ debug_cond(DLEVEL == 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) =>\
+ %lu\n", __func__, __LINE__, group, *bit_chk, param->read_correct_mask,
+ (long unsigned int)(*bit_chk == param->read_correct_mask));
+ return *bit_chk == param->read_correct_mask;
+}
+
+static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks
+ (uint32_t group, uint32_t num_tries, uint32_t *bit_chk)
+{
+ return rw_mgr_mem_calibrate_read_test_patterns(0, group,
+ num_tries, bit_chk, 1);
+}
+
+/* load up the patterns we are going to use during a read test */
+static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,
+ uint32_t all_ranks)
+{
+ uint32_t r;
+ uint32_t addr;
+ uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
+ (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
+
+ debug("%s:%d\n", __func__, __LINE__);
+ for (r = rank_bgn; r < rank_end; r++) {
+ if (param->skip_ranks[r])
+ /* request to skip the rank */
+ continue;
+
+ /* set rank */
+ set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
+
+ /* Load up a constant bursts */
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
+ writel(0x20, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT0, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
+ writel(0x20, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT1, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
+ writel(0x04, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT2, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr3);
+ writel(0x04, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT3, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ writel(RW_MGR_GUARANTEED_WRITE, SOCFPGA_SDR_ADDRESS + addr);
+ }
+
+ set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
+}
+
+/*
+ * try a read and see if it returns correct data back. has dummy reads
+ * inserted into the mix used to align dqs enable. has more thorough checks
+ * than the regular read test.
+ */
+static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
+ uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
+ uint32_t all_groups, uint32_t all_ranks)
+{
+ uint32_t r, vg;
+ uint32_t correct_mask_vg;
+ uint32_t tmp_bit_chk;
+ uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
+ (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
+ uint32_t addr;
+ uint32_t base_rw_mgr;
+
+ *bit_chk = param->read_correct_mask;
+ correct_mask_vg = param->read_correct_mask_vg;
+
+ uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
+ CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
+
+ for (r = rank_bgn; r < rank_end; r++) {
+ if (param->skip_ranks[r])
+ /* request to skip the rank */
+ continue;
+
+ /* set rank */
+ set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
+
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
+ writel(0x10, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ writel(RW_MGR_READ_B2B_WAIT1, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
+ writel(0x10, SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ writel(RW_MGR_READ_B2B_WAIT2, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
+ if (quick_read_mode)
+ writel(0x1, SOCFPGA_SDR_ADDRESS + addr);
+ /* need at least two (1+1) reads to capture failures */
+ else if (all_groups)
+ writel(0x06, SOCFPGA_SDR_ADDRESS + addr);
+ else
+ writel(0x32, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ writel(RW_MGR_READ_B2B, SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr3);
+ if (all_groups)
+ writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
+ SOCFPGA_SDR_ADDRESS + addr);
+ else
+ writel(0x0, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ writel(RW_MGR_READ_B2B, SOCFPGA_SDR_ADDRESS + addr);
+
+ tmp_bit_chk = 0;
+ for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
+ /* reset the fifos to get pointers to known state */
+ addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr((u32 *)RW_MGR_RESET_READ_DATAPATH);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
+ / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
+
+ addr = sdr_get_addr((u32 *)(all_groups ? RW_MGR_RUN_ALL_GROUPS :
+ RW_MGR_RUN_SINGLE_GROUP));
+ writel(RW_MGR_READ_B2B, SOCFPGA_SDR_ADDRESS + addr +
+ ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
+ vg) << 2));
+
+ addr = sdr_get_addr((u32 *)BASE_RW_MGR);
+ base_rw_mgr = readl(SOCFPGA_SDR_ADDRESS + addr);
+ tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
+
+ if (vg == 0)
+ break;
+ }
+ *bit_chk &= tmp_bit_chk;
+ }
+
+ addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ writel(RW_MGR_CLEAR_DQS_ENABLE, SOCFPGA_SDR_ADDRESS + addr + (group << 2));
+
+ if (all_correct) {
+ set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
+ debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
+ (%u == %u) => %lu", __func__, __LINE__, group,
+ all_groups, *bit_chk, param->read_correct_mask,
+ (long unsigned int)(*bit_chk ==
+ param->read_correct_mask));
+ return *bit_chk == param->read_correct_mask;
+ } else {
+ set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
+ debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
+ (%u != %lu) => %lu\n", __func__, __LINE__,
+ group, all_groups, *bit_chk, (long unsigned int)0,
+ (long unsigned int)(*bit_chk != 0x00));
+ return *bit_chk != 0x00;
+ }
+}
+
+static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
+ uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
+ uint32_t all_groups)
+{
+ return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
+ bit_chk, all_groups, 1);
+}
+
+static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
+{
+ uint32_t addr = sdr_get_addr(&phy_mgr_cmd->inc_vfifo_hard_phy);
+
+ writel(grp, SOCFPGA_SDR_ADDRESS + addr);
+ (*v)++;
+}
+
+static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
+{
+ uint32_t i;
+
+ for (i = 0; i < VFIFO_SIZE-1; i++)
+ rw_mgr_incr_vfifo(grp, v);
+}
+
+static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
+{
+ uint32_t v;
+ uint32_t fail_cnt = 0;
+ uint32_t test_status;
+
+ for (v = 0; v < VFIFO_SIZE; ) {
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
+ __func__, __LINE__, v);
+ test_status = rw_mgr_mem_calibrate_read_test_all_ranks
+ (grp, 1, PASS_ONE_BIT, bit_chk, 0);
+ if (!test_status) {
+ fail_cnt++;
+
+ if (fail_cnt == 2)
+ break;
+ }
+
+ /* fiddle with FIFO */
+ rw_mgr_incr_vfifo(grp, &v);
+ }
+
+ if (v >= VFIFO_SIZE) {
+ /* no failing read found!! Something must have gone wrong */
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
+ __func__, __LINE__);
+ return 0;
+ } else {
+ return v;
+ }
+}
+
+static int find_working_phase(uint32_t *grp, uint32_t *bit_chk,
+ uint32_t dtaps_per_ptap, uint32_t *work_bgn,
+ uint32_t *v, uint32_t *d, uint32_t *p,
+ uint32_t *i, uint32_t *max_working_cnt)
+{
+ uint32_t found_begin = 0;
+ uint32_t tmp_delay = 0;
+ uint32_t test_status;
+
+ for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
+ IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
+ *work_bgn = tmp_delay;
+ scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
+
+ for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
+ for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
+ IO_DELAY_PER_OPA_TAP) {
+ scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
+
+ test_status =
+ rw_mgr_mem_calibrate_read_test_all_ranks
+ (*grp, 1, PASS_ONE_BIT, bit_chk, 0);
+
+ if (test_status) {
+ *max_working_cnt = 1;
+ found_begin = 1;
+ break;
+ }
+ }
+
+ if (found_begin)
+ break;
+
+ if (*p > IO_DQS_EN_PHASE_MAX)
+ /* fiddle with FIFO */
+ rw_mgr_incr_vfifo(*grp, v);
+ }
+
+ if (found_begin)
+ break;
+ }
+
+ if (*i >= VFIFO_SIZE) {
+ /* cannot find working solution */
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
+ ptap/dtap\n", __func__, __LINE__);
+ return 0;
+ } else {
+ return 1;
+ }
+}
+
+static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
+ uint32_t *work_bgn, uint32_t *v, uint32_t *d,
+ uint32_t *p, uint32_t *max_working_cnt)
+{
+ uint32_t found_begin = 0;
+ uint32_t tmp_delay;
+
+ /* Special case code for backing up a phase */
+ if (*p == 0) {
+ *p = IO_DQS_EN_PHASE_MAX;
+ rw_mgr_decr_vfifo(*grp, v);
+ } else {
+ (*p)--;
+ }
+ tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
+ scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
+
+ for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
+ (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
+ scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
+
+ if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
+ PASS_ONE_BIT,
+ bit_chk, 0)) {
+ found_begin = 1;
+ *work_bgn = tmp_delay;
+ break;
+ }
+ }
+
+ /* We have found a working dtap before the ptap found above */
+ if (found_begin == 1)
+ (*max_working_cnt)++;
+
+ /*
+ * Restore VFIFO to old state before we decremented it
+ * (if needed).
+ */
+ (*p)++;
+ if (*p > IO_DQS_EN_PHASE_MAX) {
+ *p = 0;
+ rw_mgr_incr_vfifo(*grp, v);
+ }
+
+ scc_mgr_set_dqs_en_delay_all_ranks(*grp, 0);
+}
+
+static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
+ uint32_t *work_bgn, uint32_t *v, uint32_t *d,
+ uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
+ uint32_t *work_end)
+{
+ uint32_t found_end = 0;
+
+ (*p)++;
+ *work_end += IO_DELAY_PER_OPA_TAP;
+ if (*p > IO_DQS_EN_PHASE_MAX) {
+ /* fiddle with FIFO */
+ *p = 0;
+ rw_mgr_incr_vfifo(*grp, v);
+ }
+
+ for (; *i < VFIFO_SIZE + 1; (*i)++) {
+ for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
+ += IO_DELAY_PER_OPA_TAP) {
+ scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
+
+ if (!rw_mgr_mem_calibrate_read_test_all_ranks
+ (*grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
+ found_end = 1;
+ break;
+ } else {
+ (*max_working_cnt)++;
+ }
+ }
+
+ if (found_end)
+ break;
+
+ if (*p > IO_DQS_EN_PHASE_MAX) {
+ /* fiddle with FIFO */
+ rw_mgr_incr_vfifo(*grp, v);
+ *p = 0;
+ }
+ }
+
+ if (*i >= VFIFO_SIZE + 1) {
+ /* cannot see edge of failing read */
+ debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
+ failed\n", __func__, __LINE__);
+ return 0;
+ } else {
+ return 1;
+ }
+}
+
+static int sdr_find_window_centre(uint32_t *grp, uint32_t *bit_chk,
+ uint32_t *work_bgn, uint32_t *v, uint32_t *d,
+ uint32_t *p, uint32_t *work_mid,
+ uint32_t *work_end)
+{
+ int i;
+ int tmp_delay = 0;
+
+ *work_mid = (*work_bgn + *work_end) / 2;
+
+ debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
+ *work_bgn, *work_end, *work_mid);
+ /* Get the middle delay to be less than a VFIFO delay */
+ for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX;
+ (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
+ ;
+ debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
+ while (*work_mid > tmp_delay)
+ *work_mid -= tmp_delay;
+ debug_cond(DLEVEL == 2, "new work_mid %d\n", *work_mid);
+
+ tmp_delay = 0;
+ for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX && tmp_delay < *work_mid;
+ (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
+ ;
+ tmp_delay -= IO_DELAY_PER_OPA_TAP;
+ debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", (*p) - 1, tmp_delay);
+ for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_mid; (*d)++,
+ tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP)
+ ;
+ debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", *d, tmp_delay);
+
+ scc_mgr_set_dqs_en_phase_all_ranks(*grp, (*p) - 1);
+ scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
+
+ /*
+ * push vfifo until we can successfully calibrate. We can do this
+ * because the largest possible margin in 1 VFIFO cycle.
+ */
+ for (i = 0; i < VFIFO_SIZE; i++) {
+ debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
+ *v);
+ if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
+ PASS_ONE_BIT,
+ bit_chk, 0)) {
+ break;
+ }
+
+ /* fiddle with FIFO */
+ rw_mgr_incr_vfifo(*grp, v);
+ }
+
+ if (i >= VFIFO_SIZE) {
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center: \
+ failed\n", __func__, __LINE__);
+ return 0;
+ } else {
+ return 1;
+ }
+}
+
+/* find a good dqs enable to use */
+static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
+{
+ uint32_t v, d, p, i;
+ uint32_t max_working_cnt;
+ uint32_t bit_chk;
+ uint32_t dtaps_per_ptap;
+ uint32_t work_bgn, work_mid, work_end;
+ uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
+ uint32_t addr;
+
+ debug("%s:%d %u\n", __func__, __LINE__, grp);
+
+ reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
+
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
+ scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
+
+ /* ************************************************************** */
+ /* * Step 0 : Determine number of delay taps for each phase tap * */
+ dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+
+ /* ********************************************************* */
+ /* * Step 1 : First push vfifo until we get a failing read * */
+ v = find_vfifo_read(grp, &bit_chk);
+
+ max_working_cnt = 0;
+
+ /* ******************************************************** */
+ /* * step 2: find first working phase, increment in ptaps * */
+ work_bgn = 0;
+ if (find_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
+ &p, &i, &max_working_cnt) == 0)
+ return 0;
+
+ work_end = work_bgn;
+
+ /*
+ * If d is 0 then the working window covers a phase tap and
+ * we can follow the old procedure otherwise, we've found the beginning,
+ * and we need to increment the dtaps until we find the end.
+ */
+ if (d == 0) {
+ /* ********************************************************* */
+ /* * step 3a: if we have room, back off by one and
+ increment in dtaps * */
+
+ sdr_backup_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
+ &max_working_cnt);
+
+ /* ********************************************************* */
+ /* * step 4a: go forward from working phase to non working
+ phase, increment in ptaps * */
+ if (sdr_nonworking_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
+ &i, &max_working_cnt, &work_end) == 0)
+ return 0;
+
+ /* ********************************************************* */
+ /* * step 5a: back off one from last, increment in dtaps * */
+
+ /* Special case code for backing up a phase */
+ if (p == 0) {
+ p = IO_DQS_EN_PHASE_MAX;
+ rw_mgr_decr_vfifo(grp, &v);
+ } else {
+ p = p - 1;
+ }
+
+ work_end -= IO_DELAY_PER_OPA_TAP;
+ scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
+
+ /* * The actual increment of dtaps is done outside of
+ the if/else loop to share code */
+ d = 0;
+
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
+ vfifo=%u ptap=%u\n", __func__, __LINE__,
+ v, p);
+ } else {
+ /* ******************************************************* */
+ /* * step 3-5b: Find the right edge of the window using
+ delay taps * */
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
+ ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
+ v, p, d, work_bgn);
+
+ work_end = work_bgn;
+
+ /* * The actual increment of dtaps is done outside of the
+ if/else loop to share code */
+
+ /* Only here to counterbalance a subtract later on which is
+ not needed if this branch of the algorithm is taken */
+ max_working_cnt++;
+ }
+
+ /* The dtap increment to find the failing edge is done here */
+ for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
+ IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
+ end-2: dtap=%u\n", __func__, __LINE__, d);
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
+
+ if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
+ PASS_ONE_BIT,
+ &bit_chk, 0)) {
+ break;
+ }
+ }
+
+ /* Go back to working dtap */
+ if (d != 0)
+ work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
+ ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
+ v, p, d-1, work_end);
+
+ if (work_end < work_bgn) {
+ /* nil range */
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
+ failed\n", __func__, __LINE__);
+ return 0;
+ }
+
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
+ __func__, __LINE__, work_bgn, work_end);
+
+ /* *************************************************************** */
+ /*
+ * * We need to calculate the number of dtaps that equal a ptap
+ * * To do that we'll back up a ptap and re-find the edge of the
+ * * window using dtaps
+ */
+
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
+ for tracking\n", __func__, __LINE__);
+
+ /* Special case code for backing up a phase */
+ if (p == 0) {
+ p = IO_DQS_EN_PHASE_MAX;
+ rw_mgr_decr_vfifo(grp, &v);
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
+ cycle/phase: v=%u p=%u\n", __func__, __LINE__,
+ v, p);
+ } else {
+ p = p - 1;
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
+ phase only: v=%u p=%u", __func__, __LINE__,
+ v, p);
+ }
+
+ scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
+
+ /*
+ * Increase dtap until we first see a passing read (in case the
+ * window is smaller than a ptap),
+ * and then a failing read to mark the edge of the window again
+ */
+
+ /* Find a passing read */
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
+ __func__, __LINE__);
+ found_passing_read = 0;
+ found_failing_read = 0;
+ initial_failing_dtap = d;
+ for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
+ read d=%u\n", __func__, __LINE__, d);
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
+
+ if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
+ PASS_ONE_BIT,
+ &bit_chk, 0)) {
+ found_passing_read = 1;
+ break;
+ }
+ }
+
+ if (found_passing_read) {
+ /* Find a failing read */
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
+ read\n", __func__, __LINE__);
+ for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
+ testing read d=%u\n", __func__, __LINE__, d);
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
+
+ if (!rw_mgr_mem_calibrate_read_test_all_ranks
+ (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
+ found_failing_read = 1;
+ break;
+ }
+ }
+ } else {
+ debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
+ calculate dtaps", __func__, __LINE__);
+ debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
+ }
+
+ /*
+ * The dynamically calculated dtaps_per_ptap is only valid if we
+ * found a passing/failing read. If we didn't, it means d hit the max
+ * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
+ * statically calculated value.
+ */
+ if (found_passing_read && found_failing_read)
+ dtaps_per_ptap = d - initial_failing_dtap;
+
+ addr = sdr_get_addr(&sdr_reg_file->dtaps_per_ptap);
+ writel(dtaps_per_ptap, SOCFPGA_SDR_ADDRESS + addr);
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
+ - %u = %u", __func__, __LINE__, d,
+ initial_failing_dtap, dtaps_per_ptap);
+
+ /* ******************************************** */
+ /* * step 6: Find the centre of the window * */
+ if (sdr_find_window_centre(&grp, &bit_chk, &work_bgn, &v, &d, &p,
+ &work_mid, &work_end) == 0)
+ return 0;
+
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center found: \
+ vfifo=%u ptap=%u dtap=%u\n", __func__, __LINE__,
+ v, p-1, d);
+ return 1;
+}
+
+/*
+ * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
+ * dq_in_delay values
+ */
+static uint32_t
+rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
+(uint32_t write_group, uint32_t read_group, uint32_t test_bgn)
+{
+ uint32_t found;
+ uint32_t i;
+ uint32_t p;
+ uint32_t d;
+ uint32_t r;
+ uint32_t addr;
+
+ const uint32_t delay_step = IO_IO_IN_DELAY_MAX /
+ (RW_MGR_MEM_DQ_PER_READ_DQS-1);
+ /* we start at zero, so have one less dq to devide among */
+
+ debug("%s:%d (%u,%u,%u)", __func__, __LINE__, write_group, read_group,
+ test_bgn);
+
+ /* try different dq_in_delays since the dq path is shorter than dqs */
+
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ r += NUM_RANKS_PER_SHADOW_REG) {
+ for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS;
+ i++, p++, d += delay_step) {
+ debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_\
+ vfifo_find_dqs_", __func__, __LINE__);
+ debug_cond(DLEVEL == 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
+ write_group, read_group);
+ debug_cond(DLEVEL == 1, "r=%u, i=%u p=%u d=%u\n", r, i , p, d);
+ scc_mgr_set_dq_in_delay(write_group, p, d);
+ scc_mgr_load_dq(p);
+ }
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ }
+
+ found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
+
+ debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_vfifo_find_dqs_\
+ en_phase_sweep_dq", __func__, __LINE__);
+ debug_cond(DLEVEL == 1, "_in_delay: g=%u/%u found=%u; Reseting delay \
+ chain to zero\n", write_group, read_group, found);
+
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ r += NUM_RANKS_PER_SHADOW_REG) {
+ for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS;
+ i++, p++) {
+ scc_mgr_set_dq_in_delay(write_group, p, 0);
+ scc_mgr_load_dq(p);
+ }
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ }
+
+ return found;
+}
+
+/* per-bit deskew DQ and center */
+static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
+ uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
+ uint32_t use_read_test, uint32_t update_fom)
+{
+ uint32_t i, p, d, min_index;
+ /*
+ * Store these as signed since there are comparisons with
+ * signed numbers.
+ */
+ uint32_t bit_chk;
+ uint32_t sticky_bit_chk;
+ int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
+ int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
+ int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
+ int32_t mid;
+ int32_t orig_mid_min, mid_min;
+ int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
+ final_dqs_en;
+ int32_t dq_margin, dqs_margin;
+ uint32_t stop;
+ uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
+ uint32_t addr;
+
+ debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
+
+ addr = sdr_get_addr((u32 *)SCC_MGR_DQS_IN_DELAY);
+ start_dqs = readl(SOCFPGA_SDR_ADDRESS + addr + (read_group << 2));
+ if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
+ start_dqs_en = readl(SOCFPGA_SDR_ADDRESS + addr + ((read_group << 2)
+ - IO_DQS_EN_DELAY_OFFSET));
+
+ /* set the left and right edge of each bit to an illegal value */
+ /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
+ sticky_bit_chk = 0;
+ for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
+ left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
+ right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
+ }
+
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ /* Search for the left edge of the window for each bit */
+ for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
+ scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
+
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ /*
+ * Stop searching when the read test doesn't pass AND when
+ * we've seen a passing read on every bit.
+ */
+ if (use_read_test) {
+ stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
+ read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
+ &bit_chk, 0, 0);
+ } else {
+ rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
+ 0, PASS_ONE_BIT,
+ &bit_chk, 0);
+ bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
+ (read_group - (write_group *
+ RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
+ stop = (bit_chk == 0);
+ }
+ sticky_bit_chk = sticky_bit_chk | bit_chk;
+ stop = stop && (sticky_bit_chk == param->read_correct_mask);
+ debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
+ && %u", __func__, __LINE__, d,
+ sticky_bit_chk,
+ param->read_correct_mask, stop);
+
+ if (stop == 1) {
+ break;
+ } else {
+ for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
+ if (bit_chk & 1) {
+ /* Remember a passing test as the
+ left_edge */
+ left_edge[i] = d;
+ } else {
+ /* If a left edge has not been seen yet,
+ then a future passing test will mark
+ this edge as the right edge */
+ if (left_edge[i] ==
+ IO_IO_IN_DELAY_MAX + 1) {
+ right_edge[i] = -(d + 1);
+ }
+ }
+ bit_chk = bit_chk >> 1;
+ }
+ }
+ }
+
+ /* Reset DQ delay chains to 0 */
+ scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, 0);
+ sticky_bit_chk = 0;
+ for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
+ debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
+ %d right_edge[%u]: %d\n", __func__, __LINE__,
+ i, left_edge[i], i, right_edge[i]);
+
+ /*
+ * Check for cases where we haven't found the left edge,
+ * which makes our assignment of the the right edge invalid.
+ * Reset it to the illegal value.
+ */
+ if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
+ right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
+ right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
+ debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
+ right_edge[%u]: %d\n", __func__, __LINE__,
+ i, right_edge[i]);
+ }
+
+ /*
+ * Reset sticky bit (except for bits where we have seen
+ * both the left and right edge).
+ */
+ sticky_bit_chk = sticky_bit_chk << 1;
+ if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
+ (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
+ sticky_bit_chk = sticky_bit_chk | 1;
+ }
+
+ if (i == 0)
+ break;
+ }
+
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ /* Search for the right edge of the window for each bit */
+ for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
+ scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
+ if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
+ uint32_t delay = d + start_dqs_en;
+ if (delay > IO_DQS_EN_DELAY_MAX)
+ delay = IO_DQS_EN_DELAY_MAX;
+ scc_mgr_set_dqs_en_delay(read_group, delay);
+ }
+ scc_mgr_load_dqs(read_group);
+
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ /*
+ * Stop searching when the read test doesn't pass AND when
+ * we've seen a passing read on every bit.
+ */
+ if (use_read_test) {
+ stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
+ read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
+ &bit_chk, 0, 0);
+ } else {
+ rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
+ 0, PASS_ONE_BIT,
+ &bit_chk, 0);
+ bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
+ (read_group - (write_group *
+ RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
+ stop = (bit_chk == 0);
+ }
+ sticky_bit_chk = sticky_bit_chk | bit_chk;
+ stop = stop && (sticky_bit_chk == param->read_correct_mask);
+
+ debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
+ %u && %u", __func__, __LINE__, d,
+ sticky_bit_chk, param->read_correct_mask, stop);
+
+ if (stop == 1) {
+ break;
+ } else {
+ for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
+ if (bit_chk & 1) {
+ /* Remember a passing test as
+ the right_edge */
+ right_edge[i] = d;
+ } else {
+ if (d != 0) {
+ /* If a right edge has not been
+ seen yet, then a future passing
+ test will mark this edge as the
+ left edge */
+ if (right_edge[i] ==
+ IO_IO_IN_DELAY_MAX + 1) {
+ left_edge[i] = -(d + 1);
+ }
+ } else {
+ /* d = 0 failed, but it passed
+ when testing the left edge,
+ so it must be marginal,
+ set it to -1 */
+ if (right_edge[i] ==
+ IO_IO_IN_DELAY_MAX + 1 &&
+ left_edge[i] !=
+ IO_IO_IN_DELAY_MAX
+ + 1) {
+ right_edge[i] = -1;
+ }
+ /* If a right edge has not been
+ seen yet, then a future passing
+ test will mark this edge as the
+ left edge */
+ else if (right_edge[i] ==
+ IO_IO_IN_DELAY_MAX +
+ 1) {
+ left_edge[i] = -(d + 1);
+ }
+ }
+ }
+
+ debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
+ d=%u]: ", __func__, __LINE__, d);
+ debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
+ (int)(bit_chk & 1), i, left_edge[i]);
+ debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
+ right_edge[i]);
+ bit_chk = bit_chk >> 1;
+ }
+ }
+ }
+
+ /* Check that all bits have a window */
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
+ debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
+ %d right_edge[%u]: %d", __func__, __LINE__,
+ i, left_edge[i], i, right_edge[i]);
+ if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
+ == IO_IO_IN_DELAY_MAX + 1)) {
+ /*
+ * Restore delay chain settings before letting the loop
+ * in rw_mgr_mem_calibrate_vfifo to retry different
+ * dqs/ck relationships.
+ */
+ scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
+ if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
+ scc_mgr_set_dqs_en_delay(read_group,
+ start_dqs_en);
+ }
+ scc_mgr_load_dqs(read_group);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
+ find edge [%u]: %d %d", __func__, __LINE__,
+ i, left_edge[i], right_edge[i]);
+ if (use_read_test) {
+ set_failing_group_stage(read_group *
+ RW_MGR_MEM_DQ_PER_READ_DQS + i,
+ CAL_STAGE_VFIFO,
+ CAL_SUBSTAGE_VFIFO_CENTER);
+ } else {
+ set_failing_group_stage(read_group *
+ RW_MGR_MEM_DQ_PER_READ_DQS + i,
+ CAL_STAGE_VFIFO_AFTER_WRITES,
+ CAL_SUBSTAGE_VFIFO_CENTER);
+ }
+ return 0;
+ }
+ }
+
+ /* Find middle of window for each DQ bit */
+ mid_min = left_edge[0] - right_edge[0];
+ min_index = 0;
+ for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
+ mid = left_edge[i] - right_edge[i];
+ if (mid < mid_min) {
+ mid_min = mid;
+ min_index = i;
+ }
+ }
+
+ /*
+ * -mid_min/2 represents the amount that we need to move DQS.
+ * If mid_min is odd and positive we'll need to add one to
+ * make sure the rounding in further calculations is correct
+ * (always bias to the right), so just add 1 for all positive values.
+ */
+ if (mid_min > 0)
+ mid_min++;
+
+ mid_min = mid_min / 2;
+
+ debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
+ __func__, __LINE__, mid_min, min_index);
+
+ /* Determine the amount we can change DQS (which is -mid_min) */
+ orig_mid_min = mid_min;
+ new_dqs = start_dqs - mid_min;
+ if (new_dqs > IO_DQS_IN_DELAY_MAX)
+ new_dqs = IO_DQS_IN_DELAY_MAX;
+ else if (new_dqs < 0)
+ new_dqs = 0;
+
+ mid_min = start_dqs - new_dqs;
+ debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
+ mid_min, new_dqs);
+
+ if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
+ if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
+ mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
+ else if (start_dqs_en - mid_min < 0)
+ mid_min += start_dqs_en - mid_min;
+ }
+ new_dqs = start_dqs - mid_min;
+
+ debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
+ new_dqs=%d mid_min=%d\n", start_dqs,
+ IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
+ new_dqs, mid_min);
+
+ /* Initialize data for export structures */
+ dqs_margin = IO_IO_IN_DELAY_MAX + 1;
+ dq_margin = IO_IO_IN_DELAY_MAX + 1;
+
+ addr = sdr_get_addr((u32 *)SCC_MGR_IO_IN_DELAY);
+ /* add delay to bring centre of all DQ windows to the same "level" */
+ for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
+ /* Use values before divide by 2 to reduce round off error */
+ shift_dq = (left_edge[i] - right_edge[i] -
+ (left_edge[min_index] - right_edge[min_index]))/2 +
+ (orig_mid_min - mid_min);
+
+ debug_cond(DLEVEL == 2, "vfifo_center: before: \
+ shift_dq[%u]=%d\n", i, shift_dq);
+
+ temp_dq_in_delay1 = readl(SOCFPGA_SDR_ADDRESS + addr + (p << 2));
+ temp_dq_in_delay2 = readl(SOCFPGA_SDR_ADDRESS + addr + (i << 2));
+
+ if (shift_dq + (int32_t)temp_dq_in_delay1 >
+ (int32_t)IO_IO_IN_DELAY_MAX) {
+ shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
+ } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
+ shift_dq = -(int32_t)temp_dq_in_delay1;
+ }
+ debug_cond(DLEVEL == 2, "vfifo_center: after: \
+ shift_dq[%u]=%d\n", i, shift_dq);
+ final_dq[i] = temp_dq_in_delay1 + shift_dq;
+ scc_mgr_set_dq_in_delay(write_group, p, final_dq[i]);
+ scc_mgr_load_dq(p);
+
+ debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
+ left_edge[i] - shift_dq + (-mid_min),
+ right_edge[i] + shift_dq - (-mid_min));
+ /* To determine values for export structures */
+ if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
+ dq_margin = left_edge[i] - shift_dq + (-mid_min);
+
+ if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
+ dqs_margin = right_edge[i] + shift_dq - (-mid_min);
+ }
+
+ final_dqs = new_dqs;
+ if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
+ final_dqs_en = start_dqs_en - mid_min;
+
+ /* Move DQS-en */
+ if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
+ scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
+ scc_mgr_load_dqs(read_group);
+ }
+
+ /* Move DQS */
+ scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
+ scc_mgr_load_dqs(read_group);
+ debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
+ dqs_margin=%d", __func__, __LINE__,
+ dq_margin, dqs_margin);
+
+ /*
+ * Do not remove this line as it makes sure all of our decisions
+ * have been applied. Apply the update bit.
+ */
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ return (dq_margin >= 0) && (dqs_margin >= 0);
+}
+
+/*
+ * calibrate the read valid prediction FIFO.
+ *
+ * - read valid prediction will consist of finding a good DQS enable phase,
+ * DQS enable delay, DQS input phase, and DQS input delay.
+ * - we also do a per-bit deskew on the DQ lines.
+ */
+static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
+ uint32_t test_bgn)
+{
+ uint32_t p, d, rank_bgn, sr;
+ uint32_t dtaps_per_ptap;
+ uint32_t tmp_delay;
+ uint32_t bit_chk;
+ uint32_t grp_calibrated;
+ uint32_t write_group, write_test_bgn;
+ uint32_t failed_substage;
+
+ debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
+
+ /* update info for sims */
+ reg_file_set_stage(CAL_STAGE_VFIFO);
+
+ write_group = read_group;
+ write_test_bgn = test_bgn;
+
+ /* USER Determine number of delay taps for each phase tap */
+ dtaps_per_ptap = 0;
+ tmp_delay = 0;
+ while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
+ dtaps_per_ptap++;
+ tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+ }
+ dtaps_per_ptap--;
+ tmp_delay = 0;
+
+ /* update info for sims */
+ reg_file_set_group(read_group);
+
+ grp_calibrated = 0;
+
+ reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
+ failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
+
+ for (d = 0; d <= dtaps_per_ptap && grp_calibrated == 0; d += 2) {
+ /*
+ * In RLDRAMX we may be messing the delay of pins in
+ * the same write group but outside of the current read
+ * the group, but that's ok because we haven't
+ * calibrated output side yet.
+ */
+ if (d > 0) {
+ scc_mgr_apply_group_all_out_delay_add_all_ranks
+ (write_group, write_test_bgn, d);
+ }
+
+ for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0;
+ p++) {
+ /* set a particular dqdqs phase */
+ scc_mgr_set_dqdqs_output_phase_all_ranks(read_group, p);
+
+ debug_cond(DLEVEL == 1, "%s:%d calibrate_vfifo: g=%u \
+ p=%u d=%u\n", __func__, __LINE__,
+ read_group, p, d);
+
+ /*
+ * Load up the patterns used by read calibration
+ * using current DQDQS phase.
+ */
+ rw_mgr_mem_calibrate_read_load_patterns(0, 1);
+ if (!(gbl->phy_debug_mode_flags &
+ PHY_DEBUG_DISABLE_GUARANTEED_READ)) {
+ if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks
+ (read_group, 1, &bit_chk)) {
+ debug_cond(DLEVEL == 1, "%s:%d Guaranteed read test failed:",
+ __func__, __LINE__);
+ debug_cond(DLEVEL == 1, " g=%u p=%u d=%u\n",
+ read_group, p, d);
+ break;
+ }
+ }
+
+/* case:56390 */
+ grp_calibrated = 1;
+ if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
+ (write_group, read_group, test_bgn)) {
+ /*
+ * USER Read per-bit deskew can be done on a
+ * per shadow register basis.
+ */
+ for (rank_bgn = 0, sr = 0;
+ rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
+ rank_bgn += NUM_RANKS_PER_SHADOW_REG,
+ ++sr) {
+ /*
+ * Determine if this set of ranks
+ * should be skipped entirely.
+ */
+ if (!param->skip_shadow_regs[sr]) {
+ /*
+ * If doing read after write
+ * calibration, do not update
+ * FOM, now - do it then.
+ */
+ if (!rw_mgr_mem_calibrate_vfifo_center
+ (rank_bgn, write_group,
+ read_group, test_bgn, 1, 0)) {
+ grp_calibrated = 0;
+ failed_substage =
+ CAL_SUBSTAGE_VFIFO_CENTER;
+ }
+ }
+ }
+ } else {
+ grp_calibrated = 0;
+ failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
+ }
+ }
+ }
+
+ if (grp_calibrated == 0) {
+ set_failing_group_stage(write_group, CAL_STAGE_VFIFO,
+ failed_substage);
+ return 0;
+ }
+
+ /*
+ * Reset the delay chains back to zero if they have moved > 1
+ * (check for > 1 because loop will increase d even when pass in
+ * first case).
+ */
+ if (d > 2)
+ scc_mgr_zero_group(write_group, write_test_bgn, 1);
+
+ return 1;
+}
+
+/* VFIFO Calibration -- Read Deskew Calibration after write deskew */
+static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
+ uint32_t test_bgn)
+{
+ uint32_t rank_bgn, sr;
+ uint32_t grp_calibrated;
+ uint32_t write_group;
+
+ debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
+
+ /* update info for sims */
+
+ reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
+ reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
+
+ write_group = read_group;
+
+ /* update info for sims */
+ reg_file_set_group(read_group);
+
+ grp_calibrated = 1;
+ /* Read per-bit deskew can be done on a per shadow register basis */
+ for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
+ rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
+ /* Determine if this set of ranks should be skipped entirely */
+ if (!param->skip_shadow_regs[sr]) {
+ /* This is the last calibration round, update FOM here */
+ if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
+ write_group,
+ read_group,
+ test_bgn, 0,
+ 1)) {
+ grp_calibrated = 0;
+ }
+ }
+ }
+
+
+ if (grp_calibrated == 0) {
+ set_failing_group_stage(write_group,
+ CAL_STAGE_VFIFO_AFTER_WRITES,
+ CAL_SUBSTAGE_VFIFO_CENTER);
+ return 0;
+ }
+
+ return 1;
+}
+
+/* Calibrate LFIFO to find smallest read latency */
+static uint32_t rw_mgr_mem_calibrate_lfifo(void)
+{
+ uint32_t found_one;
+ uint32_t bit_chk;
+ uint32_t addr;
+
+ debug("%s:%d\n", __func__, __LINE__);
+
+ /* update info for sims */
+ reg_file_set_stage(CAL_STAGE_LFIFO);
+ reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
+
+ /* Load up the patterns used by read calibration for all ranks */
+ rw_mgr_mem_calibrate_read_load_patterns(0, 1);
+ found_one = 0;
+
+ addr = sdr_get_addr(&phy_mgr_cfg->phy_rlat);
+ do {
+ writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr);
+ debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
+ __func__, __LINE__, gbl->curr_read_lat);
+
+ if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
+ NUM_READ_TESTS,
+ PASS_ALL_BITS,
+ &bit_chk, 1)) {
+ break;
+ }
+
+ found_one = 1;
+ /* reduce read latency and see if things are working */
+ /* correctly */
+ gbl->curr_read_lat--;
+ } while (gbl->curr_read_lat > 0);
+
+ /* reset the fifos to get pointers to known state */
+
+ addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ if (found_one) {
+ /* add a fudge factor to the read latency that was determined */
+ gbl->curr_read_lat += 2;
+ addr = sdr_get_addr(&phy_mgr_cfg->phy_rlat);
+ writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr);
+ debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
+ read_lat=%u\n", __func__, __LINE__,
+ gbl->curr_read_lat);
+ return 1;
+ } else {
+ set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
+ CAL_SUBSTAGE_READ_LATENCY);
+
+ debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
+ read_lat=%u\n", __func__, __LINE__,
+ gbl->curr_read_lat);
+ return 0;
+ }
+}
+
+/*
+ * issue write test command.
+ * two variants are provided. one that just tests a write pattern and
+ * another that tests datamask functionality.
+ */
+static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
+ uint32_t test_dm)
+{
+ uint32_t mcc_instruction;
+ uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
+ ENABLE_SUPER_QUICK_CALIBRATION);
+ uint32_t rw_wl_nop_cycles;
+ uint32_t addr;
+
+ /*
+ * Set counter and jump addresses for the right
+ * number of NOP cycles.
+ * The number of supported NOP cycles can range from -1 to infinity
+ * Three different cases are handled:
+ *
+ * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
+ * mechanism will be used to insert the right number of NOPs
+ *
+ * 2. For a number of NOP cycles equals to 0, the micro-instruction
+ * issuing the write command will jump straight to the
+ * micro-instruction that turns on DQS (for DDRx), or outputs write
+ * data (for RLD), skipping
+ * the NOP micro-instruction all together
+ *
+ * 3. A number of NOP cycles equal to -1 indicates that DQS must be
+ * turned on in the same micro-instruction that issues the write
+ * command. Then we need
+ * to directly jump to the micro-instruction that sends out the data
+ *
+ * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
+ * (2 and 3). One jump-counter (0) is used to perform multiple
+ * write-read operations.
+ * one counter left to issue this command in "multiple-group" mode
+ */
+
+ rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
+
+ if (rw_wl_nop_cycles == -1) {
+ /*
+ * CNTR 2 - We want to execute the special write operation that
+ * turns on DQS right away and then skip directly to the
+ * instruction that sends out the data. We set the counter to a
+ * large number so that the jump is always taken.
+ */
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
+ writel(0xFF, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* CNTR 3 - Not used */
+ if (test_dm) {
+ mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
+ SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
+ SOCFPGA_SDR_ADDRESS + addr);
+ } else {
+ mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA, SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP, SOCFPGA_SDR_ADDRESS + addr);
+ }
+ } else if (rw_wl_nop_cycles == 0) {
+ /*
+ * CNTR 2 - We want to skip the NOP operation and go straight
+ * to the DQS enable instruction. We set the counter to a large
+ * number so that the jump is always taken.
+ */
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
+ writel(0xFF, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* CNTR 3 - Not used */
+ if (test_dm) {
+ mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
+ SOCFPGA_SDR_ADDRESS + addr);
+ } else {
+ mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS, SOCFPGA_SDR_ADDRESS + addr);
+ }
+ } else {
+ /*
+ * CNTR 2 - In this case we want to execute the next instruction
+ * and NOT take the jump. So we set the counter to 0. The jump
+ * address doesn't count.
+ */
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
+ writel(0x0, SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ writel(0x0, SOCFPGA_SDR_ADDRESS + addr);
+
+ /*
+ * CNTR 3 - Set the nop counter to the number of cycles we
+ * need to loop for, minus 1.
+ */
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr3);
+ writel(rw_wl_nop_cycles - 1, SOCFPGA_SDR_ADDRESS + addr);
+ if (test_dm) {
+ mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP, SOCFPGA_SDR_ADDRESS + addr);
+ } else {
+ mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP, SOCFPGA_SDR_ADDRESS + addr);
+ }
+ }
+
+ addr = sdr_get_addr((u32 *)RW_MGR_RESET_READ_DATAPATH);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
+ if (quick_write_mode)
+ writel(0x08, SOCFPGA_SDR_ADDRESS + addr);
+ else
+ writel(0x40, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ writel(mcc_instruction, SOCFPGA_SDR_ADDRESS + addr);
+
+ /*
+ * CNTR 1 - This is used to ensure enough time elapses
+ * for read data to come back.
+ */
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
+ writel(0x30, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ if (test_dm) {
+ writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT, SOCFPGA_SDR_ADDRESS + addr);
+ } else {
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT, SOCFPGA_SDR_ADDRESS + addr);
+ }
+
+ addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ writel(mcc_instruction, SOCFPGA_SDR_ADDRESS + addr + (group << 2));
+}
+
+/* Test writes, can check for a single bit pass or multiple bit pass */
+static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
+ uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
+ uint32_t *bit_chk, uint32_t all_ranks)
+{
+ uint32_t addr;
+ uint32_t r;
+ uint32_t correct_mask_vg;
+ uint32_t tmp_bit_chk;
+ uint32_t vg;
+ uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
+ (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
+ uint32_t addr_rw_mgr;
+ uint32_t base_rw_mgr;
+
+ *bit_chk = param->write_correct_mask;
+ correct_mask_vg = param->write_correct_mask_vg;
+
+ for (r = rank_bgn; r < rank_end; r++) {
+ if (param->skip_ranks[r]) {
+ /* request to skip the rank */
+ continue;
+ }
+
+ /* set rank */
+ set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
+
+ tmp_bit_chk = 0;
+ addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
+ addr_rw_mgr = sdr_get_addr((u32 *)BASE_RW_MGR);
+ for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
+ /* reset the fifos to get pointers to known state */
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ tmp_bit_chk = tmp_bit_chk <<
+ (RW_MGR_MEM_DQ_PER_WRITE_DQS /
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
+ rw_mgr_mem_calibrate_write_test_issue(write_group *
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
+ use_dm);
+
+ base_rw_mgr = readl(SOCFPGA_SDR_ADDRESS + addr_rw_mgr);
+ tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
+ if (vg == 0)
+ break;
+ }
+ *bit_chk &= tmp_bit_chk;
+ }
+
+ if (all_correct) {
+ set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
+ debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
+ %u => %lu", write_group, use_dm,
+ *bit_chk, param->write_correct_mask,
+ (long unsigned int)(*bit_chk ==
+ param->write_correct_mask));
+ return *bit_chk == param->write_correct_mask;
+ } else {
+ set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
+ debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
+ write_group, use_dm, *bit_chk);
+ debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
+ (long unsigned int)(*bit_chk != 0));
+ return *bit_chk != 0x00;
+ }
+}
+
+/*
+ * center all windows. do per-bit-deskew to possibly increase size of
+ * certain windows.
+ */
+static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
+ uint32_t write_group, uint32_t test_bgn)
+{
+ uint32_t i, p, min_index;
+ int32_t d;
+ /*
+ * Store these as signed since there are comparisons with
+ * signed numbers.
+ */
+ uint32_t bit_chk;
+ uint32_t sticky_bit_chk;
+ int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
+ int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
+ int32_t mid;
+ int32_t mid_min, orig_mid_min;
+ int32_t new_dqs, start_dqs, shift_dq;
+ int32_t dq_margin, dqs_margin, dm_margin;
+ uint32_t stop;
+ uint32_t temp_dq_out1_delay;
+ uint32_t addr;
+
+ debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
+
+ dm_margin = 0;
+
+ addr = sdr_get_addr((u32 *)SCC_MGR_IO_OUT1_DELAY);
+ start_dqs = readl(SOCFPGA_SDR_ADDRESS + addr +
+ (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
+
+ /* per-bit deskew */
+
+ /*
+ * set the left and right edge of each bit to an illegal value
+ * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
+ */
+ sticky_bit_chk = 0;
+ for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
+ left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
+ right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
+ }
+
+ /* Search for the left edge of the window for each bit */
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
+ scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, d);
+
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ /*
+ * Stop searching when the read test doesn't pass AND when
+ * we've seen a passing read on every bit.
+ */
+ stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
+ 0, PASS_ONE_BIT, &bit_chk, 0);
+ sticky_bit_chk = sticky_bit_chk | bit_chk;
+ stop = stop && (sticky_bit_chk == param->write_correct_mask);
+ debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
+ == %u && %u [bit_chk= %u ]\n",
+ d, sticky_bit_chk, param->write_correct_mask,
+ stop, bit_chk);
+
+ if (stop == 1) {
+ break;
+ } else {
+ for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
+ if (bit_chk & 1) {
+ /*
+ * Remember a passing test as the
+ * left_edge.
+ */
+ left_edge[i] = d;
+ } else {
+ /*
+ * If a left edge has not been seen
+ * yet, then a future passing test will
+ * mark this edge as the right edge.
+ */
+ if (left_edge[i] ==
+ IO_IO_OUT1_DELAY_MAX + 1) {
+ right_edge[i] = -(d + 1);
+ }
+ }
+ debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
+ debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
+ (int)(bit_chk & 1), i, left_edge[i]);
+ debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
+ right_edge[i]);
+ bit_chk = bit_chk >> 1;
+ }
+ }
+ }
+
+ /* Reset DQ delay chains to 0 */
+ scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, 0);
+ sticky_bit_chk = 0;
+ for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
+ debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
+ %d right_edge[%u]: %d\n", __func__, __LINE__,
+ i, left_edge[i], i, right_edge[i]);
+
+ /*
+ * Check for cases where we haven't found the left edge,
+ * which makes our assignment of the the right edge invalid.
+ * Reset it to the illegal value.
+ */
+ if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
+ (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
+ right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
+ debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
+ right_edge[%u]: %d\n", __func__, __LINE__,
+ i, right_edge[i]);
+ }
+
+ /*
+ * Reset sticky bit (except for bits where we have
+ * seen the left edge).
+ */
+ sticky_bit_chk = sticky_bit_chk << 1;
+ if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
+ sticky_bit_chk = sticky_bit_chk | 1;
+
+ if (i == 0)
+ break;
+ }
+
+ /* Search for the right edge of the window for each bit */
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
+ scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
+ d + start_dqs);
+
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ /*
+ * Stop searching when the read test doesn't pass AND when
+ * we've seen a passing read on every bit.
+ */
+ stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
+ 0, PASS_ONE_BIT, &bit_chk, 0);
+
+ sticky_bit_chk = sticky_bit_chk | bit_chk;
+ stop = stop && (sticky_bit_chk == param->write_correct_mask);
+
+ debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
+ %u && %u\n", d, sticky_bit_chk,
+ param->write_correct_mask, stop);
+
+ if (stop == 1) {
+ if (d == 0) {
+ for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
+ i++) {
+ /* d = 0 failed, but it passed when
+ testing the left edge, so it must be
+ marginal, set it to -1 */
+ if (right_edge[i] ==
+ IO_IO_OUT1_DELAY_MAX + 1 &&
+ left_edge[i] !=
+ IO_IO_OUT1_DELAY_MAX + 1) {
+ right_edge[i] = -1;
+ }
+ }
+ }
+ break;
+ } else {
+ for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
+ if (bit_chk & 1) {
+ /*
+ * Remember a passing test as
+ * the right_edge.
+ */
+ right_edge[i] = d;
+ } else {
+ if (d != 0) {
+ /*
+ * If a right edge has not
+ * been seen yet, then a future
+ * passing test will mark this
+ * edge as the left edge.
+ */
+ if (right_edge[i] ==
+ IO_IO_OUT1_DELAY_MAX + 1)
+ left_edge[i] = -(d + 1);
+ } else {
+ /*
+ * d = 0 failed, but it passed
+ * when testing the left edge,
+ * so it must be marginal, set
+ * it to -1.
+ */
+ if (right_edge[i] ==
+ IO_IO_OUT1_DELAY_MAX + 1 &&
+ left_edge[i] !=
+ IO_IO_OUT1_DELAY_MAX + 1)
+ right_edge[i] = -1;
+ /*
+ * If a right edge has not been
+ * seen yet, then a future
+ * passing test will mark this
+ * edge as the left edge.
+ */
+ else if (right_edge[i] ==
+ IO_IO_OUT1_DELAY_MAX +
+ 1)
+ left_edge[i] = -(d + 1);
+ }
+ }
+ debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
+ debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
+ (int)(bit_chk & 1), i, left_edge[i]);
+ debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
+ right_edge[i]);
+ bit_chk = bit_chk >> 1;
+ }
+ }
+ }
+
+ /* Check that all bits have a window */
+ for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
+ debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
+ %d right_edge[%u]: %d", __func__, __LINE__,
+ i, left_edge[i], i, right_edge[i]);
+ if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
+ (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
+ set_failing_group_stage(test_bgn + i,
+ CAL_STAGE_WRITES,
+ CAL_SUBSTAGE_WRITES_CENTER);
+ return 0;
+ }
+ }
+
+ /* Find middle of window for each DQ bit */
+ mid_min = left_edge[0] - right_edge[0];
+ min_index = 0;
+ for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
+ mid = left_edge[i] - right_edge[i];
+ if (mid < mid_min) {
+ mid_min = mid;
+ min_index = i;
+ }
+ }
+
+ /*
+ * -mid_min/2 represents the amount that we need to move DQS.
+ * If mid_min is odd and positive we'll need to add one to
+ * make sure the rounding in further calculations is correct
+ * (always bias to the right), so just add 1 for all positive values.
+ */
+ if (mid_min > 0)
+ mid_min++;
+ mid_min = mid_min / 2;
+ debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
+ __LINE__, mid_min);
+
+ /* Determine the amount we can change DQS (which is -mid_min) */
+ orig_mid_min = mid_min;
+ new_dqs = start_dqs;
+ mid_min = 0;
+ debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
+ mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
+ /* Initialize data for export structures */
+ dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
+ dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
+
+ /* add delay to bring centre of all DQ windows to the same "level" */
+ addr = sdr_get_addr((u32 *)SCC_MGR_IO_OUT1_DELAY);
+ for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
+ /* Use values before divide by 2 to reduce round off error */
+ shift_dq = (left_edge[i] - right_edge[i] -
+ (left_edge[min_index] - right_edge[min_index]))/2 +
+ (orig_mid_min - mid_min);
+
+ debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
+ [%u]=%d\n", __func__, __LINE__, i, shift_dq);
+
+ temp_dq_out1_delay = readl(SOCFPGA_SDR_ADDRESS + addr + (i << 2));
+ if (shift_dq + (int32_t)temp_dq_out1_delay >
+ (int32_t)IO_IO_OUT1_DELAY_MAX) {
+ shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
+ } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
+ shift_dq = -(int32_t)temp_dq_out1_delay;
+ }
+ debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
+ i, shift_dq);
+ scc_mgr_set_dq_out1_delay(write_group, i, temp_dq_out1_delay +
+ shift_dq);
+ scc_mgr_load_dq(i);
+
+ debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
+ left_edge[i] - shift_dq + (-mid_min),
+ right_edge[i] + shift_dq - (-mid_min));
+ /* To determine values for export structures */
+ if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
+ dq_margin = left_edge[i] - shift_dq + (-mid_min);
+
+ if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
+ dqs_margin = right_edge[i] + shift_dq - (-mid_min);
+ }
+
+ /* Move DQS */
+ scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* Centre DM */
+ debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
+
+ /*
+ * set the left and right edge of each bit to an illegal value,
+ * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
+ */
+ left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
+ right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
+ int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
+ int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
+ int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
+ int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
+ int32_t win_best = 0;
+
+ /* Search for the/part of the window with DM shift */
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
+ scc_mgr_apply_group_dm_out1_delay(write_group, d);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
+ PASS_ALL_BITS, &bit_chk,
+ 0)) {
+ /* USE Set current end of the window */
+ end_curr = -d;
+ /*
+ * If a starting edge of our window has not been seen
+ * this is our current start of the DM window.
+ */
+ if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
+ bgn_curr = -d;
+
+ /*
+ * If current window is bigger than best seen.
+ * Set best seen to be current window.
+ */
+ if ((end_curr-bgn_curr+1) > win_best) {
+ win_best = end_curr-bgn_curr+1;
+ bgn_best = bgn_curr;
+ end_best = end_curr;
+ }
+ } else {
+ /* We just saw a failing test. Reset temp edge */
+ bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
+ end_curr = IO_IO_OUT1_DELAY_MAX + 1;
+ }
+ }
+
+
+ /* Reset DM delay chains to 0 */
+ scc_mgr_apply_group_dm_out1_delay(write_group, 0);
+
+ /*
+ * Check to see if the current window nudges up aganist 0 delay.
+ * If so we need to continue the search by shifting DQS otherwise DQS
+ * search begins as a new search. */
+ if (end_curr != 0) {
+ bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
+ end_curr = IO_IO_OUT1_DELAY_MAX + 1;
+ }
+
+ /* Search for the/part of the window with DQS shifts */
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
+ /*
+ * Note: This only shifts DQS, so are we limiting ourselve to
+ * width of DQ unnecessarily.
+ */
+ scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
+ d + new_dqs);
+
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
+ PASS_ALL_BITS, &bit_chk,
+ 0)) {
+ /* USE Set current end of the window */
+ end_curr = d;
+ /*
+ * If a beginning edge of our window has not been seen
+ * this is our current begin of the DM window.
+ */
+ if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
+ bgn_curr = d;
+
+ /*
+ * If current window is bigger than best seen. Set best
+ * seen to be current window.
+ */
+ if ((end_curr-bgn_curr+1) > win_best) {
+ win_best = end_curr-bgn_curr+1;
+ bgn_best = bgn_curr;
+ end_best = end_curr;
+ }
+ } else {
+ /* We just saw a failing test. Reset temp edge */
+ bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
+ end_curr = IO_IO_OUT1_DELAY_MAX + 1;
+
+ /* Early exit optimization: if ther remaining delay
+ chain space is less than already seen largest window
+ we can exit */
+ if ((win_best-1) >
+ (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
+ break;
+ }
+ }
+ }
+
+ /* assign left and right edge for cal and reporting; */
+ left_edge[0] = -1*bgn_best;
+ right_edge[0] = end_best;
+
+ debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
+ __LINE__, left_edge[0], right_edge[0]);
+
+ /* Move DQS (back to orig) */
+ scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
+
+ /* Move DM */
+
+ /* Find middle of window for the DM bit */
+ mid = (left_edge[0] - right_edge[0]) / 2;
+
+ /* only move right, since we are not moving DQS/DQ */
+ if (mid < 0)
+ mid = 0;
+
+ /* dm_marign should fail if we never find a window */
+ if (win_best == 0)
+ dm_margin = -1;
+ else
+ dm_margin = left_edge[0] - mid;
+
+ scc_mgr_apply_group_dm_out1_delay(write_group, mid);
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
+ dm_margin=%d\n", __func__, __LINE__, left_edge[0],
+ right_edge[0], mid, dm_margin);
+ /* Export values */
+ gbl->fom_out += dq_margin + dqs_margin;
+
+ debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
+ dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
+ dq_margin, dqs_margin, dm_margin);
+
+ /*
+ * Do not remove this line as it makes sure all of our
+ * decisions have been applied.
+ */
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
+}
+
+/* calibrate the write operations */
+static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
+ uint32_t test_bgn)
+{
+ /* update info for sims */
+ debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
+
+ reg_file_set_stage(CAL_STAGE_WRITES);
+ reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
+
+ reg_file_set_group(g);
+
+ if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
+ set_failing_group_stage(g, CAL_STAGE_WRITES,
+ CAL_SUBSTAGE_WRITES_CENTER);
+ return 0;
+ }
+
+ return 1;
+}
+
+/* precharge all banks and activate row 0 in bank "000..." and bank "111..." */
+static void mem_precharge_and_activate(void)
+{
+ uint32_t r;
+ uint32_t addr;
+
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
+ if (param->skip_ranks[r]) {
+ /* request to skip the rank */
+ continue;
+ }
+
+ /* set rank */
+ set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
+
+ /* precharge all banks ... */
+ addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ writel(RW_MGR_PRECHARGE_ALL, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
+ writel(0x0F, SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
+ writel(0x0F, SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* activate rows */
+ addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ writel(RW_MGR_ACTIVATE_0_AND_1, SOCFPGA_SDR_ADDRESS + addr);
+ }
+}
+
+/* Configure various memory related parameters. */
+static void mem_config(void)
+{
+ uint32_t rlat, wlat;
+ uint32_t rw_wl_nop_cycles;
+ uint32_t max_latency;
+ uint32_t addr;
+
+ debug("%s:%d\n", __func__, __LINE__);
+ /* read in write and read latency */
+ addr = sdr_get_addr(&data_mgr->t_wl_add);
+ wlat = readl(SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&data_mgr->mem_t_add);
+ wlat += readl(SOCFPGA_SDR_ADDRESS + addr);
+ /* WL for hard phy does not include additive latency */
+
+ /*
+ * add addtional write latency to offset the address/command extra
+ * clock cycle. We change the AC mux setting causing AC to be delayed
+ * by one mem clock cycle. Only do this for DDR3
+ */
+ wlat = wlat + 1;
+
+ addr = sdr_get_addr(&data_mgr->t_rl_add);
+ rlat = readl(SOCFPGA_SDR_ADDRESS + addr);
+
+ rw_wl_nop_cycles = wlat - 2;
+ gbl->rw_wl_nop_cycles = rw_wl_nop_cycles;
+
+ /*
+ * For AV/CV, lfifo is hardened and always runs at full rate so
+ * max latency in AFI clocks, used here, is correspondingly smaller.
+ */
+ max_latency = (1<<MAX_LATENCY_COUNT_WIDTH)/1 - 1;
+ /* configure for a burst length of 8 */
+
+ /* write latency */
+ /* Adjust Write Latency for Hard PHY */
+ wlat = wlat + 1;
+
+ /* set a pretty high read latency initially */
+ gbl->curr_read_lat = rlat + 16;
+
+ if (gbl->curr_read_lat > max_latency)
+ gbl->curr_read_lat = max_latency;
+
+ addr = sdr_get_addr(&phy_mgr_cfg->phy_rlat);
+ writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* advertise write latency */
+ gbl->curr_write_lat = wlat;
+ addr = sdr_get_addr(&phy_mgr_cfg->afi_wlat);
+ writel(wlat - 2, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* initialize bit slips */
+ mem_precharge_and_activate();
+}
+
+/* Set VFIFO and LFIFO to instant-on settings in skip calibration mode */
+static void mem_skip_calibrate(void)
+{
+ uint32_t vfifo_offset;
+ uint32_t i, j, r;
+ uint32_t addr;
+
+ debug("%s:%d\n", __func__, __LINE__);
+ /* Need to update every shadow register set used by the interface */
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ r += NUM_RANKS_PER_SHADOW_REG) {
+ /*
+ * Set output phase alignment settings appropriate for
+ * skip calibration.
+ */
+ for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
+ scc_mgr_set_dqs_en_phase(i, 0);
+#if IO_DLL_CHAIN_LENGTH == 6
+ scc_mgr_set_dqdqs_output_phase(i, 6);
+#else
+ scc_mgr_set_dqdqs_output_phase(i, 7);
+#endif
+ /*
+ * Case:33398
+ *
+ * Write data arrives to the I/O two cycles before write
+ * latency is reached (720 deg).
+ * -> due to bit-slip in a/c bus
+ * -> to allow board skew where dqs is longer than ck
+ * -> how often can this happen!?
+ * -> can claim back some ptaps for high freq
+ * support if we can relax this, but i digress...
+ *
+ * The write_clk leads mem_ck by 90 deg
+ * The minimum ptap of the OPA is 180 deg
+ * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
+ * The write_clk is always delayed by 2 ptaps
+ *
+ * Hence, to make DQS aligned to CK, we need to delay
+ * DQS by:
+ * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
+ *
+ * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
+ * gives us the number of ptaps, which simplies to:
+ *
+ * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
+ */
+ scc_mgr_set_dqdqs_output_phase(i, (1.25 *
+ IO_DLL_CHAIN_LENGTH - 2));
+ }
+ addr = sdr_get_addr(&sdr_scc_mgr->dqs_ena);
+ writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&sdr_scc_mgr->dqs_io_ena);
+ writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr((u32 *)SCC_MGR_GROUP_COUNTER);
+ for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
+ writel(i, SOCFPGA_SDR_ADDRESS + addr);
+ }
+ addr = sdr_get_addr(&sdr_scc_mgr->dq_ena);
+ writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&sdr_scc_mgr->dm_ena);
+ writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ }
+
+ /* Compensate for simulation model behaviour */
+ for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
+ scc_mgr_set_dqs_bus_in_delay(i, 10);
+ scc_mgr_load_dqs(i);
+ }
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ /*
+ * ArriaV has hard FIFOs that can only be initialized by incrementing
+ * in sequencer.
+ */
+ vfifo_offset = CALIB_VFIFO_OFFSET;
+ addr = sdr_get_addr(&phy_mgr_cmd->inc_vfifo_hard_phy);
+ for (j = 0; j < vfifo_offset; j++) {
+ writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ }
+ addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ /*
+ * For ACV with hard lfifo, we get the skip-cal setting from
+ * generation-time constant.
+ */
+ gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
+ addr = sdr_get_addr(&phy_mgr_cfg->phy_rlat);
+ writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr);
+}
+
+/* Memory calibration entry point */
+static uint32_t mem_calibrate(void)
+{
+ uint32_t i;
+ uint32_t rank_bgn, sr;
+ uint32_t write_group, write_test_bgn;
+ uint32_t read_group, read_test_bgn;
+ uint32_t run_groups, current_run;
+ uint32_t failing_groups = 0;
+ uint32_t group_failed = 0;
+ uint32_t sr_failed = 0;
+ uint32_t addr;
+
+ debug("%s:%d\n", __func__, __LINE__);
+ /* Initialize the data settings */
+
+ gbl->error_substage = CAL_SUBSTAGE_NIL;
+ gbl->error_stage = CAL_STAGE_NIL;
+ gbl->error_group = 0xff;
+ gbl->fom_in = 0;
+ gbl->fom_out = 0;
+
+ mem_config();
+
+ uint32_t bypass_mode = 0x1;
+ addr = sdr_get_addr((u32 *)SCC_MGR_GROUP_COUNTER);
+ for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
+ writel(i, SOCFPGA_SDR_ADDRESS + addr);
+ scc_set_bypass_mode(i, bypass_mode);
+ }
+
+ if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
+ /*
+ * Set VFIFO and LFIFO to instant-on settings in skip
+ * calibration mode.
+ */
+ mem_skip_calibrate();
+ } else {
+ for (i = 0; i < NUM_CALIB_REPEAT; i++) {
+ /*
+ * Zero all delay chain/phase settings for all
+ * groups and all shadow register sets.
+ */
+ scc_mgr_zero_all();
+
+ run_groups = ~param->skip_groups;
+
+ for (write_group = 0, write_test_bgn = 0; write_group
+ < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
+ write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
+ /* Initialized the group failure */
+ group_failed = 0;
+
+ current_run = run_groups & ((1 <<
+ RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
+ run_groups = run_groups >>
+ RW_MGR_NUM_DQS_PER_WRITE_GROUP;
+
+ if (current_run == 0)
+ continue;
+
+ addr = sdr_get_addr((u32 *)SCC_MGR_GROUP_COUNTER);
+ writel(write_group, SOCFPGA_SDR_ADDRESS + addr);
+ scc_mgr_zero_group(write_group, write_test_bgn,
+ 0);
+
+ for (read_group = write_group *
+ RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
+ read_test_bgn = 0;
+ read_group < (write_group + 1) *
+ RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
+ group_failed == 0;
+ read_group++, read_test_bgn +=
+ RW_MGR_MEM_DQ_PER_READ_DQS) {
+ /* Calibrate the VFIFO */
+ if (!((STATIC_CALIB_STEPS) &
+ CALIB_SKIP_VFIFO)) {
+ if (!rw_mgr_mem_calibrate_vfifo
+ (read_group,
+ read_test_bgn)) {
+ group_failed = 1;
+
+ if (!(gbl->
+ phy_debug_mode_flags &
+ PHY_DEBUG_SWEEP_ALL_GROUPS)) {
+ return 0;
+ }
+ }
+ }
+ }
+
+ /* Calibrate the output side */
+ if (group_failed == 0) {
+ for (rank_bgn = 0, sr = 0; rank_bgn
+ < RW_MGR_MEM_NUMBER_OF_RANKS;
+ rank_bgn +=
+ NUM_RANKS_PER_SHADOW_REG,
+ ++sr) {
+ sr_failed = 0;
+ if (!((STATIC_CALIB_STEPS) &
+ CALIB_SKIP_WRITES)) {
+ if ((STATIC_CALIB_STEPS)
+ & CALIB_SKIP_DELAY_SWEEPS) {
+ /* not needed in quick mode! */
+ } else {
+ /*
+ * Determine if this set of
+ * ranks should be skipped
+ * entirely.
+ */
+ if (!param->skip_shadow_regs[sr]) {
+ if (!rw_mgr_mem_calibrate_writes
+ (rank_bgn, write_group,
+ write_test_bgn)) {
+ sr_failed = 1;
+ if (!(gbl->
+ phy_debug_mode_flags &
+ PHY_DEBUG_SWEEP_ALL_GROUPS)) {
+ return 0;
+ }
+ }
+ }
+ }
+ }
+ if (sr_failed != 0)
+ group_failed = 1;
+ }
+ }
+
+ if (group_failed == 0) {
+ for (read_group = write_group *
+ RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
+ read_test_bgn = 0;
+ read_group < (write_group + 1)
+ * RW_MGR_MEM_IF_READ_DQS_WIDTH
+ / RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
+ group_failed == 0;
+ read_group++, read_test_bgn +=
+ RW_MGR_MEM_DQ_PER_READ_DQS) {
+ if (!((STATIC_CALIB_STEPS) &
+ CALIB_SKIP_WRITES)) {
+ if (!rw_mgr_mem_calibrate_vfifo_end
+ (read_group, read_test_bgn)) {
+ group_failed = 1;
+
+ if (!(gbl->phy_debug_mode_flags
+ & PHY_DEBUG_SWEEP_ALL_GROUPS)) {
+ return 0;
+ }
+ }
+ }
+ }
+ }
+
+ if (group_failed != 0)
+ failing_groups++;
+ }
+
+ /*
+ * USER If there are any failing groups then report
+ * the failure.
+ */
+ if (failing_groups != 0)
+ return 0;
+
+ /* Calibrate the LFIFO */
+ if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_LFIFO)) {
+ /*
+ * If we're skipping groups as part of debug,
+ * don't calibrate LFIFO.
+ */
+ if (param->skip_groups == 0) {
+ if (!rw_mgr_mem_calibrate_lfifo())
+ return 0;
+ }
+ }
+ }
+ }
+
+ /*
+ * Do not remove this line as it makes sure all of our decisions
+ * have been applied.
+ */
+ addr = sdr_get_addr(&sdr_scc_mgr->update);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ return 1;
+}
+
+static uint32_t run_mem_calibrate(void)
+{
+ uint32_t pass;
+ uint32_t debug_info;
+ uint32_t addr;
+
+ debug("%s:%d\n", __func__, __LINE__);
+
+ /* Reset pass/fail status shown on afi_cal_success/fail */
+ addr = sdr_get_addr(&phy_mgr_cfg->cal_status);
+ writel(PHY_MGR_CAL_RESET, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr((u32 *)BASE_MMR);
+ /* stop tracking manger */
+ uint32_t ctrlcfg = readl(SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr((u32 *)BASE_MMR);
+ writel(ctrlcfg & 0xFFBFFFFF, SOCFPGA_SDR_ADDRESS + addr);
+
+ initialize();
+ rw_mgr_mem_initialize();
+
+ pass = mem_calibrate();
+
+ mem_precharge_and_activate();
+ addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ /*
+ * Handoff:
+ * Don't return control of the PHY back to AFI when in debug mode.
+ */
+ if ((gbl->phy_debug_mode_flags & PHY_DEBUG_IN_DEBUG_MODE) == 0) {
+ rw_mgr_mem_handoff();
+ /*
+ * In Hard PHY this is a 2-bit control:
+ * 0: AFI Mux Select
+ * 1: DDIO Mux Select
+ */
+ addr = sdr_get_addr(&phy_mgr_cfg->mux_sel);
+ writel(0x2, SOCFPGA_SDR_ADDRESS + addr);
+ }
+
+ addr = sdr_get_addr((u32 *)BASE_MMR);
+ writel(ctrlcfg, SOCFPGA_SDR_ADDRESS + addr);
+
+ if (pass) {
+ printf("%s: CALIBRATION PASSED\n", __FILE__);
+
+ gbl->fom_in /= 2;
+ gbl->fom_out /= 2;
+
+ if (gbl->fom_in > 0xff)
+ gbl->fom_in = 0xff;
+
+ if (gbl->fom_out > 0xff)
+ gbl->fom_out = 0xff;
+
+ /* Update the FOM in the register file */
+ debug_info = gbl->fom_in;
+ debug_info |= gbl->fom_out << 8;
+ addr = sdr_get_addr(&sdr_reg_file->fom);
+ writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&phy_mgr_cfg->cal_debug_info);
+ writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&phy_mgr_cfg->cal_status);
+ writel(PHY_MGR_CAL_SUCCESS, SOCFPGA_SDR_ADDRESS + addr);
+ } else {
+ printf("%s: CALIBRATION FAILED\n", __FILE__);
+
+ debug_info = gbl->error_stage;
+ debug_info |= gbl->error_substage << 8;
+ debug_info |= gbl->error_group << 16;
+
+ addr = sdr_get_addr(&sdr_reg_file->failing_stage);
+ writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&phy_mgr_cfg->cal_debug_info);
+ writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
+ addr = sdr_get_addr(&phy_mgr_cfg->cal_status);
+ writel(PHY_MGR_CAL_FAIL, SOCFPGA_SDR_ADDRESS + addr);
+
+ /* Update the failing group/stage in the register file */
+ debug_info = gbl->error_stage;
+ debug_info |= gbl->error_substage << 8;
+ debug_info |= gbl->error_group << 16;
+ addr = sdr_get_addr(&sdr_reg_file->failing_stage);
+ writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
+ }
+
+ return pass;
+}
+
+static void hc_initialize_rom_data(void)
+{
+ uint32_t i;
+ uint32_t addr;
+
+ addr = sdr_get_addr((u32 *)(RW_MGR_INST_ROM_WRITE));
+ for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++) {
+ uint32_t data = inst_rom_init[i];
+ writel(data, SOCFPGA_SDR_ADDRESS + addr + (i << 2));
+ }
+
+ addr = sdr_get_addr((u32 *)(RW_MGR_AC_ROM_WRITE));
+ for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++) {
+ uint32_t data = ac_rom_init[i];
+ writel(data, SOCFPGA_SDR_ADDRESS + addr + (i << 2));
+ }
+}
+
+static void initialize_reg_file(void)
+{
+ uint32_t addr;
+
+ /* Initialize the register file with the correct data */
+ addr = sdr_get_addr(&sdr_reg_file->signature);
+ writel(REG_FILE_INIT_SEQ_SIGNATURE, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_reg_file->debug_data_addr);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_reg_file->cur_stage);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_reg_file->fom);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_reg_file->failing_stage);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_reg_file->debug1);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_reg_file->debug2);
+ writel(0, SOCFPGA_SDR_ADDRESS + addr);
+}
+
+static void initialize_hps_phy(void)
+{
+ uint32_t reg;
+ uint32_t addr;
+ /*
+ * Tracking also gets configured here because it's in the
+ * same register.
+ */
+ uint32_t trk_sample_count = 7500;
+ uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
+ /*
+ * Format is number of outer loops in the 16 MSB, sample
+ * count in 16 LSB.
+ */
+
+ reg = 0;
+ reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
+ reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
+ reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
+ reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
+ reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
+ reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
+ /*
+ * This field selects the intrinsic latency to RDATA_EN/FULL path.
+ * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
+ */
+ reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
+ reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
+ trk_sample_count);
+ addr = sdr_get_addr((u32 *)BASE_MMR);
+ writel(reg, SOCFPGA_SDR_ADDRESS + addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET);
+
+ reg = 0;
+ reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
+ trk_sample_count >>
+ SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
+ reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
+ trk_long_idle_sample_count);
+ writel(reg, SOCFPGA_SDR_ADDRESS + addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET);
+
+ reg = 0;
+ reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
+ trk_long_idle_sample_count >>
+ SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
+ writel(reg, SOCFPGA_SDR_ADDRESS + addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET);
+}
+
+static void initialize_tracking(void)
+{
+ uint32_t concatenated_longidle = 0x0;
+ uint32_t concatenated_delays = 0x0;
+ uint32_t concatenated_rw_addr = 0x0;
+ uint32_t concatenated_refresh = 0x0;
+ uint32_t trk_sample_count = 7500;
+ uint32_t dtaps_per_ptap;
+ uint32_t tmp_delay;
+ uint32_t addr;
+
+ /*
+ * compute usable version of value in case we skip full
+ * computation later
+ */
+ dtaps_per_ptap = 0;
+ tmp_delay = 0;
+ while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
+ dtaps_per_ptap++;
+ tmp_delay += IO_DELAY_PER_DCHAIN_TAP;
+ }
+ dtaps_per_ptap--;
+
+ concatenated_longidle = concatenated_longidle ^ 10;
+ /*longidle outer loop */
+ concatenated_longidle = concatenated_longidle << 16;
+ concatenated_longidle = concatenated_longidle ^ 100;
+ /*longidle sample count */
+ concatenated_delays = concatenated_delays ^ 243;
+ /* trfc, worst case of 933Mhz 4Gb */
+ concatenated_delays = concatenated_delays << 8;
+ concatenated_delays = concatenated_delays ^ 14;
+ /* trcd, worst case */
+ concatenated_delays = concatenated_delays << 8;
+ concatenated_delays = concatenated_delays ^ 10;
+ /* vfifo wait */
+ concatenated_delays = concatenated_delays << 8;
+ concatenated_delays = concatenated_delays ^ 4;
+ /* mux delay */
+
+ concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_IDLE;
+ concatenated_rw_addr = concatenated_rw_addr << 8;
+ concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_ACTIVATE_1;
+ concatenated_rw_addr = concatenated_rw_addr << 8;
+ concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_SGLE_READ;
+ concatenated_rw_addr = concatenated_rw_addr << 8;
+ concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_PRECHARGE_ALL;
+
+ concatenated_refresh = concatenated_refresh ^ RW_MGR_REFRESH_ALL;
+ concatenated_refresh = concatenated_refresh << 24;
+ concatenated_refresh = concatenated_refresh ^ 1000; /* trefi */
+
+ /* Initialize the register file with the correct data */
+ addr = sdr_get_addr(&sdr_reg_file->dtaps_per_ptap);
+ writel(dtaps_per_ptap, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_reg_file->trk_sample_count);
+ writel(trk_sample_count, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_reg_file->trk_longidle);
+ writel(concatenated_longidle, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_reg_file->delays);
+ writel(concatenated_delays, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_reg_file->trk_rw_mgr_addr);
+ writel(concatenated_rw_addr, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_reg_file->trk_read_dqs_width);
+ writel(RW_MGR_MEM_IF_READ_DQS_WIDTH, SOCFPGA_SDR_ADDRESS + addr);
+
+ addr = sdr_get_addr(&sdr_reg_file->trk_rfsh);
+ writel(concatenated_refresh, SOCFPGA_SDR_ADDRESS + addr);
+}
+
+int sdram_calibration_full(void)
+{
+ struct param_type my_param;
+ struct gbl_type my_gbl;
+ uint32_t pass;
+ uint32_t i;
+
+ param = &my_param;
+ gbl = &my_gbl;
+
+ /* Initialize the debug mode flags */
+ gbl->phy_debug_mode_flags = 0;
+ /* Set the calibration enabled by default */
+ gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
+ /*
+ * Only sweep all groups (regardless of fail state) by default
+ * Set enabled read test by default.
+ */
+#if DISABLE_GUARANTEED_READ
+ gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
+#endif
+ /* Initialize the register file */
+ initialize_reg_file();
+
+ /* Initialize any PHY CSR */
+ initialize_hps_phy();
+
+ scc_mgr_initialize();
+
+ initialize_tracking();
+
+ /* USER Enable all ranks, groups */
+ for (i = 0; i < RW_MGR_MEM_NUMBER_OF_RANKS; i++)
+ param->skip_ranks[i] = 0;
+ for (i = 0; i < NUM_SHADOW_REGS; ++i)
+ param->skip_shadow_regs[i] = 0;
+ param->skip_groups = 0;
+
+ printf("%s: Preparing to start memory calibration\n", __FILE__);
+
+ debug("%s:%d\n", __func__, __LINE__);
+ debug_cond(DLEVEL == 1, "DDR3 FULL_RATE ranks=%lu cs/dimm=%lu dq/dqs=%lu,%lu vg/dqs=%lu,%lu",
+ (long unsigned int)RW_MGR_MEM_NUMBER_OF_RANKS,
+ (long unsigned int)RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
+ (long unsigned int)RW_MGR_MEM_DQ_PER_READ_DQS,
+ (long unsigned int)RW_MGR_MEM_DQ_PER_WRITE_DQS,
+ (long unsigned int)RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
+ (long unsigned int)RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
+ debug_cond(DLEVEL == 1, "dqs=%lu,%lu dq=%lu dm=%lu ptap_delay=%lu dtap_delay=%lu",
+ (long unsigned int)RW_MGR_MEM_IF_READ_DQS_WIDTH,
+ (long unsigned int)RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
+ (long unsigned int)RW_MGR_MEM_DATA_WIDTH,
+ (long unsigned int)RW_MGR_MEM_DATA_MASK_WIDTH,
+ (long unsigned int)IO_DELAY_PER_OPA_TAP,
+ (long unsigned int)IO_DELAY_PER_DCHAIN_TAP);
+ debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%lu, dll=%lu",
+ (long unsigned int)IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
+ (long unsigned int)IO_DLL_CHAIN_LENGTH);
+ debug_cond(DLEVEL == 1, "max values: en_p=%lu dqdqs_p=%lu en_d=%lu dqs_in_d=%lu",
+ (long unsigned int)IO_DQS_EN_PHASE_MAX,
+ (long unsigned int)IO_DQDQS_OUT_PHASE_MAX,
+ (long unsigned int)IO_DQS_EN_DELAY_MAX,
+ (long unsigned int)IO_DQS_IN_DELAY_MAX);
+ debug_cond(DLEVEL == 1, "io_in_d=%lu io_out1_d=%lu io_out2_d=%lu",
+ (long unsigned int)IO_IO_IN_DELAY_MAX,
+ (long unsigned int)IO_IO_OUT1_DELAY_MAX,
+ (long unsigned int)IO_IO_OUT2_DELAY_MAX);
+ debug_cond(DLEVEL == 1, "dqs_in_reserve=%lu dqs_out_reserve=%lu",
+ (long unsigned int)IO_DQS_IN_RESERVE,
+ (long unsigned int)IO_DQS_OUT_RESERVE);
+
+ hc_initialize_rom_data();
+
+ /* update info for sims */
+ reg_file_set_stage(CAL_STAGE_NIL);
+ reg_file_set_group(0);
+
+ /*
+ * Load global needed for those actions that require
+ * some dynamic calibration support.
+ */
+ dyn_calib_steps = STATIC_CALIB_STEPS;
+ /*
+ * Load global to allow dynamic selection of delay loop settings
+ * based on calibration mode.
+ */
+ if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
+ skip_delay_mask = 0xff;
+ else
+ skip_delay_mask = 0x0;
+
+ pass = run_mem_calibrate();
+
+ printf("%s: Calibration complete\n", __FILE__);
+ return pass;
+}
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
new file mode 100644
index 0000000..ed2bae2
--- /dev/null
+++ b/drivers/ddr/altera/sequencer.h
@@ -0,0 +1,322 @@
+/*
+ * Copyright Altera Corporation (C) 2012-2015
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _SEQUENCER_H_
+#define _SEQUENCER_H_
+
+#define RW_MGR_NUM_DM_PER_WRITE_GROUP (RW_MGR_MEM_DATA_MASK_WIDTH \
+ / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
+#define RW_MGR_NUM_TRUE_DM_PER_WRITE_GROUP (RW_MGR_TRUE_MEM_DATA_MASK_WIDTH \
+ / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
+
+#define RW_MGR_NUM_DQS_PER_WRITE_GROUP (RW_MGR_MEM_IF_READ_DQS_WIDTH \
+ / RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
+#define NUM_RANKS_PER_SHADOW_REG (RW_MGR_MEM_NUMBER_OF_RANKS / NUM_SHADOW_REGS)
+
+#define RW_MGR_RUN_SINGLE_GROUP (BASE_RW_MGR)
+#define RW_MGR_RUN_ALL_GROUPS (BASE_RW_MGR + 0x0400)
+
+#define RW_MGR_DI_BASE (BASE_RW_MGR + 0x0020)
+
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
+#define NUM_SHADOW_REGS 1
+
+#define RW_MGR_RESET_READ_DATAPATH (BASE_RW_MGR + 0x1000)
+#define RW_MGR_SET_CS_AND_ODT_MASK (BASE_RW_MGR + 0x1400)
+
+#define RW_MGR_RANK_NONE 0xFF
+#define RW_MGR_RANK_ALL 0x00
+
+#define RW_MGR_ODT_MODE_OFF 0
+#define RW_MGR_ODT_MODE_READ_WRITE 1
+
+#define NUM_CALIB_REPEAT 1
+
+#define NUM_READ_TESTS 7
+#define NUM_READ_PB_TESTS 7
+#define NUM_WRITE_TESTS 15
+#define NUM_WRITE_PB_TESTS 31
+
+#define PASS_ALL_BITS 1
+#define PASS_ONE_BIT 0
+
+/* calibration stages */
+#define CAL_STAGE_NIL 0
+#define CAL_STAGE_VFIFO 1
+#define CAL_STAGE_WLEVEL 2
+#define CAL_STAGE_LFIFO 3
+#define CAL_STAGE_WRITES 4
+#define CAL_STAGE_FULLTEST 5
+#define CAL_STAGE_REFRESH 6
+#define CAL_STAGE_CAL_SKIPPED 7
+#define CAL_STAGE_CAL_ABORTED 8
+#define CAL_STAGE_VFIFO_AFTER_WRITES 9
+
+/* calibration substages */
+#define CAL_SUBSTAGE_NIL 0
+#define CAL_SUBSTAGE_GUARANTEED_READ 1
+#define CAL_SUBSTAGE_DQS_EN_PHASE 2
+#define CAL_SUBSTAGE_VFIFO_CENTER 3
+#define CAL_SUBSTAGE_WORKING_DELAY 1
+#define CAL_SUBSTAGE_LAST_WORKING_DELAY 2
+#define CAL_SUBSTAGE_WLEVEL_COPY 3
+#define CAL_SUBSTAGE_WRITES_CENTER 1
+#define CAL_SUBSTAGE_READ_LATENCY 1
+#define CAL_SUBSTAGE_REFRESH 1
+
+#define MAX_RANKS (RW_MGR_MEM_NUMBER_OF_RANKS)
+#define MAX_DQS (RW_MGR_MEM_IF_WRITE_DQS_WIDTH > \
+ RW_MGR_MEM_IF_READ_DQS_WIDTH ? \
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH : \
+ RW_MGR_MEM_IF_READ_DQS_WIDTH)
+#define MAX_DQ (RW_MGR_MEM_DATA_WIDTH)
+#define MAX_DM (RW_MGR_MEM_DATA_MASK_WIDTH)
+
+/* length of VFIFO, from SW_MACROS */
+#define VFIFO_SIZE (READ_VALID_FIFO_SIZE)
+
+/* MarkW: how should these base addresses be done for A-V? */
+#define BASE_PTR_MGR 0x00040000
+#define BASE_SCC_MGR 0x00058000
+#define BASE_REG_FILE 0x00070000
+#define BASE_TIMER 0x00078000
+#define BASE_PHY_MGR 0x00088000
+#define BASE_RW_MGR 0x00090000
+#define BASE_DATA_MGR 0x00098000
+#define BASE_MMR 0x000C0000
+#define BASE_TRK_MGR 0x000D0000
+
+#define SCC_MGR_GROUP_COUNTER (BASE_SCC_MGR + 0x0000)
+#define SCC_MGR_DQS_IN_DELAY (BASE_SCC_MGR + 0x0100)
+#define SCC_MGR_DQS_EN_PHASE (BASE_SCC_MGR + 0x0200)
+#define SCC_MGR_DQS_EN_DELAY (BASE_SCC_MGR + 0x0300)
+#define SCC_MGR_DQDQS_OUT_PHASE (BASE_SCC_MGR + 0x0400)
+#define SCC_MGR_OCT_OUT1_DELAY (BASE_SCC_MGR + 0x0500)
+#define SCC_MGR_IO_OUT1_DELAY (BASE_SCC_MGR + 0x0700)
+#define SCC_MGR_IO_IN_DELAY (BASE_SCC_MGR + 0x0900)
+
+/* HHP-HPS-specific versions of some commands */
+#define SCC_MGR_DQS_EN_DELAY_GATE (BASE_SCC_MGR + 0x0600)
+#define SCC_MGR_IO_OE_DELAY (BASE_SCC_MGR + 0x0800)
+#define SCC_MGR_HHP_GLOBALS (BASE_SCC_MGR + 0x0A00)
+#define SCC_MGR_HHP_RFILE (BASE_SCC_MGR + 0x0B00)
+#define SCC_MGR_AFI_CAL_INIT (BASE_SCC_MGR + 0x0D00)
+
+#define SDR_PHYGRP_SCCGRP_ADDRESS 0x0
+#define SDR_PHYGRP_PHYMGRGRP_ADDRESS 0x1000
+#define SDR_PHYGRP_RWMGRGRP_ADDRESS 0x2000
+#define SDR_PHYGRP_DATAMGRGRP_ADDRESS 0x4000
+#define SDR_PHYGRP_REGFILEGRP_ADDRESS 0x4800
+
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET 0x150
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET 0x154
+#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET 0x158
+
+#define PHY_MGR_CAL_RESET (0)
+#define PHY_MGR_CAL_SUCCESS (1)
+#define PHY_MGR_CAL_FAIL (2)
+
+#define CALIB_SKIP_DELAY_LOOPS (1 << 0)
+#define CALIB_SKIP_ALL_BITS_CHK (1 << 1)
+#define CALIB_SKIP_DELAY_SWEEPS (1 << 2)
+#define CALIB_SKIP_VFIFO (1 << 3)
+#define CALIB_SKIP_LFIFO (1 << 4)
+#define CALIB_SKIP_WLEVEL (1 << 5)
+#define CALIB_SKIP_WRITES (1 << 6)
+#define CALIB_SKIP_FULL_TEST (1 << 7)
+#define CALIB_SKIP_ALL (CALIB_SKIP_VFIFO | \
+ CALIB_SKIP_LFIFO | CALIB_SKIP_WLEVEL | \
+ CALIB_SKIP_WRITES | CALIB_SKIP_FULL_TEST)
+#define CALIB_IN_RTL_SIM (1 << 8)
+
+/* Scan chain manager command addresses */
+#define READ_SCC_OCT_OUT2_DELAY 0
+#define READ_SCC_DQ_OUT2_DELAY 0
+#define READ_SCC_DQS_IO_OUT2_DELAY 0
+#define READ_SCC_DM_IO_OUT2_DELAY 0
+
+/* HHP-HPS-specific values */
+#define SCC_MGR_HHP_EXTRAS_OFFSET 0
+#define SCC_MGR_HHP_DQSE_MAP_OFFSET 1
+
+/* PHY Debug mode flag constants */
+#define PHY_DEBUG_IN_DEBUG_MODE 0x00000001
+#define PHY_DEBUG_ENABLE_CAL_RPT 0x00000002
+#define PHY_DEBUG_ENABLE_MARGIN_RPT 0x00000004
+#define PHY_DEBUG_SWEEP_ALL_GROUPS 0x00000008
+#define PHY_DEBUG_DISABLE_GUARANTEED_READ 0x00000010
+#define PHY_DEBUG_ENABLE_NON_DESTRUCTIVE_CALIBRATION 0x00000020
+
+/* Init and Reset delay constants - Only use if defined by sequencer_defines.h,
+ * otherwise, revert to defaults
+ * Default for Tinit = (0+1) * ((202+1) * (2 * 131 + 1) + 1) = 53532 =
+ * 200.75us @ 266MHz
+ */
+#ifdef TINIT_CNTR0_VAL
+#define SEQ_TINIT_CNTR0_VAL TINIT_CNTR0_VAL
+#else
+#define SEQ_TINIT_CNTR0_VAL 0
+#endif
+
+#ifdef TINIT_CNTR1_VAL
+#define SEQ_TINIT_CNTR1_VAL TINIT_CNTR1_VAL
+#else
+#define SEQ_TINIT_CNTR1_VAL 202
+#endif
+
+#ifdef TINIT_CNTR2_VAL
+#define SEQ_TINIT_CNTR2_VAL TINIT_CNTR2_VAL
+#else
+#define SEQ_TINIT_CNTR2_VAL 131
+#endif
+
+
+/* Default for Treset = (2+1) * ((252+1) * (2 * 131 + 1) + 1) = 133563 =
+ * 500.86us @ 266MHz
+ */
+#ifdef TRESET_CNTR0_VAL
+#define SEQ_TRESET_CNTR0_VAL TRESET_CNTR0_VAL
+#else
+#define SEQ_TRESET_CNTR0_VAL 2
+#endif
+
+#ifdef TRESET_CNTR1_VAL
+#define SEQ_TRESET_CNTR1_VAL TRESET_CNTR1_VAL
+#else
+#define SEQ_TRESET_CNTR1_VAL 252
+#endif
+
+#ifdef TRESET_CNTR2_VAL
+#define SEQ_TRESET_CNTR2_VAL TRESET_CNTR2_VAL
+#else
+#define SEQ_TRESET_CNTR2_VAL 131
+#endif
+
+#define RW_MGR_INST_ROM_WRITE BASE_RW_MGR + 0x1800
+#define RW_MGR_AC_ROM_WRITE BASE_RW_MGR + 0x1C00
+
+struct socfpga_sdr_rw_load_manager {
+ u32 load_cntr0;
+ u32 load_cntr1;
+ u32 load_cntr2;
+ u32 load_cntr3;
+};
+
+struct socfpga_sdr_rw_load_jump_manager {
+ u32 load_jump_add0;
+ u32 load_jump_add1;
+ u32 load_jump_add2;
+ u32 load_jump_add3;
+};
+
+struct socfpga_sdr_reg_file {
+ u32 signature;
+ u32 debug_data_addr;
+ u32 cur_stage;
+ u32 fom;
+ u32 failing_stage;
+ u32 debug1;
+ u32 debug2;
+ u32 dtaps_per_ptap;
+ u32 trk_sample_count;
+ u32 trk_longidle;
+ u32 delays;
+ u32 trk_rw_mgr_addr;
+ u32 trk_read_dqs_width;
+ u32 trk_rfsh;
+};
+
+/* parameter variable holder */
+struct param_type {
+ uint32_t dm_correct_mask;
+ uint32_t read_correct_mask;
+ uint32_t read_correct_mask_vg;
+ uint32_t write_correct_mask;
+ uint32_t write_correct_mask_vg;
+
+ /* set a particular entry to 1 if we need to skip a particular rank */
+
+ uint32_t skip_ranks[MAX_RANKS];
+
+ /* set a particular entry to 1 if we need to skip a particular group */
+
+ uint32_t skip_groups;
+
+ /* set a particular entry to 1 if the shadow register
+ (which represents a set of ranks) needs to be skipped */
+
+ uint32_t skip_shadow_regs[NUM_SHADOW_REGS];
+
+};
+
+
+/* global variable holder */
+struct gbl_type {
+ uint32_t phy_debug_mode_flags;
+
+ /* current read latency */
+
+ uint32_t curr_read_lat;
+
+ /* current write latency */
+
+ uint32_t curr_write_lat;
+
+ /* error code */
+
+ uint32_t error_substage;
+ uint32_t error_stage;
+ uint32_t error_group;
+
+ /* figure-of-merit in, figure-of-merit out */
+
+ uint32_t fom_in;
+ uint32_t fom_out;
+
+ /*USER Number of RW Mgr NOP cycles between
+ write command and write data */
+ uint32_t rw_wl_nop_cycles;
+};
+
+struct socfpga_sdr_scc_mgr {
+ u32 dqs_ena;
+ u32 dqs_io_ena;
+ u32 dq_ena;
+ u32 dm_ena;
+ u32 __padding1[4];
+ u32 update;
+ u32 __padding2[7];
+ u32 active_rank;
+};
+
+/* PHY manager configuration registers. */
+struct socfpga_phy_mgr_cfg {
+ u32 phy_rlat;
+ u32 reset_mem_stbl;
+ u32 mux_sel;
+ u32 cal_status;
+ u32 cal_debug_info;
+ u32 vfifo_rd_en_ovrd;
+ u32 afi_wlat;
+ u32 afi_rlat;
+};
+
+/* PHY manager command addresses. */
+struct socfpga_phy_mgr_cmd {
+ u32 inc_vfifo_fr;
+ u32 inc_vfifo_hard_phy;
+ u32 fifo_reset;
+ u32 inc_vfifo_fr_hr;
+ u32 inc_vfifo_qr;
+};
+
+struct socfpga_data_mgr {
+ u32 __padding1;
+ u32 t_wl_add;
+ u32 mem_t_add;
+ u32 t_rl_add;
+};
+#endif /* _SEQUENCER_H_ */
diff --git a/drivers/ddr/altera/sequencer_auto.h b/drivers/ddr/altera/sequencer_auto.h
new file mode 100644
index 0000000..0c5d83b
--- /dev/null
+++ b/drivers/ddr/altera/sequencer_auto.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright Altera Corporation (C) 2012-2015
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#define RW_MGR_READ_B2B_WAIT2 0x6A
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31
+#define RW_MGR_REFRESH_ALL 0x14
+#define RW_MGR_ZQCL 0x06
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23
+#define RW_MGR_ACTIVATE_0_AND_1 0x0D
+#define RW_MGR_MRS2_MIRR 0x0A
+#define RW_MGR_INIT_RESET_0_CKE_0 0x6E
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45
+#define RW_MGR_ACTIVATE_1 0x0F
+#define RW_MGR_MRS2 0x04
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34
+#define RW_MGR_MRS1 0x03
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* The if..else... is not required if generated by tools */
+#define RW_MGR_IDLE_LOOP1 0x7A
+#else
+#define RW_MGR_IDLE_LOOP1 0x7C
+#endif /* CONFIG_SOCFPGA_ARRIA5 */
+#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18
+#define RW_MGR_MRS3 0x05
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* The if..else... is not required if generated by tools */
+#define RW_MGR_IDLE_LOOP2 0x79
+#else
+#define RW_MGR_IDLE_LOOP2 0x7B
+#endif /* CONFIG_SOCFPGA_ARRIA5 */
+#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24
+#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* The if..else... is not required if generated by tools */
+#define RW_MGR_RDIMM_CMD 0x78
+#else
+#define RW_MGR_RDIMM_CMD 0x7A
+#endif /* CONFIG_SOCFPGA_ARRIA5 */
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36
+#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38
+#define RW_MGR_GUARANTEED_READ_CONT 0x53
+#define RW_MGR_MRS3_MIRR 0x0B
+#define RW_MGR_IDLE 0x00
+#define RW_MGR_READ_B2B 0x58
+#define RW_MGR_INIT_RESET_0_CKE_0_inloop 0x6F
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37
+#define RW_MGR_GUARANTEED_WRITE 0x17
+#define RW_MGR_PRECHARGE_ALL 0x12
+#define RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* The if..else... is not required if generated by tools */
+#define RW_MGR_SGLE_READ 0x7C
+#else
+#define RW_MGR_SGLE_READ 0x7E
+#endif /* CONFIG_SOCFPGA_ARRIA5 */
+#define RW_MGR_MRS0_USER_MIRR 0x0C
+#define RW_MGR_RETURN 0x01
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35
+#define RW_MGR_MRS0_USER 0x07
+#define RW_MGR_GUARANTEED_READ 0x4B
+#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08
+#define RW_MGR_INIT_RESET_1_CKE_0 0x73
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20
+#define RW_MGR_MRS0_DLL_RESET 0x02
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
+#define RW_MGR_LFSR_WR_RD_BANK_0 0x21
+#define RW_MGR_CLEAR_DQS_ENABLE 0x48
+#define RW_MGR_MRS1_MIRR 0x09
+#define RW_MGR_READ_B2B_WAIT1 0x60
+#define RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680
+#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680
+#define RW_MGR_CONTENT_REFRESH_ALL 0x000980
+#define RW_MGR_CONTENT_ZQCL 0x008380
+#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700
+#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00
+#define RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800
+#define RW_MGR_CONTENT_MRS2_MIRR 0x008580
+#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000
+#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680
+#define RW_MGR_CONTENT_ACTIVATE_1 0x000880
+#define RW_MGR_CONTENT_MRS2 0x008280
+#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00
+#define RW_MGR_CONTENT_MRS1 0x008200
+#define RW_MGR_CONTENT_IDLE_LOOP1 0x00A680
+#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8
+#define RW_MGR_CONTENT_MRS3 0x008300
+#define RW_MGR_CONTENT_IDLE_LOOP2 0x008680
+#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88
+#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0
+#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88
+#define RW_MGR_CONTENT_RDIMM_CMD 0x009180
+#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700
+#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8
+#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0
+#define RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168
+#define RW_MGR_CONTENT_MRS3_MIRR 0x008600
+#define RW_MGR_CONTENT_IDLE 0x080000
+#define RW_MGR_CONTENT_READ_B2B 0x040E88
+#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0_inloop 0x000000
+#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00
+#define RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68
+#define RW_MGR_CONTENT_PRECHARGE_ALL 0x000900
+#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0_inloop_1 0x000080
+#define RW_MGR_CONTENT_SGLE_READ 0x040F08
+#define RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400
+#define RW_MGR_CONTENT_RETURN 0x080680
+#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80
+#define RW_MGR_CONTENT_MRS0_USER 0x008100
+#define RW_MGR_CONTENT_GUARANTEED_READ 0x001168
+#define RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480
+#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080
+#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680
+#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00
+#define RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180
+#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680
+#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80
+#define RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158
+#define RW_MGR_CONTENT_MRS1_MIRR 0x008500
+#define RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680
+
diff --git a/drivers/ddr/altera/sequencer_auto_ac_init.h b/drivers/ddr/altera/sequencer_auto_ac_init.h
new file mode 100644
index 0000000..c46421b
--- /dev/null
+++ b/drivers/ddr/altera/sequencer_auto_ac_init.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright Altera Corporation (C) 2012-2015
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+const uint32_t ac_rom_init[] = {
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* The if..else... is not required if generated by tools */
+ 0x20700000,
+ 0x20780000,
+ 0x10080831,
+ 0x10080930,
+ 0x10090004,
+ 0x100a0008,
+ 0x100b0000,
+ 0x10380400,
+ 0x10080849,
+ 0x100808c8,
+ 0x100a0004,
+ 0x10090010,
+ 0x100b0000,
+ 0x30780000,
+ 0x38780000,
+ 0x30780000,
+ 0x10680000,
+ 0x106b0000,
+ 0x10280400,
+ 0x10480000,
+ 0x1c980000,
+ 0x1c9b0000,
+ 0x1c980008,
+ 0x1c9b0008,
+ 0x38f80000,
+ 0x3cf80000,
+ 0x38780000,
+ 0x18180000,
+ 0x18980000,
+ 0x13580000,
+ 0x135b0000,
+ 0x13580008,
+ 0x135b0008,
+ 0x33780000,
+ 0x10580008,
+ 0x10780000
+#else
+ 0x20700000,
+ 0x20780000,
+ 0x10080431,
+ 0x10080530,
+ 0x10090004,
+ 0x100a0008,
+ 0x100b0000,
+ 0x10380400,
+ 0x10080449,
+ 0x100804c8,
+ 0x100a0004,
+ 0x10090010,
+ 0x100b0000,
+ 0x30780000,
+ 0x38780000,
+ 0x30780000,
+ 0x10680000,
+ 0x106b0000,
+ 0x10280400,
+ 0x10480000,
+ 0x1c980000,
+ 0x1c9b0000,
+ 0x1c980008,
+ 0x1c9b0008,
+ 0x38f80000,
+ 0x3cf80000,
+ 0x38780000,
+ 0x18180000,
+ 0x18980000,
+ 0x13580000,
+ 0x135b0000,
+ 0x13580008,
+ 0x135b0008,
+ 0x33780000,
+ 0x10580008,
+ 0x10780000
+#endif /* CONFIG_SOCFPGA_ARRIA5 */
+};
diff --git a/drivers/ddr/altera/sequencer_auto_inst_init.h b/drivers/ddr/altera/sequencer_auto_inst_init.h
new file mode 100644
index 0000000..ad0395b
--- /dev/null
+++ b/drivers/ddr/altera/sequencer_auto_inst_init.h
@@ -0,0 +1,268 @@
+/*
+ * Copyright Altera Corporation (C) 2012-2015
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* The if..else... is not required if generated by tools */
+const u32 inst_rom_init[] = {
+ 0x80000,
+ 0x80680,
+ 0x8180,
+ 0x8200,
+ 0x8280,
+ 0x8300,
+ 0x8380,
+ 0x8100,
+ 0x8480,
+ 0x8500,
+ 0x8580,
+ 0x8600,
+ 0x8400,
+ 0x800,
+ 0x8680,
+ 0x880,
+ 0xa680,
+ 0x80680,
+ 0x900,
+ 0x80680,
+ 0x980,
+ 0x8680,
+ 0x80680,
+ 0xb68,
+ 0xcce8,
+ 0xae8,
+ 0x8ce8,
+ 0xb88,
+ 0xec88,
+ 0xa08,
+ 0xac88,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x60e80,
+ 0x61080,
+ 0x61080,
+ 0x61080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x70e80,
+ 0x71080,
+ 0x71080,
+ 0x71080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0x1158,
+ 0x6d8,
+ 0x80680,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0x87e8,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0xa7e8,
+ 0x80680,
+ 0x40e88,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x40f68,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0xa680,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x41008,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x1100,
+ 0xc680,
+ 0x8680,
+ 0xe680,
+ 0x80680,
+ 0x0,
+ 0x8000,
+ 0xa000,
+ 0xc000,
+ 0x80000,
+ 0x80,
+ 0x8080,
+ 0xa080,
+ 0xc080,
+ 0x80080,
+ 0x9180,
+ 0x8680,
+ 0xa680,
+ 0x80680,
+ 0x40f08,
+ 0x80680
+};
+#else
+const u32 inst_rom_init[] = {
+ 0x80000,
+ 0x80680,
+ 0x8180,
+ 0x8200,
+ 0x8280,
+ 0x8300,
+ 0x8380,
+ 0x8100,
+ 0x8480,
+ 0x8500,
+ 0x8580,
+ 0x8600,
+ 0x8400,
+ 0x800,
+ 0x8680,
+ 0x880,
+ 0xa680,
+ 0x80680,
+ 0x900,
+ 0x80680,
+ 0x980,
+ 0x8680,
+ 0x80680,
+ 0xb68,
+ 0xcce8,
+ 0xae8,
+ 0x8ce8,
+ 0xb88,
+ 0xec88,
+ 0xa08,
+ 0xac88,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x60e80,
+ 0x61080,
+ 0x61080,
+ 0x61080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x70e80,
+ 0x71080,
+ 0x71080,
+ 0x71080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0x1158,
+ 0x6d8,
+ 0x80680,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0x87e8,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0xa7e8,
+ 0x80680,
+ 0x40e88,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x40f68,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0xa680,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x41008,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x1100,
+ 0xc680,
+ 0x8680,
+ 0xe680,
+ 0x80680,
+ 0x0,
+ 0x0,
+ 0xa000,
+ 0x8000,
+ 0x80000,
+ 0x80,
+ 0x80,
+ 0x80,
+ 0x80,
+ 0xa080,
+ 0x8080,
+ 0x80080,
+ 0x9180,
+ 0x8680,
+ 0xa680,
+ 0x80680,
+ 0x40f08,
+ 0x80680
+};
+#endif /* CONFIG_SOCFPGA_ARRIA5 */
diff --git a/drivers/ddr/altera/sequencer_defines.h b/drivers/ddr/altera/sequencer_defines.h
new file mode 100644
index 0000000..32f13ac
--- /dev/null
+++ b/drivers/ddr/altera/sequencer_defines.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright Altera Corporation (C) 2012-2015
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _SEQUENCER_DEFINES_H_
+#define _SEQUENCER_DEFINES_H_
+
+#define AC_ROM_MR1_MIRR 0000000000100
+#define AC_ROM_MR1_OCD_ENABLE
+#define AC_ROM_MR2_MIRR 0000000010000
+#define AC_ROM_MR3_MIRR 0000000000000
+#define AC_ROM_MR0_CALIB
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* The if..else... is not required if generated by tools */
+#define AC_ROM_MR0_DLL_RESET_MIRR 0100011001000
+#define AC_ROM_MR0_DLL_RESET 0100100110000
+#define AC_ROM_MR0_MIRR 0100001001001
+#define AC_ROM_MR0 0100000110001
+#else
+#define AC_ROM_MR0_DLL_RESET_MIRR 0010011001000
+#define AC_ROM_MR0_DLL_RESET 0010100110000
+#define AC_ROM_MR0_MIRR 0010001001001
+#define AC_ROM_MR0 0010000110001
+#endif /* CONFIG_SOCFPGA_ARRIA5 */
+#define AC_ROM_MR1 0000000000100
+#define AC_ROM_MR2 0000000001000
+#define AC_ROM_MR3 0000000000000
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* The if..else... is not required if generated by tools */
+#define AFI_CLK_FREQ 534
+#else
+#define AFI_CLK_FREQ 401
+#endif /* CONFIG_SOCFPGA_ARRIA5 */
+#define AFI_RATE_RATIO 1
+#define AVL_CLK_FREQ 67
+#define BFM_MODE 0
+#define BURST2 0
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* The if..else... is not required if generated by tools */
+#define CALIB_LFIFO_OFFSET 8
+#define CALIB_VFIFO_OFFSET 6
+#else
+#define CALIB_LFIFO_OFFSET 7
+#define CALIB_VFIFO_OFFSET 5
+#endif /* CONFIG_SOCFPGA_ARRIA5 */
+#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define GUARANTEED_READ_BRINGUP_TEST 0
+#define HARD_PHY 1
+#define HARD_VFIFO 1
+#define HPS_HW 1
+#define HR_DDIO_OUT_HAS_THREE_REGS 0
+#define IO_DELAY_PER_DCHAIN_TAP 25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* The if..else... is not required if generated by tools */
+#define IO_DELAY_PER_OPA_TAP 234
+#else
+#define IO_DELAY_PER_OPA_TAP 312
+#endif /* CONFIG_SOCFPGA_ARRIA5 */
+#define IO_DLL_CHAIN_LENGTH 8
+#define IO_DM_OUT_RESERVE 0
+#define IO_DQDQS_OUT_PHASE_MAX 0
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* The if..else... is not required if generated by tools */
+#define IO_DQS_EN_DELAY_MAX 15
+#define IO_DQS_EN_DELAY_OFFSET 16
+#else
+#define IO_DQS_EN_DELAY_MAX 31
+#define IO_DQS_EN_DELAY_OFFSET 0
+#endif /* CONFIG_SOCFPGA_ARRIA5 */
+#define IO_DQS_EN_PHASE_MAX 7
+#define IO_DQS_IN_DELAY_MAX 31
+#define IO_DQS_IN_RESERVE 4
+#define IO_DQS_OUT_RESERVE 6
+#define IO_DQ_OUT_RESERVE 0
+#define IO_IO_IN_DELAY_MAX 31
+#define IO_IO_OUT1_DELAY_MAX 31
+#define IO_IO_OUT2_DELAY_MAX 0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define MARGIN_VARIATION_TEST 0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define MEM_ADDR_WIDTH 13
+#define READ_VALID_FIFO_SIZE 16
+#ifdef CONFIG_SOCFPGA_ARRIA5
+/* The if..else... is not required if generated by tools */
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
+#else
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550483
+#endif /* CONFIG_SOCFPGA_ARRIA5 */
+#define RW_MGR_MEM_ADDRESS_MIRRORING 0
+#define RW_MGR_MEM_ADDRESS_WIDTH 15
+#define RW_MGR_MEM_BANK_WIDTH 3
+#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1
+#define RW_MGR_MEM_CLK_EN_WIDTH 1
+#define RW_MGR_MEM_CONTROL_WIDTH 1
+#define RW_MGR_MEM_DATA_MASK_WIDTH 5
+#define RW_MGR_MEM_DATA_WIDTH 40
+#define RW_MGR_MEM_DQ_PER_READ_DQS 8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH 5
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_ODT_WIDTH 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_MR0_BL 1
+#define RW_MGR_MR0_CAS_LATENCY 3
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 5
+#define RW_MGR_WRITE_TO_DEBUG_READ 1.0
+#define SKEW_CALIBRATION 0
+#define TINIT_CNTR1_VAL 32
+#define TINIT_CNTR2_VAL 32
+#define TINIT_CNTR0_VAL 132
+#define TRESET_CNTR1_VAL 99
+#define TRESET_CNTR2_VAL 10
+#define TRESET_CNTR0_VAL 132
+
+#endif /* _SEQUENCER_DEFINES_H_ */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 003/172] arm: socfpga: enable the Altera SDRAM controller driver
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 001/172] driver/ddr/altera: Add DDR driver for Altera's SDRAM controller Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 002/172] driver/ddr/altera: Add the sdram calibration portion Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 004/172] arm: socfpga: Move sdram_config.h to board dir Marek Vasut
` (170 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
From: Dinh Nguyen <dinguyen@opensource.altera.com>
Enable the Altera SDRAM driver for the SoCFPGA platform.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Marek Vasut <marex@denx.de>
---
include/configs/socfpga_common.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 0298360..12363ae 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -75,6 +75,11 @@
#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
/*
+ * SDRAM controller
+ */
+#define CONFIG_ALTERA_SDRAM
+
+/*
* EPCS/EPCQx1 Serial Flash Controller
*/
#ifdef CONFIG_ALTERA_SPI
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 004/172] arm: socfpga: Move sdram_config.h to board dir
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (2 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 003/172] arm: socfpga: enable the Altera SDRAM controller driver Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 005/172] ddr: altera: Move struct sdram_prot_rule prototype Marek Vasut
` (169 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
This file is absolutelly positively board specific, so move it
into the correct place.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/include/mach/sdram_config.h | 100 ----------------------
board/altera/socfpga/qts/sdram_config.h | 100 ++++++++++++++++++++++
drivers/ddr/altera/sdram.c | 7 +-
3 files changed, 106 insertions(+), 101 deletions(-)
delete mode 100644 arch/arm/mach-socfpga/include/mach/sdram_config.h
create mode 100644 board/altera/socfpga/qts/sdram_config.h
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_config.h b/arch/arm/mach-socfpga/include/mach/sdram_config.h
deleted file mode 100644
index f6d51ca..0000000
--- a/arch/arm/mach-socfpga/include/mach/sdram_config.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright Altera Corporation (C) 2012-2015
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/* This file is autogenerated from tools provided by Altera.*/
-#ifndef __SDRAM_CONFIG_H
-#define __SDRAM_CONFIG_H
-
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
-#ifdef CONFIG_SOCFPGA_ARRIA5
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26
-#else
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
-#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
-#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
-#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
-#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
-#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
-#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
-#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
-#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
-#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \
-0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \
-0x01010101
-#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \
-0x0101
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0
-#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
-
-#endif /*#ifndef__SDRAM_CONFIG_H*/
diff --git a/board/altera/socfpga/qts/sdram_config.h b/board/altera/socfpga/qts/sdram_config.h
new file mode 100644
index 0000000..f6d51ca
--- /dev/null
+++ b/board/altera/socfpga/qts/sdram_config.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright Altera Corporation (C) 2012-2015
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* This file is autogenerated from tools provided by Altera.*/
+#ifndef __SDRAM_CONFIG_H
+#define __SDRAM_CONFIG_H
+
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
+#ifdef CONFIG_SOCFPGA_ARRIA5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26
+#else
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
+#endif /* CONFIG_SOCFPGA_ARRIA5 */
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
+
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \
+0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \
+0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \
+0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
+
+#endif /*#ifndef__SDRAM_CONFIG_H*/
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c
index 5d8fed3..2822d1d 100644
--- a/drivers/ddr/altera/sdram.c
+++ b/drivers/ddr/altera/sdram.c
@@ -8,10 +8,15 @@
#include <watchdog.h>
#include <asm/arch/fpga_manager.h>
#include <asm/arch/sdram.h>
-#include <asm/arch/sdram_config.h>
#include <asm/arch/system_manager.h>
#include <asm/io.h>
+/*
+ * FIXME: This path is temporary until the SDRAM driver gets
+ * a proper thorough cleanup.
+ */
+#include "../../../board/altera/socfpga/qts/sdram_config.h"
+
/* define constant for 4G memory - used for SDRAM errata workaround */
#define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 005/172] ddr: altera: Move struct sdram_prot_rule prototype
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (3 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 004/172] arm: socfpga: Move sdram_config.h to board dir Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 006/172] ddr: altera: Fix typo in mp_threshold1 programming Marek Vasut
` (168 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Move the structure prototype from sdram.h header file into sdram.c
source file, since it is used only there and for local purpose only.
There is no point in having it global.
While at this move, fix the data types in the structure from uintNN_t
to uNN and fix the coding style a bit.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/include/mach/sdram.h | 13 -------------
drivers/ddr/altera/sdram.c | 13 +++++++++++++
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index b4c1a2f..873ea25 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -73,19 +73,6 @@ struct socfpga_sdr_ctrl {
u32 phy_ctrl2;
};
-struct sdram_prot_rule {
- uint64_t sdram_start; /* SDRAM start address */
- uint64_t sdram_end; /* SDRAM end address */
- uint32_t rule; /* SDRAM protection rule number: 0-19 */
- int valid; /* Rule valid or not? 1 - valid, 0 not*/
-
- uint32_t security;
- uint32_t portmask;
- uint32_t result;
- uint32_t lo_prot_id;
- uint32_t hi_prot_id;
-};
-
#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c
index 2822d1d..45846de 100644
--- a/drivers/ddr/altera/sdram.c
+++ b/drivers/ddr/altera/sdram.c
@@ -22,6 +22,19 @@
DECLARE_GLOBAL_DATA_PTR;
+struct sdram_prot_rule {
+ u64 sdram_start; /* SDRAM start address */
+ u64 sdram_end; /* SDRAM end address */
+ u32 rule; /* SDRAM protection rule number: 0-19 */
+ int valid; /* Rule valid or not? 1 - valid, 0 not*/
+
+ u32 security;
+ u32 portmask;
+ u32 result;
+ u32 lo_prot_id;
+ u32 hi_prot_id;
+};
+
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
static struct socfpga_sdr_ctrl *sdr_ctrl =
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 006/172] ddr: altera: Fix typo in mp_threshold1 programming
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (4 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 005/172] ddr: altera: Move struct sdram_prot_rule prototype Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 007/172] ddr: altera: Fix debug message format in sequencer Marek Vasut
` (167 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
It is the configuration data that should go into the register,
not the register mask, just like the surrounding code does it.
Fix this typo.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@konsulko.com>
---
drivers/ddr/altera/sdram.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c
index 45846de..90a4b2c 100644
--- a/drivers/ddr/altera/sdram.c
+++ b/drivers/ddr/altera/sdram.c
@@ -539,7 +539,7 @@ static void set_sdr_mp_threshold(void)
clrsetbits_le32(&sdr_ctrl->mp_threshold1,
SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK,
- SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK <<
+ CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB);
clrsetbits_le32(&sdr_ctrl->mp_threshold2,
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 007/172] ddr: altera: Fix debug message format in sequencer
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (5 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 006/172] ddr: altera: Fix typo in mp_threshold1 programming Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 008/172] arm: socfpga: reset: Add missing reset manager regs Marek Vasut
` (166 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
The debug messages missed proper newlines and/or spaces in them.
Fix the formatting.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@konsulko.com>
---
drivers/ddr/altera/sequencer.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 6340859..1e96014 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -332,7 +332,7 @@ static void scc_mgr_initialize(void)
*/
uint32_t i;
for (i = 0; i < 16; i++) {
- debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u",
+ debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
__func__, __LINE__, i);
writel(0, SOCFPGA_SDR_ADDRESS + addr + (i << 2));
}
@@ -2386,7 +2386,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
uint32_t write_group, write_test_bgn;
uint32_t failed_substage;
- debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
+ debug("%s:%d: %u %u\n", __func__, __LINE__, read_group, test_bgn);
/* update info for sims */
reg_file_set_stage(CAL_STAGE_VFIFO);
@@ -3994,14 +3994,14 @@ int sdram_calibration_full(void)
printf("%s: Preparing to start memory calibration\n", __FILE__);
debug("%s:%d\n", __func__, __LINE__);
- debug_cond(DLEVEL == 1, "DDR3 FULL_RATE ranks=%lu cs/dimm=%lu dq/dqs=%lu,%lu vg/dqs=%lu,%lu",
+ debug_cond(DLEVEL == 1, "DDR3 FULL_RATE ranks=%lu cs/dimm=%lu dq/dqs=%lu,%lu vg/dqs=%lu,%lu ",
(long unsigned int)RW_MGR_MEM_NUMBER_OF_RANKS,
(long unsigned int)RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
(long unsigned int)RW_MGR_MEM_DQ_PER_READ_DQS,
(long unsigned int)RW_MGR_MEM_DQ_PER_WRITE_DQS,
(long unsigned int)RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
(long unsigned int)RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
- debug_cond(DLEVEL == 1, "dqs=%lu,%lu dq=%lu dm=%lu ptap_delay=%lu dtap_delay=%lu",
+ debug_cond(DLEVEL == 1, "dqs=%lu,%lu dq=%lu dm=%lu ptap_delay=%lu dtap_delay=%lu ",
(long unsigned int)RW_MGR_MEM_IF_READ_DQS_WIDTH,
(long unsigned int)RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
(long unsigned int)RW_MGR_MEM_DATA_WIDTH,
@@ -4011,16 +4011,16 @@ int sdram_calibration_full(void)
debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%lu, dll=%lu",
(long unsigned int)IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
(long unsigned int)IO_DLL_CHAIN_LENGTH);
- debug_cond(DLEVEL == 1, "max values: en_p=%lu dqdqs_p=%lu en_d=%lu dqs_in_d=%lu",
+ debug_cond(DLEVEL == 1, "max values: en_p=%lu dqdqs_p=%lu en_d=%lu dqs_in_d=%lu ",
(long unsigned int)IO_DQS_EN_PHASE_MAX,
(long unsigned int)IO_DQDQS_OUT_PHASE_MAX,
(long unsigned int)IO_DQS_EN_DELAY_MAX,
(long unsigned int)IO_DQS_IN_DELAY_MAX);
- debug_cond(DLEVEL == 1, "io_in_d=%lu io_out1_d=%lu io_out2_d=%lu",
+ debug_cond(DLEVEL == 1, "io_in_d=%lu io_out1_d=%lu io_out2_d=%lu ",
(long unsigned int)IO_IO_IN_DELAY_MAX,
(long unsigned int)IO_IO_OUT1_DELAY_MAX,
(long unsigned int)IO_IO_OUT2_DELAY_MAX);
- debug_cond(DLEVEL == 1, "dqs_in_reserve=%lu dqs_out_reserve=%lu",
+ debug_cond(DLEVEL == 1, "dqs_in_reserve=%lu dqs_out_reserve=%lu\n",
(long unsigned int)IO_DQS_IN_RESERVE,
(long unsigned int)IO_DQS_OUT_RESERVE);
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 008/172] arm: socfpga: reset: Add missing reset manager regs
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (6 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 007/172] ddr: altera: Fix debug message format in sequencer Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 009/172] arm: socfpga: reset: Start reworking the SoCFPGA reset manager Marek Vasut
` (165 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Define two missing reset manager registers, which are in the
SoCFPGA CV datasheet.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index d63a285..7e803f7 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -28,6 +28,8 @@ struct socfpga_reset_manager {
u32 per_mod_reset;
u32 per2_mod_reset;
u32 brg_mod_reset;
+ u32 misc_mod_reset;
+ u32 tstscratch;
};
#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 009/172] arm: socfpga: reset: Start reworking the SoCFPGA reset manager
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (7 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 008/172] arm: socfpga: reset: Add missing reset manager regs Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 010/172] arm: socfpga: reset: Implement unified function to toggle reset Marek Vasut
` (164 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Implement macro SOCFPGA_RESET(name), which produces an abstract
reset number. Implement macros which allow extracting the reset
offset in permodrstN register and which permodrstN register the
reset is located in from this abstract reset number. Use these
macros throughout the reset manager.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 47 ++++++++++++++++++----
arch/arm/mach-socfpga/reset_manager.c | 22 +++++-----
2 files changed, 50 insertions(+), 19 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 7e803f7..fff4c96 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -38,13 +38,44 @@ struct socfpga_reset_manager {
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
#endif
-#define RSTMGR_PERMODRST_EMAC0_LSB 0
-#define RSTMGR_PERMODRST_EMAC1_LSB 1
-#define RSTMGR_PERMODRST_L4WD0_LSB 6
-#define RSTMGR_PERMODRST_OSC1TIMER0_LSB 8
-#define RSTMGR_PERMODRST_UART0_LSB 16
-#define RSTMGR_PERMODRST_SPIM0_LSB 18
-#define RSTMGR_PERMODRST_SPIM1_LSB 19
-#define RSTMGR_PERMODRST_SDR_LSB 29
+/*
+ * Define a reset identifier, from which a permodrst bank ID
+ * and reset ID can be extracted using the subsequent macros
+ * RSTMGR_RESET() and RSTMGR_BANK().
+ */
+#define RSTMGR_BANK_OFFSET 8
+#define RSTMGR_BANK_MASK 0x7
+#define RSTMGR_RESET_OFFSET 0
+#define RSTMGR_RESET_MASK 0x1f
+#define RSTMGR_DEFINE(_bank, _offset) \
+ ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
+
+/* Extract reset ID from the reset identifier. */
+#define RSTMGR_RESET(_reset) \
+ (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
+
+/* Extract bank ID from the reset identifier. */
+#define RSTMGR_BANK(_reset) \
+ (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
+
+/*
+ * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... permodrst
+ * 2 ... per2modrst
+ * 3 ... brgmodrst
+ * 4 ... miscmodrst
+ */
+#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
+#define RSTMGR_L4WD0 RSTMGR_DEFINE(1, 6)
+#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(1, 8)
+#define RSTMGR_UART0 RSTMGR_DEFINE(1, 16)
+#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18)
+#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19)
+#define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
+
+/* Create a human-readable reference to SoCFPGA reset. */
+#define SOCFPGA_RESET(_name) RSTMGR_##_name
#endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index 45b352b..8ede779 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -20,11 +20,11 @@ void socfpga_watchdog_reset(void)
{
/* assert reset for watchdog */
setbits_le32(&reset_manager_base->per_mod_reset,
- 1 << RSTMGR_PERMODRST_L4WD0_LSB);
+ 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)));
/* deassert watchdog from reset (watchdog in not running state) */
clrbits_le32(&reset_manager_base->per_mod_reset,
- 1 << RSTMGR_PERMODRST_L4WD0_LSB);
+ 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)));
}
/*
@@ -94,13 +94,13 @@ void socfpga_emac_reset(int enable)
const void *reset = &reset_manager_base->per_mod_reset;
if (enable) {
- setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
- setbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
+ setbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC0)));
+ setbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC1)));
} else {
#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC0_LSB);
+ clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC0)));
#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_EMAC1_LSB);
+ clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC1)));
#endif
}
}
@@ -110,8 +110,8 @@ void socfpga_spim_enable(void)
{
const void *reset = &reset_manager_base->per_mod_reset;
- clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) |
- (1 << RSTMGR_PERMODRST_SPIM1_LSB));
+ clrbits_le32(reset, (1 << RSTMGR_RESET(SOCFPGA_RESET(SPIM0))) |
+ (1 << RSTMGR_RESET(SOCFPGA_RESET(SPIM1))));
}
/* Bring UART0 out of reset. */
@@ -119,7 +119,7 @@ void socfpga_uart0_enable(void)
{
const void *reset = &reset_manager_base->per_mod_reset;
- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_UART0_LSB);
+ clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(UART0)));
}
/* Bring SDRAM controller out of reset. */
@@ -127,7 +127,7 @@ void socfpga_sdram_enable(void)
{
const void *reset = &reset_manager_base->per_mod_reset;
- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SDR_LSB);
+ clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(SDR)));
}
/* Bring OSC1 timer out of reset. */
@@ -135,5 +135,5 @@ void socfpga_osc1timer_enable(void)
{
const void *reset = &reset_manager_base->per_mod_reset;
- clrbits_le32(reset, 1 << RSTMGR_PERMODRST_OSC1TIMER0_LSB);
+ clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(OSC1TIMER0)));
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 010/172] arm: socfpga: reset: Implement unified function to toggle reset
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (8 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 009/172] arm: socfpga: reset: Start reworking the SoCFPGA reset manager Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 011/172] arm: socfpga: reset: Replace ad-hoc reset functions Marek Vasut
` (163 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Implement function socfpga_per_reset(), which allows asserting or
de-asserting reset of each reset manager peripheral in a unified
manner. Use this function throughout reset manager.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 +
arch/arm/mach-socfpga/reset_manager.c | 58 +++++++++++++---------
2 files changed, 37 insertions(+), 23 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index fff4c96..56509c2 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -12,6 +12,8 @@ void reset_deassert_peripherals_handoff(void);
void socfpga_bridges_reset(int enable);
+void socfpga_per_reset(u32 reset, int set);
+
void socfpga_emac_reset(int enable);
void socfpga_watchdog_reset(void);
void socfpga_spim_enable(void);
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index 8ede779..452377c 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -15,16 +15,38 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
+/* Assert or de-assert SoCFPGA reset manager reset. */
+void socfpga_per_reset(u32 reset, int set)
+{
+ const void *reg;
+
+ if (RSTMGR_BANK(reset) == 0)
+ reg = &reset_manager_base->mpu_mod_reset;
+ else if (RSTMGR_BANK(reset) == 1)
+ reg = &reset_manager_base->per_mod_reset;
+ else if (RSTMGR_BANK(reset) == 2)
+ reg = &reset_manager_base->per2_mod_reset;
+ else if (RSTMGR_BANK(reset) == 3)
+ reg = &reset_manager_base->brg_mod_reset;
+ else if (RSTMGR_BANK(reset) == 4)
+ reg = &reset_manager_base->misc_mod_reset;
+ else /* Invalid reset register, do nothing */
+ return;
+
+ if (set)
+ setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ else
+ clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+}
+
/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
void socfpga_watchdog_reset(void)
{
/* assert reset for watchdog */
- setbits_le32(&reset_manager_base->per_mod_reset,
- 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)));
+ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
/* deassert watchdog from reset (watchdog in not running state) */
- clrbits_le32(&reset_manager_base->per_mod_reset,
- 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)));
+ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
}
/*
@@ -91,16 +113,14 @@ void socfpga_bridges_reset(int enable)
/* Change the reset state for EMAC 0 and EMAC 1 */
void socfpga_emac_reset(int enable)
{
- const void *reset = &reset_manager_base->per_mod_reset;
-
if (enable) {
- setbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC0)));
- setbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC1)));
+ socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
+ socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
} else {
#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
- clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC0)));
+ socfpga_per_reset(SOCFPGA_RESET(EMAC0), 0);
#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
- clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC1)));
+ socfpga_per_reset(SOCFPGA_RESET(EMAC1), 0);
#endif
}
}
@@ -108,32 +128,24 @@ void socfpga_emac_reset(int enable)
/* SPI Master enable (its held in reset by the preloader) */
void socfpga_spim_enable(void)
{
- const void *reset = &reset_manager_base->per_mod_reset;
-
- clrbits_le32(reset, (1 << RSTMGR_RESET(SOCFPGA_RESET(SPIM0))) |
- (1 << RSTMGR_RESET(SOCFPGA_RESET(SPIM1))));
+ socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
+ socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
}
/* Bring UART0 out of reset. */
void socfpga_uart0_enable(void)
{
- const void *reset = &reset_manager_base->per_mod_reset;
-
- clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(UART0)));
+ socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
}
/* Bring SDRAM controller out of reset. */
void socfpga_sdram_enable(void)
{
- const void *reset = &reset_manager_base->per_mod_reset;
-
- clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(SDR)));
+ socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
}
/* Bring OSC1 timer out of reset. */
void socfpga_osc1timer_enable(void)
{
- const void *reset = &reset_manager_base->per_mod_reset;
-
- clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(OSC1TIMER0)));
+ socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 011/172] arm: socfpga: reset: Replace ad-hoc reset functions
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (9 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 010/172] arm: socfpga: reset: Implement unified function to toggle reset Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-28 19:12 ` Dinh Nguyen
2015-07-27 20:49 ` [U-Boot] [PATCH 012/172] arm: socfpga: reset: Repair bridge reset handling Marek Vasut
` (162 subsequent siblings)
173 siblings, 1 reply; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Replace all those ad-hoc reset functions, which were all copies
of the same invocation of clrbits_le32() anyway, with one single
unified function, socfpga_per_reset(), with necessary parameters.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 7 ---
arch/arm/mach-socfpga/misc.c | 14 ++++--
arch/arm/mach-socfpga/reset_manager.c | 50 ----------------------
arch/arm/mach-socfpga/spl.c | 6 +--
4 files changed, 13 insertions(+), 64 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 56509c2..97f155d 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -14,13 +14,6 @@ void socfpga_bridges_reset(int enable);
void socfpga_per_reset(u32 reset, int set);
-void socfpga_emac_reset(int enable);
-void socfpga_watchdog_reset(void);
-void socfpga_spim_enable(void);
-void socfpga_uart0_enable(void);
-void socfpga_sdram_enable(void);
-void socfpga_osc1timer_enable(void);
-
struct socfpga_reset_manager {
u32 status;
u32 ctrl;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 3ddac4c..f03689c 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -54,8 +54,10 @@ int cpu_eth_init(bd_t *bis)
{
#if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
+ const u32 reset = SOCFPGA_RESET(EMAC0);
#elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
+ const u32 reset = SOCFPGA_RESET(EMAC1);
#else
#error "Incorrect CONFIG_EMAC_BASE value!"
#endif
@@ -66,7 +68,8 @@ int cpu_eth_init(bd_t *bis)
* Putting the EMAC controller to reset when configuring the PHY
* interface select at System Manager
*/
- socfpga_emac_reset(1);
+ socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
+ socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
/* Clearing emac0 PHY interface select to 0 */
clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
@@ -77,7 +80,7 @@ int cpu_eth_init(bd_t *bis)
SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
/* Release the EMAC controller from reset */
- socfpga_emac_reset(0);
+ socfpga_per_reset(reset, 0);
/* initialize and register the emac */
return designware_initialize(CONFIG_EMAC_BASE,
@@ -163,8 +166,10 @@ int arch_cpu_init(void)
* If the HW watchdog is NOT enabled, make sure it is not running,
* for example because it was enabled in the preloader. This might
* trigger a watchdog-triggered reboot of Linux kernel later.
+ * Toggle watchdog reset, so watchdog in not running state.
*/
- socfpga_watchdog_reset();
+ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
+ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
#endif
return 0;
@@ -214,7 +219,8 @@ int arch_early_init_r(void)
#ifdef CONFIG_DESIGNWARE_SPI
/* Get Designware SPI controller out of reset */
- socfpga_spim_enable();
+ socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
+ socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
#endif
return 0;
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index 452377c..18af25c 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -39,16 +39,6 @@ void socfpga_per_reset(u32 reset, int set)
clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
}
-/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
-void socfpga_watchdog_reset(void)
-{
- /* assert reset for watchdog */
- socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
-
- /* deassert watchdog from reset (watchdog in not running state) */
- socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
-}
-
/*
* Write the reset manager register to cause reset
*/
@@ -109,43 +99,3 @@ void socfpga_bridges_reset(int enable)
}
}
#endif
-
-/* Change the reset state for EMAC 0 and EMAC 1 */
-void socfpga_emac_reset(int enable)
-{
- if (enable) {
- socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
- socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
- } else {
-#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
- socfpga_per_reset(SOCFPGA_RESET(EMAC0), 0);
-#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
- socfpga_per_reset(SOCFPGA_RESET(EMAC1), 0);
-#endif
- }
-}
-
-/* SPI Master enable (its held in reset by the preloader) */
-void socfpga_spim_enable(void)
-{
- socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
- socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
-}
-
-/* Bring UART0 out of reset. */
-void socfpga_uart0_enable(void)
-{
- socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
-}
-
-/* Bring SDRAM controller out of reset. */
-void socfpga_sdram_enable(void)
-{
- socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
-}
-
-/* Bring OSC1 timer out of reset. */
-void socfpga_osc1timer_enable(void)
-{
- socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
-}
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index f994658..400e463 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -175,9 +175,9 @@ void spl_board_init(void)
/* freeze all IO banks */
sys_mgr_frzctrl_freeze_req();
- socfpga_sdram_enable();
- socfpga_uart0_enable();
- socfpga_osc1timer_enable();
+ socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
+ socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
+ socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
timer_init();
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 012/172] arm: socfpga: reset: Repair bridge reset handling
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (10 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 011/172] arm: socfpga: reset: Replace ad-hoc reset functions Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-28 19:21 ` Dinh Nguyen
2015-07-27 20:49 ` [U-Boot] [PATCH 013/172] arm: socfpga: reset: Add function to reset add peripherals Marek Vasut
` (161 subsequent siblings)
173 siblings, 1 reply; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
The current bridge reset code, which de-asserted the bridge reset,
was activelly polling whether the FPGA is programmed and ready and
in case it was (!), the code called hang(). This makes no sense at
all. Repair it such that the code instead checks whether the FPGA
is programmed, but without any polling involved, and only if it is
programmed, it de-asserts the reset.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/reset_manager.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index 18af25c..6a11c19 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -85,10 +85,10 @@ void socfpga_bridges_reset(int enable)
writel(0xffffffff, &reset_manager_base->brg_mod_reset);
} else {
/* Check signal from FPGA. */
- if (fpgamgr_poll_fpga_ready()) {
- /* FPGA not ready. Wait for watchdog timeout. */
- printf("%s: fpga not ready, hanging.\n", __func__);
- hang();
+ if (!fpgamgr_test_fpga_ready()) {
+ /* FPGA not ready, do nothing. */
+ printf("%s: FPGA not ready, aborting.\n", __func__);
+ return;
}
/* brdmodrst */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 013/172] arm: socfpga: reset: Add function to reset add peripherals
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (11 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 012/172] arm: socfpga: reset: Repair bridge reset handling Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 014/172] arm: socfpga: reset: Add SDMMC, QSPI and DMA defines Marek Vasut
` (160 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Add socfpga_per_reset_all() function to reset all peripherals
but the L4 watchdog. This is needed in the SPL.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 1 +
arch/arm/mach-socfpga/reset_manager.c | 13 +++++++++++++
2 files changed, 14 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 97f155d..457c4b8 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -13,6 +13,7 @@ void reset_deassert_peripherals_handoff(void);
void socfpga_bridges_reset(int enable);
void socfpga_per_reset(u32 reset, int set);
+void socfpga_per_reset_all(void);
struct socfpga_reset_manager {
u32 status;
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index 6a11c19..1186358 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -40,6 +40,19 @@ void socfpga_per_reset(u32 reset, int set)
}
/*
+ * Assert reset on every peripheral but L4WD0.
+ * Watchdog must be kept intact to prevent glitches
+ * and/or hangs.
+ */
+void socfpga_per_reset_all(void)
+{
+ const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
+
+ writel(~l4wd0, &reset_manager_base->per_mod_reset);
+ writel(0xffffffff, &reset_manager_base->per2_mod_reset);
+}
+
+/*
* Write the reset manager register to cause reset
*/
void reset_cpu(ulong addr)
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 014/172] arm: socfpga: reset: Add SDMMC, QSPI and DMA defines
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (12 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 013/172] arm: socfpga: reset: Add function to reset add peripherals Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 015/172] arm: socfpga: clock: Get rid of cm_config_t typedef Marek Vasut
` (159 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Add SDMMC, QSPI and DMA reset defines. These are needed by SPL
so that we can boot from SD card and QSPI.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 457c4b8..8e59578 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -69,6 +69,9 @@ struct socfpga_reset_manager {
#define RSTMGR_UART0 RSTMGR_DEFINE(1, 16)
#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 18)
#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 19)
+#define RSTMGR_QSPI RSTMGR_DEFINE(0, 5)
+#define RSTMGR_SDMMC RSTMGR_DEFINE(0, 22)
+#define RSTMGR_DMA RSTMGR_DEFINE(0, 28)
#define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
/* Create a human-readable reference to SoCFPGA reset. */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 015/172] arm: socfpga: clock: Get rid of cm_config_t typedef
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (13 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 014/172] arm: socfpga: reset: Add SDMMC, QSPI and DMA defines Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 016/172] arm: socfpga: clock: Clean up pll_config.h Marek Vasut
` (158 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Get rid of this cryptic typedef and replace it with explicit struct cm_config.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/clock_manager.c | 2 +-
arch/arm/mach-socfpga/include/mach/clock_manager.h | 6 +++---
arch/arm/mach-socfpga/spl.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index fa3b93a..74aa1d9 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -88,7 +88,7 @@ static void cm_write_with_phase(uint32_t value,
* Ungate clocks
*/
-void cm_basic_init(const cm_config_t *cfg)
+void cm_basic_init(const struct cm_config *cfg)
{
uint32_t start, timeout;
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 5449726..8a3362f 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -17,7 +17,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
unsigned int cm_get_spi_controller_clk_hz(void);
#endif
-typedef struct {
+struct cm_config {
/* main group */
uint32_t main_vco_base;
uint32_t mpuclk;
@@ -49,9 +49,9 @@ typedef struct {
uint32_t ddr2xdqsclk;
uint32_t ddrdqclk;
uint32_t s2fuser2clk;
-} cm_config_t;
+};
-extern void cm_basic_init(const cm_config_t *cfg);
+extern void cm_basic_init(const struct cm_config *cfg);
struct socfpga_clock_manager_main_pll {
u32 vco;
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 400e463..6850fbf 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -85,7 +85,7 @@ void spl_board_init(void)
{
unsigned long sdram_size;
#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
- cm_config_t cm_default_cfg = {
+ struct cm_config cm_default_cfg = {
/* main group */
MAIN_VCO_BASE,
(CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 016/172] arm: socfpga: clock: Clean up pll_config.h
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (14 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 015/172] arm: socfpga: clock: Get rid of cm_config_t typedef Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 017/172] arm: socfpga: scan: Staticize scan_mgr_io_scan_chain_prg() Marek Vasut
` (157 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Extract the clock configuration horribleness caused by pll_config.h in
the following manner.
First of all, introduce a few new accessors which return values of
various clocks used in clock_manager.c and use them in clock_manager.c .
These accessors replace those few macros which came from pll_config.h
originally. Also introduce an accessor which returns the struct cm_config
default configuration for the clock manager used in SPL.
The accessors are implemented in a board-specific wrap_pll_config.c
file, whose sole purpose is to include the qts-generated pll_config.h
and provide only the necessary values to the clock manager.
The purpose of this design is to limit the scope of inclusion for the
pll_config.h , which thus far was included build-wide and poluted the
namespace. With this change, the inclusion is limited to just the new
wrap_pll_config.c file, which in turn provides three simple functions
for the clock_manager.c to use.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/clock_manager.c | 28 ++--
arch/arm/mach-socfpga/include/mach/clock_manager.h | 8 +-
arch/arm/mach-socfpga/spl.c | 114 +---------------
board/altera/socfpga/Makefile | 2 +-
board/altera/socfpga/wrap_pll_config.c | 144 +++++++++++++++++++++
include/configs/socfpga_arria5.h | 1 -
include/configs/socfpga_cyclone5.h | 1 -
7 files changed, 169 insertions(+), 129 deletions(-)
create mode 100644 board/altera/socfpga/wrap_pll_config.c
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index 74aa1d9..1341df4 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -88,7 +88,7 @@ static void cm_write_with_phase(uint32_t value,
* Ungate clocks
*/
-void cm_basic_init(const struct cm_config *cfg)
+void cm_basic_init(const struct cm_config * const cfg)
{
uint32_t start, timeout;
@@ -336,7 +336,7 @@ static unsigned int cm_get_main_vco_clk_hz(void)
/* get the main VCO clock */
reg = readl(&clock_manager_base->main_pll.vco);
- clock = CONFIG_HPS_CLK_OSC1_HZ;
+ clock = cm_get_osc_clk_hz(1);
clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
@@ -354,11 +354,11 @@ static unsigned int cm_get_per_vco_clk_hz(void)
reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
if (reg == CLKMGR_VCO_SSRC_EOSC1)
- clock = CONFIG_HPS_CLK_OSC1_HZ;
+ clock = cm_get_osc_clk_hz(1);
else if (reg == CLKMGR_VCO_SSRC_EOSC2)
- clock = CONFIG_HPS_CLK_OSC2_HZ;
+ clock = cm_get_osc_clk_hz(2);
else if (reg == CLKMGR_VCO_SSRC_F2S)
- clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+ clock = cm_get_f2s_per_ref_clk_hz();
/* get the PER VCO clock */
reg = readl(&clock_manager_base->per_pll.vco);
@@ -393,11 +393,11 @@ unsigned long cm_get_sdram_clk_hz(void)
reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
if (reg == CLKMGR_VCO_SSRC_EOSC1)
- clock = CONFIG_HPS_CLK_OSC1_HZ;
+ clock = cm_get_osc_clk_hz(1);
else if (reg == CLKMGR_VCO_SSRC_EOSC2)
- clock = CONFIG_HPS_CLK_OSC2_HZ;
+ clock = cm_get_osc_clk_hz(2);
else if (reg == CLKMGR_VCO_SSRC_F2S)
- clock = CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
+ clock = cm_get_f2s_sdr_ref_clk_hz();
/* get the SDRAM VCO clock */
reg = readl(&clock_manager_base->sdr_pll.vco);
@@ -459,7 +459,7 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
- clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+ clock = cm_get_f2s_per_ref_clk_hz();
} else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
clock = cm_get_main_vco_clk_hz();
@@ -489,7 +489,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
- clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+ clock = cm_get_f2s_per_ref_clk_hz();
} else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
clock = cm_get_main_vco_clk_hz();
@@ -524,10 +524,10 @@ static void cm_print_clock_quick_summary(void)
{
printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
printf("DDR %10ld kHz\n", cm_get_sdram_clk_hz() / 1000);
- printf("EOSC1 %8d kHz\n", CONFIG_HPS_CLK_OSC1_HZ / 1000);
- printf("EOSC2 %8d kHz\n", CONFIG_HPS_CLK_OSC2_HZ / 1000);
- printf("F2S_SDR_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_SDR_REF_HZ / 1000);
- printf("F2S_PER_REF %8d kHz\n", CONFIG_HPS_CLK_F2S_PER_REF_HZ / 1000);
+ printf("EOSC1 %8d kHz\n", cm_get_osc_clk_hz(1) / 1000);
+ printf("EOSC2 %8d kHz\n", cm_get_osc_clk_hz(2) / 1000);
+ printf("F2S_SDR_REF %8d kHz\n", cm_get_f2s_sdr_ref_clk_hz() / 1000);
+ printf("F2S_PER_REF %8d kHz\n", cm_get_f2s_per_ref_clk_hz() / 1000);
printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
printf("UART %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 8a3362f..2675951 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -15,6 +15,12 @@ unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
unsigned int cm_get_spi_controller_clk_hz(void);
+const unsigned int cm_get_osc_clk_hz(const int osc);
+const unsigned int cm_get_f2s_per_ref_clk_hz(void);
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
+
+/* Clock configuration accessors */
+const struct cm_config * const cm_get_default_config(void);
#endif
struct cm_config {
@@ -51,7 +57,7 @@ struct cm_config {
uint32_t s2fuser2clk;
};
-extern void cm_basic_init(const struct cm_config *cfg);
+void cm_basic_init(const struct cm_config * const cfg);
struct socfpga_clock_manager_main_pll {
u32 vco;
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 6850fbf..1fecfdc 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -23,31 +23,6 @@ DECLARE_GLOBAL_DATA_PTR;
static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-#define MAIN_VCO_BASE ( \
- (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
- CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
- (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \
- CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
- )
-
-#define PERI_VCO_BASE ( \
- (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \
- CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \
- (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \
- CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \
- (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \
- CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
- )
-
-#define SDR_VCO_BASE ( \
- (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \
- CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \
- (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \
- CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \
- (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \
- CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
- )
-
void board_init_f(ulong dummy)
{
struct socfpga_system_manager *sysmgr_regs =
@@ -85,91 +60,8 @@ void spl_board_init(void)
{
unsigned long sdram_size;
#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
- struct cm_config cm_default_cfg = {
- /* main group */
- MAIN_VCO_BASE,
- (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
- CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
- CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
- CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
- CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
- CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
- CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
- CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
- CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
- CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
- CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
- CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
- CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
- CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
- CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
- CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
-
- /* peripheral group */
- PERI_VCO_BASE,
- (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
- CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
- CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
- CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
- CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
- CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
- CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
- CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
- CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
- CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
- CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
- (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
- CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
- (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
- CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
- CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
- CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
-
- /* sdram pll group */
- SDR_VCO_BASE,
- (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
- CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
- CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
- (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
- CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
- CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
- (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
- CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
- CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
- (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
- CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
- CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
-
- };
+ const struct cm_config *cm_default_cfg = cm_get_default_config();
+#endif
debug("Freezing all I/O banks\n");
/* freeze all IO banks */
@@ -183,7 +75,7 @@ void spl_board_init(void)
debug("Reconfigure Clock Manager\n");
/* reconfigure the PLLs */
- cm_basic_init(&cm_default_cfg);
+ cm_basic_init(cm_default_cfg);
/* Enable bootrom to configure IOs. */
sysmgr_enable_warmrstcfgio();
diff --git a/board/altera/socfpga/Makefile b/board/altera/socfpga/Makefile
index d960394..f541227 100644
--- a/board/altera/socfpga/Makefile
+++ b/board/altera/socfpga/Makefile
@@ -6,5 +6,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := socfpga.o
+obj-y := socfpga.o wrap_pll_config.o
obj-$(CONFIG_SPL_BUILD) += qts/
diff --git a/board/altera/socfpga/wrap_pll_config.c b/board/altera/socfpga/wrap_pll_config.c
new file mode 100644
index 0000000..8dbff68
--- /dev/null
+++ b/board/altera/socfpga/wrap_pll_config.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/clock_manager.h>
+#include "qts/pll_config.h"
+
+#define MAIN_VCO_BASE ( \
+ (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
+ CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
+ (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \
+ CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
+ )
+
+#define PERI_VCO_BASE ( \
+ (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \
+ CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \
+ (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \
+ CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \
+ (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \
+ CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
+ )
+
+#define SDR_VCO_BASE ( \
+ (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \
+ CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \
+ (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \
+ CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \
+ (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \
+ CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
+ )
+
+static const struct cm_config cm_default_cfg = {
+ /* main group */
+ MAIN_VCO_BASE,
+ (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
+ CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
+ CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
+ CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
+ CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
+ CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
+ CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
+ CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
+ (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
+ CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
+ (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
+ CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
+ (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
+ CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
+ CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
+ (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
+ CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
+ CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
+ (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
+ CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
+ (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
+ CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
+
+ /* peripheral group */
+ PERI_VCO_BASE,
+ (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
+ CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
+ CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
+ CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
+ CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
+ CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
+ CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
+ CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
+ (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
+ CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
+ (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
+ CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
+ (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
+ CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
+ CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
+ (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
+ CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
+ (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
+ CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
+ (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
+ CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
+
+ /* sdram pll group */
+ SDR_VCO_BASE,
+ (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
+ CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
+ (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
+ CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
+ (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
+ CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
+ (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
+ CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
+ (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
+ CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
+ (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
+ CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
+ (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
+ CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
+ (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
+ CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
+};
+
+const struct cm_config * const cm_get_default_config(void)
+{
+ return &cm_default_cfg;
+}
+
+const unsigned int cm_get_osc_clk_hz(const int osc)
+{
+ if (osc == 1)
+ return CONFIG_HPS_CLK_OSC1_HZ;
+ else if (osc == 2)
+ return CONFIG_HPS_CLK_OSC2_HZ;
+ else
+ return 0;
+}
+
+const unsigned int cm_get_f2s_per_ref_clk_hz(void)
+{
+ return CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+}
+
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void)
+{
+ return CONFIG_HPS_CLK_F2S_SDR_REF_HZ;
+}
diff --git a/include/configs/socfpga_arria5.h b/include/configs/socfpga_arria5.h
index 48744bc..861aeed 100644
--- a/include/configs/socfpga_arria5.h
+++ b/include/configs/socfpga_arria5.h
@@ -9,7 +9,6 @@
#include <asm/arch/socfpga_base_addrs.h>
#include "../../board/altera/socfpga/qts/pinmux_config.h"
#include "../../board/altera/socfpga/qts/iocsr_config.h"
-#include "../../board/altera/socfpga/qts/pll_config.h"
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index e8cd11d..75bc162 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -9,7 +9,6 @@
#include <asm/arch/socfpga_base_addrs.h>
#include "../../board/altera/socfpga/qts/pinmux_config.h"
#include "../../board/altera/socfpga/qts/iocsr_config.h"
-#include "../../board/altera/socfpga/qts/pll_config.h"
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 017/172] arm: socfpga: scan: Staticize scan_mgr_io_scan_chain_prg()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (15 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 016/172] arm: socfpga: clock: Clean up pll_config.h Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 018/172] arm: socfpga: scan: Zap redundant params in scan_mgr_io_scan_chain_prg() Marek Vasut
` (156 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
This function is never used outside of scan_manager.c , so make it static.
Zap the prototype in scan_manager.h and move the documentation above the
function. Make the documentation kerneldoc compliant.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/include/mach/scan_manager.h | 11 -----------
arch/arm/mach-socfpga/scan_manager.c | 14 +++++++++-----
2 files changed, 9 insertions(+), 16 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/scan_manager.h b/arch/arm/mach-socfpga/include/mach/scan_manager.h
index 1155fd3..3602ace 100644
--- a/arch/arm/mach-socfpga/include/mach/scan_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/scan_manager.h
@@ -68,17 +68,6 @@ struct socfpga_scan_manager {
#define SCANMGR_STAT_ACTIVE_GET(x) (((x) & 0x80000000) >> 31)
#define SCANMGR_STAT_WFIFOCNT_GET(x) (((x) & 0x70000000) >> 28)
-/*
- * Program HPS IO Scan Chain
- * io_scan_chain_id - IO scan chain ID
- * io_scan_chain_len_in_bits - IO scan chain length in bits
- * iocsr_scan_chain - IO scan chain table
- */
-uint32_t scan_mgr_io_scan_chain_prg(
- uint32_t io_scan_chain_id,
- uint32_t io_scan_chain_len_in_bits,
- const uint32_t *iocsr_scan_chain);
-
extern const uint32_t iocsr_scan_chain0_table[
((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)];
extern const uint32_t iocsr_scan_chain1_table[
diff --git a/arch/arm/mach-socfpga/scan_manager.c b/arch/arm/mach-socfpga/scan_manager.c
index a820b1b..ab7aaec 100644
--- a/arch/arm/mach-socfpga/scan_manager.c
+++ b/arch/arm/mach-socfpga/scan_manager.c
@@ -38,11 +38,15 @@ static inline uint32_t scan_chain_engine_is_idle(uint32_t max_iter)
return 1;
}
-/* Program HPS IO Scan Chain */
-uint32_t scan_mgr_io_scan_chain_prg(
- uint32_t io_scan_chain_id,
- uint32_t io_scan_chain_len_in_bits,
- const uint32_t *iocsr_scan_chain)
+/**
+ * scan_mgr_io_scan_chain_prg() - Program HPS IO Scan Chain
+ * @io_scan_chain_id: IO scan chain ID
+ * @io_scan_chain_len_in_bits: IO scan chain length in bits
+ * @iocsr_scan_chain: IO scan chain table
+ */
+static int scan_mgr_io_scan_chain_prg(const unsigned int io_scan_chain_id,
+ uint32_t io_scan_chain_len_in_bits,
+ const uint32_t *iocsr_scan_chain)
{
uint16_t tdi_tdo_header;
uint32_t io_program_iter;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 018/172] arm: socfpga: scan: Zap redundant params in scan_mgr_io_scan_chain_prg()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (16 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 017/172] arm: socfpga: scan: Staticize scan_mgr_io_scan_chain_prg() Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 019/172] arm: socfpga: scan: Zap iocsr_scan_chain*_table() Marek Vasut
` (155 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
It is sufficient to pass in the scan chain ID into the function to determine
the remaining two parameters, so drop those params and determine them locally
in the function. The big-ish switch in the function is temporary and will be
replaced by a proper function call in subsequent patch.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/scan_manager.c | 39 ++++++++++++++++++++++++------------
1 file changed, 26 insertions(+), 13 deletions(-)
diff --git a/arch/arm/mach-socfpga/scan_manager.c b/arch/arm/mach-socfpga/scan_manager.c
index ab7aaec..135f9f3 100644
--- a/arch/arm/mach-socfpga/scan_manager.c
+++ b/arch/arm/mach-socfpga/scan_manager.c
@@ -41,12 +41,8 @@ static inline uint32_t scan_chain_engine_is_idle(uint32_t max_iter)
/**
* scan_mgr_io_scan_chain_prg() - Program HPS IO Scan Chain
* @io_scan_chain_id: IO scan chain ID
- * @io_scan_chain_len_in_bits: IO scan chain length in bits
- * @iocsr_scan_chain: IO scan chain table
*/
-static int scan_mgr_io_scan_chain_prg(const unsigned int io_scan_chain_id,
- uint32_t io_scan_chain_len_in_bits,
- const uint32_t *iocsr_scan_chain)
+static int scan_mgr_io_scan_chain_prg(const unsigned int io_scan_chain_id)
{
uint16_t tdi_tdo_header;
uint32_t io_program_iter;
@@ -54,6 +50,27 @@ static int scan_mgr_io_scan_chain_prg(const unsigned int io_scan_chain_id,
uint32_t residual;
uint32_t i;
uint32_t index = 0;
+ uint32_t io_scan_chain_len_in_bits,
+ const uint32_t *iocsr_scan_chain;
+
+ switch (io_scan_chain_id) {
+ case 0:
+ io_scan_chain_len_in_bits = CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH;
+ iocsr_scan_chain = iocsr_scan_chain0_table;
+ break;
+ case 1:
+ io_scan_chain_len_in_bits = CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH;
+ iocsr_scan_chain = iocsr_scan_chain1_table;
+ break;
+ case 2:
+ io_scan_chain_len_in_bits = CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH;
+ iocsr_scan_chain = iocsr_scan_chain2_table;
+ break;
+ case 3:
+ io_scan_chain_len_in_bits = CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH;
+ iocsr_scan_chain = iocsr_scan_chain3_table;
+ break;
+ }
/*
* De-assert reinit if the IO scan chain is intended for HIO. In
@@ -201,13 +218,9 @@ int scan_mgr_configure_iocsr(void)
int status = 0;
/* configure the IOCSR through scan chain */
- status |= scan_mgr_io_scan_chain_prg(0,
- CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH, iocsr_scan_chain0_table);
- status |= scan_mgr_io_scan_chain_prg(1,
- CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH, iocsr_scan_chain1_table);
- status |= scan_mgr_io_scan_chain_prg(2,
- CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH, iocsr_scan_chain2_table);
- status |= scan_mgr_io_scan_chain_prg(3,
- CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH, iocsr_scan_chain3_table);
+ status |= scan_mgr_io_scan_chain_prg(0);
+ status |= scan_mgr_io_scan_chain_prg(1);
+ status |= scan_mgr_io_scan_chain_prg(2);
+ status |= scan_mgr_io_scan_chain_prg(3);
return status;
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 019/172] arm: socfpga: scan: Zap iocsr_scan_chain*_table()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (17 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 018/172] arm: socfpga: scan: Zap redundant params in scan_mgr_io_scan_chain_prg() Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 020/172] arm: socfpga: system: Rework sysmgr_enable_warmrstcfgio() Marek Vasut
` (154 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Introduce accessor iocsr_get_config_table() for retrieving IOCSR config
tables. This patch is again trimming down the namespace polution.
The IOCSR config tables are used only by scan manager, they are generated
by qts and are board specific. Before this patch, the approach to use
these tables in scan manager was to define an extern variable to silence
the compiler and compile board-specific iocsr_config.c into U-Boot which
defined those extern variables. Furthermore, since these are tables and
the scan manager needs to know the size of those tables, iocsr_config.h
is included build-wide.
This patch wraps all this into a single accessor which takes the scan
chain ID and returns pointer to the table and it's size. All this is
wrapped in wrap_iocsr_config.c board-specific file. The file includes
the iocsr_config.c (!) to access the original tables and transitively
iocsr_config.h . It is thus no longer necessary to include iocsr_config.h
build-wide and the namespace polution is trimmed some more.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/include/mach/scan_manager.h | 12 ++-----
arch/arm/mach-socfpga/scan_manager.c | 30 +++++------------
board/altera/socfpga/Makefile | 2 +-
board/altera/socfpga/qts/Makefile | 2 +-
board/altera/socfpga/wrap_iocsr_config.c | 41 +++++++++++++++++++++++
include/configs/socfpga_arria5.h | 1 -
include/configs/socfpga_cyclone5.h | 1 -
7 files changed, 54 insertions(+), 35 deletions(-)
create mode 100644 board/altera/socfpga/wrap_iocsr_config.c
diff --git a/arch/arm/mach-socfpga/include/mach/scan_manager.h b/arch/arm/mach-socfpga/include/mach/scan_manager.h
index 3602ace..94ad50b 100644
--- a/arch/arm/mach-socfpga/include/mach/scan_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/scan_manager.h
@@ -68,15 +68,9 @@ struct socfpga_scan_manager {
#define SCANMGR_STAT_ACTIVE_GET(x) (((x) & 0x80000000) >> 31)
#define SCANMGR_STAT_WFIFOCNT_GET(x) (((x) & 0x70000000) >> 28)
-extern const uint32_t iocsr_scan_chain0_table[
- ((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)];
-extern const uint32_t iocsr_scan_chain1_table[
- ((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)];
-extern const uint32_t iocsr_scan_chain2_table[
- ((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)];
-extern const uint32_t iocsr_scan_chain3_table[
- ((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)];
-
int scan_mgr_configure_iocsr(void);
+int iocsr_get_config_table(const unsigned int chain_id,
+ const unsigned long **table,
+ unsigned int *table_len);
#endif /* _SCAN_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/scan_manager.c b/arch/arm/mach-socfpga/scan_manager.c
index 135f9f3..ec0c630 100644
--- a/arch/arm/mach-socfpga/scan_manager.c
+++ b/arch/arm/mach-socfpga/scan_manager.c
@@ -48,29 +48,15 @@ static int scan_mgr_io_scan_chain_prg(const unsigned int io_scan_chain_id)
uint32_t io_program_iter;
uint32_t io_scan_chain_data_residual;
uint32_t residual;
- uint32_t i;
+ uint32_t i, ret;
uint32_t index = 0;
- uint32_t io_scan_chain_len_in_bits,
- const uint32_t *iocsr_scan_chain;
-
- switch (io_scan_chain_id) {
- case 0:
- io_scan_chain_len_in_bits = CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH;
- iocsr_scan_chain = iocsr_scan_chain0_table;
- break;
- case 1:
- io_scan_chain_len_in_bits = CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH;
- iocsr_scan_chain = iocsr_scan_chain1_table;
- break;
- case 2:
- io_scan_chain_len_in_bits = CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH;
- iocsr_scan_chain = iocsr_scan_chain2_table;
- break;
- case 3:
- io_scan_chain_len_in_bits = CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH;
- iocsr_scan_chain = iocsr_scan_chain3_table;
- break;
- }
+ uint32_t io_scan_chain_len_in_bits;
+ const unsigned long *iocsr_scan_chain;
+
+ ret = iocsr_get_config_table(io_scan_chain_id, &iocsr_scan_chain,
+ &io_scan_chain_len_in_bits);
+ if (ret)
+ return 1;
/*
* De-assert reinit if the IO scan chain is intended for HIO. In
diff --git a/board/altera/socfpga/Makefile b/board/altera/socfpga/Makefile
index f541227..7cd4ef9 100644
--- a/board/altera/socfpga/Makefile
+++ b/board/altera/socfpga/Makefile
@@ -7,4 +7,4 @@
#
obj-y := socfpga.o wrap_pll_config.o
-obj-$(CONFIG_SPL_BUILD) += qts/
+obj-$(CONFIG_SPL_BUILD) += qts/ wrap_iocsr_config.o
diff --git a/board/altera/socfpga/qts/Makefile b/board/altera/socfpga/qts/Makefile
index dbcedd8..cd8fecc 100644
--- a/board/altera/socfpga/qts/Makefile
+++ b/board/altera/socfpga/qts/Makefile
@@ -4,4 +4,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += pinmux_config.o iocsr_config.o
+obj-y += pinmux_config.o
diff --git a/board/altera/socfpga/wrap_iocsr_config.c b/board/altera/socfpga/wrap_iocsr_config.c
new file mode 100644
index 0000000..49e9228
--- /dev/null
+++ b/board/altera/socfpga/wrap_iocsr_config.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/clock_manager.h>
+/*
+ * Yes, dear reader, we're including a C file here, this is no mistake :-)
+ */
+#include "qts/iocsr_config.c"
+
+int iocsr_get_config_table(const unsigned int chain_id,
+ const unsigned long **table,
+ unsigned int *table_len)
+{
+ switch (chain_id) {
+ case 0:
+ *table = iocsr_scan_chain0_table;
+ *table_len = CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH;
+ break;
+ case 1:
+ *table = iocsr_scan_chain1_table;
+ *table_len = CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH;
+ break;
+ case 2:
+ *table = iocsr_scan_chain2_table;
+ *table_len = CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH;
+ break;
+ case 3:
+ *table = iocsr_scan_chain3_table;
+ *table_len = CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
diff --git a/include/configs/socfpga_arria5.h b/include/configs/socfpga_arria5.h
index 861aeed..758912c 100644
--- a/include/configs/socfpga_arria5.h
+++ b/include/configs/socfpga_arria5.h
@@ -8,7 +8,6 @@
#include <asm/arch/socfpga_base_addrs.h>
#include "../../board/altera/socfpga/qts/pinmux_config.h"
-#include "../../board/altera/socfpga/qts/iocsr_config.h"
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 75bc162..e7938f5 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -8,7 +8,6 @@
#include <asm/arch/socfpga_base_addrs.h>
#include "../../board/altera/socfpga/qts/pinmux_config.h"
-#include "../../board/altera/socfpga/qts/iocsr_config.h"
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 020/172] arm: socfpga: system: Rework sysmgr_enable_warmrstcfgio()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (18 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 019/172] arm: socfpga: scan: Zap iocsr_scan_chain*_table() Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 021/172] arm: socfpga: system: Clean up pinmux_config.c Marek Vasut
` (153 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Rework sysmgr_enable_warmrstcfgio() into sysmgr_config_warmrstcfgio(),
which allows both enabling and disabling the warm reset config I/O
functionality.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/include/mach/system_manager.h | 2 +-
arch/arm/mach-socfpga/spl.c | 2 +-
arch/arm/mach-socfpga/system_manager.c | 10 +++++++---
3 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 51d9815..de05aaf 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -10,7 +10,7 @@
#ifndef __ASSEMBLY__
void sysmgr_pinmux_init(void);
-void sysmgr_enable_warmrstcfgio(void);
+void sysmgr_config_warmrstcfgio(int enable);
/* declaration for handoff table type */
extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM];
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 1fecfdc..fd54ea9 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -78,7 +78,7 @@ void spl_board_init(void)
cm_basic_init(cm_default_cfg);
/* Enable bootrom to configure IOs. */
- sysmgr_enable_warmrstcfgio();
+ sysmgr_config_warmrstcfgio(1);
/* configure the IOCSR / IO buffer settings */
if (scan_mgr_configure_iocsr())
diff --git a/arch/arm/mach-socfpga/system_manager.c b/arch/arm/mach-socfpga/system_manager.c
index 8126e0d..5ed47c3 100644
--- a/arch/arm/mach-socfpga/system_manager.c
+++ b/arch/arm/mach-socfpga/system_manager.c
@@ -70,8 +70,12 @@ void sysmgr_pinmux_init(void)
/*
* This bit allows the bootrom to configure the IOs after a warm reset.
*/
-void sysmgr_enable_warmrstcfgio(void)
+void sysmgr_config_warmrstcfgio(int enable)
{
- setbits_le32(&sysmgr_regs->romcodegrp_ctrl,
- SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
+ if (enable)
+ setbits_le32(&sysmgr_regs->romcodegrp_ctrl,
+ SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
+ else
+ clrbits_le32(&sysmgr_regs->romcodegrp_ctrl,
+ SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 021/172] arm: socfpga: system: Clean up pinmux_config.c
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (19 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 020/172] arm: socfpga: system: Rework sysmgr_enable_warmrstcfgio() Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 022/172] arm: socfpga: spl: Toggle warm reset config I/O bit Marek Vasut
` (152 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Implement new accessor, sysmgr_get_pinmux_table(), used to obtain pinmux
table and it's size from the QTS-generated pinmux_config.c. The target
here is again to get rid of poluting global namespace by including the
pinmux_config.h into it.
Furthermore, the pinmux_config.h declares some CONFIG_HPS_* macros,
which are explicitly useless to us in U-Boot. Instead, U-Boot does
use DT to detect exactly these configuration options. This patch
makes sure that while this QTS-generated file can stay in the tree,
these obscure macros do not ooze into the namespace anymore.
Signed-off-by: Marek Vasut <marex@denx.de>
---
.../arm/mach-socfpga/include/mach/system_manager.h | 5 ++--
arch/arm/mach-socfpga/system_manager.c | 6 +++-
board/altera/socfpga/Makefile | 2 +-
board/altera/socfpga/qts/Makefile | 7 -----
board/altera/socfpga/wrap_pinmux_config.c | 35 ++++++++++++++++++++++
include/configs/socfpga_arria5.h | 1 -
include/configs/socfpga_cyclone5.h | 1 -
7 files changed, 43 insertions(+), 14 deletions(-)
delete mode 100644 board/altera/socfpga/qts/Makefile
create mode 100644 board/altera/socfpga/wrap_pinmux_config.c
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h
index de05aaf..46af30b 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -12,9 +12,8 @@
void sysmgr_pinmux_init(void);
void sysmgr_config_warmrstcfgio(int enable);
-/* declaration for handoff table type */
-extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM];
-
+void sysmgr_get_pinmux_table(const unsigned long **table,
+ unsigned int *table_len);
#endif
struct socfpga_system_manager {
diff --git a/arch/arm/mach-socfpga/system_manager.c b/arch/arm/mach-socfpga/system_manager.c
index 5ed47c3..744ec32 100644
--- a/arch/arm/mach-socfpga/system_manager.c
+++ b/arch/arm/mach-socfpga/system_manager.c
@@ -57,9 +57,13 @@ static void populate_sysmgr_fpgaintf_module(void)
void sysmgr_pinmux_init(void)
{
uint32_t regs = (uint32_t)&sysmgr_regs->emacio[0];
+ const unsigned long *sys_mgr_init_table;
+ unsigned int len;
int i;
- for (i = 0; i < ARRAY_SIZE(sys_mgr_init_table); i++) {
+ sysmgr_get_pinmux_table(&sys_mgr_init_table, &len);
+
+ for (i = 0; i < len; i++) {
writel(sys_mgr_init_table[i], regs);
regs += sizeof(regs);
}
diff --git a/board/altera/socfpga/Makefile b/board/altera/socfpga/Makefile
index 7cd4ef9..640f629 100644
--- a/board/altera/socfpga/Makefile
+++ b/board/altera/socfpga/Makefile
@@ -7,4 +7,4 @@
#
obj-y := socfpga.o wrap_pll_config.o
-obj-$(CONFIG_SPL_BUILD) += qts/ wrap_iocsr_config.o
+obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o
diff --git a/board/altera/socfpga/qts/Makefile b/board/altera/socfpga/qts/Makefile
deleted file mode 100644
index cd8fecc..0000000
--- a/board/altera/socfpga/qts/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2015 Marek Vasut <marex@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += pinmux_config.o
diff --git a/board/altera/socfpga/wrap_pinmux_config.c b/board/altera/socfpga/wrap_pinmux_config.c
new file mode 100644
index 0000000..b33e2ca
--- /dev/null
+++ b/board/altera/socfpga/wrap_pinmux_config.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+/*
+ * Yes, dear reader, we're including a C file here, this is no mistake.
+ * But this time around, we do even more perverse hacking here to be
+ * compatible with QTS headers and obtain reasonably nice results too.
+ *
+ * First, we define _PRELOADER_PINMUX_CONFIG_H_, which will neutralise
+ * the pinmux_config.h inclusion in pinmux_config.c . Since we are
+ * probing everything from DT, we do NOT want those macros from the
+ * pinmux_config.h to ooze into our build system, anywhere, ever. So
+ * we nip it at the bud.
+ *
+ * Next, pinmux_config.c needs CONFIG_HPS_PINMUX_NUM and uses it to
+ * specify sized array explicitly. Instead, we want to use ARRAY_SIZE
+ * to figure out the size of the array, so define this macro as an
+ * empty one, so that the preprocessor optimizes things such that the
+ * arrays are not sized by default.
+ */
+#define _PRELOADER_PINMUX_CONFIG_H_
+#define CONFIG_HPS_PINMUX_NUM
+#include "qts/pinmux_config.c"
+
+void sysmgr_get_pinmux_table(const unsigned long **table,
+ unsigned int *table_len)
+{
+ *table = sys_mgr_init_table;
+ *table_len = ARRAY_SIZE(sys_mgr_init_table);
+}
diff --git a/include/configs/socfpga_arria5.h b/include/configs/socfpga_arria5.h
index 758912c..329ca35 100644
--- a/include/configs/socfpga_arria5.h
+++ b/include/configs/socfpga_arria5.h
@@ -7,7 +7,6 @@
#define __CONFIG_SOCFPGA_ARRIA5_H__
#include <asm/arch/socfpga_base_addrs.h>
-#include "../../board/altera/socfpga/qts/pinmux_config.h"
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index e7938f5..c2922dd 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -7,7 +7,6 @@
#define __CONFIG_SOCFPGA_CYCLONE5_H__
#include <asm/arch/socfpga_base_addrs.h>
-#include "../../board/altera/socfpga/qts/pinmux_config.h"
/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 022/172] arm: socfpga: spl: Toggle warm reset config I/O bit
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (20 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 021/172] arm: socfpga: system: Clean up pinmux_config.c Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 023/172] arm: socfpga: spl: Configure SCU and NIC-301 early Marek Vasut
` (151 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Synchronise the SPL behavior with the original Altera code and
toggle the Warm Reset Config I/O bit accordingly.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/spl.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index fd54ea9..8345975 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -84,8 +84,13 @@ void spl_board_init(void)
if (scan_mgr_configure_iocsr())
hang();
+ sysmgr_config_warmrstcfgio(0);
+
/* configure the pin muxing through system manager */
+ sysmgr_config_warmrstcfgio(1);
sysmgr_pinmux_init();
+ sysmgr_config_warmrstcfgio(0);
+
#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
/* de-assert reset for peripherals and bridges based on handoff */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 023/172] arm: socfpga: spl: Configure SCU and NIC-301 early
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (21 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 022/172] arm: socfpga: spl: Toggle warm reset config I/O bit Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 024/172] arm: socfpga: spl: Add missing reset logic Marek Vasut
` (150 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Configure the ARM SCU and NIC301 very early. The ARM SCU SNSAC register
must be configured, so we can access all peripherals. The NIC-301 must
be configured so that the BootROM is not mapped into the SDRAM address
space.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/spl.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 8345975..15fee0a 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -17,11 +17,27 @@
#include <asm/arch/clock_manager.h>
#include <asm/arch/scan_manager.h>
#include <asm/arch/sdram.h>
+#include <asm/arch/scu.h>
+#include <asm/arch/nic301.h>
DECLARE_GLOBAL_DATA_PTR;
static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+static struct scu_registers *scu_regs =
+ (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
+static struct nic301_registers *nic301_regs =
+ (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
+
+static void socfpga_nic301_slave_ns(void)
+{
+ writel(0x1, &nic301_regs->lwhps2fpgaregs);
+ writel(0x1, &nic301_regs->hps2fpgaregs);
+ writel(0x1, &nic301_regs->acp);
+ writel(0x1, &nic301_regs->rom);
+ writel(0x1, &nic301_regs->ocram);
+ writel(0x1, &nic301_regs->sdrdata);
+}
void board_init_f(ulong dummy)
{
@@ -42,7 +58,13 @@ void board_init_f(ulong dummy)
memset(__bss_start, 0, __bss_end - __bss_start);
+ socfpga_nic301_slave_ns();
+
+ /* Configure ARM MPU SNSAC register. */
+ setbits_le32(&scu_regs->sacr, 0xfff);
+
/* Remap SDRAM to 0x0 */
+ writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
writel(0x1, &pl310->pl310_addr_filter_start);
board_init_r(NULL, 0);
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 024/172] arm: socfpga: spl: Add missing reset logic
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (22 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 023/172] arm: socfpga: spl: Configure SCU and NIC-301 early Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 025/172] arm: socfpga: spl: Merge spl_board_init() into board_init_f() Marek Vasut
` (149 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Make sure that all the peripherals are correctly reset and then
brought out of reset in the SPL. Not going through proper reset
cycle might leave the IP blocks in inconsistent state.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/spl.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 15fee0a..f134bb7 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -89,6 +89,11 @@ void spl_board_init(void)
/* freeze all IO banks */
sys_mgr_frzctrl_freeze_req();
+ /* Put everything into reset but L4WD0. */
+ socfpga_per_reset_all();
+ /* Put FPGA bridges into reset too. */
+ socfpga_bridges_reset(1);
+
socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
@@ -115,8 +120,9 @@ void spl_board_init(void)
#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
- /* de-assert reset for peripherals and bridges based on handoff */
+ /* De-assert reset for peripherals and bridges based on handoff */
reset_deassert_peripherals_handoff();
+ socfpga_bridges_reset(0);
debug("Unfreezing/Thaw all I/O banks\n");
/* unfreeze / thaw all IO banks */
@@ -145,4 +151,6 @@ void spl_board_init(void)
puts("SDRAM size check failed!\n");
hang();
}
+
+ socfpga_bridges_reset(1);
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 025/172] arm: socfpga: spl: Merge spl_board_init() into board_init_f()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (23 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 024/172] arm: socfpga: spl: Add missing reset logic Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 026/172] arm: socfpga: spl: Remove custom linker script Marek Vasut
` (148 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
The code in spl_board_init() should have been in board_init_f()
from the beginning, since it is code which configures system and
then starts DRAM. Thus, it cannot be in spl_board_init(), which
is called from board_init_r() , which already expects a working
DRAM.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/spl.c | 29 ++++++++++++-----------------
include/configs/socfpga_common.h | 1 -
2 files changed, 12 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index f134bb7..ea0ed1a 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -29,6 +29,11 @@ static struct scu_registers *scu_regs =
static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_RAM;
+}
+
static void socfpga_nic301_slave_ns(void)
{
writel(0x1, &nic301_regs->lwhps2fpgaregs);
@@ -41,9 +46,14 @@ static void socfpga_nic301_slave_ns(void)
void board_init_f(ulong dummy)
{
+#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+ const struct cm_config *cm_default_cfg = cm_get_default_config();
+#endif
struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+ unsigned long sdram_size;
unsigned long reg;
+
/*
* First C code to run. Clear fake OCRAM ECC first as SBE
* and DBE might triggered during power on
@@ -67,24 +77,7 @@ void board_init_f(ulong dummy)
writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
writel(0x1, &pl310->pl310_addr_filter_start);
- board_init_r(NULL, 0);
-}
-
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_RAM;
-}
-
-/*
- * Board initialization after bss clearance
- */
-void spl_board_init(void)
-{
- unsigned long sdram_size;
#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
- const struct cm_config *cm_default_cfg = cm_get_default_config();
-#endif
-
debug("Freezing all I/O banks\n");
/* freeze all IO banks */
sys_mgr_frzctrl_freeze_req();
@@ -153,4 +146,6 @@ void spl_board_init(void)
}
socfpga_bridges_reset(1);
+
+ board_init_r(NULL, 0);
}
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 12363ae..cfa9913 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -293,7 +293,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
* 0xFFFF_FF00 ...... End of SRAM
*/
#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_RAM_DEVICE
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 026/172] arm: socfpga: spl: Remove custom linker script
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (24 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 025/172] arm: socfpga: spl: Merge spl_board_init() into board_init_f() Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 027/172] arm: socfpga: spl: Add support for booting from SD/MMC Marek Vasut
` (147 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Remove the custom SPL linker script, use the generic one instead.
The custom script doesn't bring in anything new and is only burden
to maintain.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/u-boot-spl.lds | 45 ------------------------------------
include/configs/socfpga_common.h | 3 ---
2 files changed, 48 deletions(-)
delete mode 100644 arch/arm/mach-socfpga/u-boot-spl.lds
diff --git a/arch/arm/mach-socfpga/u-boot-spl.lds b/arch/arm/mach-socfpga/u-boot-spl.lds
deleted file mode 100644
index 569fa41..0000000
--- a/arch/arm/mach-socfpga/u-boot-spl.lds
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-MEMORY { .sdram : ORIGIN = (0), LENGTH = (0xffffffff) }
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x00000000;
-
- . = ALIGN(4);
- .text :
- {
- *(.vectors)
- arch/arm/cpu/armv7/start.o (.text*)
- *(.text*)
- } >.sdram
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } >.sdram
-
- . = ALIGN(4);
- .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sdram
-
- . = ALIGN(4);
- __image_copy_end = .;
-
- .end :
- {
- *(.__end)
- }
-
- .bss : {
- . = ALIGN(4);
- __bss_start = .;
- *(.bss*)
- . = ALIGN(4);
- __bss_end = .;
- } >.sdram
-}
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index cfa9913..0d35e26 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -302,9 +302,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */
#define CONFIG_CRC32_VERIFY
-/* Linker script for SPL */
-#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-socfpga/u-boot-spl.lds"
-
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 027/172] arm: socfpga: spl: Add support for booting from SD/MMC
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (25 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 026/172] arm: socfpga: spl: Remove custom linker script Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 028/172] arm: socfpga: spl: Add support for booting from QSPI Marek Vasut
` (146 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Add code and configuration options to support booting from RAW
SD/MMC card as well as for ext4/vfat filesystems. Enable support
for booting from SD/MMC card, but don't enable the filesystem
support just yet to retain compatibility with old SoCFPGA card
format.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/spl.c | 17 +++++++++++++++++
configs/socfpga_arria5_defconfig | 2 ++
configs/socfpga_cyclone5_defconfig | 2 ++
configs/socfpga_socrates_defconfig | 3 ++-
include/configs/socfpga_common.h | 14 ++++++++++++++
5 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index ea0ed1a..bacc845 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -31,8 +31,25 @@ static struct nic301_registers *nic301_regs =
u32 spl_boot_device(void)
{
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
+ socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
+ return BOOT_DEVICE_MMC1;
+#else
return BOOT_DEVICE_RAM;
+#endif
+}
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+u32 spl_boot_mode(void)
+{
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+ return MMCSD_MODE_FS;
+#else
+ return MMCSD_MODE_RAW;
+#endif
}
+#endif
static void socfpga_nic301_slave_ns(void)
{
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 4ba4b8c..245d53c 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -7,3 +7,5 @@ CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
CONFIG_OF_CONTROL=y
CONFIG_SPI_FLASH=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_MMC_SUPPORT=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index e101f76..00536ff 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -9,3 +9,5 @@ CONFIG_OF_CONTROL=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_MMC_SUPPORT=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 63dda73..11bbff1 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -6,7 +6,8 @@ CONFIG_SPL=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_OF_CONTROL=y
-CONFIG_SPL_DISABLE_OF_CONTROL=y
CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_MMC_SUPPORT=y
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 0d35e26..78432e6 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -306,6 +306,20 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+
+/* SPL SDMMC boot support */
+#ifdef CONFIG_SPL_MMC_SUPPORT
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#else
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 3
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xa00 /* offset 2560 sect (1M+256k) */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
+#endif
+#endif
/*
* Stack setup
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 028/172] arm: socfpga: spl: Add support for booting from QSPI
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (26 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 027/172] arm: socfpga: spl: Add support for booting from SD/MMC Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 029/172] arm: socfpga: spl: Add support for selecting boot device from BSEL Marek Vasut
` (145 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Add code and configuration options to support booting from QSPI NOR.
Enable support for booting from QSPI NOR.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/spl.c | 5 ++++-
configs/socfpga_arria5_defconfig | 4 ++++
configs/socfpga_cyclone5_defconfig | 4 ++++
configs/socfpga_socrates_defconfig | 4 ++++
include/configs/socfpga_common.h | 9 +++++++++
5 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index bacc845..7f0ebeb 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -31,7 +31,10 @@ static struct nic301_registers *nic301_regs =
u32 spl_boot_device(void)
{
-#ifdef CONFIG_SPL_MMC_SUPPORT
+#ifdef CONFIG_SPL_SPI_SUPPORT
+ socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
+ return BOOT_DEVICE_SPI;
+#elif CONFIG_SPL_MMC_SUPPORT
socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
return BOOT_DEVICE_MMC1;
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 245d53c..0204824 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -9,3 +9,7 @@ CONFIG_OF_CONTROL=y
CONFIG_SPI_FLASH=y
CONFIG_SPL_DM=y
CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_DM_SEQ_ALIAS=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPL_SPI_SUPPORT=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index 00536ff..e57270b 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -11,3 +11,7 @@ CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SPL_DM=y
CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_DM_SEQ_ALIAS=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPL_SPI_SUPPORT=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 11bbff1..d1ffe1d 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -11,3 +11,7 @@ CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SPL_DM=y
CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_DM_SEQ_ALIAS=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPL_SPI_SUPPORT=y
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 78432e6..dde6938 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -307,6 +307,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_SPI_SUPPORT
/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
@@ -321,6 +322,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#endif
#endif
+/* SPL QSPI boot support */
+#ifdef CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_DM_SEQ_ALIAS 1
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
+#endif
+
/*
* Stack setup
*/
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 029/172] arm: socfpga: spl: Add support for selecting boot device from BSEL
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (27 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 028/172] arm: socfpga: spl: Add support for booting from QSPI Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 030/172] arm: socfpga: misc: Fix warm reset Marek Vasut
` (144 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Rework spl_boot_device() such that it reads the BSEL settings from
system manager and decides from where to load U-Boot based on this
information.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/spl.c | 35 +++++++++++++++++++++++------------
1 file changed, 23 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 7f0ebeb..82570f8 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -28,19 +28,32 @@ static struct scu_registers *scu_regs =
(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
+static struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
u32 spl_boot_device(void)
{
-#ifdef CONFIG_SPL_SPI_SUPPORT
- socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
- return BOOT_DEVICE_SPI;
-#elif CONFIG_SPL_MMC_SUPPORT
- socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
- socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
- return BOOT_DEVICE_MMC1;
-#else
- return BOOT_DEVICE_RAM;
-#endif
+ const u32 bsel = readl(&sysmgr_regs->bootinfo);
+
+ switch (bsel & 0x7) {
+ case 0x1: /* FPGA (HPS2FPGA Bridge) */
+ return BOOT_DEVICE_RAM;
+ case 0x2: /* NAND Flash (1.8V) */
+ case 0x3: /* NAND Flash (3.0V) */
+ return BOOT_DEVICE_NAND;
+ case 0x4: /* SD/MMC External Transceiver (1.8V) */
+ case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
+ socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
+ socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
+ return BOOT_DEVICE_MMC1;
+ case 0x6: /* QSPI Flash (1.8V) */
+ case 0x7: /* QSPI Flash (3.0V) */
+ socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
+ return BOOT_DEVICE_SPI;
+ default:
+ printf("Invalid boot device (bsel=%08x)!\n", bsel);
+ hang();
+ }
}
#ifdef CONFIG_SPL_MMC_SUPPORT
@@ -69,8 +82,6 @@ void board_init_f(ulong dummy)
#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
const struct cm_config *cm_default_cfg = cm_get_default_config();
#endif
- struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
unsigned long sdram_size;
unsigned long reg;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 030/172] arm: socfpga: misc: Fix warm reset
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (28 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 029/172] arm: socfpga: spl: Add support for selecting boot device from BSEL Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 031/172] arm: socfpga: misc: Add support for printing boot mode Marek Vasut
` (143 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Write necessary magic value into the Warm Boot from ON-Chip RAM
group Enable register to enable Warm reset support. Instead of
doing this in the reset_cpu() function, we do it in arch early
init to avoid breaking old kernel code which expects this magic
value to be already written into this register.
This magic is originally excavated from common/spl/spl.c in the
u-boot port from altera, where this value was written just before
the SPL jumped to actual U-Boot in the RAM.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/misc.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index f03689c..5175195 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -193,6 +193,16 @@ static uint32_t iswgrp_handoff[8];
int arch_early_init_r(void)
{
int i;
+
+ /*
+ * Write magic value into magic register to unlock support for
+ * issuing warm reset. The ancient kernel code expects this
+ * value to be written into the register by the bootloader, so
+ * to support that old code, we write it here instead of in the
+ * reset_cpu() function just before reseting the CPU.
+ */
+ writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
+
for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 031/172] arm: socfpga: misc: Add support for printing boot mode
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (29 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 030/172] arm: socfpga: misc: Fix warm reset Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 032/172] arm: socfpga: misc: Export bootmode into environment variable Marek Vasut
` (142 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Add support for printing from which device the SoCFPGA board booted.
This decodes the BSEL settings and prints it in human readable form.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/misc.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 5175195..3982c29 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -100,12 +100,25 @@ int cpu_mmc_init(bd_t *bis)
#endif
#if defined(CONFIG_DISPLAY_CPUINFO)
+const char * const bsel_str[] = {
+ "Reserved",
+ "FPGA (HPS2FPGA Bridge)",
+ "NAND Flash (1.8V)",
+ "NAND Flash (3.0V)",
+ "SD/MMC External Transceiver (1.8V)",
+ "SD/MMC Internal Transceiver (3.0V)",
+ "QSPI Flash (1.8V)",
+ "QSPI Flash (3.0V)",
+};
+
/*
* Print CPU information
*/
int print_cpuinfo(void)
{
+ const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
puts("CPU: Altera SoCFPGA Platform\n");
+ printf("BOOT: %s\n", bsel_str[bsel]);
return 0;
}
#endif
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 032/172] arm: socfpga: misc: Export bootmode into environment variable
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (30 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 031/172] arm: socfpga: misc: Add support for printing boot mode Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 033/172] arm: socfpga: misc: Probe ethernet GMAC from OF Marek Vasut
` (141 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
setenv an environment variable called "bootmode" , which contains the
board boot mode. This can be in turn used in scripts to determine from
where to load kernel and such.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/misc.c | 34 +++++++++++++++++++++++-----------
include/configs/socfpga_common.h | 1 +
2 files changed, 24 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 3982c29..a2cffbb 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -99,26 +99,38 @@ int cpu_mmc_init(bd_t *bis)
}
#endif
-#if defined(CONFIG_DISPLAY_CPUINFO)
-const char * const bsel_str[] = {
- "Reserved",
- "FPGA (HPS2FPGA Bridge)",
- "NAND Flash (1.8V)",
- "NAND Flash (3.0V)",
- "SD/MMC External Transceiver (1.8V)",
- "SD/MMC Internal Transceiver (3.0V)",
- "QSPI Flash (1.8V)",
- "QSPI Flash (3.0V)",
+struct {
+ const char *mode;
+ const char *name;
+} bsel_str[] = {
+ { "rsvd", "Reserved", },
+ { "fpga", "FPGA (HPS2FPGA Bridge)", },
+ { "nand", "NAND Flash (1.8V)", },
+ { "nand", "NAND Flash (3.0V)", },
+ { "sd", "SD/MMC External Transceiver (1.8V)", },
+ { "sd", "SD/MMC Internal Transceiver (3.0V)", },
+ { "qspi", "QSPI Flash (1.8V)", },
+ { "qspi", "QSPI Flash (3.0V)", },
};
/*
* Print CPU information
*/
+#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
puts("CPU: Altera SoCFPGA Platform\n");
- printf("BOOT: %s\n", bsel_str[bsel]);
+ printf("BOOT: %s\n", bsel_str[bsel].name);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+ const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
+ setenv("bootmode", bsel_str[bsel].mode);
return 0;
}
#endif
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index dde6938..615d51e 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -18,6 +18,7 @@
*/
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_ARCH_MISC_INIT
#define CONFIG_ARCH_EARLY_INIT_R
#define CONFIG_SYS_NO_FLASH
#define CONFIG_CLOCKS
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 033/172] arm: socfpga: misc: Probe ethernet GMAC from OF
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (31 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 032/172] arm: socfpga: misc: Export bootmode into environment variable Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 034/172] arm: socfpga: misc: Reset ethernet " Marek Vasut
` (140 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
The GMAC can now be probed from OF, so enable DM ethernet and remove the
old ad-hoc designware_initialize() invocation.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
---
arch/arm/mach-socfpga/misc.c | 4 +---
configs/socfpga_cyclone5_defconfig | 1 +
configs/socfpga_socrates_defconfig | 1 +
include/configs/socfpga_arria5.h | 1 -
include/configs/socfpga_cyclone5.h | 1 -
5 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index a2cffbb..4b1c052 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -82,9 +82,7 @@ int cpu_eth_init(bd_t *bis)
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
- /* initialize and register the emac */
- return designware_initialize(CONFIG_EMAC_BASE,
- CONFIG_PHY_INTERFACE_MODE);
+ return 0;
}
#endif
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index e57270b..2beea4b 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -7,6 +7,7 @@ CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
CONFIG_OF_CONTROL=y
CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SPL_DM=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index d1ffe1d..2f7c239 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -7,6 +7,7 @@ CONFIG_SPL=y
# CONFIG_CMD_FLASH is not set
CONFIG_OF_CONTROL=y
CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
CONFIG_NETDEVICES=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SPL_DM=y
diff --git a/include/configs/socfpga_arria5.h b/include/configs/socfpga_arria5.h
index 329ca35..d8f2438 100644
--- a/include/configs/socfpga_arria5.h
+++ b/include/configs/socfpga_arria5.h
@@ -49,7 +49,6 @@
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS
-#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
/* PHY */
#define CONFIG_PHY_MICREL
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index c2922dd..a27660e 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -49,7 +49,6 @@
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS
-#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
/* PHY */
#define CONFIG_PHY_MICREL
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 034/172] arm: socfpga: misc: Reset ethernet from OF
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (32 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 033/172] arm: socfpga: misc: Probe ethernet GMAC from OF Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 035/172] arm: socfpga: config: Move SPL GD and malloc to RAM Marek Vasut
` (139 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Reset the GMAC ethernets based on the "resets" OF node instead of ad-hoc
hardcoded values in the U-Boot code. Since we don't have a proper reset
framework in place yet, we have to do this slightly ad-hoc parsing of the
OF tree instead.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
---
arch/arm/mach-socfpga/misc.c | 68 +++++++++++++++++++++++++++-----------
include/configs/socfpga_arria5.h | 1 -
include/configs/socfpga_cyclone5.h | 1 -
include/fdtdec.h | 1 +
lib/fdtdec.c | 1 +
5 files changed, 51 insertions(+), 21 deletions(-)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 4b1c052..9d34cd3 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -6,6 +6,8 @@
#include <common.h>
#include <asm/io.h>
+#include <fdtdec.h>
+#include <libfdt.h>
#include <altera.h>
#include <miiphy.h>
#include <netdev.h>
@@ -17,6 +19,8 @@
#include <asm/arch/scu.h>
#include <asm/pl310.h>
+#include <dt-bindings/reset/altr,rst-mgr.h>
+
DECLARE_GLOBAL_DATA_PTR;
static struct pl310_regs *const pl310 =
@@ -50,26 +54,20 @@ void enable_caches(void)
* DesignWare Ethernet initialization
*/
#ifdef CONFIG_ETH_DESIGNWARE
-int cpu_eth_init(bd_t *bis)
+static void dwmac_deassert_reset(const unsigned int of_reset_id)
{
-#if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
- const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
- const u32 reset = SOCFPGA_RESET(EMAC0);
-#elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
- const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
- const u32 reset = SOCFPGA_RESET(EMAC1);
-#else
-#error "Incorrect CONFIG_EMAC_BASE value!"
-#endif
-
- /* Initialize EMAC. This needs to be done at least once per boot. */
-
- /*
- * Putting the EMAC controller to reset when configuring the PHY
- * interface select at System Manager
- */
- socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
- socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
+ u32 physhift, reset;
+
+ if (of_reset_id == EMAC0_RESET) {
+ physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
+ reset = SOCFPGA_RESET(EMAC0);
+ } else if (of_reset_id == EMAC1_RESET) {
+ physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
+ reset = SOCFPGA_RESET(EMAC1);
+ } else {
+ printf("GMAC: Invalid reset ID (%i)!\n", of_reset_id);
+ return;
+ }
/* Clearing emac0 PHY interface select to 0 */
clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
@@ -81,6 +79,38 @@ int cpu_eth_init(bd_t *bis)
/* Release the EMAC controller from reset */
socfpga_per_reset(reset, 0);
+}
+
+int cpu_eth_init(bd_t *bis)
+{
+ const void *fdt = gd->fdt_blob;
+ struct fdtdec_phandle_args args;
+ int nodes[2]; /* Max. two GMACs */
+ int ret, count;
+ int i, node;
+
+ /* Put both GMACs into RESET state. */
+ socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
+ socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
+
+ count = fdtdec_find_aliases_for_id(fdt, "ethernet",
+ COMPAT_ALTERA_SOCFPGA_DWMAC,
+ nodes, ARRAY_SIZE(nodes));
+ for (i = 0; i < count; i++) {
+ node = nodes[i];
+ if (node <= 0)
+ continue;
+
+ ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
+ "#reset-cells", 1, 0,
+ &args);
+ if (ret || (args.args_count != 1)) {
+ debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
+ continue;
+ }
+
+ dwmac_deassert_reset(args.args[0]);
+ }
return 0;
}
diff --git a/include/configs/socfpga_arria5.h b/include/configs/socfpga_arria5.h
index d8f2438..ed865ce 100644
--- a/include/configs/socfpga_arria5.h
+++ b/include/configs/socfpga_arria5.h
@@ -48,7 +48,6 @@
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
-#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS
/* PHY */
#define CONFIG_PHY_MICREL
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index a27660e..f13ed3e 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -48,7 +48,6 @@
/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
-#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS
/* PHY */
#define CONFIG_PHY_MICREL
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 1a39b9f..fdac3cd 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -184,6 +184,7 @@ enum fdt_compat_id {
COMPAT_INTEL_PCH, /* Intel PCH */
COMPAT_INTEL_IRQ_ROUTER, /* Intel Interrupt Router */
COMPAT_ALTERA_SOCFPGA_DWMMC, /* SoCFPGA DWMMC controller */
+ COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */
COMPAT_COUNT,
};
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index d0f81bc..c1f40eb 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -77,6 +77,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"),
COMPAT(COMPAT_INTEL_IRQ_ROUTER, "intel,irq-router"),
COMPAT(ALTERA_SOCFPGA_DWMMC, "altr,socfpga-dw-mshc"),
+ COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 035/172] arm: socfpga: config: Move SPL GD and malloc to RAM
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (33 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 034/172] arm: socfpga: misc: Reset ethernet " Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 036/172] arm: socfpga: config: Zap incorrect config options Marek Vasut
` (138 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
Now that the SPL structure is organised such that it matches the
U-Boot's SPL design, it is possible to use the option of relocating
GD to RAM. And since we have GD in RAM, move malloc area to RAM as
well. We point the malloc base pointer 1 MiB past U-Boot's load
address. We use simple malloc for SPL because it is 3kiB smaller
in terms of code size than regular malloc which was used thus far.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/spl.c | 3 +++
configs/socfpga_arria5_defconfig | 3 +++
configs/socfpga_cyclone5_defconfig | 3 +++
configs/socfpga_socrates_defconfig | 3 +++
include/configs/socfpga_common.h | 14 ++++++++------
5 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
index 82570f8..13ec24b 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -178,5 +178,8 @@ void board_init_f(ulong dummy)
socfpga_bridges_reset(1);
+ /* Configure simple malloc base pointer into RAM. */
+ gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
+
board_init_r(NULL, 0);
}
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 0204824..21c3f0c 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -13,3 +13,6 @@ CONFIG_DM_SEQ_ALIAS=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index 2beea4b..b9b94d7 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -16,3 +16,6 @@ CONFIG_DM_SEQ_ALIAS=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 2f7c239..bd27b39 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -16,3 +16,6 @@ CONFIG_DM_SEQ_ALIAS=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 615d51e..cbe293e 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -39,10 +39,11 @@
#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE (0x10000 - CONFIG_SYS_SPL_MALLOC_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
@@ -296,9 +297,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_RAM_DEVICE
#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SYS_INIT_SP_ADDR
-#define CONFIG_SYS_SPL_MALLOC_SIZE (5 * 1024)
#define CONFIG_SPL_MAX_SIZE (64 * 1024)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */
#define CONFIG_CRC32_VERIFY
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 036/172] arm: socfpga: config: Zap incorrect config options
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (34 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 035/172] arm: socfpga: config: Move SPL GD and malloc to RAM Marek Vasut
@ 2015-07-27 20:49 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 037/172] arm: socfpga: config: Exclude CONFIG_SPI_FLASH_MTD from SPL build Marek Vasut
` (137 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:49 UTC (permalink / raw)
To: u-boot
There is no need to disable support for partitions in the SPL,
we can support partitions in SPL perfectly well. This is likely
some remnant from old times, so just remove this configuration
option.
Moreover, the CRC32 chunk size doesn't have to be adjusted anymore,
since both the GD and malloc area are in RAM by the time this CRC
check can be used and there's plenty of space. Zap this abomination
as well.
Signed-off-by: Marek Vasut <marex@denx.de>
---
include/configs/socfpga_common.h | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index cbe293e..5724eb8 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -23,6 +23,8 @@
#define CONFIG_SYS_NO_FLASH
#define CONFIG_CLOCKS
+#define CONFIG_CRC32_VERIFY
+
#define CONFIG_FIT
#define CONFIG_OF_LIBFDT
#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
@@ -302,9 +304,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_SYS_MALLOC_SIMPLE
#endif
-#define CHUNKSZ_CRC32 (1 * 1024) /* FIXME: ewww */
-#define CONFIG_CRC32_VERIFY
-
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
@@ -338,8 +337,4 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
*/
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_PARTITIONS
-#endif
-
#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 037/172] arm: socfpga: config: Exclude CONFIG_SPI_FLASH_MTD from SPL build
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (35 preceding siblings ...)
2015-07-27 20:49 ` [U-Boot] [PATCH 036/172] arm: socfpga: config: Zap incorrect config options Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 038/172] arm: socfpga: config: Enable CONFIG_SPI_FLASH_BAR Marek Vasut
` (136 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
We do not need full MTD support in the SPL build, it only adds size
and is not usable in any way. Exclude it.
Signed-off-by: Marek Vasut <marex@denx.de>
---
include/configs/socfpga_common.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 5724eb8..e112f7a 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -203,7 +203,9 @@ unsigned int cm_get_l4_sp_clk_hz(void);
/* Enable multiple SPI NOR flash manufacturers */
#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */
#define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */
+#ifndef CONFIG_SPL_BUILD
#define CONFIG_SPI_FLASH_MTD
+#endif
/* QSPI reference clock */
#ifndef __ASSEMBLY__
unsigned int cm_get_qspi_controller_clk_hz(void);
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 038/172] arm: socfpga: config: Enable CONFIG_SPI_FLASH_BAR
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (36 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 037/172] arm: socfpga: config: Exclude CONFIG_SPI_FLASH_MTD from SPL build Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 039/172] arm: socfpga: config: Fix LOADADDR Marek Vasut
` (135 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
This is needed to access broken (read: Micron) SPI flashes which
are larger than 16 MiB and don't correctly support 4-byte addressing.
Signed-off-by: Marek Vasut <marex@denx.de>
---
include/configs/socfpga_common.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index e112f7a..a069143 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -213,6 +213,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#endif
#define CONFIG_CQSPI_DECODER 0
#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_BAR
#endif
#ifdef CONFIG_OF_CONTROL /* DW SPI is controlled via DT */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 039/172] arm: socfpga: config: Fix LOADADDR
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (37 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 038/172] arm: socfpga: config: Enable CONFIG_SPI_FLASH_BAR Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 040/172] arm: socfpga: config: Make CONFIG_SPI_FLASH_MTD useful Marek Vasut
` (134 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Setting LOADADDR to 0x8000 is a bad idea, it is very likely that
some kind of overlap will happen. Move the LOADADDR 0x01000000
(16MiB from start of RAM) to make sure no overlap happens when
loading kernel for example.
Signed-off-by: Marek Vasut <marex@denx.de>
---
include/configs/socfpga_arria5.h | 2 +-
include/configs/socfpga_cyclone5.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/socfpga_arria5.h b/include/configs/socfpga_arria5.h
index ed865ce..3193684 100644
--- a/include/configs/socfpga_arria5.h
+++ b/include/configs/socfpga_arria5.h
@@ -43,7 +43,7 @@
#else
#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
#endif
-#define CONFIG_LOADADDR 0x8000
+#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index f13ed3e..9e733e5 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -43,7 +43,7 @@
#else
#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
#endif
-#define CONFIG_LOADADDR 0x8000
+#define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 040/172] arm: socfpga: config: Make CONFIG_SPI_FLASH_MTD useful
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (38 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 039/172] arm: socfpga: config: Fix LOADADDR Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 041/172] Makefile: Add target for building bootable SPL image for SoCFPGA Marek Vasut
` (133 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Enable the mtdparts command and related options to make support
for SPI NOR MTD useful in any way. With the mtdparts command in
place, it is possible to use partition of the SPI NOR in U-Boot.
Signed-off-by: Marek Vasut <marex@denx.de>
---
include/configs/socfpga_common.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index a069143..ee64377 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -205,6 +205,10 @@ unsigned int cm_get_l4_sp_clk_hz(void);
#define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SPI_FLASH_MTD
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nor0=ff705000.spi"
#endif
/* QSPI reference clock */
#ifndef __ASSEMBLY__
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 041/172] Makefile: Add target for building bootable SPL image for SoCFPGA
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (39 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 040/172] arm: socfpga: config: Make CONFIG_SPI_FLASH_MTD useful Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 042/172] ddr: altera: Minor indent fix in set_rank_and_odt_mask() Marek Vasut
` (132 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Add build target for generating boot partition images recognised by
the SoCFPGA BootROM. The SoCFPGA BootROM expects four copies of the
u-boot-spl-dtb.sfp at the beginning of boot partition. Those are
u-boot-spl-dtb.bin augmented by a header with which the BootROM can
work. The u-boot-dtb.img uImage is appended to this to produce a
full boot partition image, the u-boot-with-spl-dtb.sfp . This is
the name of the final target.
Signed-off-by: Marek Vasut <marex@denx.de>
---
Makefile | 12 ++++++++++++
scripts/Makefile.spl | 10 ++++++++++
2 files changed, 22 insertions(+)
diff --git a/Makefile b/Makefile
index 041dea7..6215f91 100644
--- a/Makefile
+++ b/Makefile
@@ -1007,6 +1007,15 @@ u-boot-nand.gph: u-boot.bin FORCE
$(call if_changed,mkimage)
@dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@
+ifneq ($(CONFIG_ARCH_SOCFPGA),)
+quiet_cmd_socboot = SOCBOOT $@
+cmd_socboot = cat spl/u-boot-spl-dtb.sfp spl/u-boot-spl-dtb.sfp \
+ spl/u-boot-spl-dtb.sfp spl/u-boot-spl-dtb.sfp \
+ u-boot-dtb.img > $@ || rm -f $@
+u-boot-with-spl-dtb.sfp: spl/u-boot-spl-dtb.sfp u-boot-dtb.img FORCE
+ $(call if_changed,socboot)
+endif
+
# x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including
# reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in
# the middle.
@@ -1266,6 +1275,9 @@ spl/u-boot-spl: tools prepare $(if $(CONFIG_OF_SEPARATE),dts/dt.dtb)
spl/sunxi-spl.bin: spl/u-boot-spl
@:
+spl/u-boot-spl-dtb.sfp: spl/u-boot-spl
+ @:
+
tpl/u-boot-tpl.bin: tools prepare
$(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 4879d0a..239ee48 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -163,6 +163,10 @@ ifdef CONFIG_SAMSUNG
ALL-y += $(obj)/$(BOARD)-spl.bin
endif
+ifdef CONFIG_ARCH_SOCFPGA
+ALL-y += $(obj)/$(SPL_BIN)-dtb.sfp
+endif
+
ifdef CONFIG_SUNXI
ALL-y += $(obj)/sunxi-spl.bin
endif
@@ -231,6 +235,12 @@ ifneq ($(CONFIG_SPL_TEXT_BASE),)
LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE)
endif
+ifdef CONFIG_ARCH_SOCFPGA
+MKIMAGEFLAGS_$(SPL_BIN)-dtb.sfp = -T socfpgaimage
+$(obj)/$(SPL_BIN)-dtb.sfp: $(obj)/$(SPL_BIN)-dtb.bin FORCE
+ $(call if_changed,mkimage)
+endif
+
ifdef CONFIG_SUNXI
quiet_cmd_mksunxiboot = MKSUNXI $@
cmd_mksunxiboot = $(objtree)/tools/mksunxiboot $< $@
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 042/172] ddr: altera: Minor indent fix in set_rank_and_odt_mask()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (40 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 041/172] Makefile: Add target for building bootable SPL image for SoCFPGA Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 043/172] ddr: altera: Clean up ugly casts in sdram_calibration_full() Marek Vasut
` (131 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Fix the position of the } else { statement to make it correctly
indented.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 1e96014..746c97a 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -260,7 +260,7 @@ static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
odt_mask_0 = 0x0;
odt_mask_1 = 0x3 & (1 << rank);
}
- } else {
+ } else {
/* 4 Ranks
* Read:
* ----------+-----------------------+
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 043/172] ddr: altera: Clean up ugly casts in sdram_calibration_full()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (41 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 042/172] ddr: altera: Minor indent fix in set_rank_and_odt_mask() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 044/172] ddr: altera: Zap invocation of sdr_get_addr((u32 *)BASE_RW_MGR)" Marek Vasut
` (130 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Use the correct formating string in those debug_cond() invocations
and zap those unnecessary ugly casts.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 50 ++++++++++++++++++------------------------
1 file changed, 21 insertions(+), 29 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 746c97a..9471ed5 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3994,35 +3994,27 @@ int sdram_calibration_full(void)
printf("%s: Preparing to start memory calibration\n", __FILE__);
debug("%s:%d\n", __func__, __LINE__);
- debug_cond(DLEVEL == 1, "DDR3 FULL_RATE ranks=%lu cs/dimm=%lu dq/dqs=%lu,%lu vg/dqs=%lu,%lu ",
- (long unsigned int)RW_MGR_MEM_NUMBER_OF_RANKS,
- (long unsigned int)RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
- (long unsigned int)RW_MGR_MEM_DQ_PER_READ_DQS,
- (long unsigned int)RW_MGR_MEM_DQ_PER_WRITE_DQS,
- (long unsigned int)RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
- (long unsigned int)RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
- debug_cond(DLEVEL == 1, "dqs=%lu,%lu dq=%lu dm=%lu ptap_delay=%lu dtap_delay=%lu ",
- (long unsigned int)RW_MGR_MEM_IF_READ_DQS_WIDTH,
- (long unsigned int)RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
- (long unsigned int)RW_MGR_MEM_DATA_WIDTH,
- (long unsigned int)RW_MGR_MEM_DATA_MASK_WIDTH,
- (long unsigned int)IO_DELAY_PER_OPA_TAP,
- (long unsigned int)IO_DELAY_PER_DCHAIN_TAP);
- debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%lu, dll=%lu",
- (long unsigned int)IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
- (long unsigned int)IO_DLL_CHAIN_LENGTH);
- debug_cond(DLEVEL == 1, "max values: en_p=%lu dqdqs_p=%lu en_d=%lu dqs_in_d=%lu ",
- (long unsigned int)IO_DQS_EN_PHASE_MAX,
- (long unsigned int)IO_DQDQS_OUT_PHASE_MAX,
- (long unsigned int)IO_DQS_EN_DELAY_MAX,
- (long unsigned int)IO_DQS_IN_DELAY_MAX);
- debug_cond(DLEVEL == 1, "io_in_d=%lu io_out1_d=%lu io_out2_d=%lu ",
- (long unsigned int)IO_IO_IN_DELAY_MAX,
- (long unsigned int)IO_IO_OUT1_DELAY_MAX,
- (long unsigned int)IO_IO_OUT2_DELAY_MAX);
- debug_cond(DLEVEL == 1, "dqs_in_reserve=%lu dqs_out_reserve=%lu\n",
- (long unsigned int)IO_DQS_IN_RESERVE,
- (long unsigned int)IO_DQS_OUT_RESERVE);
+ debug_cond(DLEVEL == 1,
+ "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
+ RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
+ RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
+ debug_cond(DLEVEL == 1,
+ "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
+ RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
+ RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
+ IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
+ debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
+ IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
+ debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
+ IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
+ IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
+ debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
+ IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
+ IO_IO_OUT2_DELAY_MAX);
+ debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
+ IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
hc_initialize_rom_data();
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 044/172] ddr: altera: Zap invocation of sdr_get_addr((u32 *)BASE_RW_MGR)"
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (42 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 043/172] ddr: altera: Clean up ugly casts in sdram_calibration_full() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 045/172] ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_reg_file->.*) Marek Vasut
` (129 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Instead of this indirection, just adjust the register pointer and
directly use the register base address.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 9471ed5..9b81a51 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1248,7 +1248,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
vg) << 2));
- addr = sdr_get_addr((u32 *)BASE_RW_MGR);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
base_rw_mgr = readl(SOCFPGA_SDR_ADDRESS + addr);
tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
@@ -1406,7 +1406,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group
((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
vg) << 2));
- addr = sdr_get_addr((u32 *)BASE_RW_MGR);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
base_rw_mgr = readl(SOCFPGA_SDR_ADDRESS + addr);
tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
@@ -2789,7 +2789,7 @@ static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
tmp_bit_chk = 0;
addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
- addr_rw_mgr = sdr_get_addr((u32 *)BASE_RW_MGR);
+ addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
/* reset the fifos to get pointers to known state */
writel(0, SOCFPGA_SDR_ADDRESS + addr);
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 045/172] ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_reg_file->.*)
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (43 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 044/172] ddr: altera: Zap invocation of sdr_get_addr((u32 *)BASE_RW_MGR)" Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 046/172] ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_scc_mgr->.*) Marek Vasut
` (128 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Instead of this indirection, just adjust the register pointer and
directly use the register base address.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 46 ++++++++++++++++++++++--------------------
1 file changed, 24 insertions(+), 22 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 9b81a51..9866b04 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -22,7 +22,7 @@ static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
(struct socfpga_sdr_rw_load_jump_manager *)(BASE_RW_MGR + 0xC00);
static struct socfpga_sdr_reg_file *sdr_reg_file =
- (struct socfpga_sdr_reg_file *)(BASE_REG_FILE);
+ (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
(struct socfpga_sdr_scc_mgr *)(BASE_SCC_MGR + 0x0E00);
@@ -130,7 +130,7 @@ static void set_failing_group_stage(uint32_t group, uint32_t stage,
static void reg_file_set_group(uint32_t set_group)
{
- u32 addr = sdr_get_addr(&sdr_reg_file->cur_stage);
+ u32 addr = (u32)&sdr_reg_file->cur_stage;
/* Read the current group and stage */
uint32_t cur_stage_group = readl(SOCFPGA_SDR_ADDRESS + addr);
@@ -147,7 +147,8 @@ static void reg_file_set_group(uint32_t set_group)
static void reg_file_set_stage(uint32_t set_stage)
{
- u32 addr = sdr_get_addr(&sdr_reg_file->cur_stage);
+ u32 addr = (u32)&sdr_reg_file->cur_stage;
+
/* Read the current group and stage */
uint32_t cur_stage_group = readl(SOCFPGA_SDR_ADDRESS + addr);
@@ -163,7 +164,8 @@ static void reg_file_set_stage(uint32_t set_stage)
static void reg_file_set_sub_stage(uint32_t set_sub_stage)
{
- u32 addr = sdr_get_addr(&sdr_reg_file->cur_stage);
+ u32 addr = (u32)&sdr_reg_file->cur_stage;
+
/* Read the current group and stage */
uint32_t cur_stage_group = readl(SOCFPGA_SDR_ADDRESS + addr);
@@ -1911,7 +1913,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
if (found_passing_read && found_failing_read)
dtaps_per_ptap = d - initial_failing_dtap;
- addr = sdr_get_addr(&sdr_reg_file->dtaps_per_ptap);
+ addr = (u32)&sdr_reg_file->dtaps_per_ptap;
writel(dtaps_per_ptap, SOCFPGA_SDR_ADDRESS + addr);
debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
- %u = %u", __func__, __LINE__, d,
@@ -3754,7 +3756,7 @@ static uint32_t run_mem_calibrate(void)
/* Update the FOM in the register file */
debug_info = gbl->fom_in;
debug_info |= gbl->fom_out << 8;
- addr = sdr_get_addr(&sdr_reg_file->fom);
+ addr = (u32)&sdr_reg_file->fom;
writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
addr = sdr_get_addr(&phy_mgr_cfg->cal_debug_info);
@@ -3768,7 +3770,7 @@ static uint32_t run_mem_calibrate(void)
debug_info |= gbl->error_substage << 8;
debug_info |= gbl->error_group << 16;
- addr = sdr_get_addr(&sdr_reg_file->failing_stage);
+ addr = (u32)&sdr_reg_file->failing_stage;
writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
addr = sdr_get_addr(&phy_mgr_cfg->cal_debug_info);
writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
@@ -3779,7 +3781,7 @@ static uint32_t run_mem_calibrate(void)
debug_info = gbl->error_stage;
debug_info |= gbl->error_substage << 8;
debug_info |= gbl->error_group << 16;
- addr = sdr_get_addr(&sdr_reg_file->failing_stage);
+ addr = (u32)&sdr_reg_file->failing_stage;
writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
}
@@ -3809,25 +3811,25 @@ static void initialize_reg_file(void)
uint32_t addr;
/* Initialize the register file with the correct data */
- addr = sdr_get_addr(&sdr_reg_file->signature);
+ addr = (u32)&sdr_reg_file->signature;
writel(REG_FILE_INIT_SEQ_SIGNATURE, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_reg_file->debug_data_addr);
+ addr = (u32)&sdr_reg_file->debug_data_addr;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_reg_file->cur_stage);
+ addr = (u32)&sdr_reg_file->cur_stage;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_reg_file->fom);
+ addr = (u32)&sdr_reg_file->fom;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_reg_file->failing_stage);
+ addr = (u32)&sdr_reg_file->failing_stage;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_reg_file->debug1);
+ addr = (u32)&sdr_reg_file->debug1;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_reg_file->debug2);
+ addr = (u32)&sdr_reg_file->debug2;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
}
@@ -3931,25 +3933,25 @@ static void initialize_tracking(void)
concatenated_refresh = concatenated_refresh ^ 1000; /* trefi */
/* Initialize the register file with the correct data */
- addr = sdr_get_addr(&sdr_reg_file->dtaps_per_ptap);
+ addr = (u32)&sdr_reg_file->dtaps_per_ptap;
writel(dtaps_per_ptap, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_reg_file->trk_sample_count);
+ addr = (u32)&sdr_reg_file->trk_sample_count;
writel(trk_sample_count, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_reg_file->trk_longidle);
+ addr = (u32)&sdr_reg_file->trk_longidle;
writel(concatenated_longidle, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_reg_file->delays);
+ addr = (u32)&sdr_reg_file->delays;
writel(concatenated_delays, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_reg_file->trk_rw_mgr_addr);
+ addr = (u32)&sdr_reg_file->trk_rw_mgr_addr;
writel(concatenated_rw_addr, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_reg_file->trk_read_dqs_width);
+ addr = (u32)&sdr_reg_file->trk_read_dqs_width;
writel(RW_MGR_MEM_IF_READ_DQS_WIDTH, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_reg_file->trk_rfsh);
+ addr = (u32)&sdr_reg_file->trk_rfsh;
writel(concatenated_refresh, SOCFPGA_SDR_ADDRESS + addr);
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 046/172] ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_scc_mgr->.*)
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (44 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 045/172] ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_reg_file->.*) Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 047/172] ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_rw_load.*->.*) Marek Vasut
` (127 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Instead of this indirection, just adjust the register pointer and
directly use the register base address.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 90 +++++++++++++++++++++---------------------
1 file changed, 45 insertions(+), 45 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 9866b04..4cc2a96 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -25,7 +25,7 @@ static struct socfpga_sdr_reg_file *sdr_reg_file =
(struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
- (struct socfpga_sdr_scc_mgr *)(BASE_SCC_MGR + 0x0E00);
+ (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
(struct socfpga_phy_mgr_cmd *)(BASE_PHY_MGR);
@@ -387,10 +387,10 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,
scc_mgr_set_dqs_en_phase(read_group, phase);
if (update_scan_chains) {
- addr = sdr_get_addr(&sdr_scc_mgr->dqs_ena);
+ addr = (u32)&sdr_scc_mgr->dqs_ena;
writel(read_group, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
}
}
@@ -427,10 +427,10 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
scc_mgr_set_dqdqs_output_phase(write_group, phase);
if (update_scan_chains) {
- addr = sdr_get_addr(&sdr_scc_mgr->dqs_ena);
+ addr = (u32)&sdr_scc_mgr->dqs_ena;
writel(write_group, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
}
}
@@ -455,7 +455,7 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
r += NUM_RANKS_PER_SHADOW_REG) {
scc_mgr_set_dqs_en_delay(read_group, delay);
- addr = sdr_get_addr(&sdr_scc_mgr->dqs_ena);
+ addr = (u32)&sdr_scc_mgr->dqs_ena;
writel(read_group, SOCFPGA_SDR_ADDRESS + addr);
/*
* In shadow register mode, the T11 settings are stored in
@@ -465,7 +465,7 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
* select_shadow_regs_for_update with update_scan_chains
* set to 0.
*/
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
}
/*
@@ -476,7 +476,7 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
* select_shadow_regs_for_update with update_scan_chains
* set to 0.
*/
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
}
@@ -587,10 +587,10 @@ static void scc_mgr_zero_all(void)
}
/* multicast to all DQS group enables */
- addr = sdr_get_addr(&sdr_scc_mgr->dqs_ena);
+ addr = (u32)&sdr_scc_mgr->dqs_ena;
writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
}
@@ -609,22 +609,22 @@ static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)
__func__, __LINE__);
}
/* multicast to all DQ enables */
- addr = sdr_get_addr(&sdr_scc_mgr->dq_ena);
+ addr = (u32)&sdr_scc_mgr->dq_ena;
writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_scc_mgr->dm_ena);
+ addr = (u32)&sdr_scc_mgr->dm_ena;
writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
/* update current DQS IO enable */
- addr = sdr_get_addr(&sdr_scc_mgr->dqs_io_ena);
+ addr = (u32)&sdr_scc_mgr->dqs_io_ena;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
/* update the DQS logic */
- addr = sdr_get_addr(&sdr_scc_mgr->dqs_ena);
+ addr = (u32)&sdr_scc_mgr->dqs_ena;
writel(write_group, SOCFPGA_SDR_ADDRESS + addr);
/* hit update */
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
}
@@ -644,7 +644,7 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
}
/* multicast to all DQ enables */
- addr = sdr_get_addr(&sdr_scc_mgr->dq_ena);
+ addr = (u32)&sdr_scc_mgr->dq_ena;
writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
/* Zero all DM config settings */
@@ -653,7 +653,7 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
}
/* multicast to all DM enables */
- addr = sdr_get_addr(&sdr_scc_mgr->dm_ena);
+ addr = (u32)&sdr_scc_mgr->dm_ena;
writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
/* zero all DQS io settings */
@@ -665,11 +665,11 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
scc_mgr_load_dqs_for_write_group(write_group);
/* multicast to all DQS IO enables (only 1) */
- addr = sdr_get_addr(&sdr_scc_mgr->dqs_io_ena);
+ addr = (u32)&sdr_scc_mgr->dqs_io_ena;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
/* hit update to zero everything */
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
}
}
@@ -677,7 +677,7 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
/* load up dqs config settings */
static void scc_mgr_load_dqs(uint32_t dqs)
{
- uint32_t addr = sdr_get_addr(&sdr_scc_mgr->dqs_ena);
+ uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena;
writel(dqs, SOCFPGA_SDR_ADDRESS + addr);
}
@@ -685,7 +685,7 @@ static void scc_mgr_load_dqs(uint32_t dqs)
static void scc_mgr_load_dqs_for_write_group(uint32_t write_group)
{
uint32_t read_group;
- uint32_t addr = sdr_get_addr(&sdr_scc_mgr->dqs_ena);
+ uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena;
/*
* Although OCT affects only write data, the OCT delay is controlled
* by the DQS logic block which is instantiated once per read group.
@@ -702,7 +702,7 @@ static void scc_mgr_load_dqs_for_write_group(uint32_t write_group)
/* load up dqs io config settings */
static void scc_mgr_load_dqs_io(void)
{
- uint32_t addr = sdr_get_addr(&sdr_scc_mgr->dqs_io_ena);
+ uint32_t addr = (u32)&sdr_scc_mgr->dqs_io_ena;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
}
@@ -710,7 +710,7 @@ static void scc_mgr_load_dqs_io(void)
/* load up dq config settings */
static void scc_mgr_load_dq(uint32_t dq_in_group)
{
- uint32_t addr = sdr_get_addr(&sdr_scc_mgr->dq_ena);
+ uint32_t addr = (u32)&sdr_scc_mgr->dq_ena;
writel(dq_in_group, SOCFPGA_SDR_ADDRESS + addr);
}
@@ -718,7 +718,7 @@ static void scc_mgr_load_dq(uint32_t dq_in_group)
/* load up dm config settings */
static void scc_mgr_load_dm(uint32_t dm)
{
- uint32_t addr = sdr_get_addr(&sdr_scc_mgr->dm_ena);
+ uint32_t addr = (u32)&sdr_scc_mgr->dm_ena;
writel(dm, SOCFPGA_SDR_ADDRESS + addr);
}
@@ -859,7 +859,7 @@ static void scc_mgr_apply_group_all_out_delay_add_all_ranks(
uint32_t write_group, uint32_t group_bgn, uint32_t delay)
{
uint32_t r;
- uint32_t addr = sdr_get_addr(&sdr_scc_mgr->update);
+ uint32_t addr = (u32)&sdr_scc_mgr->update;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
@@ -1967,7 +1967,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
scc_mgr_set_dq_in_delay(write_group, p, d);
scc_mgr_load_dq(p);
}
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
}
@@ -1985,7 +1985,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
scc_mgr_set_dq_in_delay(write_group, p, 0);
scc_mgr_load_dq(p);
}
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
}
@@ -2032,7 +2032,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
}
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
/* Search for the left edge of the window for each bit */
for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
@@ -2121,7 +2121,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
break;
}
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
/* Search for the right edge of the window for each bit */
for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
@@ -2214,7 +2214,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
}
/* Check that all bits have a window */
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
%d right_edge[%u]: %d", __func__, __LINE__,
@@ -2364,7 +2364,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
* Do not remove this line as it makes sure all of our decisions
* have been applied. Apply the update bit.
*/
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
return (dq_margin >= 0) && (dqs_margin >= 0);
@@ -2875,7 +2875,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
}
/* Search for the left edge of the window for each bit */
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, d);
@@ -2959,7 +2959,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
}
/* Search for the right edge of the window for each bit */
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
d + start_dqs);
@@ -3133,7 +3133,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
/* Move DQS */
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
/* Centre DM */
@@ -3152,7 +3152,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
int32_t win_best = 0;
/* Search for the/part of the window with DM shift */
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
scc_mgr_apply_group_dm_out1_delay(write_group, d);
writel(0, SOCFPGA_SDR_ADDRESS + addr);
@@ -3199,7 +3199,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
}
/* Search for the/part of the window with DQS shifts */
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
/*
* Note: This only shifts DQS, so are we limiting ourselve to
@@ -3271,7 +3271,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
dm_margin = left_edge[0] - mid;
scc_mgr_apply_group_dm_out1_delay(write_group, mid);
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
@@ -3288,7 +3288,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
* Do not remove this line as it makes sure all of our
* decisions have been applied.
*/
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
}
@@ -3458,20 +3458,20 @@ static void mem_skip_calibrate(void)
scc_mgr_set_dqdqs_output_phase(i, (1.25 *
IO_DLL_CHAIN_LENGTH - 2));
}
- addr = sdr_get_addr(&sdr_scc_mgr->dqs_ena);
+ addr = (u32)&sdr_scc_mgr->dqs_ena;
writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_scc_mgr->dqs_io_ena);
+ addr = (u32)&sdr_scc_mgr->dqs_io_ena;
writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
addr = sdr_get_addr((u32 *)SCC_MGR_GROUP_COUNTER);
for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
writel(i, SOCFPGA_SDR_ADDRESS + addr);
}
- addr = sdr_get_addr(&sdr_scc_mgr->dq_ena);
+ addr = (u32)&sdr_scc_mgr->dq_ena;
writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_scc_mgr->dm_ena);
+ addr = (u32)&sdr_scc_mgr->dm_ena;
writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
}
@@ -3480,7 +3480,7 @@ static void mem_skip_calibrate(void)
scc_mgr_set_dqs_bus_in_delay(i, 10);
scc_mgr_load_dqs(i);
}
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
/*
@@ -3690,7 +3690,7 @@ static uint32_t mem_calibrate(void)
* Do not remove this line as it makes sure all of our decisions
* have been applied.
*/
- addr = sdr_get_addr(&sdr_scc_mgr->update);
+ addr = (u32)&sdr_scc_mgr->update;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
return 1;
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 047/172] ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_rw_load.*->.*)
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (45 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 046/172] ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_scc_mgr->.*) Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 048/172] ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_mgr_.*->.*) Marek Vasut
` (126 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Instead of this indirection, just adjust the register pointer and
directly use the register base address.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 126 ++++++++++++++++++++---------------------
1 file changed, 63 insertions(+), 63 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 4cc2a96..2ff746f 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -16,10 +16,10 @@
static void scc_mgr_load_dqs_for_write_group(uint32_t write_group);
static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
- (struct socfpga_sdr_rw_load_manager *)(BASE_RW_MGR + 0x800);
+ (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
- (struct socfpga_sdr_rw_load_jump_manager *)(BASE_RW_MGR + 0xC00);
+ (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
static struct socfpga_sdr_reg_file *sdr_reg_file =
(struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
@@ -873,7 +873,7 @@ static void scc_mgr_apply_group_all_out_delay_add_all_ranks(
/* could be applied to other protocols if we wanted to */
static void set_jump_as_return(void)
{
- uint32_t addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
+ uint32_t addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
/*
* to save space, we replace return with jump to special shared
@@ -881,7 +881,7 @@ static void set_jump_as_return(void)
* we always jump
*/
writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
writel(RW_MGR_RETURN, SOCFPGA_SDR_ADDRESS + addr);
}
@@ -944,25 +944,25 @@ static void delay_for_n_mem_clocks(const uint32_t clocks)
* overhead
*/
if (afi_clocks <= 0x100) {
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
writel(RW_MGR_IDLE_LOOP1, SOCFPGA_SDR_ADDRESS + addr);
addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
writel(RW_MGR_IDLE_LOOP1, SOCFPGA_SDR_ADDRESS + addr);
} else {
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer), SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
writel(RW_MGR_IDLE_LOOP2, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
writel(RW_MGR_IDLE_LOOP2, SOCFPGA_SDR_ADDRESS + addr);
/* hack to get around compiler not being smart enough */
@@ -1016,24 +1016,24 @@ static void rw_mgr_mem_initialize(void)
*/
/* Load counters */
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL),
SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL),
SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL),
SOCFPGA_SDR_ADDRESS + addr);
/* Load jump address */
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
/* Execute count instruction */
@@ -1060,22 +1060,22 @@ static void rw_mgr_mem_initialize(void)
*/
/* Load counters */
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR0_VAL),
SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR1_VAL),
SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR2_VAL),
SOCFPGA_SDR_ADDRESS + addr);
/* Load jump address */
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
@@ -1223,14 +1223,14 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
/* Load up a constant bursts of read commands */
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
writel(0x20, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
writel(RW_MGR_GUARANTEED_READ, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
writel(0x20, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
writel(RW_MGR_GUARANTEED_READ_CONT, SOCFPGA_SDR_ADDRESS + addr);
tmp_bit_chk = 0;
@@ -1296,28 +1296,28 @@ static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
/* Load up a constant bursts */
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
writel(0x20, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
writel(RW_MGR_GUARANTEED_WRITE_WAIT0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
writel(0x20, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
writel(RW_MGR_GUARANTEED_WRITE_WAIT1, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
writel(0x04, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
writel(RW_MGR_GUARANTEED_WRITE_WAIT2, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr3);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3;
writel(0x04, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
writel(RW_MGR_GUARANTEED_WRITE_WAIT3, SOCFPGA_SDR_ADDRESS + addr);
addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
@@ -1358,18 +1358,18 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group
/* set rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
writel(0x10, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
writel(RW_MGR_READ_B2B_WAIT1, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
writel(0x10, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
writel(RW_MGR_READ_B2B_WAIT2, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
if (quick_read_mode)
writel(0x1, SOCFPGA_SDR_ADDRESS + addr);
/* need at least two (1+1) reads to capture failures */
@@ -1378,9 +1378,9 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group
else
writel(0x32, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
writel(RW_MGR_READ_B2B, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr3);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3;
if (all_groups)
writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
@@ -1388,7 +1388,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group
else
writel(0x0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
writel(RW_MGR_READ_B2B, SOCFPGA_SDR_ADDRESS + addr);
tmp_bit_chk = 0;
@@ -2665,23 +2665,23 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
* instruction that sends out the data. We set the counter to a
* large number so that the jump is always taken.
*/
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
writel(0xFF, SOCFPGA_SDR_ADDRESS + addr);
/* CNTR 3 - Not used */
if (test_dm) {
mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
SOCFPGA_SDR_ADDRESS + addr);
} else {
mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP, SOCFPGA_SDR_ADDRESS + addr);
}
} else if (rw_wl_nop_cycles == 0) {
@@ -2690,18 +2690,18 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
* to the DQS enable instruction. We set the counter to a large
* number so that the jump is always taken.
*/
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
writel(0xFF, SOCFPGA_SDR_ADDRESS + addr);
/* CNTR 3 - Not used */
if (test_dm) {
mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
SOCFPGA_SDR_ADDRESS + addr);
} else {
mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS, SOCFPGA_SDR_ADDRESS + addr);
}
} else {
@@ -2710,24 +2710,24 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
* and NOT take the jump. So we set the counter to 0. The jump
* address doesn't count.
*/
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr2);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
writel(0x0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
writel(0x0, SOCFPGA_SDR_ADDRESS + addr);
/*
* CNTR 3 - Set the nop counter to the number of cycles we
* need to loop for, minus 1.
*/
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr3);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3;
writel(rw_wl_nop_cycles - 1, SOCFPGA_SDR_ADDRESS + addr);
if (test_dm) {
mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP, SOCFPGA_SDR_ADDRESS + addr);
} else {
mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP, SOCFPGA_SDR_ADDRESS + addr);
}
}
@@ -2735,23 +2735,23 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
addr = sdr_get_addr((u32 *)RW_MGR_RESET_READ_DATAPATH);
writel(0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
if (quick_write_mode)
writel(0x08, SOCFPGA_SDR_ADDRESS + addr);
else
writel(0x40, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
writel(mcc_instruction, SOCFPGA_SDR_ADDRESS + addr);
/*
* CNTR 1 - This is used to ensure enough time elapses
* for read data to come back.
*/
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
writel(0x30, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
if (test_dm) {
writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT, SOCFPGA_SDR_ADDRESS + addr);
} else {
@@ -3333,14 +3333,14 @@ static void mem_precharge_and_activate(void)
addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
writel(RW_MGR_PRECHARGE_ALL, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr0);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
writel(0x0F, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_mgr_regs->load_cntr1);
+ addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
writel(0x0F, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2, SOCFPGA_SDR_ADDRESS + addr);
/* activate rows */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 048/172] ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_mgr_.*->.*)
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (46 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 047/172] ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_rw_load.*->.*) Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 049/172] ddr: altera: Pluck out remaining sdr_get_addr() calls Marek Vasut
` (125 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Instead of this indirection, just adjust the register pointer and
directly use the register base address.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 52 +++++++++++++++++++++---------------------
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 2ff746f..7ba73ab 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -28,10 +28,10 @@ static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
(struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
- (struct socfpga_phy_mgr_cmd *)(BASE_PHY_MGR);
+ (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
- (struct socfpga_phy_mgr_cfg *)(BASE_PHY_MGR + 0x4000);
+ (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
static struct socfpga_data_mgr *data_mgr =
(struct socfpga_data_mgr *)(BASE_DATA_MGR);
@@ -181,7 +181,7 @@ static void reg_file_set_sub_stage(uint32_t set_sub_stage)
static void initialize(void)
{
- u32 addr = sdr_get_addr(&phy_mgr_cfg->mux_sel);
+ u32 addr = (u32)&phy_mgr_cfg->mux_sel;
debug("%s:%d\n", __func__, __LINE__);
/* USER calibration has control over path to memory */
@@ -193,14 +193,14 @@ static void initialize(void)
writel(0x3, SOCFPGA_SDR_ADDRESS + addr);
/* USER memory clock is not stable we begin initialization */
- addr = sdr_get_addr(&phy_mgr_cfg->reset_mem_stbl);
+ addr = (u32)&phy_mgr_cfg->reset_mem_stbl;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
/* USER calibration status all set to zero */
- addr = sdr_get_addr(&phy_mgr_cfg->cal_status);
+ addr = (u32)&phy_mgr_cfg->cal_status;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&phy_mgr_cfg->cal_debug_info);
+ addr = (u32)&phy_mgr_cfg->cal_debug_info;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
if ((dyn_calib_steps & CALIB_SKIP_ALL) != CALIB_SKIP_ALL) {
@@ -1041,7 +1041,7 @@ static void rw_mgr_mem_initialize(void)
writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
/* indicate that memory is stable */
- addr = sdr_get_addr(&phy_mgr_cfg->reset_mem_stbl);
+ addr = (u32)&phy_mgr_cfg->reset_mem_stbl;
writel(1, SOCFPGA_SDR_ADDRESS + addr);
/*
@@ -1237,7 +1237,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
/* reset the fifos to get pointers to known state */
- addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
+ addr = (u32)&phy_mgr_cmd->fifo_reset;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
addr = sdr_get_addr((u32 *)RW_MGR_RESET_READ_DATAPATH);
writel(0, SOCFPGA_SDR_ADDRESS + addr);
@@ -1394,7 +1394,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group
tmp_bit_chk = 0;
for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
/* reset the fifos to get pointers to known state */
- addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
+ addr = (u32)&phy_mgr_cmd->fifo_reset;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
addr = sdr_get_addr((u32 *)RW_MGR_RESET_READ_DATAPATH);
writel(0, SOCFPGA_SDR_ADDRESS + addr);
@@ -1449,7 +1449,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
{
- uint32_t addr = sdr_get_addr(&phy_mgr_cmd->inc_vfifo_hard_phy);
+ uint32_t addr = (u32)&phy_mgr_cmd->inc_vfifo_hard_phy;
writel(grp, SOCFPGA_SDR_ADDRESS + addr);
(*v)++;
@@ -2572,7 +2572,7 @@ static uint32_t rw_mgr_mem_calibrate_lfifo(void)
rw_mgr_mem_calibrate_read_load_patterns(0, 1);
found_one = 0;
- addr = sdr_get_addr(&phy_mgr_cfg->phy_rlat);
+ addr = (u32)&phy_mgr_cfg->phy_rlat;
do {
writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr);
debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
@@ -2593,13 +2593,13 @@ static uint32_t rw_mgr_mem_calibrate_lfifo(void)
/* reset the fifos to get pointers to known state */
- addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
+ addr = (u32)&phy_mgr_cmd->fifo_reset;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
if (found_one) {
/* add a fudge factor to the read latency that was determined */
gbl->curr_read_lat += 2;
- addr = sdr_get_addr(&phy_mgr_cfg->phy_rlat);
+ addr = (u32)&phy_mgr_cfg->phy_rlat;
writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr);
debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
read_lat=%u\n", __func__, __LINE__,
@@ -2790,7 +2790,7 @@ static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
tmp_bit_chk = 0;
- addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
+ addr = (u32)&phy_mgr_cmd->fifo_reset;
addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
/* reset the fifos to get pointers to known state */
@@ -3396,12 +3396,12 @@ static void mem_config(void)
if (gbl->curr_read_lat > max_latency)
gbl->curr_read_lat = max_latency;
- addr = sdr_get_addr(&phy_mgr_cfg->phy_rlat);
+ addr = (u32)&phy_mgr_cfg->phy_rlat;
writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr);
/* advertise write latency */
gbl->curr_write_lat = wlat;
- addr = sdr_get_addr(&phy_mgr_cfg->afi_wlat);
+ addr = (u32)&phy_mgr_cfg->afi_wlat;
writel(wlat - 2, SOCFPGA_SDR_ADDRESS + addr);
/* initialize bit slips */
@@ -3488,11 +3488,11 @@ static void mem_skip_calibrate(void)
* in sequencer.
*/
vfifo_offset = CALIB_VFIFO_OFFSET;
- addr = sdr_get_addr(&phy_mgr_cmd->inc_vfifo_hard_phy);
+ addr = (u32)&phy_mgr_cmd->inc_vfifo_hard_phy;
for (j = 0; j < vfifo_offset; j++) {
writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
}
- addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
+ addr = (u32)&phy_mgr_cmd->fifo_reset;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
/*
@@ -3500,7 +3500,7 @@ static void mem_skip_calibrate(void)
* generation-time constant.
*/
gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
- addr = sdr_get_addr(&phy_mgr_cfg->phy_rlat);
+ addr = (u32)&phy_mgr_cfg->phy_rlat;
writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr);
}
@@ -3704,7 +3704,7 @@ static uint32_t run_mem_calibrate(void)
debug("%s:%d\n", __func__, __LINE__);
/* Reset pass/fail status shown on afi_cal_success/fail */
- addr = sdr_get_addr(&phy_mgr_cfg->cal_status);
+ addr = (u32)&phy_mgr_cfg->cal_status;
writel(PHY_MGR_CAL_RESET, SOCFPGA_SDR_ADDRESS + addr);
addr = sdr_get_addr((u32 *)BASE_MMR);
@@ -3720,7 +3720,7 @@ static uint32_t run_mem_calibrate(void)
pass = mem_calibrate();
mem_precharge_and_activate();
- addr = sdr_get_addr(&phy_mgr_cmd->fifo_reset);
+ addr = (u32)&phy_mgr_cmd->fifo_reset;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
/*
@@ -3734,7 +3734,7 @@ static uint32_t run_mem_calibrate(void)
* 0: AFI Mux Select
* 1: DDIO Mux Select
*/
- addr = sdr_get_addr(&phy_mgr_cfg->mux_sel);
+ addr = (u32)&phy_mgr_cfg->mux_sel;
writel(0x2, SOCFPGA_SDR_ADDRESS + addr);
}
@@ -3759,9 +3759,9 @@ static uint32_t run_mem_calibrate(void)
addr = (u32)&sdr_reg_file->fom;
writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&phy_mgr_cfg->cal_debug_info);
+ addr = (u32)&phy_mgr_cfg->cal_debug_info;
writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&phy_mgr_cfg->cal_status);
+ addr = (u32)&phy_mgr_cfg->cal_status;
writel(PHY_MGR_CAL_SUCCESS, SOCFPGA_SDR_ADDRESS + addr);
} else {
printf("%s: CALIBRATION FAILED\n", __FILE__);
@@ -3772,9 +3772,9 @@ static uint32_t run_mem_calibrate(void)
addr = (u32)&sdr_reg_file->failing_stage;
writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&phy_mgr_cfg->cal_debug_info);
+ addr = (u32)&phy_mgr_cfg->cal_debug_info;
writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&phy_mgr_cfg->cal_status);
+ addr = (u32)&phy_mgr_cfg->cal_status;
writel(PHY_MGR_CAL_FAIL, SOCFPGA_SDR_ADDRESS + addr);
/* Update the failing group/stage in the register file */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 049/172] ddr: altera: Pluck out remaining sdr_get_addr() calls
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (47 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 048/172] ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_mgr_.*->.*) Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 050/172] ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESS Marek Vasut
` (124 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Remove the remaining invocations of sdr_get_addr() and the function
itself. This makes the code a bit less cryptic.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 141 ++++++++++++++++-------------------------
drivers/ddr/altera/sequencer.h | 53 ++++++----------
2 files changed, 75 insertions(+), 119 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 7ba73ab..7c563dd 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -34,10 +34,9 @@ static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
(struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
static struct socfpga_data_mgr *data_mgr =
- (struct socfpga_data_mgr *)(BASE_DATA_MGR);
+ (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
#define DELTA_D 1
-#define MGR_SELECT_MASK 0xf8000
/*
* In order to reduce ROM size, most of the selectable calibration steps are
@@ -83,37 +82,6 @@ static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
uint32_t write_group, uint32_t use_dm,
uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
-static u32 sdr_get_addr(u32 *base)
-{
- u32 addr = (u32)base & MGR_SELECT_MASK;
-
- switch (addr) {
- case BASE_PHY_MGR:
- addr = (((u32)base >> 8) & (1 << 6)) | ((u32)base & 0x3f) |
- SDR_PHYGRP_PHYMGRGRP_ADDRESS;
- break;
- case BASE_RW_MGR:
- addr = ((u32)base & 0x1fff) | SDR_PHYGRP_RWMGRGRP_ADDRESS;
- break;
- case BASE_DATA_MGR:
- addr = ((u32)base & 0x7ff) | SDR_PHYGRP_DATAMGRGRP_ADDRESS;
- break;
- case BASE_SCC_MGR:
- addr = ((u32)base & 0xfff) | SDR_PHYGRP_SCCGRP_ADDRESS;
- break;
- case BASE_REG_FILE:
- addr = ((u32)base & 0x7ff) | SDR_PHYGRP_REGFILEGRP_ADDRESS;
- break;
- case BASE_MMR:
- addr = ((u32)base & 0xfff) | SDR_CTRLGRP_ADDRESS;
- break;
- default:
- return -1;
- }
-
- return addr;
-}
-
static void set_failing_group_stage(uint32_t group, uint32_t stage,
uint32_t substage)
{
@@ -318,13 +286,13 @@ static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
(0xFF & ~(1 << rank)) |
((0xFF & odt_mask_0) << 8) |
((0xFF & odt_mask_1) << 16);
- addr = sdr_get_addr((u32 *)RW_MGR_SET_CS_AND_ODT_MASK);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_SET_CS_AND_ODT_MASK_OFFSET;
writel(cs_and_odt_mask, SOCFPGA_SDR_ADDRESS + addr);
}
static void scc_mgr_initialize(void)
{
- u32 addr = sdr_get_addr((u32 *)SCC_MGR_HHP_RFILE);
+ u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_HHP_RFILE_OFFSET;
/*
* Clear register file for HPS
@@ -343,7 +311,7 @@ static void scc_mgr_initialize(void)
static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group,
uint32_t delay)
{
- u32 addr = sdr_get_addr((u32 *)SCC_MGR_DQS_IN_DELAY);
+ u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
/* Load the setting in the SCC manager */
writel(delay, SOCFPGA_SDR_ADDRESS + addr + (read_group << 2));
@@ -352,14 +320,14 @@ static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group,
static void scc_mgr_set_dqs_io_in_delay(uint32_t write_group,
uint32_t delay)
{
- u32 addr = sdr_get_addr((u32 *)SCC_MGR_IO_IN_DELAY);
+ u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
writel(delay, SOCFPGA_SDR_ADDRESS + addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
}
static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
{
- u32 addr = sdr_get_addr((u32 *)SCC_MGR_DQS_EN_PHASE);
+ u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_EN_PHASE_OFFSET;
/* Load the setting in the SCC manager */
writel(phase, SOCFPGA_SDR_ADDRESS + addr + (read_group << 2));
@@ -399,7 +367,7 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,
static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group,
uint32_t phase)
{
- u32 addr = sdr_get_addr((u32 *)SCC_MGR_DQDQS_OUT_PHASE);
+ u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQDQS_OUT_PHASE_OFFSET;
/* Load the setting in the SCC manager */
writel(phase, SOCFPGA_SDR_ADDRESS + addr + (write_group << 2));
@@ -438,7 +406,7 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
{
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_DQS_EN_DELAY);
+ uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_EN_DELAY_OFFSET;
/* Load the setting in the SCC manager */
writel(delay + IO_DQS_EN_DELAY_OFFSET, SOCFPGA_SDR_ADDRESS + addr +
@@ -483,7 +451,7 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)
{
uint32_t read_group;
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_OCT_OUT1_DELAY);
+ uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_OCT_OUT1_DELAY_OFFSET;
/*
* Load the setting in the SCC manager
@@ -502,7 +470,7 @@ static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)
static void scc_mgr_set_dq_out1_delay(uint32_t write_group,
uint32_t dq_in_group, uint32_t delay)
{
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_IO_OUT1_DELAY);
+ uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
/* Load the setting in the SCC manager */
writel(delay, SOCFPGA_SDR_ADDRESS + addr + (dq_in_group << 2));
@@ -511,7 +479,7 @@ static void scc_mgr_set_dq_out1_delay(uint32_t write_group,
static void scc_mgr_set_dq_in_delay(uint32_t write_group,
uint32_t dq_in_group, uint32_t delay)
{
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_IO_IN_DELAY);
+ uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
/* Load the setting in the SCC manager */
writel(delay, SOCFPGA_SDR_ADDRESS + addr + (dq_in_group << 2));
@@ -529,7 +497,7 @@ static void scc_mgr_set_hhp_extras(void)
* bits: 8:8 = 1'b0 - separate OE from Output delay setting
*/
uint32_t value = (0<<8) | (0<<7) | (1<<5) | (1<<2) | (1<<1) | (1<<0);
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_HHP_GLOBALS);
+ uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_HHP_GLOBALS_OFFSET;
writel(value, SOCFPGA_SDR_ADDRESS + addr + SCC_MGR_HHP_EXTRAS_OFFSET);
}
@@ -537,7 +505,7 @@ static void scc_mgr_set_hhp_extras(void)
static void scc_mgr_set_dqs_out1_delay(uint32_t write_group,
uint32_t delay)
{
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_IO_OUT1_DELAY);
+ uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
/* Load the setting in the SCC manager */
writel(delay, SOCFPGA_SDR_ADDRESS + addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
@@ -546,7 +514,7 @@ static void scc_mgr_set_dqs_out1_delay(uint32_t write_group,
static void scc_mgr_set_dm_out1_delay(uint32_t write_group,
uint32_t dm, uint32_t delay)
{
- uint32_t addr = sdr_get_addr((u32 *)SCC_MGR_IO_OUT1_DELAY);
+ uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
/* Load the setting in the SCC manager */
writel(delay, SOCFPGA_SDR_ADDRESS + addr +
@@ -950,7 +918,7 @@ static void delay_for_n_mem_clocks(const uint32_t clocks)
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
writel(RW_MGR_IDLE_LOOP1, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
writel(RW_MGR_IDLE_LOOP1, SOCFPGA_SDR_ADDRESS + addr);
} else {
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
@@ -968,11 +936,11 @@ static void delay_for_n_mem_clocks(const uint32_t clocks)
/* hack to get around compiler not being smart enough */
if (afi_clocks <= 0x10000) {
/* only need to run once */
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
writel(RW_MGR_IDLE_LOOP2, SOCFPGA_SDR_ADDRESS + addr);
} else {
do {
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
writel(RW_MGR_IDLE_LOOP2, SOCFPGA_SDR_ADDRESS + addr);
} while (c_loop-- != 0);
}
@@ -988,7 +956,7 @@ static void rw_mgr_mem_initialize(void)
debug("%s:%d\n", __func__, __LINE__);
/* The reset / cke part of initialization is broadcasted to all ranks */
- addr = sdr_get_addr((u32 *)RW_MGR_SET_CS_AND_ODT_MASK);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_SET_CS_AND_ODT_MASK_OFFSET;
writel(RW_MGR_RANK_ALL, SOCFPGA_SDR_ADDRESS + addr);
/*
@@ -1037,7 +1005,7 @@ static void rw_mgr_mem_initialize(void)
writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
/* Execute count instruction */
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
/* indicate that memory is stable */
@@ -1078,7 +1046,7 @@ static void rw_mgr_mem_initialize(void)
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
/* bring up clock enable */
@@ -1101,7 +1069,7 @@ static void rw_mgr_mem_initialize(void)
*/
if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
set_jump_as_return();
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
writel(RW_MGR_MRS2_MIRR, SOCFPGA_SDR_ADDRESS + addr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
@@ -1114,7 +1082,7 @@ static void rw_mgr_mem_initialize(void)
writel(RW_MGR_MRS0_DLL_RESET_MIRR, SOCFPGA_SDR_ADDRESS + addr);
} else {
set_jump_as_return();
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
writel(RW_MGR_MRS2, SOCFPGA_SDR_ADDRESS + addr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
@@ -1126,7 +1094,7 @@ static void rw_mgr_mem_initialize(void)
writel(RW_MGR_MRS0_DLL_RESET, SOCFPGA_SDR_ADDRESS + addr);
}
set_jump_as_return();
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
writel(RW_MGR_ZQCL, SOCFPGA_SDR_ADDRESS + addr);
/* tZQinit = tDLLK = 512 ck cycles */
@@ -1152,7 +1120,7 @@ static void rw_mgr_mem_handoff(void)
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
/* precharge all banks ... */
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
writel(RW_MGR_PRECHARGE_ALL, SOCFPGA_SDR_ADDRESS + addr);
/* load up MR settings specified by user */
@@ -1161,7 +1129,7 @@ static void rw_mgr_mem_handoff(void)
* Use Mirror-ed commands for odd ranks if address
* mirrorring is on
*/
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
set_jump_as_return();
writel(RW_MGR_MRS2_MIRR, SOCFPGA_SDR_ADDRESS + addr);
@@ -1239,13 +1207,13 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
addr = (u32)&phy_mgr_cmd->fifo_reset;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr((u32 *)RW_MGR_RESET_READ_DATAPATH);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RESET_READ_DATAPATH_OFFSET;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
/ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
writel(RW_MGR_GUARANTEED_READ, SOCFPGA_SDR_ADDRESS + addr +
((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
vg) << 2));
@@ -1260,7 +1228,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
*bit_chk &= tmp_bit_chk;
}
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
writel(RW_MGR_CLEAR_DQS_ENABLE, SOCFPGA_SDR_ADDRESS + addr + (group << 2));
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
@@ -1320,7 +1288,7 @@ static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
writel(RW_MGR_GUARANTEED_WRITE_WAIT3, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
writel(RW_MGR_GUARANTEED_WRITE, SOCFPGA_SDR_ADDRESS + addr);
}
@@ -1396,14 +1364,17 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group
/* reset the fifos to get pointers to known state */
addr = (u32)&phy_mgr_cmd->fifo_reset;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr((u32 *)RW_MGR_RESET_READ_DATAPATH);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RESET_READ_DATAPATH_OFFSET;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
/ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
- addr = sdr_get_addr((u32 *)(all_groups ? RW_MGR_RUN_ALL_GROUPS :
- RW_MGR_RUN_SINGLE_GROUP));
+ if (all_groups)
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
+ else
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+
writel(RW_MGR_READ_B2B, SOCFPGA_SDR_ADDRESS + addr +
((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
vg) << 2));
@@ -1418,7 +1389,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group
*bit_chk &= tmp_bit_chk;
}
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
writel(RW_MGR_CLEAR_DQS_ENABLE, SOCFPGA_SDR_ADDRESS + addr + (group << 2));
if (all_correct) {
@@ -2018,7 +1989,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
- addr = sdr_get_addr((u32 *)SCC_MGR_DQS_IN_DELAY);
+ addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
start_dqs = readl(SOCFPGA_SDR_ADDRESS + addr + (read_group << 2));
if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
start_dqs_en = readl(SOCFPGA_SDR_ADDRESS + addr + ((read_group << 2)
@@ -2306,7 +2277,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
dqs_margin = IO_IO_IN_DELAY_MAX + 1;
dq_margin = IO_IO_IN_DELAY_MAX + 1;
- addr = sdr_get_addr((u32 *)SCC_MGR_IO_IN_DELAY);
+ addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
/* add delay to bring centre of all DQ windows to the same "level" */
for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
/* Use values before divide by 2 to reduce round off error */
@@ -2732,7 +2703,7 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
}
}
- addr = sdr_get_addr((u32 *)RW_MGR_RESET_READ_DATAPATH);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RESET_READ_DATAPATH_OFFSET;
writel(0, SOCFPGA_SDR_ADDRESS + addr);
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
@@ -2758,7 +2729,7 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT, SOCFPGA_SDR_ADDRESS + addr);
}
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
writel(mcc_instruction, SOCFPGA_SDR_ADDRESS + addr + (group << 2));
}
@@ -2858,7 +2829,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
dm_margin = 0;
- addr = sdr_get_addr((u32 *)SCC_MGR_IO_OUT1_DELAY);
+ addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
start_dqs = readl(SOCFPGA_SDR_ADDRESS + addr +
(RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
@@ -3097,7 +3068,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
/* add delay to bring centre of all DQ windows to the same "level" */
- addr = sdr_get_addr((u32 *)SCC_MGR_IO_OUT1_DELAY);
+ addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
/* Use values before divide by 2 to reduce round off error */
shift_dq = (left_edge[i] - right_edge[i] -
@@ -3330,7 +3301,7 @@ static void mem_precharge_and_activate(void)
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
/* precharge all banks ... */
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
writel(RW_MGR_PRECHARGE_ALL, SOCFPGA_SDR_ADDRESS + addr);
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
@@ -3344,7 +3315,7 @@ static void mem_precharge_and_activate(void)
writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2, SOCFPGA_SDR_ADDRESS + addr);
/* activate rows */
- addr = sdr_get_addr((u32 *)RW_MGR_RUN_SINGLE_GROUP);
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
writel(RW_MGR_ACTIVATE_0_AND_1, SOCFPGA_SDR_ADDRESS + addr);
}
}
@@ -3359,10 +3330,10 @@ static void mem_config(void)
debug("%s:%d\n", __func__, __LINE__);
/* read in write and read latency */
- addr = sdr_get_addr(&data_mgr->t_wl_add);
+ addr = (u32)&data_mgr->t_wl_add;
wlat = readl(SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr(&data_mgr->mem_t_add);
+ addr = (u32)&data_mgr->mem_t_add;
wlat += readl(SOCFPGA_SDR_ADDRESS + addr);
/* WL for hard phy does not include additive latency */
@@ -3373,7 +3344,7 @@ static void mem_config(void)
*/
wlat = wlat + 1;
- addr = sdr_get_addr(&data_mgr->t_rl_add);
+ addr = (u32)&data_mgr->t_rl_add;
rlat = readl(SOCFPGA_SDR_ADDRESS + addr);
rw_wl_nop_cycles = wlat - 2;
@@ -3463,7 +3434,7 @@ static void mem_skip_calibrate(void)
addr = (u32)&sdr_scc_mgr->dqs_io_ena;
writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr((u32 *)SCC_MGR_GROUP_COUNTER);
+ addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_GROUP_COUNTER_OFFSET;
for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
writel(i, SOCFPGA_SDR_ADDRESS + addr);
}
@@ -3529,7 +3500,7 @@ static uint32_t mem_calibrate(void)
mem_config();
uint32_t bypass_mode = 0x1;
- addr = sdr_get_addr((u32 *)SCC_MGR_GROUP_COUNTER);
+ addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_GROUP_COUNTER_OFFSET;
for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
writel(i, SOCFPGA_SDR_ADDRESS + addr);
scc_set_bypass_mode(i, bypass_mode);
@@ -3565,7 +3536,7 @@ static uint32_t mem_calibrate(void)
if (current_run == 0)
continue;
- addr = sdr_get_addr((u32 *)SCC_MGR_GROUP_COUNTER);
+ addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_GROUP_COUNTER_OFFSET;
writel(write_group, SOCFPGA_SDR_ADDRESS + addr);
scc_mgr_zero_group(write_group, write_test_bgn,
0);
@@ -3707,11 +3678,11 @@ static uint32_t run_mem_calibrate(void)
addr = (u32)&phy_mgr_cfg->cal_status;
writel(PHY_MGR_CAL_RESET, SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr((u32 *)BASE_MMR);
+ addr = SDR_CTRLGRP_ADDRESS;
/* stop tracking manger */
uint32_t ctrlcfg = readl(SOCFPGA_SDR_ADDRESS + addr);
- addr = sdr_get_addr((u32 *)BASE_MMR);
+ addr = SDR_CTRLGRP_ADDRESS;
writel(ctrlcfg & 0xFFBFFFFF, SOCFPGA_SDR_ADDRESS + addr);
initialize();
@@ -3738,7 +3709,7 @@ static uint32_t run_mem_calibrate(void)
writel(0x2, SOCFPGA_SDR_ADDRESS + addr);
}
- addr = sdr_get_addr((u32 *)BASE_MMR);
+ addr = SDR_CTRLGRP_ADDRESS;
writel(ctrlcfg, SOCFPGA_SDR_ADDRESS + addr);
if (pass) {
@@ -3793,13 +3764,13 @@ static void hc_initialize_rom_data(void)
uint32_t i;
uint32_t addr;
- addr = sdr_get_addr((u32 *)(RW_MGR_INST_ROM_WRITE));
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++) {
uint32_t data = inst_rom_init[i];
writel(data, SOCFPGA_SDR_ADDRESS + addr + (i << 2));
}
- addr = sdr_get_addr((u32 *)(RW_MGR_AC_ROM_WRITE));
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++) {
uint32_t data = ac_rom_init[i];
writel(data, SOCFPGA_SDR_ADDRESS + addr + (i << 2));
@@ -3862,7 +3833,7 @@ static void initialize_hps_phy(void)
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
trk_sample_count);
- addr = sdr_get_addr((u32 *)BASE_MMR);
+ addr = SDR_CTRLGRP_ADDRESS;
writel(reg, SOCFPGA_SDR_ADDRESS + addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET);
reg = 0;
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
index ed2bae2..0aa9579 100644
--- a/drivers/ddr/altera/sequencer.h
+++ b/drivers/ddr/altera/sequencer.h
@@ -16,17 +16,16 @@
/ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)
#define NUM_RANKS_PER_SHADOW_REG (RW_MGR_MEM_NUMBER_OF_RANKS / NUM_SHADOW_REGS)
-#define RW_MGR_RUN_SINGLE_GROUP (BASE_RW_MGR)
-#define RW_MGR_RUN_ALL_GROUPS (BASE_RW_MGR + 0x0400)
-
-#define RW_MGR_DI_BASE (BASE_RW_MGR + 0x0020)
+#define RW_MGR_RUN_SINGLE_GROUP_OFFSET 0x0
+#define RW_MGR_RUN_ALL_GROUPS_OFFSET 0x0400
+#define RW_MGR_RESET_READ_DATAPATH_OFFSET 0x1000
+#define RW_MGR_SET_CS_AND_ODT_MASK_OFFSET 0x1400
+#define RW_MGR_INST_ROM_WRITE_OFFSET 0x1800
+#define RW_MGR_AC_ROM_WRITE_OFFSET 0x1C00
#define RW_MGR_MEM_NUMBER_OF_RANKS 1
#define NUM_SHADOW_REGS 1
-#define RW_MGR_RESET_READ_DATAPATH (BASE_RW_MGR + 0x1000)
-#define RW_MGR_SET_CS_AND_ODT_MASK (BASE_RW_MGR + 0x1400)
-
#define RW_MGR_RANK_NONE 0xFF
#define RW_MGR_RANK_ALL 0x00
@@ -78,32 +77,21 @@
/* length of VFIFO, from SW_MACROS */
#define VFIFO_SIZE (READ_VALID_FIFO_SIZE)
-/* MarkW: how should these base addresses be done for A-V? */
-#define BASE_PTR_MGR 0x00040000
-#define BASE_SCC_MGR 0x00058000
-#define BASE_REG_FILE 0x00070000
-#define BASE_TIMER 0x00078000
-#define BASE_PHY_MGR 0x00088000
-#define BASE_RW_MGR 0x00090000
-#define BASE_DATA_MGR 0x00098000
-#define BASE_MMR 0x000C0000
-#define BASE_TRK_MGR 0x000D0000
-
-#define SCC_MGR_GROUP_COUNTER (BASE_SCC_MGR + 0x0000)
-#define SCC_MGR_DQS_IN_DELAY (BASE_SCC_MGR + 0x0100)
-#define SCC_MGR_DQS_EN_PHASE (BASE_SCC_MGR + 0x0200)
-#define SCC_MGR_DQS_EN_DELAY (BASE_SCC_MGR + 0x0300)
-#define SCC_MGR_DQDQS_OUT_PHASE (BASE_SCC_MGR + 0x0400)
-#define SCC_MGR_OCT_OUT1_DELAY (BASE_SCC_MGR + 0x0500)
-#define SCC_MGR_IO_OUT1_DELAY (BASE_SCC_MGR + 0x0700)
-#define SCC_MGR_IO_IN_DELAY (BASE_SCC_MGR + 0x0900)
+#define SCC_MGR_GROUP_COUNTER_OFFSET 0x0000
+#define SCC_MGR_DQS_IN_DELAY_OFFSET 0x0100
+#define SCC_MGR_DQS_EN_PHASE_OFFSET 0x0200
+#define SCC_MGR_DQS_EN_DELAY_OFFSET 0x0300
+#define SCC_MGR_DQDQS_OUT_PHASE_OFFSET 0x0400
+#define SCC_MGR_OCT_OUT1_DELAY_OFFSET 0x0500
+#define SCC_MGR_IO_OUT1_DELAY_OFFSET 0x0700
+#define SCC_MGR_IO_IN_DELAY_OFFSET 0x0900
/* HHP-HPS-specific versions of some commands */
-#define SCC_MGR_DQS_EN_DELAY_GATE (BASE_SCC_MGR + 0x0600)
-#define SCC_MGR_IO_OE_DELAY (BASE_SCC_MGR + 0x0800)
-#define SCC_MGR_HHP_GLOBALS (BASE_SCC_MGR + 0x0A00)
-#define SCC_MGR_HHP_RFILE (BASE_SCC_MGR + 0x0B00)
-#define SCC_MGR_AFI_CAL_INIT (BASE_SCC_MGR + 0x0D00)
+#define SCC_MGR_DQS_EN_DELAY_GATE_OFFSET 0x0600
+#define SCC_MGR_IO_OE_DELAY_OFFSET 0x0800
+#define SCC_MGR_HHP_GLOBALS_OFFSET 0x0A00
+#define SCC_MGR_HHP_RFILE_OFFSET 0x0B00
+#define SCC_MGR_AFI_CAL_INIT_OFFSET 0x0D00
#define SDR_PHYGRP_SCCGRP_ADDRESS 0x0
#define SDR_PHYGRP_PHYMGRGRP_ADDRESS 0x1000
@@ -195,9 +183,6 @@
#define SEQ_TRESET_CNTR2_VAL 131
#endif
-#define RW_MGR_INST_ROM_WRITE BASE_RW_MGR + 0x1800
-#define RW_MGR_AC_ROM_WRITE BASE_RW_MGR + 0x1C00
-
struct socfpga_sdr_rw_load_manager {
u32 load_cntr0;
u32 load_cntr1;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 050/172] ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESS
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (48 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 049/172] ddr: altera: Pluck out remaining sdr_get_addr() calls Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 051/172] ddr: altera: Stop using SDR_CTRLGRP_ADDRESS directly Marek Vasut
` (123 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Just trim down the constant SOCFPGA_SDR_ADDRESS + SDR_PHYGRP.*ADDRESS
in the code.
Signed-off-by: Marek Vasut <marex@denx.de>
---
arch/arm/mach-socfpga/include/mach/sdram.h | 2 +-
drivers/ddr/altera/sdram.c | 2 +-
drivers/ddr/altera/sequencer.c | 458 ++++++++++++++---------------
drivers/ddr/altera/sequencer.h | 10 +-
4 files changed, 236 insertions(+), 236 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index 873ea25..d57257d 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -14,7 +14,7 @@ int sdram_calibration_full(void);
extern int sdram_calibration(void);
-#define SDR_CTRLGRP_ADDRESS 0x5000
+#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
struct socfpga_sdr_ctrl {
u32 ctrl_cfg;
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c
index 90a4b2c..474df42 100644
--- a/drivers/ddr/altera/sdram.c
+++ b/drivers/ddr/altera/sdram.c
@@ -38,7 +38,7 @@ struct sdram_prot_rule {
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
static struct socfpga_sdr_ctrl *sdr_ctrl =
- (struct socfpga_sdr_ctrl *)(SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_ADDRESS);
+ (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
static int compute_errata_rows(unsigned long long memsize, int cs, int width,
int rows, int banks, int cols)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 7c563dd..591e8f6 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -101,7 +101,7 @@ static void reg_file_set_group(uint32_t set_group)
u32 addr = (u32)&sdr_reg_file->cur_stage;
/* Read the current group and stage */
- uint32_t cur_stage_group = readl(SOCFPGA_SDR_ADDRESS + addr);
+ uint32_t cur_stage_group = readl(addr);
/* Clear the group */
cur_stage_group &= 0x0000FFFF;
@@ -110,7 +110,7 @@ static void reg_file_set_group(uint32_t set_group)
cur_stage_group |= (set_group << 16);
/* Write the data back */
- writel(cur_stage_group, SOCFPGA_SDR_ADDRESS + addr);
+ writel(cur_stage_group, addr);
}
static void reg_file_set_stage(uint32_t set_stage)
@@ -118,7 +118,7 @@ static void reg_file_set_stage(uint32_t set_stage)
u32 addr = (u32)&sdr_reg_file->cur_stage;
/* Read the current group and stage */
- uint32_t cur_stage_group = readl(SOCFPGA_SDR_ADDRESS + addr);
+ uint32_t cur_stage_group = readl(addr);
/* Clear the stage and substage */
cur_stage_group &= 0xFFFF0000;
@@ -127,7 +127,7 @@ static void reg_file_set_stage(uint32_t set_stage)
cur_stage_group |= (set_stage & 0x000000FF);
/* Write the data back */
- writel(cur_stage_group, SOCFPGA_SDR_ADDRESS + addr);
+ writel(cur_stage_group, addr);
}
static void reg_file_set_sub_stage(uint32_t set_sub_stage)
@@ -135,7 +135,7 @@ static void reg_file_set_sub_stage(uint32_t set_sub_stage)
u32 addr = (u32)&sdr_reg_file->cur_stage;
/* Read the current group and stage */
- uint32_t cur_stage_group = readl(SOCFPGA_SDR_ADDRESS + addr);
+ uint32_t cur_stage_group = readl(addr);
/* Clear the substage */
cur_stage_group &= 0xFFFF00FF;
@@ -144,7 +144,7 @@ static void reg_file_set_sub_stage(uint32_t set_sub_stage)
cur_stage_group |= ((set_sub_stage << 8) & 0x0000FF00);
/* Write the data back */
- writel(cur_stage_group, SOCFPGA_SDR_ADDRESS + addr);
+ writel(cur_stage_group, addr);
}
static void initialize(void)
@@ -158,18 +158,18 @@ static void initialize(void)
* 0: AFI Mux Select
* 1: DDIO Mux Select
*/
- writel(0x3, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x3, addr);
/* USER memory clock is not stable we begin initialization */
addr = (u32)&phy_mgr_cfg->reset_mem_stbl;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
/* USER calibration status all set to zero */
addr = (u32)&phy_mgr_cfg->cal_status;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
addr = (u32)&phy_mgr_cfg->cal_debug_info;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
if ((dyn_calib_steps & CALIB_SKIP_ALL) != CALIB_SKIP_ALL) {
param->read_correct_mask_vg = ((uint32_t)1 <<
@@ -287,7 +287,7 @@ static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
((0xFF & odt_mask_0) << 8) |
((0xFF & odt_mask_1) << 16);
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_SET_CS_AND_ODT_MASK_OFFSET;
- writel(cs_and_odt_mask, SOCFPGA_SDR_ADDRESS + addr);
+ writel(cs_and_odt_mask, addr);
}
static void scc_mgr_initialize(void)
@@ -304,7 +304,7 @@ static void scc_mgr_initialize(void)
for (i = 0; i < 16; i++) {
debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
__func__, __LINE__, i);
- writel(0, SOCFPGA_SDR_ADDRESS + addr + (i << 2));
+ writel(0, addr + (i << 2));
}
}
@@ -314,7 +314,7 @@ static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group,
u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
/* Load the setting in the SCC manager */
- writel(delay, SOCFPGA_SDR_ADDRESS + addr + (read_group << 2));
+ writel(delay, addr + (read_group << 2));
}
static void scc_mgr_set_dqs_io_in_delay(uint32_t write_group,
@@ -322,7 +322,7 @@ static void scc_mgr_set_dqs_io_in_delay(uint32_t write_group,
{
u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
- writel(delay, SOCFPGA_SDR_ADDRESS + addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
+ writel(delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
}
static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
@@ -330,7 +330,7 @@ static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_EN_PHASE_OFFSET;
/* Load the setting in the SCC manager */
- writel(phase, SOCFPGA_SDR_ADDRESS + addr + (read_group << 2));
+ writel(phase, addr + (read_group << 2));
}
static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,
@@ -356,10 +356,10 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,
if (update_scan_chains) {
addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(read_group, SOCFPGA_SDR_ADDRESS + addr);
+ writel(read_group, addr);
addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
}
}
}
@@ -370,7 +370,7 @@ static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group,
u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQDQS_OUT_PHASE_OFFSET;
/* Load the setting in the SCC manager */
- writel(phase, SOCFPGA_SDR_ADDRESS + addr + (write_group << 2));
+ writel(phase, addr + (write_group << 2));
}
static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
@@ -396,10 +396,10 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
if (update_scan_chains) {
addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(write_group, SOCFPGA_SDR_ADDRESS + addr);
+ writel(write_group, addr);
addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
}
}
}
@@ -409,7 +409,7 @@ static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_EN_DELAY_OFFSET;
/* Load the setting in the SCC manager */
- writel(delay + IO_DQS_EN_DELAY_OFFSET, SOCFPGA_SDR_ADDRESS + addr +
+ writel(delay + IO_DQS_EN_DELAY_OFFSET, addr +
(read_group << 2));
}
@@ -424,7 +424,7 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
scc_mgr_set_dqs_en_delay(read_group, delay);
addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(read_group, SOCFPGA_SDR_ADDRESS + addr);
+ writel(read_group, addr);
/*
* In shadow register mode, the T11 settings are stored in
* registers in the core, which are updated by the DQS_ENA
@@ -434,7 +434,7 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
* set to 0.
*/
addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
}
/*
* In shadow register mode, the T11 settings are stored in
@@ -445,7 +445,7 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
* set to 0.
*/
addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
}
static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)
@@ -464,7 +464,7 @@ static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)
RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
- writel(delay, SOCFPGA_SDR_ADDRESS + addr + (read_group << 2));
+ writel(delay, addr + (read_group << 2));
}
static void scc_mgr_set_dq_out1_delay(uint32_t write_group,
@@ -473,7 +473,7 @@ static void scc_mgr_set_dq_out1_delay(uint32_t write_group,
uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
/* Load the setting in the SCC manager */
- writel(delay, SOCFPGA_SDR_ADDRESS + addr + (dq_in_group << 2));
+ writel(delay, addr + (dq_in_group << 2));
}
static void scc_mgr_set_dq_in_delay(uint32_t write_group,
@@ -482,7 +482,7 @@ static void scc_mgr_set_dq_in_delay(uint32_t write_group,
uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
/* Load the setting in the SCC manager */
- writel(delay, SOCFPGA_SDR_ADDRESS + addr + (dq_in_group << 2));
+ writel(delay, addr + (dq_in_group << 2));
}
static void scc_mgr_set_hhp_extras(void)
@@ -499,7 +499,7 @@ static void scc_mgr_set_hhp_extras(void)
uint32_t value = (0<<8) | (0<<7) | (1<<5) | (1<<2) | (1<<1) | (1<<0);
uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_HHP_GLOBALS_OFFSET;
- writel(value, SOCFPGA_SDR_ADDRESS + addr + SCC_MGR_HHP_EXTRAS_OFFSET);
+ writel(value, addr + SCC_MGR_HHP_EXTRAS_OFFSET);
}
static void scc_mgr_set_dqs_out1_delay(uint32_t write_group,
@@ -508,7 +508,7 @@ static void scc_mgr_set_dqs_out1_delay(uint32_t write_group,
uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
/* Load the setting in the SCC manager */
- writel(delay, SOCFPGA_SDR_ADDRESS + addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
+ writel(delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
}
static void scc_mgr_set_dm_out1_delay(uint32_t write_group,
@@ -517,7 +517,7 @@ static void scc_mgr_set_dm_out1_delay(uint32_t write_group,
uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
/* Load the setting in the SCC manager */
- writel(delay, SOCFPGA_SDR_ADDRESS + addr +
+ writel(delay, addr +
((RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm) << 2));
}
@@ -556,10 +556,10 @@ static void scc_mgr_zero_all(void)
/* multicast to all DQS group enables */
addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, addr);
addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
}
static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)
@@ -578,22 +578,22 @@ static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)
}
/* multicast to all DQ enables */
addr = (u32)&sdr_scc_mgr->dq_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, addr);
addr = (u32)&sdr_scc_mgr->dm_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, addr);
/* update current DQS IO enable */
addr = (u32)&sdr_scc_mgr->dqs_io_ena;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
/* update the DQS logic */
addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(write_group, SOCFPGA_SDR_ADDRESS + addr);
+ writel(write_group, addr);
/* hit update */
addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
}
static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
@@ -613,7 +613,7 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
/* multicast to all DQ enables */
addr = (u32)&sdr_scc_mgr->dq_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, addr);
/* Zero all DM config settings */
for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
@@ -622,7 +622,7 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
/* multicast to all DM enables */
addr = (u32)&sdr_scc_mgr->dm_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, addr);
/* zero all DQS io settings */
if (!out_only)
@@ -634,11 +634,11 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
/* multicast to all DQS IO enables (only 1) */
addr = (u32)&sdr_scc_mgr->dqs_io_ena;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
/* hit update to zero everything */
addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
}
}
@@ -647,7 +647,7 @@ static void scc_mgr_load_dqs(uint32_t dqs)
{
uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(dqs, SOCFPGA_SDR_ADDRESS + addr);
+ writel(dqs, addr);
}
static void scc_mgr_load_dqs_for_write_group(uint32_t write_group)
@@ -664,7 +664,7 @@ static void scc_mgr_load_dqs_for_write_group(uint32_t write_group)
RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
- writel(read_group, SOCFPGA_SDR_ADDRESS + addr);
+ writel(read_group, addr);
}
/* load up dqs io config settings */
@@ -672,7 +672,7 @@ static void scc_mgr_load_dqs_io(void)
{
uint32_t addr = (u32)&sdr_scc_mgr->dqs_io_ena;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
}
/* load up dq config settings */
@@ -680,7 +680,7 @@ static void scc_mgr_load_dq(uint32_t dq_in_group)
{
uint32_t addr = (u32)&sdr_scc_mgr->dq_ena;
- writel(dq_in_group, SOCFPGA_SDR_ADDRESS + addr);
+ writel(dq_in_group, addr);
}
/* load up dm config settings */
@@ -688,7 +688,7 @@ static void scc_mgr_load_dm(uint32_t dm)
{
uint32_t addr = (u32)&sdr_scc_mgr->dm_ena;
- writel(dm, SOCFPGA_SDR_ADDRESS + addr);
+ writel(dm, addr);
}
/*
@@ -833,7 +833,7 @@ static void scc_mgr_apply_group_all_out_delay_add_all_ranks(
r += NUM_RANKS_PER_SHADOW_REG) {
scc_mgr_apply_group_all_out_delay_add(write_group,
group_bgn, delay);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
}
}
@@ -848,9 +848,9 @@ static void set_jump_as_return(void)
* RETURN instruction so we set the counter to large value so that
* we always jump
*/
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_RETURN, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_RETURN, addr);
}
/*
@@ -913,35 +913,35 @@ static void delay_for_n_mem_clocks(const uint32_t clocks)
*/
if (afi_clocks <= 0x100) {
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), SOCFPGA_SDR_ADDRESS + addr);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_IDLE_LOOP1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_IDLE_LOOP1, addr);
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_IDLE_LOOP1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_IDLE_LOOP1, addr);
} else {
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), SOCFPGA_SDR_ADDRESS + addr);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), addr);
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer), SOCFPGA_SDR_ADDRESS + addr);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer), addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_IDLE_LOOP2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_IDLE_LOOP2, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_IDLE_LOOP2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_IDLE_LOOP2, addr);
/* hack to get around compiler not being smart enough */
if (afi_clocks <= 0x10000) {
/* only need to run once */
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_IDLE_LOOP2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_IDLE_LOOP2, addr);
} else {
do {
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_IDLE_LOOP2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_IDLE_LOOP2, addr);
} while (c_loop-- != 0);
}
}
@@ -957,7 +957,7 @@ static void rw_mgr_mem_initialize(void)
/* The reset / cke part of initialization is broadcasted to all ranks */
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_SET_CS_AND_ODT_MASK_OFFSET;
- writel(RW_MGR_RANK_ALL, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_RANK_ALL, addr);
/*
* Here's how you load register for a loop
@@ -986,31 +986,31 @@ static void rw_mgr_mem_initialize(void)
/* Load counters */
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL),
- SOCFPGA_SDR_ADDRESS + addr);
+ addr);
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL),
- SOCFPGA_SDR_ADDRESS + addr);
+ addr);
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL),
- SOCFPGA_SDR_ADDRESS + addr);
+ addr);
/* Load jump address */
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_INIT_RESET_0_CKE_0, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_INIT_RESET_0_CKE_0, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_INIT_RESET_0_CKE_0, addr);
/* Execute count instruction */
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_INIT_RESET_0_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_INIT_RESET_0_CKE_0, addr);
/* indicate that memory is stable */
addr = (u32)&phy_mgr_cfg->reset_mem_stbl;
- writel(1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(1, addr);
/*
* transition the RESET to high
@@ -1030,24 +1030,24 @@ static void rw_mgr_mem_initialize(void)
/* Load counters */
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR0_VAL),
- SOCFPGA_SDR_ADDRESS + addr);
+ addr);
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR1_VAL),
- SOCFPGA_SDR_ADDRESS + addr);
+ addr);
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR2_VAL),
- SOCFPGA_SDR_ADDRESS + addr);
+ addr);
/* Load jump address */
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_INIT_RESET_1_CKE_0, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_INIT_RESET_1_CKE_0, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_INIT_RESET_1_CKE_0, addr);
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_INIT_RESET_1_CKE_0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_INIT_RESET_1_CKE_0, addr);
/* bring up clock enable */
@@ -1070,32 +1070,32 @@ static void rw_mgr_mem_initialize(void)
if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
set_jump_as_return();
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_MRS2_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS2_MIRR, addr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS3_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS3_MIRR, addr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS1_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS1_MIRR, addr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS0_DLL_RESET_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS0_DLL_RESET_MIRR, addr);
} else {
set_jump_as_return();
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_MRS2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS2, addr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS3, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS3, addr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS1, addr);
set_jump_as_return();
- writel(RW_MGR_MRS0_DLL_RESET, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS0_DLL_RESET, addr);
}
set_jump_as_return();
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_ZQCL, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_ZQCL, addr);
/* tZQinit = tDLLK = 512 ck cycles */
delay_for_n_mem_clocks(512);
@@ -1121,7 +1121,7 @@ static void rw_mgr_mem_handoff(void)
/* precharge all banks ... */
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_PRECHARGE_ALL, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_PRECHARGE_ALL, addr);
/* load up MR settings specified by user */
@@ -1132,28 +1132,28 @@ static void rw_mgr_mem_handoff(void)
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
set_jump_as_return();
- writel(RW_MGR_MRS2_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS2_MIRR, addr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS3_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS3_MIRR, addr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS1_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS1_MIRR, addr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS0_USER_MIRR, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS0_USER_MIRR, addr);
} else {
set_jump_as_return();
- writel(RW_MGR_MRS2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS2, addr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS3, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS3, addr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS1, addr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS0_USER, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MRS0_USER, addr);
}
/*
* USER need to wait tMOD (12CK or 15ns) time before issuing
@@ -1192,34 +1192,34 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
/* Load up a constant bursts of read commands */
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
- writel(0x20, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x20, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_GUARANTEED_READ, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_GUARANTEED_READ, addr);
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(0x20, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x20, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_GUARANTEED_READ_CONT, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_GUARANTEED_READ_CONT, addr);
tmp_bit_chk = 0;
for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
/* reset the fifos to get pointers to known state */
addr = (u32)&phy_mgr_cmd->fifo_reset;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RESET_READ_DATAPATH_OFFSET;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
/ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_GUARANTEED_READ, SOCFPGA_SDR_ADDRESS + addr +
+ writel(RW_MGR_GUARANTEED_READ, addr +
((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
vg) << 2));
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
- base_rw_mgr = readl(SOCFPGA_SDR_ADDRESS + addr);
+ base_rw_mgr = readl(addr);
tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
if (vg == 0)
@@ -1229,7 +1229,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
}
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_CLEAR_DQS_ENABLE, SOCFPGA_SDR_ADDRESS + addr + (group << 2));
+ writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
debug_cond(DLEVEL == 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) =>\
@@ -1265,31 +1265,31 @@ static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,
/* Load up a constant bursts */
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
- writel(0x20, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x20, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_GUARANTEED_WRITE_WAIT0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT0, addr);
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(0x20, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x20, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_GUARANTEED_WRITE_WAIT1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT1, addr);
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(0x04, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x04, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_GUARANTEED_WRITE_WAIT2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT2, addr);
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3;
- writel(0x04, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x04, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
- writel(RW_MGR_GUARANTEED_WRITE_WAIT3, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT3, addr);
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_GUARANTEED_WRITE, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_GUARANTEED_WRITE, addr);
}
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
@@ -1327,45 +1327,45 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(0x10, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x10, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_READ_B2B_WAIT1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_READ_B2B_WAIT1, addr);
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(0x10, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x10, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_READ_B2B_WAIT2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_READ_B2B_WAIT2, addr);
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
if (quick_read_mode)
- writel(0x1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x1, addr);
/* need at least two (1+1) reads to capture failures */
else if (all_groups)
- writel(0x06, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x06, addr);
else
- writel(0x32, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x32, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_READ_B2B, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_READ_B2B, addr);
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3;
if (all_groups)
writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
- SOCFPGA_SDR_ADDRESS + addr);
+ addr);
else
- writel(0x0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x0, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
- writel(RW_MGR_READ_B2B, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_READ_B2B, addr);
tmp_bit_chk = 0;
for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
/* reset the fifos to get pointers to known state */
addr = (u32)&phy_mgr_cmd->fifo_reset;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RESET_READ_DATAPATH_OFFSET;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
/ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
@@ -1375,12 +1375,12 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group
else
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_READ_B2B, SOCFPGA_SDR_ADDRESS + addr +
+ writel(RW_MGR_READ_B2B, addr +
((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
vg) << 2));
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
- base_rw_mgr = readl(SOCFPGA_SDR_ADDRESS + addr);
+ base_rw_mgr = readl(addr);
tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
if (vg == 0)
@@ -1390,7 +1390,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group
}
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_CLEAR_DQS_ENABLE, SOCFPGA_SDR_ADDRESS + addr + (group << 2));
+ writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
if (all_correct) {
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
@@ -1422,7 +1422,7 @@ static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
{
uint32_t addr = (u32)&phy_mgr_cmd->inc_vfifo_hard_phy;
- writel(grp, SOCFPGA_SDR_ADDRESS + addr);
+ writel(grp, addr);
(*v)++;
}
@@ -1885,7 +1885,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
dtaps_per_ptap = d - initial_failing_dtap;
addr = (u32)&sdr_reg_file->dtaps_per_ptap;
- writel(dtaps_per_ptap, SOCFPGA_SDR_ADDRESS + addr);
+ writel(dtaps_per_ptap, addr);
debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
- %u = %u", __func__, __LINE__, d,
initial_failing_dtap, dtaps_per_ptap);
@@ -1939,7 +1939,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
scc_mgr_load_dq(p);
}
addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
}
found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
@@ -1957,7 +1957,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
scc_mgr_load_dq(p);
}
addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
}
return found;
@@ -1990,9 +1990,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
- start_dqs = readl(SOCFPGA_SDR_ADDRESS + addr + (read_group << 2));
+ start_dqs = readl(addr + (read_group << 2));
if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
- start_dqs_en = readl(SOCFPGA_SDR_ADDRESS + addr + ((read_group << 2)
+ start_dqs_en = readl(addr + ((read_group << 2)
- IO_DQS_EN_DELAY_OFFSET));
/* set the left and right edge of each bit to an illegal value */
@@ -2008,7 +2008,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
/*
* Stop searching when the read test doesn't pass AND when
@@ -2104,7 +2104,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
}
scc_mgr_load_dqs(read_group);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
/*
* Stop searching when the read test doesn't pass AND when
@@ -2203,7 +2203,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
start_dqs_en);
}
scc_mgr_load_dqs(read_group);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
find edge [%u]: %d %d", __func__, __LINE__,
@@ -2288,8 +2288,8 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
debug_cond(DLEVEL == 2, "vfifo_center: before: \
shift_dq[%u]=%d\n", i, shift_dq);
- temp_dq_in_delay1 = readl(SOCFPGA_SDR_ADDRESS + addr + (p << 2));
- temp_dq_in_delay2 = readl(SOCFPGA_SDR_ADDRESS + addr + (i << 2));
+ temp_dq_in_delay1 = readl(addr + (p << 2));
+ temp_dq_in_delay2 = readl(addr + (i << 2));
if (shift_dq + (int32_t)temp_dq_in_delay1 >
(int32_t)IO_IO_IN_DELAY_MAX) {
@@ -2336,7 +2336,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
* have been applied. Apply the update bit.
*/
addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
return (dq_margin >= 0) && (dqs_margin >= 0);
}
@@ -2545,7 +2545,7 @@ static uint32_t rw_mgr_mem_calibrate_lfifo(void)
addr = (u32)&phy_mgr_cfg->phy_rlat;
do {
- writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr);
+ writel(gbl->curr_read_lat, addr);
debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
__func__, __LINE__, gbl->curr_read_lat);
@@ -2565,13 +2565,13 @@ static uint32_t rw_mgr_mem_calibrate_lfifo(void)
/* reset the fifos to get pointers to known state */
addr = (u32)&phy_mgr_cmd->fifo_reset;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
if (found_one) {
/* add a fudge factor to the read latency that was determined */
gbl->curr_read_lat += 2;
addr = (u32)&phy_mgr_cfg->phy_rlat;
- writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr);
+ writel(gbl->curr_read_lat, addr);
debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
read_lat=%u\n", __func__, __LINE__,
gbl->curr_read_lat);
@@ -2637,23 +2637,23 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
* large number so that the jump is always taken.
*/
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(0xFF, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xFF, addr);
/* CNTR 3 - Not used */
if (test_dm) {
mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
- SOCFPGA_SDR_ADDRESS + addr);
+ addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
- SOCFPGA_SDR_ADDRESS + addr);
+ addr);
} else {
mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP, addr);
}
} else if (rw_wl_nop_cycles == 0) {
/*
@@ -2662,18 +2662,18 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
* number so that the jump is always taken.
*/
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(0xFF, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xFF, addr);
/* CNTR 3 - Not used */
if (test_dm) {
mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
- SOCFPGA_SDR_ADDRESS + addr);
+ addr);
} else {
mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS, addr);
}
} else {
/*
@@ -2682,55 +2682,55 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
* address doesn't count.
*/
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(0x0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x0, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(0x0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x0, addr);
/*
* CNTR 3 - Set the nop counter to the number of cycles we
* need to loop for, minus 1.
*/
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3;
- writel(rw_wl_nop_cycles - 1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(rw_wl_nop_cycles - 1, addr);
if (test_dm) {
mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP, addr);
} else {
mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP, addr);
}
}
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RESET_READ_DATAPATH_OFFSET;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
if (quick_write_mode)
- writel(0x08, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x08, addr);
else
- writel(0x40, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x40, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(mcc_instruction, SOCFPGA_SDR_ADDRESS + addr);
+ writel(mcc_instruction, addr);
/*
* CNTR 1 - This is used to ensure enough time elapses
* for read data to come back.
*/
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(0x30, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x30, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
if (test_dm) {
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT, addr);
} else {
- writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT, addr);
}
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(mcc_instruction, SOCFPGA_SDR_ADDRESS + addr + (group << 2));
+ writel(mcc_instruction, addr + (group << 2));
}
/* Test writes, can check for a single bit pass or multiple bit pass */
@@ -2765,7 +2765,7 @@ static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
/* reset the fifos to get pointers to known state */
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
tmp_bit_chk = tmp_bit_chk <<
(RW_MGR_MEM_DQ_PER_WRITE_DQS /
@@ -2774,7 +2774,7 @@ static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
use_dm);
- base_rw_mgr = readl(SOCFPGA_SDR_ADDRESS + addr_rw_mgr);
+ base_rw_mgr = readl(addr_rw_mgr);
tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
if (vg == 0)
break;
@@ -2830,7 +2830,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
dm_margin = 0;
addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
- start_dqs = readl(SOCFPGA_SDR_ADDRESS + addr +
+ start_dqs = readl(addr +
(RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
/* per-bit deskew */
@@ -2850,7 +2850,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, d);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
/*
* Stop searching when the read test doesn't pass AND when
@@ -2935,7 +2935,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
d + start_dqs);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
/*
* Stop searching when the read test doesn't pass AND when
@@ -3078,7 +3078,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
[%u]=%d\n", __func__, __LINE__, i, shift_dq);
- temp_dq_out1_delay = readl(SOCFPGA_SDR_ADDRESS + addr + (i << 2));
+ temp_dq_out1_delay = readl(addr + (i << 2));
if (shift_dq + (int32_t)temp_dq_out1_delay >
(int32_t)IO_IO_OUT1_DELAY_MAX) {
shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
@@ -3105,7 +3105,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
/* Move DQS */
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
/* Centre DM */
debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
@@ -3126,7 +3126,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
addr = (u32)&sdr_scc_mgr->update;
for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
scc_mgr_apply_group_dm_out1_delay(write_group, d);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
PASS_ALL_BITS, &bit_chk,
@@ -3179,7 +3179,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
d + new_dqs);
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
PASS_ALL_BITS, &bit_chk,
0)) {
@@ -3243,7 +3243,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
scc_mgr_apply_group_dm_out1_delay(write_group, mid);
addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
dm_margin=%d\n", __func__, __LINE__, left_edge[0],
@@ -3260,7 +3260,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
* decisions have been applied.
*/
addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
}
@@ -3302,21 +3302,21 @@ static void mem_precharge_and_activate(void)
/* precharge all banks ... */
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_PRECHARGE_ALL, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_PRECHARGE_ALL, addr);
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
- writel(0x0F, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x0F, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1, addr);
addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(0x0F, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x0F, addr);
addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2, addr);
/* activate rows */
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_ACTIVATE_0_AND_1, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_ACTIVATE_0_AND_1, addr);
}
}
@@ -3331,10 +3331,10 @@ static void mem_config(void)
debug("%s:%d\n", __func__, __LINE__);
/* read in write and read latency */
addr = (u32)&data_mgr->t_wl_add;
- wlat = readl(SOCFPGA_SDR_ADDRESS + addr);
+ wlat = readl(addr);
addr = (u32)&data_mgr->mem_t_add;
- wlat += readl(SOCFPGA_SDR_ADDRESS + addr);
+ wlat += readl(addr);
/* WL for hard phy does not include additive latency */
/*
@@ -3345,7 +3345,7 @@ static void mem_config(void)
wlat = wlat + 1;
addr = (u32)&data_mgr->t_rl_add;
- rlat = readl(SOCFPGA_SDR_ADDRESS + addr);
+ rlat = readl(addr);
rw_wl_nop_cycles = wlat - 2;
gbl->rw_wl_nop_cycles = rw_wl_nop_cycles;
@@ -3368,12 +3368,12 @@ static void mem_config(void)
gbl->curr_read_lat = max_latency;
addr = (u32)&phy_mgr_cfg->phy_rlat;
- writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr);
+ writel(gbl->curr_read_lat, addr);
/* advertise write latency */
gbl->curr_write_lat = wlat;
addr = (u32)&phy_mgr_cfg->afi_wlat;
- writel(wlat - 2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(wlat - 2, addr);
/* initialize bit slips */
mem_precharge_and_activate();
@@ -3430,20 +3430,20 @@ static void mem_skip_calibrate(void)
IO_DLL_CHAIN_LENGTH - 2));
}
addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, addr);
addr = (u32)&sdr_scc_mgr->dqs_io_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, addr);
addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_GROUP_COUNTER_OFFSET;
for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
- writel(i, SOCFPGA_SDR_ADDRESS + addr);
+ writel(i, addr);
}
addr = (u32)&sdr_scc_mgr->dq_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, addr);
addr = (u32)&sdr_scc_mgr->dm_ena;
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, addr);
addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
}
/* Compensate for simulation model behaviour */
@@ -3452,7 +3452,7 @@ static void mem_skip_calibrate(void)
scc_mgr_load_dqs(i);
}
addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
/*
* ArriaV has hard FIFOs that can only be initialized by incrementing
@@ -3461,10 +3461,10 @@ static void mem_skip_calibrate(void)
vfifo_offset = CALIB_VFIFO_OFFSET;
addr = (u32)&phy_mgr_cmd->inc_vfifo_hard_phy;
for (j = 0; j < vfifo_offset; j++) {
- writel(0xff, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0xff, addr);
}
addr = (u32)&phy_mgr_cmd->fifo_reset;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
/*
* For ACV with hard lfifo, we get the skip-cal setting from
@@ -3472,7 +3472,7 @@ static void mem_skip_calibrate(void)
*/
gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
addr = (u32)&phy_mgr_cfg->phy_rlat;
- writel(gbl->curr_read_lat, SOCFPGA_SDR_ADDRESS + addr);
+ writel(gbl->curr_read_lat, addr);
}
/* Memory calibration entry point */
@@ -3502,7 +3502,7 @@ static uint32_t mem_calibrate(void)
uint32_t bypass_mode = 0x1;
addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_GROUP_COUNTER_OFFSET;
for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
- writel(i, SOCFPGA_SDR_ADDRESS + addr);
+ writel(i, addr);
scc_set_bypass_mode(i, bypass_mode);
}
@@ -3537,7 +3537,7 @@ static uint32_t mem_calibrate(void)
continue;
addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_GROUP_COUNTER_OFFSET;
- writel(write_group, SOCFPGA_SDR_ADDRESS + addr);
+ writel(write_group, addr);
scc_mgr_zero_group(write_group, write_test_bgn,
0);
@@ -3662,7 +3662,7 @@ static uint32_t mem_calibrate(void)
* have been applied.
*/
addr = (u32)&sdr_scc_mgr->update;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
return 1;
}
@@ -3676,14 +3676,14 @@ static uint32_t run_mem_calibrate(void)
/* Reset pass/fail status shown on afi_cal_success/fail */
addr = (u32)&phy_mgr_cfg->cal_status;
- writel(PHY_MGR_CAL_RESET, SOCFPGA_SDR_ADDRESS + addr);
+ writel(PHY_MGR_CAL_RESET, addr);
addr = SDR_CTRLGRP_ADDRESS;
/* stop tracking manger */
- uint32_t ctrlcfg = readl(SOCFPGA_SDR_ADDRESS + addr);
+ uint32_t ctrlcfg = readl(addr);
addr = SDR_CTRLGRP_ADDRESS;
- writel(ctrlcfg & 0xFFBFFFFF, SOCFPGA_SDR_ADDRESS + addr);
+ writel(ctrlcfg & 0xFFBFFFFF, addr);
initialize();
rw_mgr_mem_initialize();
@@ -3692,7 +3692,7 @@ static uint32_t run_mem_calibrate(void)
mem_precharge_and_activate();
addr = (u32)&phy_mgr_cmd->fifo_reset;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
/*
* Handoff:
@@ -3706,11 +3706,11 @@ static uint32_t run_mem_calibrate(void)
* 1: DDIO Mux Select
*/
addr = (u32)&phy_mgr_cfg->mux_sel;
- writel(0x2, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0x2, addr);
}
addr = SDR_CTRLGRP_ADDRESS;
- writel(ctrlcfg, SOCFPGA_SDR_ADDRESS + addr);
+ writel(ctrlcfg, addr);
if (pass) {
printf("%s: CALIBRATION PASSED\n", __FILE__);
@@ -3728,12 +3728,12 @@ static uint32_t run_mem_calibrate(void)
debug_info = gbl->fom_in;
debug_info |= gbl->fom_out << 8;
addr = (u32)&sdr_reg_file->fom;
- writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
+ writel(debug_info, addr);
addr = (u32)&phy_mgr_cfg->cal_debug_info;
- writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
+ writel(debug_info, addr);
addr = (u32)&phy_mgr_cfg->cal_status;
- writel(PHY_MGR_CAL_SUCCESS, SOCFPGA_SDR_ADDRESS + addr);
+ writel(PHY_MGR_CAL_SUCCESS, addr);
} else {
printf("%s: CALIBRATION FAILED\n", __FILE__);
@@ -3742,18 +3742,18 @@ static uint32_t run_mem_calibrate(void)
debug_info |= gbl->error_group << 16;
addr = (u32)&sdr_reg_file->failing_stage;
- writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
+ writel(debug_info, addr);
addr = (u32)&phy_mgr_cfg->cal_debug_info;
- writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
+ writel(debug_info, addr);
addr = (u32)&phy_mgr_cfg->cal_status;
- writel(PHY_MGR_CAL_FAIL, SOCFPGA_SDR_ADDRESS + addr);
+ writel(PHY_MGR_CAL_FAIL, addr);
/* Update the failing group/stage in the register file */
debug_info = gbl->error_stage;
debug_info |= gbl->error_substage << 8;
debug_info |= gbl->error_group << 16;
addr = (u32)&sdr_reg_file->failing_stage;
- writel(debug_info, SOCFPGA_SDR_ADDRESS + addr);
+ writel(debug_info, addr);
}
return pass;
@@ -3767,13 +3767,13 @@ static void hc_initialize_rom_data(void)
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++) {
uint32_t data = inst_rom_init[i];
- writel(data, SOCFPGA_SDR_ADDRESS + addr + (i << 2));
+ writel(data, addr + (i << 2));
}
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++) {
uint32_t data = ac_rom_init[i];
- writel(data, SOCFPGA_SDR_ADDRESS + addr + (i << 2));
+ writel(data, addr + (i << 2));
}
}
@@ -3783,25 +3783,25 @@ static void initialize_reg_file(void)
/* Initialize the register file with the correct data */
addr = (u32)&sdr_reg_file->signature;
- writel(REG_FILE_INIT_SEQ_SIGNATURE, SOCFPGA_SDR_ADDRESS + addr);
+ writel(REG_FILE_INIT_SEQ_SIGNATURE, addr);
addr = (u32)&sdr_reg_file->debug_data_addr;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
addr = (u32)&sdr_reg_file->cur_stage;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
addr = (u32)&sdr_reg_file->fom;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
addr = (u32)&sdr_reg_file->failing_stage;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
addr = (u32)&sdr_reg_file->debug1;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
addr = (u32)&sdr_reg_file->debug2;
- writel(0, SOCFPGA_SDR_ADDRESS + addr);
+ writel(0, addr);
}
static void initialize_hps_phy(void)
@@ -3834,7 +3834,7 @@ static void initialize_hps_phy(void)
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
trk_sample_count);
addr = SDR_CTRLGRP_ADDRESS;
- writel(reg, SOCFPGA_SDR_ADDRESS + addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET);
+ writel(reg, addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET);
reg = 0;
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
@@ -3842,13 +3842,13 @@ static void initialize_hps_phy(void)
SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
trk_long_idle_sample_count);
- writel(reg, SOCFPGA_SDR_ADDRESS + addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET);
+ writel(reg, addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET);
reg = 0;
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
trk_long_idle_sample_count >>
SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
- writel(reg, SOCFPGA_SDR_ADDRESS + addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET);
+ writel(reg, addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET);
}
static void initialize_tracking(void)
@@ -3905,25 +3905,25 @@ static void initialize_tracking(void)
/* Initialize the register file with the correct data */
addr = (u32)&sdr_reg_file->dtaps_per_ptap;
- writel(dtaps_per_ptap, SOCFPGA_SDR_ADDRESS + addr);
+ writel(dtaps_per_ptap, addr);
addr = (u32)&sdr_reg_file->trk_sample_count;
- writel(trk_sample_count, SOCFPGA_SDR_ADDRESS + addr);
+ writel(trk_sample_count, addr);
addr = (u32)&sdr_reg_file->trk_longidle;
- writel(concatenated_longidle, SOCFPGA_SDR_ADDRESS + addr);
+ writel(concatenated_longidle, addr);
addr = (u32)&sdr_reg_file->delays;
- writel(concatenated_delays, SOCFPGA_SDR_ADDRESS + addr);
+ writel(concatenated_delays, addr);
addr = (u32)&sdr_reg_file->trk_rw_mgr_addr;
- writel(concatenated_rw_addr, SOCFPGA_SDR_ADDRESS + addr);
+ writel(concatenated_rw_addr, addr);
addr = (u32)&sdr_reg_file->trk_read_dqs_width;
- writel(RW_MGR_MEM_IF_READ_DQS_WIDTH, SOCFPGA_SDR_ADDRESS + addr);
+ writel(RW_MGR_MEM_IF_READ_DQS_WIDTH, addr);
addr = (u32)&sdr_reg_file->trk_rfsh;
- writel(concatenated_refresh, SOCFPGA_SDR_ADDRESS + addr);
+ writel(concatenated_refresh, addr);
}
int sdram_calibration_full(void)
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
index 0aa9579..7591d40 100644
--- a/drivers/ddr/altera/sequencer.h
+++ b/drivers/ddr/altera/sequencer.h
@@ -93,11 +93,11 @@
#define SCC_MGR_HHP_RFILE_OFFSET 0x0B00
#define SCC_MGR_AFI_CAL_INIT_OFFSET 0x0D00
-#define SDR_PHYGRP_SCCGRP_ADDRESS 0x0
-#define SDR_PHYGRP_PHYMGRGRP_ADDRESS 0x1000
-#define SDR_PHYGRP_RWMGRGRP_ADDRESS 0x2000
-#define SDR_PHYGRP_DATAMGRGRP_ADDRESS 0x4000
-#define SDR_PHYGRP_REGFILEGRP_ADDRESS 0x4800
+#define SDR_PHYGRP_SCCGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x0)
+#define SDR_PHYGRP_PHYMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x1000)
+#define SDR_PHYGRP_RWMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x2000)
+#define SDR_PHYGRP_DATAMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4000)
+#define SDR_PHYGRP_REGFILEGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4800)
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET 0x150
#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET 0x154
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 051/172] ddr: altera: Stop using SDR_CTRLGRP_ADDRESS directly
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (49 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 050/172] ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESS Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 052/172] ddr: altera: Massage addr into I/O accessors Marek Vasut
` (122 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Use the proper structure which describes these registers,
especially since this is already in place.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 20 +++++++++-----------
drivers/ddr/altera/sequencer.h | 4 ----
2 files changed, 9 insertions(+), 15 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 591e8f6..9b9b65e 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -36,6 +36,9 @@ static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
static struct socfpga_data_mgr *data_mgr =
(struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
+static struct socfpga_sdr_ctrl *sdr_ctrl =
+ (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
+
#define DELTA_D 1
/*
@@ -3678,12 +3681,10 @@ static uint32_t run_mem_calibrate(void)
addr = (u32)&phy_mgr_cfg->cal_status;
writel(PHY_MGR_CAL_RESET, addr);
- addr = SDR_CTRLGRP_ADDRESS;
/* stop tracking manger */
- uint32_t ctrlcfg = readl(addr);
+ uint32_t ctrlcfg = readl(&sdr_ctrl->ctrl_cfg);
- addr = SDR_CTRLGRP_ADDRESS;
- writel(ctrlcfg & 0xFFBFFFFF, addr);
+ writel(ctrlcfg & 0xFFBFFFFF, &sdr_ctrl->ctrl_cfg);
initialize();
rw_mgr_mem_initialize();
@@ -3709,8 +3710,7 @@ static uint32_t run_mem_calibrate(void)
writel(0x2, addr);
}
- addr = SDR_CTRLGRP_ADDRESS;
- writel(ctrlcfg, addr);
+ writel(ctrlcfg, &sdr_ctrl->ctrl_cfg);
if (pass) {
printf("%s: CALIBRATION PASSED\n", __FILE__);
@@ -3807,7 +3807,6 @@ static void initialize_reg_file(void)
static void initialize_hps_phy(void)
{
uint32_t reg;
- uint32_t addr;
/*
* Tracking also gets configured here because it's in the
* same register.
@@ -3833,8 +3832,7 @@ static void initialize_hps_phy(void)
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
trk_sample_count);
- addr = SDR_CTRLGRP_ADDRESS;
- writel(reg, addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET);
+ writel(reg, &sdr_ctrl->phy_ctrl0);
reg = 0;
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
@@ -3842,13 +3840,13 @@ static void initialize_hps_phy(void)
SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
trk_long_idle_sample_count);
- writel(reg, addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET);
+ writel(reg, &sdr_ctrl->phy_ctrl1);
reg = 0;
reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
trk_long_idle_sample_count >>
SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
- writel(reg, addr + SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET);
+ writel(reg, &sdr_ctrl->phy_ctrl2);
}
static void initialize_tracking(void)
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
index 7591d40..5d4d800 100644
--- a/drivers/ddr/altera/sequencer.h
+++ b/drivers/ddr/altera/sequencer.h
@@ -99,10 +99,6 @@
#define SDR_PHYGRP_DATAMGRGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4000)
#define SDR_PHYGRP_REGFILEGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x4800)
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_OFFSET 0x150
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_OFFSET 0x154
-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_OFFSET 0x158
-
#define PHY_MGR_CAL_RESET (0)
#define PHY_MGR_CAL_SUCCESS (1)
#define PHY_MGR_CAL_FAIL (2)
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 052/172] ddr: altera: Massage addr into I/O accessors
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (50 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 051/172] ddr: altera: Stop using SDR_CTRLGRP_ADDRESS directly Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 053/172] ddr: altera: Clean up hc_initialize_rom_data() Marek Vasut
` (121 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Get rid of invocations of this sort:
addr = (u32)&base->reg;
writel(val, addr);
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 672 +++++++++++++++--------------------------
1 file changed, 248 insertions(+), 424 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 9b9b65e..23fc459 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -101,10 +101,8 @@ static void set_failing_group_stage(uint32_t group, uint32_t stage,
static void reg_file_set_group(uint32_t set_group)
{
- u32 addr = (u32)&sdr_reg_file->cur_stage;
-
/* Read the current group and stage */
- uint32_t cur_stage_group = readl(addr);
+ uint32_t cur_stage_group = readl(&sdr_reg_file->cur_stage);
/* Clear the group */
cur_stage_group &= 0x0000FFFF;
@@ -113,15 +111,13 @@ static void reg_file_set_group(uint32_t set_group)
cur_stage_group |= (set_group << 16);
/* Write the data back */
- writel(cur_stage_group, addr);
+ writel(cur_stage_group, &sdr_reg_file->cur_stage);
}
static void reg_file_set_stage(uint32_t set_stage)
{
- u32 addr = (u32)&sdr_reg_file->cur_stage;
-
/* Read the current group and stage */
- uint32_t cur_stage_group = readl(addr);
+ uint32_t cur_stage_group = readl(&sdr_reg_file->cur_stage);
/* Clear the stage and substage */
cur_stage_group &= 0xFFFF0000;
@@ -130,15 +126,13 @@ static void reg_file_set_stage(uint32_t set_stage)
cur_stage_group |= (set_stage & 0x000000FF);
/* Write the data back */
- writel(cur_stage_group, addr);
+ writel(cur_stage_group, &sdr_reg_file->cur_stage);
}
static void reg_file_set_sub_stage(uint32_t set_sub_stage)
{
- u32 addr = (u32)&sdr_reg_file->cur_stage;
-
/* Read the current group and stage */
- uint32_t cur_stage_group = readl(addr);
+ uint32_t cur_stage_group = readl(&sdr_reg_file->cur_stage);
/* Clear the substage */
cur_stage_group &= 0xFFFF00FF;
@@ -147,13 +141,11 @@ static void reg_file_set_sub_stage(uint32_t set_sub_stage)
cur_stage_group |= ((set_sub_stage << 8) & 0x0000FF00);
/* Write the data back */
- writel(cur_stage_group, addr);
+ writel(cur_stage_group, &sdr_reg_file->cur_stage);
}
static void initialize(void)
{
- u32 addr = (u32)&phy_mgr_cfg->mux_sel;
-
debug("%s:%d\n", __func__, __LINE__);
/* USER calibration has control over path to memory */
/*
@@ -161,18 +153,15 @@ static void initialize(void)
* 0: AFI Mux Select
* 1: DDIO Mux Select
*/
- writel(0x3, addr);
+ writel(0x3, &phy_mgr_cfg->mux_sel);
/* USER memory clock is not stable we begin initialization */
- addr = (u32)&phy_mgr_cfg->reset_mem_stbl;
- writel(0, addr);
+ writel(0, &phy_mgr_cfg->reset_mem_stbl);
/* USER calibration status all set to zero */
- addr = (u32)&phy_mgr_cfg->cal_status;
- writel(0, addr);
+ writel(0, &phy_mgr_cfg->cal_status);
- addr = (u32)&phy_mgr_cfg->cal_debug_info;
- writel(0, addr);
+ writel(0, &phy_mgr_cfg->cal_debug_info);
if ((dyn_calib_steps & CALIB_SKIP_ALL) != CALIB_SKIP_ALL) {
param->read_correct_mask_vg = ((uint32_t)1 <<
@@ -196,7 +185,6 @@ static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
uint32_t odt_mask_0 = 0;
uint32_t odt_mask_1 = 0;
uint32_t cs_and_odt_mask;
- uint32_t addr;
if (odt_mode == RW_MGR_ODT_MODE_READ_WRITE) {
if (RW_MGR_MEM_NUMBER_OF_RANKS == 1) {
@@ -289,8 +277,8 @@ static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
(0xFF & ~(1 << rank)) |
((0xFF & odt_mask_0) << 8) |
((0xFF & odt_mask_1) << 16);
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_SET_CS_AND_ODT_MASK_OFFSET;
- writel(cs_and_odt_mask, addr);
+ writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
}
static void scc_mgr_initialize(void)
@@ -341,7 +329,6 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,
{
uint32_t r;
uint32_t update_scan_chains;
- uint32_t addr;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
@@ -358,11 +345,8 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,
scc_mgr_set_dqs_en_phase(read_group, phase);
if (update_scan_chains) {
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(read_group, addr);
-
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(read_group, &sdr_scc_mgr->dqs_ena);
+ writel(0, &sdr_scc_mgr->update);
}
}
}
@@ -381,7 +365,6 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
{
uint32_t r;
uint32_t update_scan_chains;
- uint32_t addr;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
@@ -398,11 +381,8 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
scc_mgr_set_dqdqs_output_phase(write_group, phase);
if (update_scan_chains) {
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(write_group, addr);
-
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(write_group, &sdr_scc_mgr->dqs_ena);
+ writel(0, &sdr_scc_mgr->update);
}
}
}
@@ -420,14 +400,12 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
uint32_t delay)
{
uint32_t r;
- uint32_t addr;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
scc_mgr_set_dqs_en_delay(read_group, delay);
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(read_group, addr);
+ writel(read_group, &sdr_scc_mgr->dqs_ena);
/*
* In shadow register mode, the T11 settings are stored in
* registers in the core, which are updated by the DQS_ENA
@@ -436,8 +414,7 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
* select_shadow_regs_for_update with update_scan_chains
* set to 0.
*/
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
}
/*
* In shadow register mode, the T11 settings are stored in
@@ -447,8 +424,7 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
* select_shadow_regs_for_update with update_scan_chains
* set to 0.
*/
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
}
static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)
@@ -531,7 +507,6 @@ static void scc_mgr_set_dm_out1_delay(uint32_t write_group,
static void scc_mgr_zero_all(void)
{
uint32_t i, r;
- uint32_t addr;
/*
* USER Zero all DQS config settings, across all groups and all
@@ -558,16 +533,12 @@ static void scc_mgr_zero_all(void)
}
/* multicast to all DQS group enables */
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(0xff, addr);
-
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0xff, &sdr_scc_mgr->dqs_ena);
+ writel(0, &sdr_scc_mgr->update);
}
static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)
{
- uint32_t addr;
/* mode = 0 : Do NOT bypass - Half Rate Mode */
/* mode = 1 : Bypass - Full Rate Mode */
@@ -580,30 +551,23 @@ static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)
__func__, __LINE__);
}
/* multicast to all DQ enables */
- addr = (u32)&sdr_scc_mgr->dq_ena;
- writel(0xff, addr);
-
- addr = (u32)&sdr_scc_mgr->dm_ena;
- writel(0xff, addr);
+ writel(0xff, &sdr_scc_mgr->dq_ena);
+ writel(0xff, &sdr_scc_mgr->dm_ena);
/* update current DQS IO enable */
- addr = (u32)&sdr_scc_mgr->dqs_io_ena;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->dqs_io_ena);
/* update the DQS logic */
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(write_group, addr);
+ writel(write_group, &sdr_scc_mgr->dqs_ena);
/* hit update */
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
}
static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
int32_t out_only)
{
uint32_t i, r;
- uint32_t addr;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
NUM_RANKS_PER_SHADOW_REG) {
@@ -615,8 +579,7 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
}
/* multicast to all DQ enables */
- addr = (u32)&sdr_scc_mgr->dq_ena;
- writel(0xff, addr);
+ writel(0xff, &sdr_scc_mgr->dq_ena);
/* Zero all DM config settings */
for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
@@ -624,8 +587,7 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
}
/* multicast to all DM enables */
- addr = (u32)&sdr_scc_mgr->dm_ena;
- writel(0xff, addr);
+ writel(0xff, &sdr_scc_mgr->dm_ena);
/* zero all DQS io settings */
if (!out_only)
@@ -636,21 +598,17 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
scc_mgr_load_dqs_for_write_group(write_group);
/* multicast to all DQS IO enables (only 1) */
- addr = (u32)&sdr_scc_mgr->dqs_io_ena;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->dqs_io_ena);
/* hit update to zero everything */
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
}
}
/* load up dqs config settings */
static void scc_mgr_load_dqs(uint32_t dqs)
{
- uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena;
-
- writel(dqs, addr);
+ writel(dqs, &sdr_scc_mgr->dqs_ena);
}
static void scc_mgr_load_dqs_for_write_group(uint32_t write_group)
@@ -673,25 +631,19 @@ static void scc_mgr_load_dqs_for_write_group(uint32_t write_group)
/* load up dqs io config settings */
static void scc_mgr_load_dqs_io(void)
{
- uint32_t addr = (u32)&sdr_scc_mgr->dqs_io_ena;
-
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->dqs_io_ena);
}
/* load up dq config settings */
static void scc_mgr_load_dq(uint32_t dq_in_group)
{
- uint32_t addr = (u32)&sdr_scc_mgr->dq_ena;
-
- writel(dq_in_group, addr);
+ writel(dq_in_group, &sdr_scc_mgr->dq_ena);
}
/* load up dm config settings */
static void scc_mgr_load_dm(uint32_t dm)
{
- uint32_t addr = (u32)&sdr_scc_mgr->dm_ena;
-
- writel(dm, addr);
+ writel(dm, &sdr_scc_mgr->dm_ena);
}
/*
@@ -830,13 +782,12 @@ static void scc_mgr_apply_group_all_out_delay_add_all_ranks(
uint32_t write_group, uint32_t group_bgn, uint32_t delay)
{
uint32_t r;
- uint32_t addr = (u32)&sdr_scc_mgr->update;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
scc_mgr_apply_group_all_out_delay_add(write_group,
group_bgn, delay);
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
}
}
@@ -844,16 +795,13 @@ static void scc_mgr_apply_group_all_out_delay_add_all_ranks(
/* could be applied to other protocols if we wanted to */
static void set_jump_as_return(void)
{
- uint32_t addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
-
/*
* to save space, we replace return with jump to special shared
* RETURN instruction so we set the counter to large value so that
* we always jump
*/
- writel(0xff, addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_RETURN, addr);
+ writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
+ writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
}
/*
@@ -866,7 +814,6 @@ static void delay_for_n_mem_clocks(const uint32_t clocks)
uint8_t inner = 0;
uint8_t outer = 0;
uint16_t c_loop = 0;
- uint32_t addr;
debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
@@ -915,36 +862,37 @@ static void delay_for_n_mem_clocks(const uint32_t clocks)
* overhead
*/
if (afi_clocks <= 0x100) {
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), addr);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
+ &sdr_rw_load_mgr_regs->load_cntr1);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_IDLE_LOOP1, addr);
+ writel(RW_MGR_IDLE_LOOP1,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_IDLE_LOOP1, addr);
+ writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} else {
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner), addr);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
+ &sdr_rw_load_mgr_regs->load_cntr0);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer), addr);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
+ &sdr_rw_load_mgr_regs->load_cntr1);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_IDLE_LOOP2, addr);
+ writel(RW_MGR_IDLE_LOOP2,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_IDLE_LOOP2, addr);
+ writel(RW_MGR_IDLE_LOOP2,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
/* hack to get around compiler not being smart enough */
if (afi_clocks <= 0x10000) {
/* only need to run once */
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_IDLE_LOOP2, addr);
+ writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} else {
do {
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_IDLE_LOOP2, addr);
+ writel(RW_MGR_IDLE_LOOP2,
+ SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
} while (c_loop-- != 0);
}
}
@@ -954,13 +902,14 @@ static void delay_for_n_mem_clocks(const uint32_t clocks)
static void rw_mgr_mem_initialize(void)
{
uint32_t r;
- uint32_t addr;
+ uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET;
debug("%s:%d\n", __func__, __LINE__);
/* The reset / cke part of initialization is broadcasted to all ranks */
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_SET_CS_AND_ODT_MASK_OFFSET;
- writel(RW_MGR_RANK_ALL, addr);
+ writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
/*
* Here's how you load register for a loop
@@ -987,33 +936,26 @@ static void rw_mgr_mem_initialize(void)
*/
/* Load counters */
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL),
- addr);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
+ &sdr_rw_load_mgr_regs->load_cntr0);
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL),
- addr);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
+ &sdr_rw_load_mgr_regs->load_cntr1);
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL),
- addr);
+ &sdr_rw_load_mgr_regs->load_cntr2);
/* Load jump address */
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_INIT_RESET_0_CKE_0, addr);
-
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_INIT_RESET_0_CKE_0, addr);
-
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_INIT_RESET_0_CKE_0, addr);
+ writel(RW_MGR_INIT_RESET_0_CKE_0,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ writel(RW_MGR_INIT_RESET_0_CKE_0,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ writel(RW_MGR_INIT_RESET_0_CKE_0,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
/* Execute count instruction */
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_INIT_RESET_0_CKE_0, addr);
+ writel(RW_MGR_INIT_RESET_0_CKE_0, grpaddr);
/* indicate that memory is stable */
- addr = (u32)&phy_mgr_cfg->reset_mem_stbl;
- writel(1, addr);
+ writel(1, &phy_mgr_cfg->reset_mem_stbl);
/*
* transition the RESET to high
@@ -1031,26 +973,22 @@ static void rw_mgr_mem_initialize(void)
*/
/* Load counters */
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR0_VAL),
- addr);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
+ &sdr_rw_load_mgr_regs->load_cntr0);
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR1_VAL),
- addr);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
+ &sdr_rw_load_mgr_regs->load_cntr1);
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR2_VAL),
- addr);
+ &sdr_rw_load_mgr_regs->load_cntr2);
/* Load jump address */
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_INIT_RESET_1_CKE_0, addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_INIT_RESET_1_CKE_0, addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_INIT_RESET_1_CKE_0, addr);
+ writel(RW_MGR_INIT_RESET_1_CKE_0,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ writel(RW_MGR_INIT_RESET_1_CKE_0,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ writel(RW_MGR_INIT_RESET_1_CKE_0,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_INIT_RESET_1_CKE_0, addr);
+ writel(RW_MGR_INIT_RESET_1_CKE_0, grpaddr);
/* bring up clock enable */
@@ -1072,33 +1010,30 @@ static void rw_mgr_mem_initialize(void)
*/
if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
set_jump_as_return();
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_MRS2_MIRR, addr);
+ writel(RW_MGR_MRS2_MIRR, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS3_MIRR, addr);
+ writel(RW_MGR_MRS3_MIRR, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS1_MIRR, addr);
+ writel(RW_MGR_MRS1_MIRR, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS0_DLL_RESET_MIRR, addr);
+ writel(RW_MGR_MRS0_DLL_RESET_MIRR, grpaddr);
} else {
set_jump_as_return();
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_MRS2, addr);
+ writel(RW_MGR_MRS2, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS3, addr);
+ writel(RW_MGR_MRS3, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS1, addr);
+ writel(RW_MGR_MRS1, grpaddr);
set_jump_as_return();
- writel(RW_MGR_MRS0_DLL_RESET, addr);
+ writel(RW_MGR_MRS0_DLL_RESET, grpaddr);
}
set_jump_as_return();
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_ZQCL, addr);
+ writel(RW_MGR_ZQCL, grpaddr);
/* tZQinit = tDLLK = 512 ck cycles */
delay_for_n_mem_clocks(512);
@@ -1112,7 +1047,8 @@ static void rw_mgr_mem_initialize(void)
static void rw_mgr_mem_handoff(void)
{
uint32_t r;
- uint32_t addr;
+ uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET;
debug("%s:%d\n", __func__, __LINE__);
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
@@ -1123,8 +1059,7 @@ static void rw_mgr_mem_handoff(void)
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
/* precharge all banks ... */
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_PRECHARGE_ALL, addr);
+ writel(RW_MGR_PRECHARGE_ALL, grpaddr);
/* load up MR settings specified by user */
@@ -1132,31 +1067,30 @@ static void rw_mgr_mem_handoff(void)
* Use Mirror-ed commands for odd ranks if address
* mirrorring is on
*/
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
set_jump_as_return();
- writel(RW_MGR_MRS2_MIRR, addr);
+ writel(RW_MGR_MRS2_MIRR, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS3_MIRR, addr);
+ writel(RW_MGR_MRS3_MIRR, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS1_MIRR, addr);
+ writel(RW_MGR_MRS1_MIRR, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS0_USER_MIRR, addr);
+ writel(RW_MGR_MRS0_USER_MIRR, grpaddr);
} else {
set_jump_as_return();
- writel(RW_MGR_MRS2, addr);
+ writel(RW_MGR_MRS2, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS3, addr);
+ writel(RW_MGR_MRS3, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS1, addr);
+ writel(RW_MGR_MRS1, grpaddr);
delay_for_n_mem_clocks(4);
set_jump_as_return();
- writel(RW_MGR_MRS0_USER, addr);
+ writel(RW_MGR_MRS0_USER, grpaddr);
}
/*
* USER need to wait tMOD (12CK or 15ns) time before issuing
@@ -1194,24 +1128,21 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
/* Load up a constant bursts of read commands */
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
- writel(0x20, addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_GUARANTEED_READ, addr);
+ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
+ writel(RW_MGR_GUARANTEED_READ,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(0x20, addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_GUARANTEED_READ_CONT, addr);
+ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
+ writel(RW_MGR_GUARANTEED_READ_CONT,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
tmp_bit_chk = 0;
for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
/* reset the fifos to get pointers to known state */
- addr = (u32)&phy_mgr_cmd->fifo_reset;
- writel(0, addr);
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RESET_READ_DATAPATH_OFFSET;
- writel(0, addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
+ writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RESET_READ_DATAPATH_OFFSET);
tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
/ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
@@ -1221,8 +1152,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
vg) << 2));
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
- base_rw_mgr = readl(addr);
+ base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
if (vg == 0)
@@ -1253,7 +1183,6 @@ static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,
uint32_t all_ranks)
{
uint32_t r;
- uint32_t addr;
uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
(rank_bgn + NUM_RANKS_PER_SHADOW_REG);
@@ -1267,32 +1196,28 @@ static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
/* Load up a constant bursts */
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
- writel(0x20, addr);
+ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_GUARANTEED_WRITE_WAIT0, addr);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(0x20, addr);
+ writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_GUARANTEED_WRITE_WAIT1, addr);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(0x04, addr);
+ writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_GUARANTEED_WRITE_WAIT2, addr);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3;
- writel(0x04, addr);
+ writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
- writel(RW_MGR_GUARANTEED_WRITE_WAIT3, addr);
+ writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_GUARANTEED_WRITE, addr);
+ writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
}
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
@@ -1329,46 +1254,41 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group
/* set rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(0x10, addr);
+ writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_READ_B2B_WAIT1, addr);
+ writel(RW_MGR_READ_B2B_WAIT1,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(0x10, addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_READ_B2B_WAIT2, addr);
+ writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
+ writel(RW_MGR_READ_B2B_WAIT2,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
if (quick_read_mode)
- writel(0x1, addr);
+ writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
/* need at least two (1+1) reads to capture failures */
else if (all_groups)
- writel(0x06, addr);
+ writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
else
- writel(0x32, addr);
+ writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_READ_B2B, addr);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3;
+ writel(RW_MGR_READ_B2B,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
if (all_groups)
writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
- addr);
+ &sdr_rw_load_mgr_regs->load_cntr3);
else
- writel(0x0, addr);
+ writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
- writel(RW_MGR_READ_B2B, addr);
+ writel(RW_MGR_READ_B2B,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
tmp_bit_chk = 0;
for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
/* reset the fifos to get pointers to known state */
- addr = (u32)&phy_mgr_cmd->fifo_reset;
- writel(0, addr);
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RESET_READ_DATAPATH_OFFSET;
- writel(0, addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
+ writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RESET_READ_DATAPATH_OFFSET);
tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
/ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
@@ -1382,8 +1302,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group
((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
vg) << 2));
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
- base_rw_mgr = readl(addr);
+ base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
if (vg == 0)
@@ -1423,9 +1342,7 @@ static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
{
- uint32_t addr = (u32)&phy_mgr_cmd->inc_vfifo_hard_phy;
-
- writel(grp, addr);
+ writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
(*v)++;
}
@@ -1687,7 +1604,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
uint32_t dtaps_per_ptap;
uint32_t work_bgn, work_mid, work_end;
uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
- uint32_t addr;
debug("%s:%d %u\n", __func__, __LINE__, grp);
@@ -1887,8 +1803,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
if (found_passing_read && found_failing_read)
dtaps_per_ptap = d - initial_failing_dtap;
- addr = (u32)&sdr_reg_file->dtaps_per_ptap;
- writel(dtaps_per_ptap, addr);
+ writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
- %u = %u", __func__, __LINE__, d,
initial_failing_dtap, dtaps_per_ptap);
@@ -1918,7 +1833,6 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
uint32_t p;
uint32_t d;
uint32_t r;
- uint32_t addr;
const uint32_t delay_step = IO_IO_IN_DELAY_MAX /
(RW_MGR_MEM_DQ_PER_READ_DQS-1);
@@ -1941,8 +1855,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
scc_mgr_set_dq_in_delay(write_group, p, d);
scc_mgr_load_dq(p);
}
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
}
found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
@@ -1959,8 +1872,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
scc_mgr_set_dq_in_delay(write_group, p, 0);
scc_mgr_load_dq(p);
}
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
}
return found;
@@ -2006,12 +1918,11 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
}
- addr = (u32)&sdr_scc_mgr->update;
/* Search for the left edge of the window for each bit */
for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
/*
* Stop searching when the read test doesn't pass AND when
@@ -2095,7 +2006,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
break;
}
- addr = (u32)&sdr_scc_mgr->update;
/* Search for the right edge of the window for each bit */
for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
@@ -2107,7 +2017,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
}
scc_mgr_load_dqs(read_group);
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
/*
* Stop searching when the read test doesn't pass AND when
@@ -2188,7 +2098,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
}
/* Check that all bits have a window */
- addr = (u32)&sdr_scc_mgr->update;
for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
%d right_edge[%u]: %d", __func__, __LINE__,
@@ -2206,7 +2115,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
start_dqs_en);
}
scc_mgr_load_dqs(read_group);
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
find edge [%u]: %d %d", __func__, __LINE__,
@@ -2280,7 +2189,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
dqs_margin = IO_IO_IN_DELAY_MAX + 1;
dq_margin = IO_IO_IN_DELAY_MAX + 1;
- addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
/* add delay to bring centre of all DQ windows to the same "level" */
for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
/* Use values before divide by 2 to reduce round off error */
@@ -2291,6 +2199,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
debug_cond(DLEVEL == 2, "vfifo_center: before: \
shift_dq[%u]=%d\n", i, shift_dq);
+ addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
temp_dq_in_delay1 = readl(addr + (p << 2));
temp_dq_in_delay2 = readl(addr + (i << 2));
@@ -2338,8 +2247,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
* Do not remove this line as it makes sure all of our decisions
* have been applied. Apply the update bit.
*/
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
return (dq_margin >= 0) && (dqs_margin >= 0);
}
@@ -2534,7 +2442,6 @@ static uint32_t rw_mgr_mem_calibrate_lfifo(void)
{
uint32_t found_one;
uint32_t bit_chk;
- uint32_t addr;
debug("%s:%d\n", __func__, __LINE__);
@@ -2546,9 +2453,8 @@ static uint32_t rw_mgr_mem_calibrate_lfifo(void)
rw_mgr_mem_calibrate_read_load_patterns(0, 1);
found_one = 0;
- addr = (u32)&phy_mgr_cfg->phy_rlat;
do {
- writel(gbl->curr_read_lat, addr);
+ writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
__func__, __LINE__, gbl->curr_read_lat);
@@ -2567,14 +2473,12 @@ static uint32_t rw_mgr_mem_calibrate_lfifo(void)
/* reset the fifos to get pointers to known state */
- addr = (u32)&phy_mgr_cmd->fifo_reset;
- writel(0, addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
if (found_one) {
/* add a fudge factor to the read latency that was determined */
gbl->curr_read_lat += 2;
- addr = (u32)&phy_mgr_cfg->phy_rlat;
- writel(gbl->curr_read_lat, addr);
+ writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
read_lat=%u\n", __func__, __LINE__,
gbl->curr_read_lat);
@@ -2639,24 +2543,21 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
* instruction that sends out the data. We set the counter to a
* large number so that the jump is always taken.
*/
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(0xFF, addr);
+ writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
/* CNTR 3 - Not used */
if (test_dm) {
mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
- addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
- addr);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
} else {
mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA, addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP, addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
}
} else if (rw_wl_nop_cycles == 0) {
/*
@@ -2664,19 +2565,17 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
* to the DQS enable instruction. We set the counter to a large
* number so that the jump is always taken.
*/
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(0xFF, addr);
+ writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
/* CNTR 3 - Not used */
if (test_dm) {
mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
- addr);
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
} else {
mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS, addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
}
} else {
/*
@@ -2684,52 +2583,47 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
* and NOT take the jump. So we set the counter to 0. The jump
* address doesn't count.
*/
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr2;
- writel(0x0, addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add2;
- writel(0x0, addr);
+ writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
+ writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
/*
* CNTR 3 - Set the nop counter to the number of cycles we
* need to loop for, minus 1.
*/
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr3;
- writel(rw_wl_nop_cycles - 1, addr);
+ writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
if (test_dm) {
mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP, addr);
+ writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
} else {
mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add3;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP, addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
}
}
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RESET_READ_DATAPATH_OFFSET;
- writel(0, addr);
+ writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RESET_READ_DATAPATH_OFFSET);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
if (quick_write_mode)
- writel(0x08, addr);
+ writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
else
- writel(0x40, addr);
+ writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(mcc_instruction, addr);
+ writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
/*
* CNTR 1 - This is used to ensure enough time elapses
* for read data to come back.
*/
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(0x30, addr);
+ writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
if (test_dm) {
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT, addr);
+ writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
} else {
- writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT, addr);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
}
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
@@ -2741,7 +2635,6 @@ static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
uint32_t *bit_chk, uint32_t all_ranks)
{
- uint32_t addr;
uint32_t r;
uint32_t correct_mask_vg;
uint32_t tmp_bit_chk;
@@ -2764,11 +2657,10 @@ static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
tmp_bit_chk = 0;
- addr = (u32)&phy_mgr_cmd->fifo_reset;
addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
/* reset the fifos to get pointers to known state */
- writel(0, addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
tmp_bit_chk = tmp_bit_chk <<
(RW_MGR_MEM_DQ_PER_WRITE_DQS /
@@ -2849,11 +2741,10 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
}
/* Search for the left edge of the window for each bit */
- addr = (u32)&sdr_scc_mgr->update;
for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, d);
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
/*
* Stop searching when the read test doesn't pass AND when
@@ -2933,12 +2824,11 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
}
/* Search for the right edge of the window for each bit */
- addr = (u32)&sdr_scc_mgr->update;
for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
d + start_dqs);
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
/*
* Stop searching when the read test doesn't pass AND when
@@ -3071,7 +2961,6 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
/* add delay to bring centre of all DQ windows to the same "level" */
- addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
/* Use values before divide by 2 to reduce round off error */
shift_dq = (left_edge[i] - right_edge[i] -
@@ -3081,6 +2970,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
[%u]=%d\n", __func__, __LINE__, i, shift_dq);
+ addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
temp_dq_out1_delay = readl(addr + (i << 2));
if (shift_dq + (int32_t)temp_dq_out1_delay >
(int32_t)IO_IO_OUT1_DELAY_MAX) {
@@ -3107,8 +2997,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
/* Move DQS */
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
/* Centre DM */
debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
@@ -3126,10 +3015,9 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
int32_t win_best = 0;
/* Search for the/part of the window with DM shift */
- addr = (u32)&sdr_scc_mgr->update;
for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
scc_mgr_apply_group_dm_out1_delay(write_group, d);
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
PASS_ALL_BITS, &bit_chk,
@@ -3173,7 +3061,6 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
}
/* Search for the/part of the window with DQS shifts */
- addr = (u32)&sdr_scc_mgr->update;
for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
/*
* Note: This only shifts DQS, so are we limiting ourselve to
@@ -3182,7 +3069,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
d + new_dqs);
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
PASS_ALL_BITS, &bit_chk,
0)) {
@@ -3245,8 +3132,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
dm_margin = left_edge[0] - mid;
scc_mgr_apply_group_dm_out1_delay(write_group, mid);
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
dm_margin=%d\n", __func__, __LINE__, left_edge[0],
@@ -3262,8 +3148,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
* Do not remove this line as it makes sure all of our
* decisions have been applied.
*/
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
}
@@ -3292,7 +3177,6 @@ static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
static void mem_precharge_and_activate(void)
{
uint32_t r;
- uint32_t addr;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
if (param->skip_ranks[r]) {
@@ -3304,22 +3188,20 @@ static void mem_precharge_and_activate(void)
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
/* precharge all banks ... */
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_PRECHARGE_ALL, addr);
+ writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr0;
- writel(0x0F, addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add0;
- writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1, addr);
+ writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
+ writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add0);
- addr = (u32)&sdr_rw_load_mgr_regs->load_cntr1;
- writel(0x0F, addr);
- addr = (u32)&sdr_rw_load_jump_mgr_regs->load_jump_add1;
- writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2, addr);
+ writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
+ writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
/* activate rows */
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_ACTIVATE_0_AND_1, addr);
+ writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
}
}
@@ -3329,15 +3211,12 @@ static void mem_config(void)
uint32_t rlat, wlat;
uint32_t rw_wl_nop_cycles;
uint32_t max_latency;
- uint32_t addr;
debug("%s:%d\n", __func__, __LINE__);
/* read in write and read latency */
- addr = (u32)&data_mgr->t_wl_add;
- wlat = readl(addr);
+ wlat = readl(&data_mgr->t_wl_add);
+ wlat += readl(&data_mgr->mem_t_add);
- addr = (u32)&data_mgr->mem_t_add;
- wlat += readl(addr);
/* WL for hard phy does not include additive latency */
/*
@@ -3347,8 +3226,7 @@ static void mem_config(void)
*/
wlat = wlat + 1;
- addr = (u32)&data_mgr->t_rl_add;
- rlat = readl(addr);
+ rlat = readl(&data_mgr->t_rl_add);
rw_wl_nop_cycles = wlat - 2;
gbl->rw_wl_nop_cycles = rw_wl_nop_cycles;
@@ -3370,13 +3248,11 @@ static void mem_config(void)
if (gbl->curr_read_lat > max_latency)
gbl->curr_read_lat = max_latency;
- addr = (u32)&phy_mgr_cfg->phy_rlat;
- writel(gbl->curr_read_lat, addr);
+ writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
/* advertise write latency */
gbl->curr_write_lat = wlat;
- addr = (u32)&phy_mgr_cfg->afi_wlat;
- writel(wlat - 2, addr);
+ writel(wlat - 2, &phy_mgr_cfg->afi_wlat);
/* initialize bit slips */
mem_precharge_and_activate();
@@ -3387,7 +3263,6 @@ static void mem_skip_calibrate(void)
{
uint32_t vfifo_offset;
uint32_t i, j, r;
- uint32_t addr;
debug("%s:%d\n", __func__, __LINE__);
/* Need to update every shadow register set used by the interface */
@@ -3432,21 +3307,16 @@ static void mem_skip_calibrate(void)
scc_mgr_set_dqdqs_output_phase(i, (1.25 *
IO_DLL_CHAIN_LENGTH - 2));
}
- addr = (u32)&sdr_scc_mgr->dqs_ena;
- writel(0xff, addr);
- addr = (u32)&sdr_scc_mgr->dqs_io_ena;
- writel(0xff, addr);
+ writel(0xff, &sdr_scc_mgr->dqs_ena);
+ writel(0xff, &sdr_scc_mgr->dqs_io_ena);
- addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_GROUP_COUNTER_OFFSET;
for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
- writel(i, addr);
+ writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
+ SCC_MGR_GROUP_COUNTER_OFFSET);
}
- addr = (u32)&sdr_scc_mgr->dq_ena;
- writel(0xff, addr);
- addr = (u32)&sdr_scc_mgr->dm_ena;
- writel(0xff, addr);
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0xff, &sdr_scc_mgr->dq_ena);
+ writel(0xff, &sdr_scc_mgr->dm_ena);
+ writel(0, &sdr_scc_mgr->update);
}
/* Compensate for simulation model behaviour */
@@ -3454,28 +3324,24 @@ static void mem_skip_calibrate(void)
scc_mgr_set_dqs_bus_in_delay(i, 10);
scc_mgr_load_dqs(i);
}
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
/*
* ArriaV has hard FIFOs that can only be initialized by incrementing
* in sequencer.
*/
vfifo_offset = CALIB_VFIFO_OFFSET;
- addr = (u32)&phy_mgr_cmd->inc_vfifo_hard_phy;
for (j = 0; j < vfifo_offset; j++) {
- writel(0xff, addr);
+ writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
}
- addr = (u32)&phy_mgr_cmd->fifo_reset;
- writel(0, addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
/*
* For ACV with hard lfifo, we get the skip-cal setting from
* generation-time constant.
*/
gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
- addr = (u32)&phy_mgr_cfg->phy_rlat;
- writel(gbl->curr_read_lat, addr);
+ writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
}
/* Memory calibration entry point */
@@ -3489,7 +3355,6 @@ static uint32_t mem_calibrate(void)
uint32_t failing_groups = 0;
uint32_t group_failed = 0;
uint32_t sr_failed = 0;
- uint32_t addr;
debug("%s:%d\n", __func__, __LINE__);
/* Initialize the data settings */
@@ -3503,9 +3368,9 @@ static uint32_t mem_calibrate(void)
mem_config();
uint32_t bypass_mode = 0x1;
- addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_GROUP_COUNTER_OFFSET;
for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
- writel(i, addr);
+ writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
+ SCC_MGR_GROUP_COUNTER_OFFSET);
scc_set_bypass_mode(i, bypass_mode);
}
@@ -3539,8 +3404,8 @@ static uint32_t mem_calibrate(void)
if (current_run == 0)
continue;
- addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_GROUP_COUNTER_OFFSET;
- writel(write_group, addr);
+ writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
+ SCC_MGR_GROUP_COUNTER_OFFSET);
scc_mgr_zero_group(write_group, write_test_bgn,
0);
@@ -3664,8 +3529,7 @@ static uint32_t mem_calibrate(void)
* Do not remove this line as it makes sure all of our decisions
* have been applied.
*/
- addr = (u32)&sdr_scc_mgr->update;
- writel(0, addr);
+ writel(0, &sdr_scc_mgr->update);
return 1;
}
@@ -3673,13 +3537,11 @@ static uint32_t run_mem_calibrate(void)
{
uint32_t pass;
uint32_t debug_info;
- uint32_t addr;
debug("%s:%d\n", __func__, __LINE__);
/* Reset pass/fail status shown on afi_cal_success/fail */
- addr = (u32)&phy_mgr_cfg->cal_status;
- writel(PHY_MGR_CAL_RESET, addr);
+ writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
/* stop tracking manger */
uint32_t ctrlcfg = readl(&sdr_ctrl->ctrl_cfg);
@@ -3692,8 +3554,7 @@ static uint32_t run_mem_calibrate(void)
pass = mem_calibrate();
mem_precharge_and_activate();
- addr = (u32)&phy_mgr_cmd->fifo_reset;
- writel(0, addr);
+ writel(0, &phy_mgr_cmd->fifo_reset);
/*
* Handoff:
@@ -3706,8 +3567,7 @@ static uint32_t run_mem_calibrate(void)
* 0: AFI Mux Select
* 1: DDIO Mux Select
*/
- addr = (u32)&phy_mgr_cfg->mux_sel;
- writel(0x2, addr);
+ writel(0x2, &phy_mgr_cfg->mux_sel);
}
writel(ctrlcfg, &sdr_ctrl->ctrl_cfg);
@@ -3727,13 +3587,10 @@ static uint32_t run_mem_calibrate(void)
/* Update the FOM in the register file */
debug_info = gbl->fom_in;
debug_info |= gbl->fom_out << 8;
- addr = (u32)&sdr_reg_file->fom;
- writel(debug_info, addr);
+ writel(debug_info, &sdr_reg_file->fom);
- addr = (u32)&phy_mgr_cfg->cal_debug_info;
- writel(debug_info, addr);
- addr = (u32)&phy_mgr_cfg->cal_status;
- writel(PHY_MGR_CAL_SUCCESS, addr);
+ writel(debug_info, &phy_mgr_cfg->cal_debug_info);
+ writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
} else {
printf("%s: CALIBRATION FAILED\n", __FILE__);
@@ -3741,19 +3598,15 @@ static uint32_t run_mem_calibrate(void)
debug_info |= gbl->error_substage << 8;
debug_info |= gbl->error_group << 16;
- addr = (u32)&sdr_reg_file->failing_stage;
- writel(debug_info, addr);
- addr = (u32)&phy_mgr_cfg->cal_debug_info;
- writel(debug_info, addr);
- addr = (u32)&phy_mgr_cfg->cal_status;
- writel(PHY_MGR_CAL_FAIL, addr);
+ writel(debug_info, &sdr_reg_file->failing_stage);
+ writel(debug_info, &phy_mgr_cfg->cal_debug_info);
+ writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
/* Update the failing group/stage in the register file */
debug_info = gbl->error_stage;
debug_info |= gbl->error_substage << 8;
debug_info |= gbl->error_group << 16;
- addr = (u32)&sdr_reg_file->failing_stage;
- writel(debug_info, addr);
+ writel(debug_info, &sdr_reg_file->failing_stage);
}
return pass;
@@ -3779,29 +3632,14 @@ static void hc_initialize_rom_data(void)
static void initialize_reg_file(void)
{
- uint32_t addr;
-
/* Initialize the register file with the correct data */
- addr = (u32)&sdr_reg_file->signature;
- writel(REG_FILE_INIT_SEQ_SIGNATURE, addr);
-
- addr = (u32)&sdr_reg_file->debug_data_addr;
- writel(0, addr);
-
- addr = (u32)&sdr_reg_file->cur_stage;
- writel(0, addr);
-
- addr = (u32)&sdr_reg_file->fom;
- writel(0, addr);
-
- addr = (u32)&sdr_reg_file->failing_stage;
- writel(0, addr);
-
- addr = (u32)&sdr_reg_file->debug1;
- writel(0, addr);
-
- addr = (u32)&sdr_reg_file->debug2;
- writel(0, addr);
+ writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
+ writel(0, &sdr_reg_file->debug_data_addr);
+ writel(0, &sdr_reg_file->cur_stage);
+ writel(0, &sdr_reg_file->fom);
+ writel(0, &sdr_reg_file->failing_stage);
+ writel(0, &sdr_reg_file->debug1);
+ writel(0, &sdr_reg_file->debug2);
}
static void initialize_hps_phy(void)
@@ -3858,7 +3696,6 @@ static void initialize_tracking(void)
uint32_t trk_sample_count = 7500;
uint32_t dtaps_per_ptap;
uint32_t tmp_delay;
- uint32_t addr;
/*
* compute usable version of value in case we skip full
@@ -3902,26 +3739,13 @@ static void initialize_tracking(void)
concatenated_refresh = concatenated_refresh ^ 1000; /* trefi */
/* Initialize the register file with the correct data */
- addr = (u32)&sdr_reg_file->dtaps_per_ptap;
- writel(dtaps_per_ptap, addr);
-
- addr = (u32)&sdr_reg_file->trk_sample_count;
- writel(trk_sample_count, addr);
-
- addr = (u32)&sdr_reg_file->trk_longidle;
- writel(concatenated_longidle, addr);
-
- addr = (u32)&sdr_reg_file->delays;
- writel(concatenated_delays, addr);
-
- addr = (u32)&sdr_reg_file->trk_rw_mgr_addr;
- writel(concatenated_rw_addr, addr);
-
- addr = (u32)&sdr_reg_file->trk_read_dqs_width;
- writel(RW_MGR_MEM_IF_READ_DQS_WIDTH, addr);
-
- addr = (u32)&sdr_reg_file->trk_rfsh;
- writel(concatenated_refresh, addr);
+ writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
+ writel(trk_sample_count, &sdr_reg_file->trk_sample_count);
+ writel(concatenated_longidle, &sdr_reg_file->trk_longidle);
+ writel(concatenated_delays, &sdr_reg_file->delays);
+ writel(concatenated_rw_addr, &sdr_reg_file->trk_rw_mgr_addr);
+ writel(RW_MGR_MEM_IF_READ_DQS_WIDTH, &sdr_reg_file->trk_read_dqs_width);
+ writel(concatenated_refresh, &sdr_reg_file->trk_rfsh);
}
int sdram_calibration_full(void)
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 053/172] ddr: altera: Clean up hc_initialize_rom_data()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (51 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 052/172] ddr: altera: Massage addr into I/O accessors Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 054/172] ddr: altera: Clean up initialize_reg_file() Marek Vasut
` (120 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Clean the function up, fix data types, add kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 23fc459..7907b63 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3612,22 +3612,22 @@ static uint32_t run_mem_calibrate(void)
return pass;
}
+/**
+ * hc_initialize_rom_data() - Initialize ROM data
+ *
+ * Initialize ROM data.
+ */
static void hc_initialize_rom_data(void)
{
- uint32_t i;
- uint32_t addr;
+ u32 i, addr;
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
- for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++) {
- uint32_t data = inst_rom_init[i];
- writel(data, addr + (i << 2));
- }
+ for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
+ writel(inst_rom_init[i], addr + (i << 2));
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
- for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++) {
- uint32_t data = ac_rom_init[i];
- writel(data, addr + (i << 2));
- }
+ for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
+ writel(ac_rom_init[i], addr + (i << 2));
}
static void initialize_reg_file(void)
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 054/172] ddr: altera: Clean up initialize_reg_file()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (52 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 053/172] ddr: altera: Clean up hc_initialize_rom_data() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 055/172] ddr: altera: Clean up initialize_hps_phy() Marek Vasut
` (119 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Add brief kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 7907b63..72b2021 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3630,6 +3630,11 @@ static void hc_initialize_rom_data(void)
writel(ac_rom_init[i], addr + (i << 2));
}
+/**
+ * initialize_reg_file() - Initialize SDR register file
+ *
+ * Initialize SDR register file.
+ */
static void initialize_reg_file(void)
{
/* Initialize the register file with the correct data */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 055/172] ddr: altera: Clean up initialize_hps_phy()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (53 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 054/172] ddr: altera: Clean up initialize_reg_file() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 056/172] ddr: altera: Clean up reg_file_set*() Marek Vasut
` (118 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Add brief kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 72b2021..8273bde 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3647,6 +3647,11 @@ static void initialize_reg_file(void)
writel(0, &sdr_reg_file->debug2);
}
+/**
+ * initialize_hps_phy() - Initialize HPS PHY
+ *
+ * Initialize HPS PHY.
+ */
static void initialize_hps_phy(void)
{
uint32_t reg;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 056/172] ddr: altera: Clean up reg_file_set*()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (54 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 055/172] ddr: altera: Clean up initialize_hps_phy() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 057/172] ddr: altera: Clean up scc manager function args Marek Vasut
` (117 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Turn the insides of these functions into trivial clrsetbits_le32()
and fix the data type of their argument to reflect it's actual size.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 43 +++++++-----------------------------------
1 file changed, 7 insertions(+), 36 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 8273bde..7aae4cc 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -99,49 +99,20 @@ static void set_failing_group_stage(uint32_t group, uint32_t stage,
}
}
-static void reg_file_set_group(uint32_t set_group)
+static void reg_file_set_group(u16 set_group)
{
- /* Read the current group and stage */
- uint32_t cur_stage_group = readl(&sdr_reg_file->cur_stage);
-
- /* Clear the group */
- cur_stage_group &= 0x0000FFFF;
-
- /* Set the group */
- cur_stage_group |= (set_group << 16);
-
- /* Write the data back */
- writel(cur_stage_group, &sdr_reg_file->cur_stage);
+ clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
}
-static void reg_file_set_stage(uint32_t set_stage)
+static void reg_file_set_stage(u8 set_stage)
{
- /* Read the current group and stage */
- uint32_t cur_stage_group = readl(&sdr_reg_file->cur_stage);
-
- /* Clear the stage and substage */
- cur_stage_group &= 0xFFFF0000;
-
- /* Set the stage */
- cur_stage_group |= (set_stage & 0x000000FF);
-
- /* Write the data back */
- writel(cur_stage_group, &sdr_reg_file->cur_stage);
+ clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
}
-static void reg_file_set_sub_stage(uint32_t set_sub_stage)
+static void reg_file_set_sub_stage(u8 set_sub_stage)
{
- /* Read the current group and stage */
- uint32_t cur_stage_group = readl(&sdr_reg_file->cur_stage);
-
- /* Clear the substage */
- cur_stage_group &= 0xFFFF00FF;
-
- /* Set the sub stage */
- cur_stage_group |= ((set_sub_stage << 8) & 0x0000FF00);
-
- /* Write the data back */
- writel(cur_stage_group, &sdr_reg_file->cur_stage);
+ set_sub_stage &= 0xff;
+ clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
}
static void initialize(void)
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 057/172] ddr: altera: Clean up scc manager function args
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (55 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 056/172] ddr: altera: Clean up reg_file_set*() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 058/172] ddr: altera: Reorder scc manager functions Marek Vasut
` (116 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Clean up the unused args of the functions used to configure the
SCC manager.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 30 +++++++++++++-----------------
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 7aae4cc..2fcc3ee 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -417,8 +417,7 @@ static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)
writel(delay, addr + (read_group << 2));
}
-static void scc_mgr_set_dq_out1_delay(uint32_t write_group,
- uint32_t dq_in_group, uint32_t delay)
+static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
{
uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
@@ -426,8 +425,7 @@ static void scc_mgr_set_dq_out1_delay(uint32_t write_group,
writel(delay, addr + (dq_in_group << 2));
}
-static void scc_mgr_set_dq_in_delay(uint32_t write_group,
- uint32_t dq_in_group, uint32_t delay)
+static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
{
uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
@@ -461,8 +459,7 @@ static void scc_mgr_set_dqs_out1_delay(uint32_t write_group,
writel(delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
}
-static void scc_mgr_set_dm_out1_delay(uint32_t write_group,
- uint32_t dm, uint32_t delay)
+static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
{
uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
@@ -544,9 +541,9 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
NUM_RANKS_PER_SHADOW_REG) {
/* Zero all DQ config settings */
for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
- scc_mgr_set_dq_out1_delay(write_group, i, 0);
+ scc_mgr_set_dq_out1_delay(i, 0);
if (!out_only)
- scc_mgr_set_dq_in_delay(write_group, i, 0);
+ scc_mgr_set_dq_in_delay(i, 0);
}
/* multicast to all DQ enables */
@@ -554,7 +551,7 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
/* Zero all DM config settings */
for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
- scc_mgr_set_dm_out1_delay(write_group, i, 0);
+ scc_mgr_set_dm_out1_delay(i, 0);
}
/* multicast to all DM enables */
@@ -627,7 +624,7 @@ static void scc_mgr_apply_group_dq_in_delay(uint32_t write_group,
uint32_t i, p;
for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
- scc_mgr_set_dq_in_delay(write_group, p, delay);
+ scc_mgr_set_dq_in_delay(p, delay);
scc_mgr_load_dq(p);
}
}
@@ -640,7 +637,7 @@ static void scc_mgr_apply_group_dq_out1_delay(uint32_t write_group,
uint32_t i, p;
for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
- scc_mgr_set_dq_out1_delay(write_group, i, delay1);
+ scc_mgr_set_dq_out1_delay(i, delay1);
scc_mgr_load_dq(i);
}
}
@@ -652,7 +649,7 @@ static void scc_mgr_apply_group_dm_out1_delay(uint32_t write_group,
uint32_t i;
for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
- scc_mgr_set_dm_out1_delay(write_group, i, delay1);
+ scc_mgr_set_dm_out1_delay(i, delay1);
scc_mgr_load_dm(i);
}
}
@@ -1823,7 +1820,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
debug_cond(DLEVEL == 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
write_group, read_group);
debug_cond(DLEVEL == 1, "r=%u, i=%u p=%u d=%u\n", r, i , p, d);
- scc_mgr_set_dq_in_delay(write_group, p, d);
+ scc_mgr_set_dq_in_delay(p, d);
scc_mgr_load_dq(p);
}
writel(0, &sdr_scc_mgr->update);
@@ -1840,7 +1837,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
r += NUM_RANKS_PER_SHADOW_REG) {
for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS;
i++, p++) {
- scc_mgr_set_dq_in_delay(write_group, p, 0);
+ scc_mgr_set_dq_in_delay(p, 0);
scc_mgr_load_dq(p);
}
writel(0, &sdr_scc_mgr->update);
@@ -2183,7 +2180,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
debug_cond(DLEVEL == 2, "vfifo_center: after: \
shift_dq[%u]=%d\n", i, shift_dq);
final_dq[i] = temp_dq_in_delay1 + shift_dq;
- scc_mgr_set_dq_in_delay(write_group, p, final_dq[i]);
+ scc_mgr_set_dq_in_delay(p, final_dq[i]);
scc_mgr_load_dq(p);
debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
@@ -2951,8 +2948,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
}
debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
i, shift_dq);
- scc_mgr_set_dq_out1_delay(write_group, i, temp_dq_out1_delay +
- shift_dq);
+ scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
scc_mgr_load_dq(i);
debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 058/172] ddr: altera: Reorder scc manager functions
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (56 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 057/172] ddr: altera: Clean up scc manager function args Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 059/172] ddr: altera: Implement universal scc manager config function Marek Vasut
` (115 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
This patch just puts functions which look similar next to each
other, so they can be sorted out. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 195 ++++++++++++++++++++---------------------
1 file changed, 95 insertions(+), 100 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 2fcc3ee..e839646 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -270,8 +270,15 @@ static void scc_mgr_initialize(void)
}
}
-static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group,
- uint32_t delay)
+static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
+{
+ u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQDQS_OUT_PHASE_OFFSET;
+
+ /* Load the setting in the SCC manager */
+ writel(phase, addr + (write_group << 2));
+}
+
+static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
{
u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
@@ -279,20 +286,84 @@ static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group,
writel(delay, addr + (read_group << 2));
}
-static void scc_mgr_set_dqs_io_in_delay(uint32_t write_group,
- uint32_t delay)
+static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
+{
+ u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_EN_PHASE_OFFSET;
+
+ /* Load the setting in the SCC manager */
+ writel(phase, addr + (read_group << 2));
+}
+
+static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
+{
+ uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_EN_DELAY_OFFSET;
+
+ /* Load the setting in the SCC manager */
+ writel(delay + IO_DQS_EN_DELAY_OFFSET, addr + (read_group << 2));
+}
+
+static void scc_mgr_set_dqs_io_in_delay(uint32_t write_group, uint32_t delay)
{
u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
writel(delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
}
-static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
+static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
{
- u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_EN_PHASE_OFFSET;
+ uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
/* Load the setting in the SCC manager */
- writel(phase, addr + (read_group << 2));
+ writel(delay, addr + (dq_in_group << 2));
+}
+
+static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
+{
+ uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
+
+ /* Load the setting in the SCC manager */
+ writel(delay, addr + (dq_in_group << 2));
+}
+
+static void scc_mgr_set_dqs_out1_delay(uint32_t write_group,
+ uint32_t delay)
+{
+ uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
+
+ /* Load the setting in the SCC manager */
+ writel(delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
+}
+
+static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
+{
+ uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
+
+ /* Load the setting in the SCC manager */
+ writel(delay, addr + ((RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm) << 2));
+}
+
+/* load up dqs config settings */
+static void scc_mgr_load_dqs(uint32_t dqs)
+{
+ writel(dqs, &sdr_scc_mgr->dqs_ena);
+}
+
+/* load up dqs io config settings */
+static void scc_mgr_load_dqs_io(void)
+{
+ writel(0, &sdr_scc_mgr->dqs_io_ena);
+}
+
+/* load up dq config settings */
+static void scc_mgr_load_dq(uint32_t dq_in_group)
+{
+ writel(dq_in_group, &sdr_scc_mgr->dq_ena);
+}
+
+/* load up dm config settings */
+static void scc_mgr_load_dm(uint32_t dm)
+{
+ writel(dm, &sdr_scc_mgr->dm_ena);
}
static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,
@@ -322,15 +393,6 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,
}
}
-static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group,
- uint32_t phase)
-{
- u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQDQS_OUT_PHASE_OFFSET;
-
- /* Load the setting in the SCC manager */
- writel(phase, addr + (write_group << 2));
-}
-
static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
uint32_t phase)
{
@@ -358,15 +420,6 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
}
}
-static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
-{
- uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_EN_DELAY_OFFSET;
-
- /* Load the setting in the SCC manager */
- writel(delay + IO_DQS_EN_DELAY_OFFSET, addr +
- (read_group << 2));
-}
-
static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
uint32_t delay)
{
@@ -417,22 +470,6 @@ static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)
writel(delay, addr + (read_group << 2));
}
-static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
-{
- uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
-
- /* Load the setting in the SCC manager */
- writel(delay, addr + (dq_in_group << 2));
-}
-
-static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
-{
- uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
-
- /* Load the setting in the SCC manager */
- writel(delay, addr + (dq_in_group << 2));
-}
-
static void scc_mgr_set_hhp_extras(void)
{
/*
@@ -450,24 +487,6 @@ static void scc_mgr_set_hhp_extras(void)
writel(value, addr + SCC_MGR_HHP_EXTRAS_OFFSET);
}
-static void scc_mgr_set_dqs_out1_delay(uint32_t write_group,
- uint32_t delay)
-{
- uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
-
- /* Load the setting in the SCC manager */
- writel(delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
-}
-
-static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
-{
- uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
-
- /* Load the setting in the SCC manager */
- writel(delay, addr +
- ((RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm) << 2));
-}
-
/*
* USER Zero all DQS config
* TODO: maybe rename to scc_mgr_zero_dqs_config (or something)
@@ -532,6 +551,23 @@ static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)
writel(0, &sdr_scc_mgr->update);
}
+static void scc_mgr_load_dqs_for_write_group(uint32_t write_group)
+{
+ uint32_t read_group;
+ uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena;
+ /*
+ * Although OCT affects only write data, the OCT delay is controlled
+ * by the DQS logic block which is instantiated once per read group.
+ * For protocols where a write group consists of multiple read groups,
+ * the setting must be scanned multiple times.
+ */
+ for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
+ read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
+ writel(read_group, addr);
+}
+
static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
int32_t out_only)
{
@@ -573,47 +609,6 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
}
}
-/* load up dqs config settings */
-static void scc_mgr_load_dqs(uint32_t dqs)
-{
- writel(dqs, &sdr_scc_mgr->dqs_ena);
-}
-
-static void scc_mgr_load_dqs_for_write_group(uint32_t write_group)
-{
- uint32_t read_group;
- uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena;
- /*
- * Although OCT affects only write data, the OCT delay is controlled
- * by the DQS logic block which is instantiated once per read group.
- * For protocols where a write group consists of multiple read groups,
- * the setting must be scanned multiple times.
- */
- for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
- read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
- writel(read_group, addr);
-}
-
-/* load up dqs io config settings */
-static void scc_mgr_load_dqs_io(void)
-{
- writel(0, &sdr_scc_mgr->dqs_io_ena);
-}
-
-/* load up dq config settings */
-static void scc_mgr_load_dq(uint32_t dq_in_group)
-{
- writel(dq_in_group, &sdr_scc_mgr->dq_ena);
-}
-
-/* load up dm config settings */
-static void scc_mgr_load_dm(uint32_t dm)
-{
- writel(dm, &sdr_scc_mgr->dm_ena);
-}
-
/*
* apply and load a particular input delay for the DQ pins in a group
* group_bgn is the index of the first dq pin (in the write group)
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 059/172] ddr: altera: Implement universal scc manager config function
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (57 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 058/172] ddr: altera: Reorder scc manager functions Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 060/172] ddr: altera: Clean up scc_mgr_initialize() Marek Vasut
` (114 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Implement unified scc_mgr_set() function and convert all those
9 scc_mgr_set_*() ad-hoc functions to call this one function.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 69 ++++++++++++++++++------------------------
1 file changed, 29 insertions(+), 40 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index e839646..d0d0e6a 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -252,94 +252,83 @@ static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
}
-static void scc_mgr_initialize(void)
+/**
+ * scc_mgr_set() - Set SCC Manager register
+ * @off: Base offset in SCC Manager space
+ * @grp: Read/Write group
+ * @val: Value to be set
+ *
+ * This function sets the SCC Manager (Scan Chain Control Manager) register.
+ */
+static void scc_mgr_set(u32 off, u32 grp, u32 val)
{
- u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_HHP_RFILE_OFFSET;
+ writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
+}
+static void scc_mgr_initialize(void)
+{
/*
* Clear register file for HPS
* 16 (2^4) is the size of the full register file in the scc mgr:
* RFILE_DEPTH = log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
- * MEM_IF_READ_DQS_WIDTH - 1) + 1;
+ * MEM_IF_READ_DQS_WIDTH - 1) + 1;
*/
- uint32_t i;
+ int i;
for (i = 0; i < 16; i++) {
debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
__func__, __LINE__, i);
- writel(0, addr + (i << 2));
+ scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
}
}
static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
{
- u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQDQS_OUT_PHASE_OFFSET;
-
- /* Load the setting in the SCC manager */
- writel(phase, addr + (write_group << 2));
+ scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
}
static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
{
- u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
-
- /* Load the setting in the SCC manager */
- writel(delay, addr + (read_group << 2));
+ scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
}
static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
{
- u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_EN_PHASE_OFFSET;
-
- /* Load the setting in the SCC manager */
- writel(phase, addr + (read_group << 2));
+ scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
}
static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
{
- uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_EN_DELAY_OFFSET;
-
- /* Load the setting in the SCC manager */
- writel(delay + IO_DQS_EN_DELAY_OFFSET, addr + (read_group << 2));
+ scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
}
static void scc_mgr_set_dqs_io_in_delay(uint32_t write_group, uint32_t delay)
{
- u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
-
- writel(delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
+ scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
+ delay);
}
static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
{
- uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
-
- /* Load the setting in the SCC manager */
- writel(delay, addr + (dq_in_group << 2));
+ scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
}
static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
{
- uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
-
- /* Load the setting in the SCC manager */
- writel(delay, addr + (dq_in_group << 2));
+ scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
}
static void scc_mgr_set_dqs_out1_delay(uint32_t write_group,
uint32_t delay)
{
- uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
-
- /* Load the setting in the SCC manager */
- writel(delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
+ scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
+ delay);
}
static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
{
- uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
-
- /* Load the setting in the SCC manager */
- writel(delay, addr + ((RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm) << 2));
+ scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
+ RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
+ delay);
}
/* load up dqs config settings */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 060/172] ddr: altera: Clean up scc_mgr_initialize()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (58 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 059/172] ddr: altera: Implement universal scc manager config function Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 061/172] ddr: altera: Shuffle around scc_mgr_set_*all_ranks() Marek Vasut
` (113 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Clean up the comments and add kerneldoc. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index d0d0e6a..4bdc3a7 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -265,15 +265,21 @@ static void scc_mgr_set(u32 off, u32 grp, u32 val)
writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
}
+/**
+ * scc_mgr_initialize() - Initialize SCC Manager registers
+ *
+ * Initialize SCC Manager registers.
+ */
static void scc_mgr_initialize(void)
{
/*
- * Clear register file for HPS
- * 16 (2^4) is the size of the full register file in the scc mgr:
- * RFILE_DEPTH = log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
- * MEM_IF_READ_DQS_WIDTH - 1) + 1;
+ * Clear register file for HPS. 16 (2^4) is the size of the
+ * full register file in the scc mgr:
+ * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
+ * MEM_IF_READ_DQS_WIDTH - 1);
*/
int i;
+
for (i = 0; i < 16; i++) {
debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
__func__, __LINE__, i);
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 061/172] ddr: altera: Shuffle around scc_mgr_set_*all_ranks()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (59 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 060/172] ddr: altera: Clean up scc_mgr_initialize() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 062/172] ddr: altera: Implement universal scc_mgr_set_all_ranks() Marek Vasut
` (112 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Shuffle the code around a bit, but without any functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 19 ++++++++-----------
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 4bdc3a7..1718ebf 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -365,10 +365,11 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,
uint32_t phase)
{
uint32_t r;
- uint32_t update_scan_chains;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
+ scc_mgr_set_dqs_en_phase(read_group, phase);
+
/*
* USER although the h/w doesn't support different phases per
* shadow register, for simplicity our scc manager modeling
@@ -377,11 +378,8 @@ static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,
* for efficiency, the scan chain update should occur only
* once to sr0.
*/
- update_scan_chains = (r == 0) ? 1 : 0;
-
- scc_mgr_set_dqs_en_phase(read_group, phase);
- if (update_scan_chains) {
+ if (r == 0) {
writel(read_group, &sdr_scc_mgr->dqs_ena);
writel(0, &sdr_scc_mgr->update);
}
@@ -392,10 +390,11 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
uint32_t phase)
{
uint32_t r;
- uint32_t update_scan_chains;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
+ scc_mgr_set_dqdqs_output_phase(write_group, phase);
+
/*
* USER although the h/w doesn't support different phases per
* shadow register, for simplicity our scc manager modeling
@@ -404,11 +403,8 @@ static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
* for efficiency, the scan chain update should occur only
* once to sr0.
*/
- update_scan_chains = (r == 0) ? 1 : 0;
- scc_mgr_set_dqdqs_output_phase(write_group, phase);
-
- if (update_scan_chains) {
+ if (r == 0) {
writel(write_group, &sdr_scc_mgr->dqs_ena);
writel(0, &sdr_scc_mgr->update);
}
@@ -424,7 +420,6 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
r += NUM_RANKS_PER_SHADOW_REG) {
scc_mgr_set_dqs_en_delay(read_group, delay);
- writel(read_group, &sdr_scc_mgr->dqs_ena);
/*
* In shadow register mode, the T11 settings are stored in
* registers in the core, which are updated by the DQS_ENA
@@ -433,6 +428,8 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
* select_shadow_regs_for_update with update_scan_chains
* set to 0.
*/
+
+ writel(read_group, &sdr_scc_mgr->dqs_ena);
writel(0, &sdr_scc_mgr->update);
}
/*
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 062/172] ddr: altera: Implement universal scc_mgr_set_all_ranks()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (60 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 061/172] ddr: altera: Shuffle around scc_mgr_set_*all_ranks() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 063/172] ddr: altera: Clean up scc_mgr_load_dqs_for_write_group() Marek Vasut
` (111 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Implement universal scc_mgr_set_all_ranks() function and convert
various ad-hoc implementations of similar functionality to use
this single function. Document the function in kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 95 +++++++++++++++++++-----------------------
1 file changed, 42 insertions(+), 53 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 1718ebf..df78146 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -361,77 +361,64 @@ static void scc_mgr_load_dm(uint32_t dm)
writel(dm, &sdr_scc_mgr->dm_ena);
}
-static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,
- uint32_t phase)
+/**
+ * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
+ * @off: Base offset in SCC Manager space
+ * @grp: Read/Write group
+ * @val: Value to be set
+ * @update: If non-zero, trigger SCC Manager update for all ranks
+ *
+ * This function sets the SCC Manager (Scan Chain Control Manager) register
+ * and optionally triggers the SCC update for all ranks.
+ */
+static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
+ const int update)
{
- uint32_t r;
+ u32 r;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
- scc_mgr_set_dqs_en_phase(read_group, phase);
-
- /*
- * USER although the h/w doesn't support different phases per
- * shadow register, for simplicity our scc manager modeling
- * keeps different phase settings per shadow reg, and it's
- * important for us to keep them in sync to match h/w.
- * for efficiency, the scan chain update should occur only
- * once to sr0.
- */
+ scc_mgr_set(off, grp, val);
- if (r == 0) {
- writel(read_group, &sdr_scc_mgr->dqs_ena);
+ if (update || (r == 0)) {
+ writel(grp, &sdr_scc_mgr->dqs_ena);
writel(0, &sdr_scc_mgr->update);
}
}
}
+static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
+{
+ /*
+ * USER although the h/w doesn't support different phases per
+ * shadow register, for simplicity our scc manager modeling
+ * keeps different phase settings per shadow reg, and it's
+ * important for us to keep them in sync to match h/w.
+ * for efficiency, the scan chain update should occur only
+ * once to sr0.
+ */
+ scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
+ read_group, phase, 0);
+}
+
static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
uint32_t phase)
{
- uint32_t r;
-
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
- r += NUM_RANKS_PER_SHADOW_REG) {
- scc_mgr_set_dqdqs_output_phase(write_group, phase);
-
- /*
- * USER although the h/w doesn't support different phases per
- * shadow register, for simplicity our scc manager modeling
- * keeps different phase settings per shadow reg, and it's
- * important for us to keep them in sync to match h/w.
- * for efficiency, the scan chain update should occur only
- * once to sr0.
- */
-
- if (r == 0) {
- writel(write_group, &sdr_scc_mgr->dqs_ena);
- writel(0, &sdr_scc_mgr->update);
- }
- }
+ /*
+ * USER although the h/w doesn't support different phases per
+ * shadow register, for simplicity our scc manager modeling
+ * keeps different phase settings per shadow reg, and it's
+ * important for us to keep them in sync to match h/w.
+ * for efficiency, the scan chain update should occur only
+ * once to sr0.
+ */
+ scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
+ write_group, phase, 0);
}
static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
uint32_t delay)
{
- uint32_t r;
-
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
- r += NUM_RANKS_PER_SHADOW_REG) {
- scc_mgr_set_dqs_en_delay(read_group, delay);
-
- /*
- * In shadow register mode, the T11 settings are stored in
- * registers in the core, which are updated by the DQS_ENA
- * signals. Not issuing the SCC_MGR_UPD command allows us to
- * save lots of rank switching overhead, by calling
- * select_shadow_regs_for_update with update_scan_chains
- * set to 0.
- */
-
- writel(read_group, &sdr_scc_mgr->dqs_ena);
- writel(0, &sdr_scc_mgr->update);
- }
/*
* In shadow register mode, the T11 settings are stored in
* registers in the core, which are updated by the DQS_ENA
@@ -440,6 +427,8 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
* select_shadow_regs_for_update with update_scan_chains
* set to 0.
*/
+ scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
+ read_group, delay, 1);
writel(0, &sdr_scc_mgr->update);
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 063/172] ddr: altera: Clean up scc_mgr_load_dqs_for_write_group()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (61 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 062/172] ddr: altera: Implement universal scc_mgr_set_all_ranks() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 064/172] ddr: altera: Clean up scc_set_bypass_mode() Marek Vasut
` (110 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Make this function more readable, no functional change. Also, zap the
forward declaration, which is no longer needed.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 26 +++++++++++++++-----------
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index df78146..1122cfa 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -13,8 +13,6 @@
#include "sequencer_auto_inst_init.h"
#include "sequencer_defines.h"
-static void scc_mgr_load_dqs_for_write_group(uint32_t write_group);
-
static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
(struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
@@ -532,21 +530,27 @@ static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)
writel(0, &sdr_scc_mgr->update);
}
-static void scc_mgr_load_dqs_for_write_group(uint32_t write_group)
+/**
+ * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
+ * @write_group: Write group
+ *
+ * Load DQS settings for Write Group, do not trigger SCC update.
+ */
+static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
{
- uint32_t read_group;
- uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena;
+ const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
+ const int base = write_group * ratio;
+ int i;
/*
+ * Load the setting in the SCC manager
* Although OCT affects only write data, the OCT delay is controlled
* by the DQS logic block which is instantiated once per read group.
* For protocols where a write group consists of multiple read groups,
- * the setting must be scanned multiple times.
+ * the setting must be set multiple times.
*/
- for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
- read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
- writel(read_group, addr);
+ for (i = 0; i < ratio; i++)
+ writel(base + i, &sdr_scc_mgr->dqs_ena);
}
static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 064/172] ddr: altera: Clean up scc_set_bypass_mode()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (62 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 063/172] ddr: altera: Clean up scc_mgr_load_dqs_for_write_group() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 065/172] ddr: altera: Clean up scc_mgr_set_oct_out1_delay() Marek Vasut
` (109 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
The mode argument of this function is not used at all, zap it.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 25 ++++++++++++++-----------
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 1122cfa..0b76ba2 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -503,12 +503,15 @@ static void scc_mgr_zero_all(void)
writel(0, &sdr_scc_mgr->update);
}
-static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)
+/**
+ * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
+ * @write_group: Write group
+ *
+ * Set bypass mode and trigger SCC update.
+ */
+static void scc_set_bypass_mode(const u32 write_group)
{
- /* mode = 0 : Do NOT bypass - Half Rate Mode */
- /* mode = 1 : Bypass - Full Rate Mode */
-
- /* only need to set once for all groups, pins, dq, dqs, dm */
+ /* Only needed once to set all groups, pins, DQ, DQS, DM. */
if (write_group == 0) {
debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n", __func__,
__LINE__);
@@ -516,17 +519,18 @@ static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)
debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
__func__, __LINE__);
}
- /* multicast to all DQ enables */
+
+ /* Multicast to all DQ enables. */
writel(0xff, &sdr_scc_mgr->dq_ena);
writel(0xff, &sdr_scc_mgr->dm_ena);
- /* update current DQS IO enable */
+ /* Update current DQS IO enable. */
writel(0, &sdr_scc_mgr->dqs_io_ena);
- /* update the DQS logic */
+ /* Update the DQS logic. */
writel(write_group, &sdr_scc_mgr->dqs_ena);
- /* hit update */
+ /* Hit update. */
writel(0, &sdr_scc_mgr->update);
}
@@ -3314,11 +3318,10 @@ static uint32_t mem_calibrate(void)
mem_config();
- uint32_t bypass_mode = 0x1;
for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
SCC_MGR_GROUP_COUNTER_OFFSET);
- scc_set_bypass_mode(i, bypass_mode);
+ scc_set_bypass_mode(i);
}
if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 065/172] ddr: altera: Clean up scc_mgr_set_oct_out1_delay()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (63 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 064/172] ddr: altera: Clean up scc_set_bypass_mode() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 066/172] ddr: altera: Clean up scc_mgr_apply_group_dq_out1_delay() Marek Vasut
` (108 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Make this function more readable, no functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 23 ++++++++++++++---------
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 0b76ba2..cc2fa47 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -430,11 +430,19 @@ static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
writel(0, &sdr_scc_mgr->update);
}
-static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)
+/**
+ * scc_mgr_set_oct_out1_delay() - Set OCT output delay
+ * @write_group: Write group
+ * @delay: Delay value
+ *
+ * This function sets the OCT output delay in SCC manager.
+ */
+static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
{
- uint32_t read_group;
- uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_OCT_OUT1_DELAY_OFFSET;
-
+ const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
+ const int base = write_group * ratio;
+ int i;
/*
* Load the setting in the SCC manager
* Although OCT affects only write data, the OCT delay is controlled
@@ -442,11 +450,8 @@ static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)
* For protocols where a write group consists of multiple read groups,
* the setting must be set multiple times.
*/
- for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
- read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
- writel(delay, addr + (read_group << 2));
+ for (i = 0; i < ratio; i++)
+ scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
}
static void scc_mgr_set_hhp_extras(void)
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 066/172] ddr: altera: Clean up scc_mgr_apply_group_dq_out1_delay()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (64 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 065/172] ddr: altera: Clean up scc_mgr_set_oct_out1_delay() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 067/172] ddr: altera: Clean up scc_mgr_*_delay() args Marek Vasut
` (107 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Remove unused write_group and group_bgn argument from this function.
Document the function using kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index cc2fa47..7eeadc2 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -618,15 +618,18 @@ static void scc_mgr_apply_group_dq_in_delay(uint32_t write_group,
}
}
-/* apply and load a particular output delay for the DQ pins in a group */
-static void scc_mgr_apply_group_dq_out1_delay(uint32_t write_group,
- uint32_t group_bgn,
- uint32_t delay1)
+/**
+ * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
+ * @delay: Delay value
+ *
+ * Apply and load a particular output delay for the DQ pins in a group.
+ */
+static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
{
- uint32_t i, p;
+ int i;
- for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
- scc_mgr_set_dq_out1_delay(i, delay1);
+ for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
+ scc_mgr_set_dq_out1_delay(i, delay);
scc_mgr_load_dq(i);
}
}
@@ -2699,7 +2702,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
/* Search for the left edge of the window for each bit */
for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
- scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, d);
+ scc_mgr_apply_group_dq_out1_delay(write_group, d);
writel(0, &sdr_scc_mgr->update);
@@ -2748,7 +2751,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
}
/* Reset DQ delay chains to 0 */
- scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, 0);
+ scc_mgr_apply_group_dq_out1_delay(write_group, 0);
sticky_bit_chk = 0;
for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 067/172] ddr: altera: Clean up scc_mgr_*_delay() args
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (65 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 066/172] ddr: altera: Clean up scc_mgr_apply_group_dq_out1_delay() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 068/172] ddr: altera: Clean up scc_mgr_set_hhp_extras() Marek Vasut
` (106 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Zap args which are not used by these functions, in particular
the write_group is often passed, but unused.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 32 ++++++++++++++------------------
1 file changed, 14 insertions(+), 18 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 7eeadc2..066d7f6 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -305,7 +305,7 @@ static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
}
-static void scc_mgr_set_dqs_io_in_delay(uint32_t write_group, uint32_t delay)
+static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
{
scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
delay);
@@ -321,8 +321,7 @@ static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
}
-static void scc_mgr_set_dqs_out1_delay(uint32_t write_group,
- uint32_t delay)
+static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
{
scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
delay);
@@ -589,9 +588,9 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
/* zero all DQS io settings */
if (!out_only)
- scc_mgr_set_dqs_io_in_delay(write_group, 0);
+ scc_mgr_set_dqs_io_in_delay(0);
/* av/cv don't have out2 */
- scc_mgr_set_dqs_out1_delay(write_group, IO_DQS_OUT_RESERVE);
+ scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
scc_mgr_load_dqs_for_write_group(write_group);
@@ -607,8 +606,7 @@ static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
* apply and load a particular input delay for the DQ pins in a group
* group_bgn is the index of the first dq pin (in the write group)
*/
-static void scc_mgr_apply_group_dq_in_delay(uint32_t write_group,
- uint32_t group_bgn, uint32_t delay)
+static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
{
uint32_t i, p;
@@ -635,8 +633,7 @@ static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
}
/* apply and load a particular output delay for the DM pins in a group */
-static void scc_mgr_apply_group_dm_out1_delay(uint32_t write_group,
- uint32_t delay1)
+static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
{
uint32_t i;
@@ -651,7 +648,7 @@ static void scc_mgr_apply_group_dm_out1_delay(uint32_t write_group,
static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
uint32_t delay)
{
- scc_mgr_set_dqs_out1_delay(write_group, delay);
+ scc_mgr_set_dqs_out1_delay(delay);
scc_mgr_load_dqs_io();
scc_mgr_set_oct_out1_delay(write_group, delay);
@@ -709,7 +706,7 @@ static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group,
write_group, group_bgn, delay, new_delay,
IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
new_delay - IO_IO_OUT2_DELAY_MAX);
- scc_mgr_set_dqs_out1_delay(write_group, new_delay -
+ scc_mgr_set_dqs_out1_delay(new_delay -
IO_IO_OUT2_DELAY_MAX);
new_delay = IO_IO_OUT2_DELAY_MAX;
}
@@ -1805,8 +1802,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
- for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS;
- i++, p++, d += delay_step) {
+ for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++, d += delay_step) {
debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_\
vfifo_find_dqs_", __func__, __LINE__);
debug_cond(DLEVEL == 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
@@ -1932,7 +1928,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
}
/* Reset DQ delay chains to 0 */
- scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, 0);
+ scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
sticky_bit_chk = 0;
for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
@@ -2751,7 +2747,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
}
/* Reset DQ delay chains to 0 */
- scc_mgr_apply_group_dq_out1_delay(write_group, 0);
+ scc_mgr_apply_group_dq_out1_delay(0);
sticky_bit_chk = 0;
for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
@@ -2975,7 +2971,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
/* Search for the/part of the window with DM shift */
for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
- scc_mgr_apply_group_dm_out1_delay(write_group, d);
+ scc_mgr_apply_group_dm_out1_delay(d);
writel(0, &sdr_scc_mgr->update);
if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
@@ -3008,7 +3004,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
/* Reset DM delay chains to 0 */
- scc_mgr_apply_group_dm_out1_delay(write_group, 0);
+ scc_mgr_apply_group_dm_out1_delay(0);
/*
* Check to see if the current window nudges up aganist 0 delay.
@@ -3090,7 +3086,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
else
dm_margin = left_edge[0] - mid;
- scc_mgr_apply_group_dm_out1_delay(write_group, mid);
+ scc_mgr_apply_group_dm_out1_delay(mid);
writel(0, &sdr_scc_mgr->update);
debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 068/172] ddr: altera: Clean up scc_mgr_set_hhp_extras()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (66 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 067/172] ddr: altera: Clean up scc_mgr_*_delay() args Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 069/172] ddr: altera: Extract scc_mgr_set_hhp_extras() Marek Vasut
` (105 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Minor coding style cleanup for this function. Furthermore, move
ad-hoc debug_cond() calls from the only location from where this
function is invoked into this actual function.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 37 ++++++++++++++++++++++---------------
1 file changed, 22 insertions(+), 15 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 066d7f6..baa6868 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -453,21 +453,33 @@ static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
}
+/**
+ * scc_mgr_set_hhp_extras() - Set HHP extras.
+ *
+ * Load the fixed setting in the SCC manager HHP extras.
+ */
static void scc_mgr_set_hhp_extras(void)
{
/*
* Load the fixed setting in the SCC manager
- * bits: 0:0 = 1'b1 - dqs bypass
- * bits: 1:1 = 1'b1 - dq bypass
- * bits: 4:2 = 3'b001 - rfifo_mode
- * bits: 6:5 = 2'b01 - rfifo clock_select
- * bits: 7:7 = 1'b0 - separate gating from ungating setting
- * bits: 8:8 = 1'b0 - separate OE from Output delay setting
+ * bits: 0:0 = 1'b1 - DQS bypass
+ * bits: 1:1 = 1'b1 - DQ bypass
+ * bits: 4:2 = 3'b001 - rfifo_mode
+ * bits: 6:5 = 2'b01 - rfifo clock_select
+ * bits: 7:7 = 1'b0 - separate gating from ungating setting
+ * bits: 8:8 = 1'b0 - separate OE from Output delay setting
*/
- uint32_t value = (0<<8) | (0<<7) | (1<<5) | (1<<2) | (1<<1) | (1<<0);
- uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_HHP_GLOBALS_OFFSET;
+ const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
+ (1 << 2) | (1 << 1) | (1 << 0);
+ const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
+ SCC_MGR_HHP_GLOBALS_OFFSET |
+ SCC_MGR_HHP_EXTRAS_OFFSET;
- writel(value, addr + SCC_MGR_HHP_EXTRAS_OFFSET);
+ debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
+ __func__, __LINE__);
+ writel(value, addr);
+ debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
+ __func__, __LINE__);
}
/*
@@ -516,13 +528,8 @@ static void scc_mgr_zero_all(void)
static void scc_set_bypass_mode(const u32 write_group)
{
/* Only needed once to set all groups, pins, DQ, DQS, DM. */
- if (write_group == 0) {
- debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n", __func__,
- __LINE__);
+ if (write_group == 0)
scc_mgr_set_hhp_extras();
- debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
- __func__, __LINE__);
- }
/* Multicast to all DQ enables. */
writel(0xff, &sdr_scc_mgr->dq_ena);
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 069/172] ddr: altera: Extract scc_mgr_set_hhp_extras()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (67 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 068/172] ddr: altera: Clean up scc_mgr_set_hhp_extras() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 070/172] ddr: altera: Clean up scc_mgr_zero_all() Marek Vasut
` (104 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Move scc_mgr_set_hhp_extras() out of scc_set_bypass_mode() as it
has nothing to do in there. Instead, invoke it from mem_calibrate()
just before invoking scc_set_bypass_mode().
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index baa6868..8020651 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -527,10 +527,6 @@ static void scc_mgr_zero_all(void)
*/
static void scc_set_bypass_mode(const u32 write_group)
{
- /* Only needed once to set all groups, pins, DQ, DQS, DM. */
- if (write_group == 0)
- scc_mgr_set_hhp_extras();
-
/* Multicast to all DQ enables. */
writel(0xff, &sdr_scc_mgr->dq_ena);
writel(0xff, &sdr_scc_mgr->dm_ena);
@@ -3332,6 +3328,10 @@ static uint32_t mem_calibrate(void)
for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
SCC_MGR_GROUP_COUNTER_OFFSET);
+ /* Only needed once to set all groups, pins, DQ, DQS, DM. */
+ if (i == 0)
+ scc_mgr_set_hhp_extras();
+
scc_set_bypass_mode(i);
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 070/172] ddr: altera: Clean up scc_mgr_zero_all()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (68 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 069/172] ddr: altera: Extract scc_mgr_set_hhp_extras() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 071/172] ddr: altera: Clean up scc_mgr_zero_group() Marek Vasut
` (103 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Add kerneldoc, clean up datatypes and fix minor indentation issue.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 8020651..7287d61 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -482,20 +482,21 @@ static void scc_mgr_set_hhp_extras(void)
__func__, __LINE__);
}
-/*
- * USER Zero all DQS config
- * TODO: maybe rename to scc_mgr_zero_dqs_config (or something)
+/**
+ * scc_mgr_zero_all() - Zero all DQS config
+ *
+ * Zero all DQS config.
*/
static void scc_mgr_zero_all(void)
{
- uint32_t i, r;
+ int i, r;
/*
* USER Zero all DQS config settings, across all groups and all
* shadow registers
*/
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
- NUM_RANKS_PER_SHADOW_REG) {
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ r += NUM_RANKS_PER_SHADOW_REG) {
for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
/*
* The phases actually don't exist on a per-rank basis,
@@ -509,12 +510,12 @@ static void scc_mgr_zero_all(void)
for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
scc_mgr_set_dqdqs_output_phase(i, 0);
- /* av/cv don't have out2 */
+ /* Arria V/Cyclone V don't have out2. */
scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
}
}
- /* multicast to all DQS group enables */
+ /* Multicast to all DQS group enables. */
writel(0xff, &sdr_scc_mgr->dqs_ena);
writel(0, &sdr_scc_mgr->update);
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 071/172] ddr: altera: Clean up scc_mgr_zero_group()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (69 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 070/172] ddr: altera: Clean up scc_mgr_zero_all() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 072/172] FIXME: ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add() cleanup part 1 Marek Vasut
` (102 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
First, zap unused argument of the function. Next, clean up
the data types, constify where applicable, clean up comments
and add kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 39 +++++++++++++++++++++------------------
1 file changed, 21 insertions(+), 18 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 7287d61..3a95a53 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -565,43 +565,47 @@ static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
writel(base + i, &sdr_scc_mgr->dqs_ena);
}
-static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
- int32_t out_only)
+/**
+ * scc_mgr_zero_group() - Zero all configs for a group
+ *
+ * Zero DQ, DM, DQS and OCT configs for a group.
+ */
+static void scc_mgr_zero_group(const u32 write_group, const int out_only)
{
- uint32_t i, r;
+ int i, r;
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
- NUM_RANKS_PER_SHADOW_REG) {
- /* Zero all DQ config settings */
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ r += NUM_RANKS_PER_SHADOW_REG) {
+ /* Zero all DQ config settings. */
for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
scc_mgr_set_dq_out1_delay(i, 0);
if (!out_only)
scc_mgr_set_dq_in_delay(i, 0);
}
- /* multicast to all DQ enables */
+ /* Multicast to all DQ enables. */
writel(0xff, &sdr_scc_mgr->dq_ena);
- /* Zero all DM config settings */
- for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
+ /* Zero all DM config settings. */
+ for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
scc_mgr_set_dm_out1_delay(i, 0);
- }
- /* multicast to all DM enables */
+ /* Multicast to all DM enables. */
writel(0xff, &sdr_scc_mgr->dm_ena);
- /* zero all DQS io settings */
+ /* Zero all DQS IO settings. */
if (!out_only)
scc_mgr_set_dqs_io_in_delay(0);
- /* av/cv don't have out2 */
+
+ /* Arria V/Cyclone V don't have out2. */
scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
scc_mgr_load_dqs_for_write_group(write_group);
- /* multicast to all DQS IO enables (only 1) */
+ /* Multicast to all DQS IO enables (only 1 in total). */
writel(0, &sdr_scc_mgr->dqs_io_ena);
- /* hit update to zero everything */
+ /* Hit update to zero everything. */
writel(0, &sdr_scc_mgr->update);
}
}
@@ -2344,7 +2348,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
* first case).
*/
if (d > 2)
- scc_mgr_zero_group(write_group, write_test_bgn, 1);
+ scc_mgr_zero_group(write_group, 1);
return 1;
}
@@ -3368,8 +3372,7 @@ static uint32_t mem_calibrate(void)
writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
SCC_MGR_GROUP_COUNTER_OFFSET);
- scc_mgr_zero_group(write_group, write_test_bgn,
- 0);
+ scc_mgr_zero_group(write_group, 0);
for (read_group = write_group *
RW_MGR_MEM_IF_READ_DQS_WIDTH /
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 072/172] FIXME: ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add() cleanup part 1
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (70 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 071/172] ddr: altera: Clean up scc_mgr_zero_group() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 073/172] ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add() cleanup part 2 Marek Vasut
` (101 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Apparently, in case of the DQ and DM, the value if the new_delay variable
is calculated, but the value is not used. Zap the entire code which does
calculate the value.
It is not clear to me whether or not the code is doing the right thing
in the first place. Right now, it calls scc_mgr_load_dq() and
scc_mgr_load_dm() respectively, but I suspect it might need to call
scc_mgr_apply_group_dq_out1_delay() and scc_mgr_apply_group_dm_out1_delay()
instead. This is something Altera must investigate.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 44 +++++++++---------------------------------
1 file changed, 9 insertions(+), 35 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 3a95a53..11213c6 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -664,45 +664,19 @@ static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
}
/* apply a delay to the entire output side: DQ, DM, DQS, OCT */
-static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group,
- uint32_t group_bgn,
- uint32_t delay)
-{
- uint32_t i, p, new_delay;
-
- /* dq shift */
- for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
- new_delay = READ_SCC_DQ_OUT2_DELAY;
- new_delay += delay;
-
- if (new_delay > IO_IO_OUT2_DELAY_MAX) {
- debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQ[%u,%u]:\
- %u > %lu => %lu", __func__, __LINE__,
- write_group, group_bgn, delay, i, p, new_delay,
- (long unsigned int)IO_IO_OUT2_DELAY_MAX,
- (long unsigned int)IO_IO_OUT2_DELAY_MAX);
- new_delay = IO_IO_OUT2_DELAY_MAX;
- }
+static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
+ const u32 group_bgn,
+ const u32 delay)
+{
+ u32 i, new_delay;
+ /* DQ shift */
+ for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
scc_mgr_load_dq(i);
- }
-
- /* dm shift */
- for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
- new_delay = READ_SCC_DM_IO_OUT2_DELAY;
- new_delay += delay;
-
- if (new_delay > IO_IO_OUT2_DELAY_MAX) {
- debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DM[%u]:\
- %u > %lu => %lu\n", __func__, __LINE__,
- write_group, group_bgn, delay, i, new_delay,
- (long unsigned int)IO_IO_OUT2_DELAY_MAX,
- (long unsigned int)IO_IO_OUT2_DELAY_MAX);
- new_delay = IO_IO_OUT2_DELAY_MAX;
- }
+ /* DM shift */
+ for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
scc_mgr_load_dm(i);
- }
/* dqs shift */
new_delay = READ_SCC_DQS_IO_OUT2_DELAY;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 073/172] ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add() cleanup part 2
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (71 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 072/172] FIXME: ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add() cleanup part 1 Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 074/172] ddr: altera: Clean up scc_mgr_apply_group_all_out_delay_add_all_ranks() Marek Vasut
` (100 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Clean the DQS and OCT parts of the function, clean up the chopped
formatting strings in debug_cond() and slightly improve the code.
Zap group_bgn argument as it is used only in debug messages. Document
the function using kerneldoc. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 50 ++++++++++++++++++++----------------------
1 file changed, 24 insertions(+), 26 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 11213c6..3b26726 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -663,9 +663,14 @@ static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
scc_mgr_load_dqs_for_write_group(write_group);
}
-/* apply a delay to the entire output side: DQ, DM, DQS, OCT */
+/**
+ * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
+ * @write_group: Write group
+ * @delay: Delay value
+ *
+ * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
+ */
static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
- const u32 group_bgn,
const u32 delay)
{
u32 i, new_delay;
@@ -678,36 +683,30 @@ static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
scc_mgr_load_dm(i);
- /* dqs shift */
- new_delay = READ_SCC_DQS_IO_OUT2_DELAY;
- new_delay += delay;
-
+ /* DQS shift */
+ new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
if (new_delay > IO_IO_OUT2_DELAY_MAX) {
- debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQS: %u > %d => %d;"
- " adding %u to OUT1\n", __func__, __LINE__,
- write_group, group_bgn, delay, new_delay,
- IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
+ debug_cond(DLEVEL == 1,
+ "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
+ __func__, __LINE__, write_group, delay, new_delay,
+ IO_IO_OUT2_DELAY_MAX,
new_delay - IO_IO_OUT2_DELAY_MAX);
- scc_mgr_set_dqs_out1_delay(new_delay -
- IO_IO_OUT2_DELAY_MAX);
- new_delay = IO_IO_OUT2_DELAY_MAX;
+ new_delay -= IO_IO_OUT2_DELAY_MAX;
+ scc_mgr_set_dqs_out1_delay(new_delay);
}
scc_mgr_load_dqs_io();
- /* oct shift */
- new_delay = READ_SCC_OCT_OUT2_DELAY;
- new_delay += delay;
-
+ /* OCT shift */
+ new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
if (new_delay > IO_IO_OUT2_DELAY_MAX) {
- debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQS: %u > %d => %d;"
- " adding %u to OUT1\n", __func__, __LINE__,
- write_group, group_bgn, delay, new_delay,
- IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
+ debug_cond(DLEVEL == 1,
+ "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
+ __func__, __LINE__, write_group, delay,
+ new_delay, IO_IO_OUT2_DELAY_MAX,
new_delay - IO_IO_OUT2_DELAY_MAX);
- scc_mgr_set_oct_out1_delay(write_group, new_delay -
- IO_IO_OUT2_DELAY_MAX);
- new_delay = IO_IO_OUT2_DELAY_MAX;
+ new_delay -= IO_IO_OUT2_DELAY_MAX;
+ scc_mgr_set_oct_out1_delay(write_group, new_delay);
}
scc_mgr_load_dqs_for_write_group(write_group);
@@ -724,8 +723,7 @@ static void scc_mgr_apply_group_all_out_delay_add_all_ranks(
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
- scc_mgr_apply_group_all_out_delay_add(write_group,
- group_bgn, delay);
+ scc_mgr_apply_group_all_out_delay_add(write_group, delay);
writel(0, &sdr_scc_mgr->update);
}
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 074/172] ddr: altera: Clean up scc_mgr_apply_group_all_out_delay_add_all_ranks()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (72 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 073/172] ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add() cleanup part 2 Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 075/172] ddr: altera: Factor out instruction loading from rw_mgr_mem_initialize() Marek Vasut
` (99 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Zap unused group_bgn parameter, fix and constify data types.
Document in kerneldoc. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 22 +++++++++++++---------
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 3b26726..b2119a6 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -712,17 +712,21 @@ static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
scc_mgr_load_dqs_for_write_group(write_group);
}
-/*
- * USER apply a delay to the entire output side (DQ, DM, DQS, OCT)
- * and to all ranks
+/**
+ * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
+ * @write_group: Write group
+ * @delay: Delay value
+ *
+ * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
*/
-static void scc_mgr_apply_group_all_out_delay_add_all_ranks(
- uint32_t write_group, uint32_t group_bgn, uint32_t delay)
+static void
+scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
+ const u32 delay)
{
- uint32_t r;
+ int r;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
- r += NUM_RANKS_PER_SHADOW_REG) {
+ r += NUM_RANKS_PER_SHADOW_REG) {
scc_mgr_apply_group_all_out_delay_add(write_group, delay);
writel(0, &sdr_scc_mgr->update);
}
@@ -2240,8 +2244,8 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
* calibrated output side yet.
*/
if (d > 0) {
- scc_mgr_apply_group_all_out_delay_add_all_ranks
- (write_group, write_test_bgn, d);
+ scc_mgr_apply_group_all_out_delay_add_all_ranks(
+ write_group, d);
}
for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 075/172] ddr: altera: Factor out instruction loading from rw_mgr_mem_initialize()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (73 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 074/172] ddr: altera: Clean up scc_mgr_apply_group_all_out_delay_add_all_ranks() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 076/172] ddr: altera: Factor out common code Marek Vasut
` (98 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Pull the duplicate code out into a separate function.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 74 +++++++++++++++++++++---------------------
1 file changed, 37 insertions(+), 37 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index b2119a6..2d3f446 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -840,6 +840,37 @@ static void delay_for_n_mem_clocks(const uint32_t clocks)
debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
}
+/**
+ * rw_mgr_mem_init_load_regs() - Load instruction registers
+ * @cntr0: Counter 0 value
+ * @cntr1: Counter 1 value
+ * @cntr2: Counter 2 value
+ * @jump: Jump instruction value
+ *
+ * Load instruction registers.
+ */
+static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
+{
+ uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+
+ /* Load counters */
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
+ &sdr_rw_load_mgr_regs->load_cntr0);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
+ &sdr_rw_load_mgr_regs->load_cntr1);
+ writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
+ &sdr_rw_load_mgr_regs->load_cntr2);
+
+ /* Load jump address */
+ writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+ writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+
+ /* Execute count instruction */
+ writel(jump, grpaddr);
+}
+
static void rw_mgr_mem_initialize(void)
{
uint32_t r;
@@ -875,25 +906,9 @@ static void rw_mgr_mem_initialize(void)
* One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
* b = 6A
*/
-
- /* Load counters */
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL),
- &sdr_rw_load_mgr_regs->load_cntr0);
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL),
- &sdr_rw_load_mgr_regs->load_cntr1);
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL),
- &sdr_rw_load_mgr_regs->load_cntr2);
-
- /* Load jump address */
- writel(RW_MGR_INIT_RESET_0_CKE_0,
- &sdr_rw_load_jump_mgr_regs->load_jump_add0);
- writel(RW_MGR_INIT_RESET_0_CKE_0,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
- writel(RW_MGR_INIT_RESET_0_CKE_0,
- &sdr_rw_load_jump_mgr_regs->load_jump_add2);
-
- /* Execute count instruction */
- writel(RW_MGR_INIT_RESET_0_CKE_0, grpaddr);
+ rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
+ SEQ_TINIT_CNTR2_VAL,
+ RW_MGR_INIT_RESET_0_CKE_0);
/* indicate that memory is stable */
writel(1, &phy_mgr_cfg->reset_mem_stbl);
@@ -912,24 +927,9 @@ static void rw_mgr_mem_initialize(void)
* One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
* b = FF
*/
-
- /* Load counters */
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR0_VAL),
- &sdr_rw_load_mgr_regs->load_cntr0);
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR1_VAL),
- &sdr_rw_load_mgr_regs->load_cntr1);
- writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR2_VAL),
- &sdr_rw_load_mgr_regs->load_cntr2);
-
- /* Load jump address */
- writel(RW_MGR_INIT_RESET_1_CKE_0,
- &sdr_rw_load_jump_mgr_regs->load_jump_add0);
- writel(RW_MGR_INIT_RESET_1_CKE_0,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
- writel(RW_MGR_INIT_RESET_1_CKE_0,
- &sdr_rw_load_jump_mgr_regs->load_jump_add2);
-
- writel(RW_MGR_INIT_RESET_1_CKE_0, grpaddr);
+ rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
+ SEQ_TRESET_CNTR2_VAL,
+ RW_MGR_INIT_RESET_1_CKE_0);
/* bring up clock enable */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 076/172] ddr: altera: Factor out common code
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (74 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 075/172] ddr: altera: Factor out instruction loading from rw_mgr_mem_initialize() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 077/172] ddr: altera: Minor clean up of set_jump_as_return() Marek Vasut
` (97 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Factor out almost common code from rw_mgr_mem_handoff() and
rw_mgr_mem_initialize() into separate rw_mgr_mem_load_user().
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 175 ++++++++++++++++++-----------------------
1 file changed, 76 insertions(+), 99 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 2d3f446..35ecc67 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -871,12 +871,76 @@ static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
writel(jump, grpaddr);
}
-static void rw_mgr_mem_initialize(void)
+/**
+ * rw_mgr_mem_load_user() - Load user calibration values
+ * @fin1: Final instruction 1
+ * @fin2: Final instruction 2
+ * @precharge: If 1, precharge the banks at the end
+ *
+ * Load user calibration values and optionally precharge the banks.
+ */
+static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
+ const int precharge)
{
- uint32_t r;
- uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
- RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+ u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+ u32 r;
+
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
+ if (param->skip_ranks[r]) {
+ /* request to skip the rank */
+ continue;
+ }
+
+ /* set rank */
+ set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
+
+ /* precharge all banks ... */
+ if (precharge)
+ writel(RW_MGR_PRECHARGE_ALL, grpaddr);
+ /*
+ * USER Use Mirror-ed commands for odd ranks if address
+ * mirrorring is on
+ */
+ if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
+ set_jump_as_return();
+ writel(RW_MGR_MRS2_MIRR, grpaddr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(RW_MGR_MRS3_MIRR, grpaddr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(RW_MGR_MRS1_MIRR, grpaddr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(fin1, grpaddr);
+ } else {
+ set_jump_as_return();
+ writel(RW_MGR_MRS2, grpaddr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(RW_MGR_MRS3, grpaddr);
+ delay_for_n_mem_clocks(4);
+ set_jump_as_return();
+ writel(RW_MGR_MRS1, grpaddr);
+ set_jump_as_return();
+ writel(fin2, grpaddr);
+ }
+
+ if (precharge)
+ continue;
+
+ set_jump_as_return();
+ writel(RW_MGR_ZQCL, grpaddr);
+
+ /* tZQinit = tDLLK = 512 ck cycles */
+ delay_for_n_mem_clocks(512);
+ }
+}
+
+static void rw_mgr_mem_initialize(void)
+{
debug("%s:%d\n", __func__, __LINE__);
/* The reset / cke part of initialization is broadcasted to all ranks */
@@ -936,49 +1000,8 @@ static void rw_mgr_mem_initialize(void)
/* tXRP < 250 ck cycles */
delay_for_n_mem_clocks(250);
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
- if (param->skip_ranks[r]) {
- /* request to skip the rank */
- continue;
- }
-
- /* set rank */
- set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
-
- /*
- * USER Use Mirror-ed commands for odd ranks if address
- * mirrorring is on
- */
- if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
- set_jump_as_return();
- writel(RW_MGR_MRS2_MIRR, grpaddr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS3_MIRR, grpaddr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS1_MIRR, grpaddr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS0_DLL_RESET_MIRR, grpaddr);
- } else {
- set_jump_as_return();
- writel(RW_MGR_MRS2, grpaddr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS3, grpaddr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS1, grpaddr);
- set_jump_as_return();
- writel(RW_MGR_MRS0_DLL_RESET, grpaddr);
- }
- set_jump_as_return();
- writel(RW_MGR_ZQCL, grpaddr);
-
- /* tZQinit = tDLLK = 512 ck cycles */
- delay_for_n_mem_clocks(512);
- }
+ rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
+ 0);
}
/*
@@ -987,58 +1010,12 @@ static void rw_mgr_mem_initialize(void)
*/
static void rw_mgr_mem_handoff(void)
{
- uint32_t r;
- uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
- RW_MGR_RUN_SINGLE_GROUP_OFFSET;
-
- debug("%s:%d\n", __func__, __LINE__);
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
- if (param->skip_ranks[r])
- /* request to skip the rank */
- continue;
- /* set rank */
- set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
-
- /* precharge all banks ... */
- writel(RW_MGR_PRECHARGE_ALL, grpaddr);
-
- /* load up MR settings specified by user */
-
- /*
- * Use Mirror-ed commands for odd ranks if address
- * mirrorring is on
- */
- if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
- set_jump_as_return();
- writel(RW_MGR_MRS2_MIRR, grpaddr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS3_MIRR, grpaddr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS1_MIRR, grpaddr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS0_USER_MIRR, grpaddr);
- } else {
- set_jump_as_return();
- writel(RW_MGR_MRS2, grpaddr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS3, grpaddr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS1, grpaddr);
- delay_for_n_mem_clocks(4);
- set_jump_as_return();
- writel(RW_MGR_MRS0_USER, grpaddr);
- }
- /*
- * USER need to wait tMOD (12CK or 15ns) time before issuing
- * other commands, but we will have plenty of NIOS cycles before
- * actual handoff so its okay.
- */
- }
+ rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
+ /*
+ * USER need to wait tMOD (12CK or 15ns) time before issuing
+ * other commands, but we will have plenty of NIOS cycles before
+ * actual handoff so its okay.
+ */
}
/*
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 077/172] ddr: altera: Minor clean up of set_jump_as_return()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (75 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 076/172] ddr: altera: Factor out common code Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 078/172] ddr: altera: Fix ad-hoc iterative division implementation Marek Vasut
` (96 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Add kerneldoc and do a minor comment cleanup.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 35ecc67..8c56f02 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -732,14 +732,18 @@ scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
}
}
-/* optimization used to recover some slots in ddr3 inst_rom */
-/* could be applied to other protocols if we wanted to */
+/**
+ * set_jump_as_return() - Return instruction optimization
+ *
+ * Optimization used to recover some slots in ddr3 inst_rom could be
+ * applied to other protocols if we wanted to
+ */
static void set_jump_as_return(void)
{
/*
- * to save space, we replace return with jump to special shared
+ * To save space, we replace return with jump to special shared
* RETURN instruction so we set the counter to large value so that
- * we always jump
+ * we always jump.
*/
writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 078/172] ddr: altera: Fix ad-hoc iterative division implementation
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (76 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 077/172] ddr: altera: Minor clean up of set_jump_as_return() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 079/172] ddr: altera: Rework initialize_tracking() Marek Vasut
` (95 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Contemporary CPUs can perform division just fine, use this
functionality and zap another implementation of iterative
division :-)
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 8c56f02..28e32ff 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2185,7 +2185,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
{
uint32_t p, d, rank_bgn, sr;
uint32_t dtaps_per_ptap;
- uint32_t tmp_delay;
uint32_t bit_chk;
uint32_t grp_calibrated;
uint32_t write_group, write_test_bgn;
@@ -2200,14 +2199,8 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
write_test_bgn = test_bgn;
/* USER Determine number of delay taps for each phase tap */
- dtaps_per_ptap = 0;
- tmp_delay = 0;
- while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
- dtaps_per_ptap++;
- tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
- }
- dtaps_per_ptap--;
- tmp_delay = 0;
+ dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
+ IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
/* update info for sims */
reg_file_set_group(read_group);
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 079/172] ddr: altera: Rework initialize_tracking()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (77 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 078/172] ddr: altera: Fix ad-hoc iterative division implementation Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 080/172] ddr: altera: Init my_param and my_gbl Marek Vasut
` (94 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Clean the function up by getting rid of all the insane XOR-leftshift
combos when assembling register values. While at it, remove all the
ad-hoc variables necessary for this XOR-leftshift voodoo. Finally,
get rid of the iterative division implementation of two constants
and replace it with a DIV_ROUND_UP() macro :-)
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 88 +++++++++++++++++-------------------------
1 file changed, 35 insertions(+), 53 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 28e32ff..aceb6a0 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3612,65 +3612,47 @@ static void initialize_hps_phy(void)
writel(reg, &sdr_ctrl->phy_ctrl2);
}
+/**
+ * initialize_tracking() - Initialize tracking
+ *
+ * Initialize the register file with usable initial data.
+ */
static void initialize_tracking(void)
{
- uint32_t concatenated_longidle = 0x0;
- uint32_t concatenated_delays = 0x0;
- uint32_t concatenated_rw_addr = 0x0;
- uint32_t concatenated_refresh = 0x0;
- uint32_t trk_sample_count = 7500;
- uint32_t dtaps_per_ptap;
- uint32_t tmp_delay;
+ /*
+ * Initialize the register file with the correct data.
+ * Compute usable version of value in case we skip full
+ * computation later.
+ */
+ writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
+ &sdr_reg_file->dtaps_per_ptap);
+
+ /* trk_sample_count */
+ writel(7500, &sdr_reg_file->trk_sample_count);
+
+ /* longidle outer loop [15:0] */
+ writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
/*
- * compute usable version of value in case we skip full
- * computation later
+ * longidle sample count [31:24]
+ * trfc, worst case of 933Mhz 4Gb [23:16]
+ * trcd, worst case [15:8]
+ * vfifo wait [7:0]
*/
- dtaps_per_ptap = 0;
- tmp_delay = 0;
- while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
- dtaps_per_ptap++;
- tmp_delay += IO_DELAY_PER_DCHAIN_TAP;
- }
- dtaps_per_ptap--;
-
- concatenated_longidle = concatenated_longidle ^ 10;
- /*longidle outer loop */
- concatenated_longidle = concatenated_longidle << 16;
- concatenated_longidle = concatenated_longidle ^ 100;
- /*longidle sample count */
- concatenated_delays = concatenated_delays ^ 243;
- /* trfc, worst case of 933Mhz 4Gb */
- concatenated_delays = concatenated_delays << 8;
- concatenated_delays = concatenated_delays ^ 14;
- /* trcd, worst case */
- concatenated_delays = concatenated_delays << 8;
- concatenated_delays = concatenated_delays ^ 10;
- /* vfifo wait */
- concatenated_delays = concatenated_delays << 8;
- concatenated_delays = concatenated_delays ^ 4;
- /* mux delay */
-
- concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_IDLE;
- concatenated_rw_addr = concatenated_rw_addr << 8;
- concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_ACTIVATE_1;
- concatenated_rw_addr = concatenated_rw_addr << 8;
- concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_SGLE_READ;
- concatenated_rw_addr = concatenated_rw_addr << 8;
- concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_PRECHARGE_ALL;
-
- concatenated_refresh = concatenated_refresh ^ RW_MGR_REFRESH_ALL;
- concatenated_refresh = concatenated_refresh << 24;
- concatenated_refresh = concatenated_refresh ^ 1000; /* trefi */
+ writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
+ &sdr_reg_file->delays);
- /* Initialize the register file with the correct data */
- writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
- writel(trk_sample_count, &sdr_reg_file->trk_sample_count);
- writel(concatenated_longidle, &sdr_reg_file->trk_longidle);
- writel(concatenated_delays, &sdr_reg_file->delays);
- writel(concatenated_rw_addr, &sdr_reg_file->trk_rw_mgr_addr);
- writel(RW_MGR_MEM_IF_READ_DQS_WIDTH, &sdr_reg_file->trk_read_dqs_width);
- writel(concatenated_refresh, &sdr_reg_file->trk_rfsh);
+ /* mux delay */
+ writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
+ (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
+ &sdr_reg_file->trk_rw_mgr_addr);
+
+ writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
+ &sdr_reg_file->trk_read_dqs_width);
+
+ /* trefi [7:0] */
+ writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
+ &sdr_reg_file->trk_rfsh);
}
int sdram_calibration_full(void)
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 080/172] ddr: altera: Init my_param and my_gbl
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (78 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 079/172] ddr: altera: Rework initialize_tracking() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 081/172] ddr: altera: Rename initialize() to phy_mgr_initialize() Marek Vasut
` (93 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Init both structures with zeroes and zap all those zeroing shenanigans
further down in the sdram_calibration_full().
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 13 +++----------
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index aceb6a0..2aa93c1 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3660,13 +3660,13 @@ int sdram_calibration_full(void)
struct param_type my_param;
struct gbl_type my_gbl;
uint32_t pass;
- uint32_t i;
+
+ memset(&my_param, 0, sizeof(my_param));
+ memset(&my_gbl, 0, sizeof(my_gbl));
param = &my_param;
gbl = &my_gbl;
- /* Initialize the debug mode flags */
- gbl->phy_debug_mode_flags = 0;
/* Set the calibration enabled by default */
gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
/*
@@ -3686,13 +3686,6 @@ int sdram_calibration_full(void)
initialize_tracking();
- /* USER Enable all ranks, groups */
- for (i = 0; i < RW_MGR_MEM_NUMBER_OF_RANKS; i++)
- param->skip_ranks[i] = 0;
- for (i = 0; i < NUM_SHADOW_REGS; ++i)
- param->skip_shadow_regs[i] = 0;
- param->skip_groups = 0;
-
printf("%s: Preparing to start memory calibration\n", __FILE__);
debug("%s:%d\n", __func__, __LINE__);
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 081/172] ddr: altera: Rename initialize() to phy_mgr_initialize()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (79 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 080/172] ddr: altera: Init my_param and my_gbl Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 082/172] ddr: altera: Clean up run_mem_calibrate() Marek Vasut
` (92 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Just perform the rename to make the name more descriptive,
no functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 2aa93c1..885bdd8 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -113,7 +113,7 @@ static void reg_file_set_sub_stage(u8 set_sub_stage)
clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
}
-static void initialize(void)
+static void phy_mgr_initialize(void)
{
debug("%s:%d\n", __func__, __LINE__);
/* USER calibration has control over path to memory */
@@ -3463,7 +3463,7 @@ static uint32_t run_mem_calibrate(void)
writel(ctrlcfg & 0xFFBFFFFF, &sdr_ctrl->ctrl_cfg);
- initialize();
+ phy_mgr_initialize();
rw_mgr_mem_initialize();
pass = mem_calibrate();
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 082/172] ddr: altera: Clean up run_mem_calibrate()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (80 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 081/172] ddr: altera: Rename initialize() to phy_mgr_initialize() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 083/172] ddr: altera: Clean up phy_mgr_initialize() Marek Vasut
` (91 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Clean the function up slightly by using clrsetbits_le32() to flip
bits in registers instead of cryptic bitmasks. Zap condition checking
for PHY_DEBUG_IN_DEBUG_MODE flag, which is never set. Split the
calibration report into separate debug_mem_calibrate() function.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 56 +++++++++++++++++++++++++-----------------
1 file changed, 34 insertions(+), 22 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 885bdd8..13551db 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3448,44 +3448,57 @@ static uint32_t mem_calibrate(void)
return 1;
}
-static uint32_t run_mem_calibrate(void)
+/**
+ * run_mem_calibrate() - Perform memory calibration
+ *
+ * This function triggers the entire memory calibration procedure.
+ */
+static int run_mem_calibrate(void)
{
- uint32_t pass;
- uint32_t debug_info;
+ int pass;
debug("%s:%d\n", __func__, __LINE__);
/* Reset pass/fail status shown on afi_cal_success/fail */
writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
- /* stop tracking manger */
- uint32_t ctrlcfg = readl(&sdr_ctrl->ctrl_cfg);
-
- writel(ctrlcfg & 0xFFBFFFFF, &sdr_ctrl->ctrl_cfg);
+ /* Stop tracking manager. */
+ clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
phy_mgr_initialize();
rw_mgr_mem_initialize();
+ /* Perform the actual memory calibration. */
pass = mem_calibrate();
mem_precharge_and_activate();
writel(0, &phy_mgr_cmd->fifo_reset);
+ /* Handoff. */
+ rw_mgr_mem_handoff();
/*
- * Handoff:
- * Don't return control of the PHY back to AFI when in debug mode.
+ * In Hard PHY this is a 2-bit control:
+ * 0: AFI Mux Select
+ * 1: DDIO Mux Select
*/
- if ((gbl->phy_debug_mode_flags & PHY_DEBUG_IN_DEBUG_MODE) == 0) {
- rw_mgr_mem_handoff();
- /*
- * In Hard PHY this is a 2-bit control:
- * 0: AFI Mux Select
- * 1: DDIO Mux Select
- */
- writel(0x2, &phy_mgr_cfg->mux_sel);
- }
+ writel(0x2, &phy_mgr_cfg->mux_sel);
- writel(ctrlcfg, &sdr_ctrl->ctrl_cfg);
+ /* Start tracking manager. */
+ setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
+
+ return pass;
+}
+
+/**
+ * debug_mem_calibrate() - Report result of memory calibration
+ * @pass: Value indicating whether calibration passed or failed
+ *
+ * This function reports the results of the memory calibration
+ * and writes debug information into the register file.
+ */
+static void debug_mem_calibrate(int pass)
+{
+ uint32_t debug_info;
if (pass) {
printf("%s: CALIBRATION PASSED\n", __FILE__);
@@ -3524,7 +3537,7 @@ static uint32_t run_mem_calibrate(void)
writel(debug_info, &sdr_reg_file->failing_stage);
}
- return pass;
+ printf("%s: Calibration complete\n", __FILE__);
}
/**
@@ -3732,7 +3745,6 @@ int sdram_calibration_full(void)
skip_delay_mask = 0x0;
pass = run_mem_calibrate();
-
- printf("%s: Calibration complete\n", __FILE__);
+ debug_mem_calibrate(pass);
return pass;
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 083/172] ddr: altera: Clean up phy_mgr_initialize()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (81 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 082/172] ddr: altera: Clean up run_mem_calibrate() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 084/172] ddr: altera: Clean up mem_config() Marek Vasut
` (90 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Zap the cryptic casts and rework the code into a slightly more
readable form. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 37 +++++++++++++++++++++----------------
1 file changed, 21 insertions(+), 16 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 13551db..25b7b14 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -113,10 +113,17 @@ static void reg_file_set_sub_stage(u8 set_sub_stage)
clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
}
+/**
+ * phy_mgr_initialize() - Initialize PHY Manager
+ *
+ * Initialize PHY Manager.
+ */
static void phy_mgr_initialize(void)
{
+ u32 ratio;
+
debug("%s:%d\n", __func__, __LINE__);
- /* USER calibration has control over path to memory */
+ /* Calibration has control over path to memory */
/*
* In Hard PHY this is a 2-bit control:
* 0: AFI Mux Select
@@ -132,21 +139,19 @@ static void phy_mgr_initialize(void)
writel(0, &phy_mgr_cfg->cal_debug_info);
- if ((dyn_calib_steps & CALIB_SKIP_ALL) != CALIB_SKIP_ALL) {
- param->read_correct_mask_vg = ((uint32_t)1 <<
- (RW_MGR_MEM_DQ_PER_READ_DQS /
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
- param->write_correct_mask_vg = ((uint32_t)1 <<
- (RW_MGR_MEM_DQ_PER_READ_DQS /
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
- param->read_correct_mask = ((uint32_t)1 <<
- RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
- param->write_correct_mask = ((uint32_t)1 <<
- RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
- param->dm_correct_mask = ((uint32_t)1 <<
- (RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH))
- - 1;
- }
+ /* Init params only if we do NOT skip calibration. */
+ if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
+ return;
+
+ ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
+ param->read_correct_mask_vg = (1 << ratio) - 1;
+ param->write_correct_mask_vg = (1 << ratio) - 1;
+ param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
+ param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
+ ratio = RW_MGR_MEM_DATA_WIDTH /
+ RW_MGR_MEM_DATA_MASK_WIDTH;
+ param->dm_correct_mask = (1 << ratio) - 1;
}
static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 084/172] ddr: altera: Clean up mem_config()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (82 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 083/172] ddr: altera: Clean up phy_mgr_initialize() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 085/172] ddr: altera: Clean up mem_precharge_and_activate() Marek Vasut
` (89 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Clean mem_config() function. First, reorder the math done in the
function such that WLAT and RLAT computation is together. Then,
scrap contradictory comments which do not match the result of the
math at all. Next, extract the mem_precharge_and_activate() call
from the end of the function as it is completely unrelated here.
Finally, rename the function to mem_init_latency().
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 67 ++++++++++++++++++------------------------
drivers/ddr/altera/sequencer.h | 4 ---
2 files changed, 29 insertions(+), 42 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 25b7b14..a215c20 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3123,57 +3123,44 @@ static void mem_precharge_and_activate(void)
}
}
-/* Configure various memory related parameters. */
-static void mem_config(void)
+/**
+ * mem_init_latency() - Configure memory RLAT and WLAT settings
+ *
+ * Configure memory RLAT and WLAT parameters.
+ */
+static void mem_init_latency(void)
{
- uint32_t rlat, wlat;
- uint32_t rw_wl_nop_cycles;
- uint32_t max_latency;
-
- debug("%s:%d\n", __func__, __LINE__);
- /* read in write and read latency */
- wlat = readl(&data_mgr->t_wl_add);
- wlat += readl(&data_mgr->mem_t_add);
-
- /* WL for hard phy does not include additive latency */
-
/*
- * add addtional write latency to offset the address/command extra
- * clock cycle. We change the AC mux setting causing AC to be delayed
- * by one mem clock cycle. Only do this for DDR3
+ * For AV/CV, LFIFO is hardened and always runs at full rate
+ * so max latency in AFI clocks, used here, is correspondingly
+ * smaller.
*/
- wlat = wlat + 1;
-
- rlat = readl(&data_mgr->t_rl_add);
+ const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
+ u32 rlat, wlat;
- rw_wl_nop_cycles = wlat - 2;
- gbl->rw_wl_nop_cycles = rw_wl_nop_cycles;
+ debug("%s:%d\n", __func__, __LINE__);
/*
- * For AV/CV, lfifo is hardened and always runs at full rate so
- * max latency in AFI clocks, used here, is correspondingly smaller.
+ * Read in write latency.
+ * WL for Hard PHY does not include additive latency.
*/
- max_latency = (1<<MAX_LATENCY_COUNT_WIDTH)/1 - 1;
- /* configure for a burst length of 8 */
+ wlat = readl(&data_mgr->t_wl_add);
+ wlat += readl(&data_mgr->mem_t_add);
- /* write latency */
- /* Adjust Write Latency for Hard PHY */
- wlat = wlat + 1;
+ gbl->rw_wl_nop_cycles = wlat - 1;
- /* set a pretty high read latency initially */
- gbl->curr_read_lat = rlat + 16;
+ /* Read in readl latency. */
+ rlat = readl(&data_mgr->t_rl_add);
+ /* Set a pretty high read latency initially. */
+ gbl->curr_read_lat = rlat + 16;
if (gbl->curr_read_lat > max_latency)
gbl->curr_read_lat = max_latency;
writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
- /* advertise write latency */
- gbl->curr_write_lat = wlat;
- writel(wlat - 2, &phy_mgr_cfg->afi_wlat);
-
- /* initialize bit slips */
- mem_precharge_and_activate();
+ /* Advertise write latency. */
+ writel(wlat, &phy_mgr_cfg->afi_wlat);
}
/* Set VFIFO and LFIFO to instant-on settings in skip calibration mode */
@@ -3275,15 +3262,19 @@ static uint32_t mem_calibrate(void)
uint32_t sr_failed = 0;
debug("%s:%d\n", __func__, __LINE__);
- /* Initialize the data settings */
+ /* Initialize the data settings */
gbl->error_substage = CAL_SUBSTAGE_NIL;
gbl->error_stage = CAL_STAGE_NIL;
gbl->error_group = 0xff;
gbl->fom_in = 0;
gbl->fom_out = 0;
- mem_config();
+ /* Initialize WLAT and RLAT. */
+ mem_init_latency();
+
+ /* Initialize bit slips. */
+ mem_precharge_and_activate();
for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
diff --git a/drivers/ddr/altera/sequencer.h b/drivers/ddr/altera/sequencer.h
index 5d4d800..3e4152f 100644
--- a/drivers/ddr/altera/sequencer.h
+++ b/drivers/ddr/altera/sequencer.h
@@ -242,10 +242,6 @@ struct gbl_type {
uint32_t curr_read_lat;
- /* current write latency */
-
- uint32_t curr_write_lat;
-
/* error code */
uint32_t error_substage;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 085/172] ddr: altera: Clean up mem_precharge_and_activate()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (83 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 084/172] ddr: altera: Clean up mem_config() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 086/172] ddr: altera: Clean up set_rank_and_odt_mask() part 1 Marek Vasut
` (88 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Perform minor cleanup of this function, fix datatype and add kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 19 +++++++++++--------
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index a215c20..b010543 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3091,21 +3091,24 @@ static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
return 1;
}
-/* precharge all banks and activate row 0 in bank "000..." and bank "111..." */
+/**
+ * mem_precharge_and_activate() - Precharge all banks and activate
+ *
+ * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
+ */
static void mem_precharge_and_activate(void)
{
- uint32_t r;
+ int r;
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
- if (param->skip_ranks[r]) {
- /* request to skip the rank */
+ /* Test if the rank should be skipped. */
+ if (param->skip_ranks[r])
continue;
- }
- /* set rank */
+ /* Set rank. */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
- /* precharge all banks ... */
+ /* Precharge all banks. */
writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET);
@@ -3117,7 +3120,7 @@ static void mem_precharge_and_activate(void)
writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
- /* activate rows */
+ /* Activate rows. */
writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RUN_SINGLE_GROUP_OFFSET);
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 086/172] ddr: altera: Clean up set_rank_and_odt_mask() part 1
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (84 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 085/172] ddr: altera: Clean up mem_precharge_and_activate() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 087/172] ddr: altera: Clean up set_rank_and_odt_mask() part 2 Marek Vasut
` (87 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
First, invert the logic of the if (odt_mode == ...) conditional to make
the OFF mode harder to miss. It is a short piece of code right at the
end, so move it up.
Also, clean up data types and constify where applicable and clean up
the cs_and_odt_mask assignment. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 23 +++++++++++------------
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index b010543..7dd9a66 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -154,13 +154,16 @@ static void phy_mgr_initialize(void)
param->dm_correct_mask = (1 << ratio) - 1;
}
-static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
+static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
{
- uint32_t odt_mask_0 = 0;
- uint32_t odt_mask_1 = 0;
- uint32_t cs_and_odt_mask;
+ u32 odt_mask_0 = 0;
+ u32 odt_mask_1 = 0;
+ u32 cs_and_odt_mask;
- if (odt_mode == RW_MGR_ODT_MODE_READ_WRITE) {
+ if (odt_mode == RW_MGR_ODT_MODE_OFF) {
+ odt_mask_0 = 0x0;
+ odt_mask_1 = 0x0;
+ } else { /* RW_MGR_ODT_MODE_READ_WRITE */
if (RW_MGR_MEM_NUMBER_OF_RANKS == 1) {
/*
* 1 Rank
@@ -242,15 +245,11 @@ static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
break;
}
}
- } else {
- odt_mask_0 = 0x0;
- odt_mask_1 = 0x0;
}
- cs_and_odt_mask =
- (0xFF & ~(1 << rank)) |
- ((0xFF & odt_mask_0) << 8) |
- ((0xFF & odt_mask_1) << 16);
+ cs_and_odt_mask = (0xFF & ~(1 << rank)) |
+ ((0xFF & odt_mask_0) << 8) |
+ ((0xFF & odt_mask_1) << 16);
writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 087/172] ddr: altera: Clean up set_rank_and_odt_mask() part 2
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (85 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 086/172] ddr: altera: Clean up set_rank_and_odt_mask() part 1 Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 088/172] ddr: altera: Clean up set_rank_and_odt_mask() part 3 Marek Vasut
` (86 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Turn the big inner if (RW_MGR_MEM_NUMBER_OF_RANKS == ...) conditional
into a switch {} statement instead. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 20 +++++++++-----------
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 7dd9a66..f7b5f52 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -164,16 +164,13 @@ static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
odt_mask_0 = 0x0;
odt_mask_1 = 0x0;
} else { /* RW_MGR_ODT_MODE_READ_WRITE */
- if (RW_MGR_MEM_NUMBER_OF_RANKS == 1) {
- /*
- * 1 Rank
- * Read: ODT = 0
- * Write: ODT = 1
- */
+ switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
+ case 1: /* 1 Rank */
+ /* Read: ODT = 0 ; Write: ODT = 1 */
odt_mask_0 = 0x0;
odt_mask_1 = 0x1;
- } else if (RW_MGR_MEM_NUMBER_OF_RANKS == 2) {
- /* 2 Ranks */
+ break;
+ case 2: /* 2 Ranks */
if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
/* - Dual-Slot , Single-Rank
* (1 chip-select per DIMM)
@@ -198,9 +195,9 @@ static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
odt_mask_0 = 0x0;
odt_mask_1 = 0x3 & (1 << rank);
}
- } else {
- /* 4 Ranks
- * Read:
+ break;
+ case 4: /* 4 Ranks */
+ /* Read:
* ----------+-----------------------+
* | |
* | ODT |
@@ -244,6 +241,7 @@ static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
odt_mask_1 = 0xA;
break;
}
+ break;
}
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 088/172] ddr: altera: Clean up set_rank_and_odt_mask() part 3
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (86 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 087/172] ddr: altera: Clean up set_rank_and_odt_mask() part 2 Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 089/172] ddr: altera: Minor clean up of mem_skip_calibrate() Marek Vasut
` (85 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Clean up comments and add kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 34 ++++++++++++++++++++--------------
1 file changed, 20 insertions(+), 14 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index f7b5f52..56ca6f3 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -154,6 +154,13 @@ static void phy_mgr_initialize(void)
param->dm_correct_mask = (1 << ratio) - 1;
}
+/**
+ * set_rank_and_odt_mask() - Set Rank and ODT mask
+ * @rank: Rank mask
+ * @odt_mode: ODT mode, OFF or READ_WRITE
+ *
+ * Set Rank and ODT mask (On-Die Termination).
+ */
static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
{
u32 odt_mask_0 = 0;
@@ -172,14 +179,15 @@ static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
break;
case 2: /* 2 Ranks */
if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
- /* - Dual-Slot , Single-Rank
- * (1 chip-select per DIMM)
- * OR
- * - RDIMM, 4 total CS (2 CS per DIMM)
- * means 2 DIMM
- * Since MEM_NUMBER_OF_RANKS is 2 they are
- * both single rank
- * with 2 CS each (special for RDIMM)
+ /*
+ * - Dual-Slot , Single-Rank (1 CS per DIMM)
+ * OR
+ * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
+ *
+ * Since MEM_NUMBER_OF_RANKS is 2, they
+ * are both single rank with 2 CS each
+ * (special for RDIMM).
+ *
* Read: Turn on ODT on the opposite rank
* Write: Turn on ODT on all ranks
*/
@@ -187,10 +195,10 @@ static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
odt_mask_1 = 0x3;
} else {
/*
- * USER - Single-Slot , Dual-rank DIMMs
- * (2 chip-selects per DIMM)
- * USER Read: Turn on ODT off on all ranks
- * USER Write: Turn on ODT on active rank
+ * - Single-Slot , Dual-Rank (2 CS per DIMM)
+ *
+ * Read: Turn on ODT off on all ranks
+ * Write: Turn on ODT on active rank
*/
odt_mask_0 = 0x0;
odt_mask_1 = 0x3 & (1 << rank);
@@ -199,7 +207,6 @@ static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
case 4: /* 4 Ranks */
/* Read:
* ----------+-----------------------+
- * | |
* | ODT |
* Read From +-----------------------+
* Rank | 3 | 2 | 1 | 0 |
@@ -212,7 +219,6 @@ static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
*
* Write:
* ----------+-----------------------+
- * | |
* | ODT |
* Write To +-----------------------+
* Rank | 3 | 2 | 1 | 0 |
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 089/172] ddr: altera: Minor clean up of mem_skip_calibrate()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (87 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 088/172] ddr: altera: Clean up set_rank_and_odt_mask() part 3 Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 090/172] ddr: altera: Trivial mem_calibrate() indent cleanup Marek Vasut
` (84 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Perform minor coding style cleanup of the mem_skip_calibrate() function,
clean up comments and add kerneldoc. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 19 +++++++++++--------
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 56ca6f3..874868d 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3169,7 +3169,11 @@ static void mem_init_latency(void)
writel(wlat, &phy_mgr_cfg->afi_wlat);
}
-/* Set VFIFO and LFIFO to instant-on settings in skip calibration mode */
+/**
+ * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
+ *
+ * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
+ */
static void mem_skip_calibrate(void)
{
uint32_t vfifo_offset;
@@ -3178,7 +3182,7 @@ static void mem_skip_calibrate(void)
debug("%s:%d\n", __func__, __LINE__);
/* Need to update every shadow register set used by the interface */
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
- r += NUM_RANKS_PER_SHADOW_REG) {
+ r += NUM_RANKS_PER_SHADOW_REG) {
/*
* Set output phase alignment settings appropriate for
* skip calibration.
@@ -3215,8 +3219,8 @@ static void mem_skip_calibrate(void)
*
* (1.25 * IO_DLL_CHAIN_LENGTH - 2)
*/
- scc_mgr_set_dqdqs_output_phase(i, (1.25 *
- IO_DLL_CHAIN_LENGTH - 2));
+ scc_mgr_set_dqdqs_output_phase(i,
+ 1.25 * IO_DLL_CHAIN_LENGTH - 2);
}
writel(0xff, &sdr_scc_mgr->dqs_ena);
writel(0xff, &sdr_scc_mgr->dqs_io_ena);
@@ -3242,14 +3246,13 @@ static void mem_skip_calibrate(void)
* in sequencer.
*/
vfifo_offset = CALIB_VFIFO_OFFSET;
- for (j = 0; j < vfifo_offset; j++) {
+ for (j = 0; j < vfifo_offset; j++)
writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
- }
writel(0, &phy_mgr_cmd->fifo_reset);
/*
- * For ACV with hard lfifo, we get the skip-cal setting from
- * generation-time constant.
+ * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
+ * setting from generation-time constant.
*/
gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 090/172] ddr: altera: Trivial mem_calibrate() indent cleanup
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (88 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 089/172] ddr: altera: Minor clean up of mem_skip_calibrate() Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 091/172] ddr: altera: Internal mem_calibrate() cleanup part 1 Marek Vasut
` (83 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Redo the mega-condition such that if the calibration is to be skipped,
the positive branch of the condition does all the work and returns.
The negative branch, which is in fact the default behavior, is then
converted to a code which is no longer conditional. This trims down
the indent by one level.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 249 +++++++++++++++++++++--------------------
1 file changed, 129 insertions(+), 120 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 874868d..77a1308 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3295,152 +3295,161 @@ static uint32_t mem_calibrate(void)
scc_set_bypass_mode(i);
}
+ /* Calibration is skipped. */
if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
/*
* Set VFIFO and LFIFO to instant-on settings in skip
* calibration mode.
*/
mem_skip_calibrate();
- } else {
- for (i = 0; i < NUM_CALIB_REPEAT; i++) {
- /*
- * Zero all delay chain/phase settings for all
- * groups and all shadow register sets.
- */
- scc_mgr_zero_all();
-
- run_groups = ~param->skip_groups;
-
- for (write_group = 0, write_test_bgn = 0; write_group
- < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
- write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
- /* Initialized the group failure */
- group_failed = 0;
-
- current_run = run_groups & ((1 <<
- RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
- run_groups = run_groups >>
- RW_MGR_NUM_DQS_PER_WRITE_GROUP;
-
- if (current_run == 0)
- continue;
- writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
- SCC_MGR_GROUP_COUNTER_OFFSET);
- scc_mgr_zero_group(write_group, 0);
+ /*
+ * Do not remove this line as it makes sure all of our
+ * decisions have been applied.
+ */
+ writel(0, &sdr_scc_mgr->update);
+ return 1;
+ }
- for (read_group = write_group *
- RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
- read_test_bgn = 0;
- read_group < (write_group + 1) *
- RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
- group_failed == 0;
- read_group++, read_test_bgn +=
- RW_MGR_MEM_DQ_PER_READ_DQS) {
- /* Calibrate the VFIFO */
- if (!((STATIC_CALIB_STEPS) &
- CALIB_SKIP_VFIFO)) {
- if (!rw_mgr_mem_calibrate_vfifo
- (read_group,
- read_test_bgn)) {
- group_failed = 1;
-
- if (!(gbl->
- phy_debug_mode_flags &
- PHY_DEBUG_SWEEP_ALL_GROUPS)) {
- return 0;
- }
+ /* Calibration is not skipped. */
+ for (i = 0; i < NUM_CALIB_REPEAT; i++) {
+ /*
+ * Zero all delay chain/phase settings for all
+ * groups and all shadow register sets.
+ */
+ scc_mgr_zero_all();
+
+ run_groups = ~param->skip_groups;
+
+ for (write_group = 0, write_test_bgn = 0; write_group
+ < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
+ write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
+ /* Initialized the group failure */
+ group_failed = 0;
+
+ current_run = run_groups & ((1 <<
+ RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
+ run_groups = run_groups >>
+ RW_MGR_NUM_DQS_PER_WRITE_GROUP;
+
+ if (current_run == 0)
+ continue;
+
+ writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
+ SCC_MGR_GROUP_COUNTER_OFFSET);
+ scc_mgr_zero_group(write_group, 0);
+
+ for (read_group = write_group *
+ RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
+ read_test_bgn = 0;
+ read_group < (write_group + 1) *
+ RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
+ group_failed == 0;
+ read_group++, read_test_bgn +=
+ RW_MGR_MEM_DQ_PER_READ_DQS) {
+ /* Calibrate the VFIFO */
+ if (!((STATIC_CALIB_STEPS) &
+ CALIB_SKIP_VFIFO)) {
+ if (!rw_mgr_mem_calibrate_vfifo
+ (read_group,
+ read_test_bgn)) {
+ group_failed = 1;
+
+ if (!(gbl->
+ phy_debug_mode_flags &
+ PHY_DEBUG_SWEEP_ALL_GROUPS)) {
+ return 0;
}
}
}
+ }
- /* Calibrate the output side */
- if (group_failed == 0) {
- for (rank_bgn = 0, sr = 0; rank_bgn
- < RW_MGR_MEM_NUMBER_OF_RANKS;
- rank_bgn +=
- NUM_RANKS_PER_SHADOW_REG,
- ++sr) {
- sr_failed = 0;
- if (!((STATIC_CALIB_STEPS) &
- CALIB_SKIP_WRITES)) {
- if ((STATIC_CALIB_STEPS)
- & CALIB_SKIP_DELAY_SWEEPS) {
- /* not needed in quick mode! */
- } else {
- /*
- * Determine if this set of
- * ranks should be skipped
- * entirely.
- */
- if (!param->skip_shadow_regs[sr]) {
- if (!rw_mgr_mem_calibrate_writes
- (rank_bgn, write_group,
- write_test_bgn)) {
- sr_failed = 1;
- if (!(gbl->
- phy_debug_mode_flags &
- PHY_DEBUG_SWEEP_ALL_GROUPS)) {
- return 0;
- }
- }
+ /* Calibrate the output side */
+ if (group_failed == 0) {
+ for (rank_bgn = 0, sr = 0; rank_bgn
+ < RW_MGR_MEM_NUMBER_OF_RANKS;
+ rank_bgn +=
+ NUM_RANKS_PER_SHADOW_REG,
+ ++sr) {
+ sr_failed = 0;
+ if (!((STATIC_CALIB_STEPS) &
+ CALIB_SKIP_WRITES)) {
+ if ((STATIC_CALIB_STEPS)
+ & CALIB_SKIP_DELAY_SWEEPS) {
+ /* not needed in quick mode! */
+ } else {
+ /*
+ * Determine if this set of
+ * ranks should be skipped
+ * entirely.
+ */
+ if (!param->skip_shadow_regs[sr]) {
+ if (!rw_mgr_mem_calibrate_writes
+ (rank_bgn, write_group,
+ write_test_bgn)) {
+ sr_failed = 1;
+ if (!(gbl->
+ phy_debug_mode_flags &
+ PHY_DEBUG_SWEEP_ALL_GROUPS)) {
+ return 0;
+ }
}
}
}
- if (sr_failed != 0)
- group_failed = 1;
}
+ if (sr_failed != 0)
+ group_failed = 1;
}
+ }
- if (group_failed == 0) {
- for (read_group = write_group *
- RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
- read_test_bgn = 0;
- read_group < (write_group + 1)
- * RW_MGR_MEM_IF_READ_DQS_WIDTH
- / RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
- group_failed == 0;
- read_group++, read_test_bgn +=
- RW_MGR_MEM_DQ_PER_READ_DQS) {
- if (!((STATIC_CALIB_STEPS) &
- CALIB_SKIP_WRITES)) {
- if (!rw_mgr_mem_calibrate_vfifo_end
- (read_group, read_test_bgn)) {
- group_failed = 1;
-
- if (!(gbl->phy_debug_mode_flags
- & PHY_DEBUG_SWEEP_ALL_GROUPS)) {
- return 0;
- }
+ if (group_failed == 0) {
+ for (read_group = write_group *
+ RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
+ read_test_bgn = 0;
+ read_group < (write_group + 1)
+ * RW_MGR_MEM_IF_READ_DQS_WIDTH
+ / RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
+ group_failed == 0;
+ read_group++, read_test_bgn +=
+ RW_MGR_MEM_DQ_PER_READ_DQS) {
+ if (!((STATIC_CALIB_STEPS) &
+ CALIB_SKIP_WRITES)) {
+ if (!rw_mgr_mem_calibrate_vfifo_end
+ (read_group, read_test_bgn)) {
+ group_failed = 1;
+
+ if (!(gbl->phy_debug_mode_flags
+ & PHY_DEBUG_SWEEP_ALL_GROUPS)) {
+ return 0;
}
}
}
}
-
- if (group_failed != 0)
- failing_groups++;
}
+ if (group_failed != 0)
+ failing_groups++;
+ }
+
+ /*
+ * USER If there are any failing groups then report
+ * the failure.
+ */
+ if (failing_groups != 0)
+ return 0;
+
+ /* Calibrate the LFIFO */
+ if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_LFIFO)) {
/*
- * USER If there are any failing groups then report
- * the failure.
+ * If we're skipping groups as part of debug,
+ * don't calibrate LFIFO.
*/
- if (failing_groups != 0)
- return 0;
-
- /* Calibrate the LFIFO */
- if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_LFIFO)) {
- /*
- * If we're skipping groups as part of debug,
- * don't calibrate LFIFO.
- */
- if (param->skip_groups == 0) {
- if (!rw_mgr_mem_calibrate_lfifo())
- return 0;
- }
+ if (param->skip_groups == 0) {
+ if (!rw_mgr_mem_calibrate_lfifo())
+ return 0;
}
}
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 091/172] ddr: altera: Internal mem_calibrate() cleanup part 1
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (89 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 090/172] ddr: altera: Trivial mem_calibrate() indent cleanup Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 092/172] ddr: altera: Internal mem_calibrate() cleanup part 2 Marek Vasut
` (82 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
This is kind of microseries-within-series indent cleanup.
Rework the code for the first loop within the middle-loop
of the mega-loop to make it actually readable and not an
insane cryptic pile of indent failure.
It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 40 +++++++++++++++++-----------------------
1 file changed, 17 insertions(+), 23 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 77a1308..59c09b6 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3270,6 +3270,9 @@ static uint32_t mem_calibrate(void)
uint32_t group_failed = 0;
uint32_t sr_failed = 0;
+ const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
+
debug("%s:%d\n", __func__, __LINE__);
/* Initialize the data settings */
@@ -3339,31 +3342,22 @@ static uint32_t mem_calibrate(void)
SCC_MGR_GROUP_COUNTER_OFFSET);
scc_mgr_zero_group(write_group, 0);
- for (read_group = write_group *
- RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
- read_test_bgn = 0;
- read_group < (write_group + 1) *
- RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
- group_failed == 0;
- read_group++, read_test_bgn +=
- RW_MGR_MEM_DQ_PER_READ_DQS) {
+ for (read_group = write_group * rwdqs_ratio,
+ read_test_bgn = 0;
+ read_group < (write_group + 1) * rwdqs_ratio && group_failed == 0;
+ read_group++,
+ read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
+ if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
+ continue;
+
/* Calibrate the VFIFO */
- if (!((STATIC_CALIB_STEPS) &
- CALIB_SKIP_VFIFO)) {
- if (!rw_mgr_mem_calibrate_vfifo
- (read_group,
- read_test_bgn)) {
- group_failed = 1;
+ if (rw_mgr_mem_calibrate_vfifo(read_group,
+ read_test_bgn))
+ continue;
- if (!(gbl->
- phy_debug_mode_flags &
- PHY_DEBUG_SWEEP_ALL_GROUPS)) {
- return 0;
- }
- }
- }
+ group_failed = 1;
+ if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
+ return 0;
}
/* Calibrate the output side */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 092/172] ddr: altera: Internal mem_calibrate() cleanup part 2
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (90 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 091/172] ddr: altera: Internal mem_calibrate() cleanup part 1 Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 093/172] ddr: altera: Internal mem_calibrate() cleanup part 3 Marek Vasut
` (81 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
This is kind of microseries-within-series indent cleanup.
Rework the code for the second loop within the middle-loop
of the mega-loop to make it actually readable and not an
insane cryptic pile of indent failure.
It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 57 ++++++++++++++++++------------------------
1 file changed, 24 insertions(+), 33 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 59c09b6..e2e7184 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3268,7 +3268,6 @@ static uint32_t mem_calibrate(void)
uint32_t run_groups, current_run;
uint32_t failing_groups = 0;
uint32_t group_failed = 0;
- uint32_t sr_failed = 0;
const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
@@ -3361,40 +3360,32 @@ static uint32_t mem_calibrate(void)
}
/* Calibrate the output side */
- if (group_failed == 0) {
- for (rank_bgn = 0, sr = 0; rank_bgn
- < RW_MGR_MEM_NUMBER_OF_RANKS;
- rank_bgn +=
- NUM_RANKS_PER_SHADOW_REG,
- ++sr) {
- sr_failed = 0;
- if (!((STATIC_CALIB_STEPS) &
- CALIB_SKIP_WRITES)) {
- if ((STATIC_CALIB_STEPS)
- & CALIB_SKIP_DELAY_SWEEPS) {
- /* not needed in quick mode! */
- } else {
+ if (group_failed == 0) {
+ for (rank_bgn = 0, sr = 0;
+ rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
+ rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
+ if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
+ continue;
+
+ /* Not needed in quick mode! */
+ if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
+ continue;
+
/*
- * Determine if this set of
- * ranks should be skipped
- * entirely.
+ * Determine if this set of ranks
+ * should be skipped entirely.
*/
- if (!param->skip_shadow_regs[sr]) {
- if (!rw_mgr_mem_calibrate_writes
- (rank_bgn, write_group,
- write_test_bgn)) {
- sr_failed = 1;
- if (!(gbl->
- phy_debug_mode_flags &
- PHY_DEBUG_SWEEP_ALL_GROUPS)) {
- return 0;
- }
- }
- }
- }
- }
- if (sr_failed != 0)
- group_failed = 1;
+ if (param->skip_shadow_regs[sr])
+ continue;
+
+ /* Calibrate WRITEs */
+ if (rw_mgr_mem_calibrate_writes(rank_bgn,
+ write_group, write_test_bgn))
+ continue;
+
+ group_failed = 1;
+ if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
+ return 0;
}
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 093/172] ddr: altera: Internal mem_calibrate() cleanup part 3
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (91 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 092/172] ddr: altera: Internal mem_calibrate() cleanup part 2 Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 094/172] ddr: altera: Internal mem_calibrate() cleanup part 4 Marek Vasut
` (80 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
This is kind of microseries-within-series indent cleanup.
Rework the code for the third loop within the middle-loop
of the mega-loop to make it actually readable and not an
insane cryptic pile of indent failure.
It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 37 +++++++++++++++----------------------
1 file changed, 15 insertions(+), 22 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index e2e7184..7384c16 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3390,28 +3390,21 @@ static uint32_t mem_calibrate(void)
}
if (group_failed == 0) {
- for (read_group = write_group *
- RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
- read_test_bgn = 0;
- read_group < (write_group + 1)
- * RW_MGR_MEM_IF_READ_DQS_WIDTH
- / RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
- group_failed == 0;
- read_group++, read_test_bgn +=
- RW_MGR_MEM_DQ_PER_READ_DQS) {
- if (!((STATIC_CALIB_STEPS) &
- CALIB_SKIP_WRITES)) {
- if (!rw_mgr_mem_calibrate_vfifo_end
- (read_group, read_test_bgn)) {
- group_failed = 1;
-
- if (!(gbl->phy_debug_mode_flags
- & PHY_DEBUG_SWEEP_ALL_GROUPS)) {
- return 0;
- }
- }
- }
+ for (read_group = write_group * rwdqs_ratio,
+ read_test_bgn = 0;
+ read_group < (write_group + 1) * rwdqs_ratio && group_failed == 0;
+ read_group++,
+ read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
+ if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
+ continue;
+
+ if (rw_mgr_mem_calibrate_vfifo_end(read_group,
+ read_test_bgn))
+ continue;
+
+ group_failed = 1;
+ if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
+ return 0;
}
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 094/172] ddr: altera: Internal mem_calibrate() cleanup part 4
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (92 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 093/172] ddr: altera: Internal mem_calibrate() cleanup part 3 Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 095/172] ddr: altera: Internal mem_calibrate() cleanup part 5 Marek Vasut
` (79 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
This is kind of microseries-within-series indent cleanup.
Rework the code for the last loop within the mega-loop
to make it actually readable and not an insane cryptic pile
of indent failure.
It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 7384c16..5e3fec3 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3419,17 +3419,19 @@ static uint32_t mem_calibrate(void)
if (failing_groups != 0)
return 0;
+ if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
+ continue;
+
+ /*
+ * If we're skipping groups as part of debug,
+ * don't calibrate LFIFO.
+ */
+ if (param->skip_groups != 0)
+ continue;
+
/* Calibrate the LFIFO */
- if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_LFIFO)) {
- /*
- * If we're skipping groups as part of debug,
- * don't calibrate LFIFO.
- */
- if (param->skip_groups == 0) {
- if (!rw_mgr_mem_calibrate_lfifo())
- return 0;
- }
- }
+ if (!rw_mgr_mem_calibrate_lfifo())
+ return 0;
}
/*
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 095/172] ddr: altera: Internal mem_calibrate() cleanup part 5
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (93 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 094/172] ddr: altera: Internal mem_calibrate() cleanup part 4 Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 096/172] ddr: altera: Internal mem_calibrate() cleanup part 6 Marek Vasut
` (78 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
This is kind of microseries-within-series indent cleanup.
Rework the code for the the middle-loop of the mega-loop
this time and deal with the group_failed variable. Instead
of checking if the group failed in the previous calibration
part, just jump to the end of the loop if calibration did
fail and increment the counter. This shaves away one more
level of indent while making the code slightly more readable.
It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 98 +++++++++++++++++++++++-------------------
1 file changed, 53 insertions(+), 45 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 5e3fec3..6cc11b9 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3326,7 +3326,8 @@ static uint32_t mem_calibrate(void)
for (write_group = 0, write_test_bgn = 0; write_group
< RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
- /* Initialized the group failure */
+
+ /* Initialize the group failure */
group_failed = 0;
current_run = run_groups & ((1 <<
@@ -3343,7 +3344,7 @@ static uint32_t mem_calibrate(void)
for (read_group = write_group * rwdqs_ratio,
read_test_bgn = 0;
- read_group < (write_group + 1) * rwdqs_ratio && group_failed == 0;
+ read_group < (write_group + 1) * rwdqs_ratio;
read_group++,
read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
@@ -3354,62 +3355,69 @@ static uint32_t mem_calibrate(void)
read_test_bgn))
continue;
- group_failed = 1;
if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
return 0;
+
+ /* The group failed, we're done. */
+ goto grp_failed;
}
/* Calibrate the output side */
- if (group_failed == 0) {
- for (rank_bgn = 0, sr = 0;
- rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
- rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
- if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
- continue;
+ for (rank_bgn = 0, sr = 0;
+ rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
+ rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
+ if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
+ continue;
- /* Not needed in quick mode! */
- if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
- continue;
+ /* Not needed in quick mode! */
+ if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
+ continue;
- /*
- * Determine if this set of ranks
- * should be skipped entirely.
- */
- if (param->skip_shadow_regs[sr])
- continue;
+ /*
+ * Determine if this set of ranks
+ * should be skipped entirely.
+ */
+ if (param->skip_shadow_regs[sr])
+ continue;
- /* Calibrate WRITEs */
- if (rw_mgr_mem_calibrate_writes(rank_bgn,
- write_group, write_test_bgn))
- continue;
+ /* Calibrate WRITEs */
+ if (rw_mgr_mem_calibrate_writes(rank_bgn,
+ write_group, write_test_bgn))
+ continue;
- group_failed = 1;
- if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
- return 0;
- }
+ group_failed = 1;
+ if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
+ return 0;
}
- if (group_failed == 0) {
- for (read_group = write_group * rwdqs_ratio,
- read_test_bgn = 0;
- read_group < (write_group + 1) * rwdqs_ratio && group_failed == 0;
- read_group++,
- read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
- if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
- continue;
-
- if (rw_mgr_mem_calibrate_vfifo_end(read_group,
- read_test_bgn))
- continue;
-
- group_failed = 1;
- if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
- return 0;
- }
+ /* Some group failed, we're done. */
+ if (group_failed)
+ goto grp_failed;
+
+ for (read_group = write_group * rwdqs_ratio,
+ read_test_bgn = 0;
+ read_group < (write_group + 1) * rwdqs_ratio;
+ read_group++,
+ read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
+ if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
+ continue;
+
+ if (rw_mgr_mem_calibrate_vfifo_end(read_group,
+ read_test_bgn))
+ continue;
+
+ if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
+ return 0;
+
+ /* The group failed, we're done. */
+ goto grp_failed;
}
- if (group_failed != 0)
- failing_groups++;
+ /* No group failed, continue as usual. */
+ continue;
+
+grp_failed: /* A group failed, increment the counter. */
+ failing_groups++;
}
/*
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 096/172] ddr: altera: Internal mem_calibrate() cleanup part 6
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (94 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 095/172] ddr: altera: Internal mem_calibrate() cleanup part 5 Marek Vasut
@ 2015-07-27 20:50 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 097/172] ddr: altera: Minor clean up of rw_mgr_mem_initialize() Marek Vasut
` (77 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:50 UTC (permalink / raw)
To: u-boot
Add kerneldoc to this function.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 6cc11b9..a94f88e 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3258,7 +3258,11 @@ static void mem_skip_calibrate(void)
writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
}
-/* Memory calibration entry point */
+/**
+ * mem_calibrate() - Memory calibration entry point.
+ *
+ * Perform memory calibration.
+ */
static uint32_t mem_calibrate(void)
{
uint32_t i;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 097/172] ddr: altera: Minor clean up of rw_mgr_mem_initialize()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (95 preceding siblings ...)
2015-07-27 20:50 ` [U-Boot] [PATCH 096/172] ddr: altera: Internal mem_calibrate() cleanup part 6 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 098/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 1 Marek Vasut
` (76 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Add kerneldoc and do a minor comment cleanup. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index a94f88e..c0fa92f 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -951,6 +951,11 @@ static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
}
}
+/**
+ * rw_mgr_mem_initialize() - Initialize RW Manager
+ *
+ * Initialize RW Manager.
+ */
static void rw_mgr_mem_initialize(void)
{
debug("%s:%d\n", __func__, __LINE__);
@@ -969,7 +974,7 @@ static void rw_mgr_mem_initialize(void)
* significant bits
*/
- /* start with memory RESET activated */
+ /* Start with memory RESET activated */
/* tINIT = 200us */
@@ -986,7 +991,7 @@ static void rw_mgr_mem_initialize(void)
SEQ_TINIT_CNTR2_VAL,
RW_MGR_INIT_RESET_0_CKE_0);
- /* indicate that memory is stable */
+ /* Indicate that memory is stable. */
writel(1, &phy_mgr_cfg->reset_mem_stbl);
/*
@@ -1007,7 +1012,7 @@ static void rw_mgr_mem_initialize(void)
SEQ_TRESET_CNTR2_VAL,
RW_MGR_INIT_RESET_1_CKE_0);
- /* bring up clock enable */
+ /* Bring up clock enable. */
/* tXRP < 250 ck cycles */
delay_for_n_mem_clocks(250);
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 098/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 1
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (96 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 097/172] ddr: altera: Minor clean up of rw_mgr_mem_initialize() Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 099/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 2 Marek Vasut
` (75 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
This patch just adds an expanded documentation header to the
aforementioned function. This is needed to make it easier to
match the purpose of this function with the documentation.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index c0fa92f..32713a8 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2186,11 +2186,19 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
return (dq_margin >= 0) && (dqs_margin >= 0);
}
-/*
- * calibrate the read valid prediction FIFO.
+/**
+ * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
+ * @rw_group: Read/Write Group
+ * @test_bgn: Rank at which the test begins
+ *
+ * Stage 1: Calibrate the read valid prediction FIFO.
+ *
+ * This function implements UniPHY calibration Stage 1, as explained in
+ * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
*
- * - read valid prediction will consist of finding a good DQS enable phase,
- * DQS enable delay, DQS input phase, and DQS input delay.
+ * - read valid prediction will consist of finding:
+ * - DQS enable phase and DQS enable delay (DQS Enable Calibration)
+ * - DQS input phase and DQS input delay (DQ/DQS Centering)
* - we also do a per-bit deskew on the DQ lines.
*/
static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 099/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 2
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (97 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 098/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 1 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 100/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 3 Marek Vasut
` (74 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
This is kind of microseries-within-series indent cleanup.
This patch just tweaks the indentation so it is visible
what is supposed to go where.
It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 56 ++++++++++++++++++++----------------------
1 file changed, 27 insertions(+), 29 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 32713a8..2f2b88b 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2243,8 +2243,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
write_group, d);
}
- for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0;
- p++) {
+ for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0; p++) {
/* set a particular dqdqs phase */
scc_mgr_set_dqdqs_output_phase_all_ranks(read_group, p);
@@ -2257,10 +2256,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
* using current DQDQS phase.
*/
rw_mgr_mem_calibrate_read_load_patterns(0, 1);
- if (!(gbl->phy_debug_mode_flags &
- PHY_DEBUG_DISABLE_GUARANTEED_READ)) {
+ if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)) {
if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks
- (read_group, 1, &bit_chk)) {
+ (read_group, 1, &bit_chk)) {
debug_cond(DLEVEL == 1, "%s:%d Guaranteed read test failed:",
__func__, __LINE__);
debug_cond(DLEVEL == 1, " g=%u p=%u d=%u\n",
@@ -2269,37 +2267,37 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
}
}
-/* case:56390 */
+ /* case:56390 */
grp_calibrated = 1;
- if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
- (write_group, read_group, test_bgn)) {
- /*
- * USER Read per-bit deskew can be done on a
- * per shadow register basis.
- */
- for (rank_bgn = 0, sr = 0;
- rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
- rank_bgn += NUM_RANKS_PER_SHADOW_REG,
- ++sr) {
+ if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
+ (write_group, read_group, test_bgn)) {
/*
- * Determine if this set of ranks
- * should be skipped entirely.
+ * USER Read per-bit deskew can be done on a
+ * per shadow register basis.
*/
- if (!param->skip_shadow_regs[sr]) {
+ for (rank_bgn = 0, sr = 0;
+ rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
+ rank_bgn += NUM_RANKS_PER_SHADOW_REG,
+ ++sr) {
/*
- * If doing read after write
- * calibration, do not update
- * FOM, now - do it then.
+ * Determine if this set of ranks
+ * should be skipped entirely.
*/
- if (!rw_mgr_mem_calibrate_vfifo_center
- (rank_bgn, write_group,
- read_group, test_bgn, 1, 0)) {
- grp_calibrated = 0;
- failed_substage =
- CAL_SUBSTAGE_VFIFO_CENTER;
+ if (!param->skip_shadow_regs[sr]) {
+ /*
+ * If doing read after write
+ * calibration, do not update
+ * FOM, now - do it then.
+ */
+ if (!rw_mgr_mem_calibrate_vfifo_center
+ (rank_bgn, write_group,
+ read_group, test_bgn,
+ 1, 0)) {
+ grp_calibrated = 0;
+ failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
+ }
}
}
- }
} else {
grp_calibrated = 0;
failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 100/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 3
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (98 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 099/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 2 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 101/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 4 Marek Vasut
` (73 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
This is kind of microseries-within-series indent cleanup.
This patch just tweaks the indentation so it is visible
what to do with the grp_calibrated variable.
It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 38 +++++++++++++++++++-------------------
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 2f2b88b..81c3307 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2235,8 +2235,8 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
/*
* In RLDRAMX we may be messing the delay of pins in
* the same write group but outside of the current read
- * the group, but that's ok because we haven't
- * calibrated output side yet.
+ * the group, but that's ok because we haven't calibrated
+ * output side yet.
*/
if (d > 0) {
scc_mgr_apply_group_all_out_delay_add_all_ranks(
@@ -2276,27 +2276,27 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
* per shadow register basis.
*/
for (rank_bgn = 0, sr = 0;
- rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
- rank_bgn += NUM_RANKS_PER_SHADOW_REG,
- ++sr) {
+ rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
+ rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
/*
* Determine if this set of ranks
* should be skipped entirely.
*/
- if (!param->skip_shadow_regs[sr]) {
- /*
- * If doing read after write
- * calibration, do not update
- * FOM, now - do it then.
- */
- if (!rw_mgr_mem_calibrate_vfifo_center
- (rank_bgn, write_group,
- read_group, test_bgn,
- 1, 0)) {
- grp_calibrated = 0;
- failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
- }
- }
+ if (param->skip_shadow_regs[sr])
+ continue;
+ /*
+ * If doing read after write
+ * calibration, do not update
+ * FOM, now - do it then.
+ */
+ if (rw_mgr_mem_calibrate_vfifo_center
+ (rank_bgn, write_group,
+ read_group, test_bgn,
+ 1, 0))
+ continue;
+
+ grp_calibrated = 0;
+ failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
}
} else {
grp_calibrated = 0;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 101/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 4
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (99 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 100/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 3 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 102/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 5 Marek Vasut
` (72 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
This is kind of microseries-within-series indent cleanup.
This patch cleans up the handling of grp_calibrated such
that the variable isn't used all over the place, but just
very localy. This allows trimming down the indent issues.
It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 81 +++++++++++++++++++++---------------------
1 file changed, 41 insertions(+), 40 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 81c3307..2d16ce5 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2226,12 +2226,10 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
/* update info for sims */
reg_file_set_group(read_group);
- grp_calibrated = 0;
-
reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
- for (d = 0; d <= dtaps_per_ptap && grp_calibrated == 0; d += 2) {
+ for (d = 0; d <= dtaps_per_ptap; d += 2) {
/*
* In RLDRAMX we may be messing the delay of pins in
* the same write group but outside of the current read
@@ -2243,7 +2241,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
write_group, d);
}
- for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0; p++) {
+ for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
/* set a particular dqdqs phase */
scc_mgr_set_dqdqs_output_phase_all_ranks(read_group, p);
@@ -2268,49 +2266,52 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
}
/* case:56390 */
- grp_calibrated = 1;
- if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
+ if (!rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
(write_group, read_group, test_bgn)) {
- /*
- * USER Read per-bit deskew can be done on a
- * per shadow register basis.
- */
- for (rank_bgn = 0, sr = 0;
- rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
- rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
- /*
- * Determine if this set of ranks
- * should be skipped entirely.
- */
- if (param->skip_shadow_regs[sr])
- continue;
- /*
- * If doing read after write
- * calibration, do not update
- * FOM, now - do it then.
- */
- if (rw_mgr_mem_calibrate_vfifo_center
- (rank_bgn, write_group,
- read_group, test_bgn,
- 1, 0))
- continue;
-
- grp_calibrated = 0;
- failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
- }
- } else {
- grp_calibrated = 0;
failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
+ continue;
+ }
+
+ /*
+ * USER Read per-bit deskew can be done on a
+ * per shadow register basis.
+ */
+ grp_calibrated = 1;
+ for (rank_bgn = 0, sr = 0;
+ rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
+ rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
+ /*
+ * Determine if this set of ranks
+ * should be skipped entirely.
+ */
+ if (param->skip_shadow_regs[sr])
+ continue;
+ /*
+ * If doing read after write
+ * calibration, do not update
+ * FOM, now - do it then.
+ */
+ if (rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
+ write_group, read_group,
+ test_bgn, 1, 0))
+
+ continue;
+
+ grp_calibrated = 0;
+ failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
}
+
+ if (grp_calibrated)
+ goto cal_done_ok;
}
}
- if (grp_calibrated == 0) {
- set_failing_group_stage(write_group, CAL_STAGE_VFIFO,
- failed_substage);
- return 0;
- }
+ /* Calibration Stage 1 failed. */
+ set_failing_group_stage(write_group, CAL_STAGE_VFIFO, failed_substage);
+ return 0;
+ /* Calibration Stage 1 completed OK. */
+cal_done_ok:
/*
* Reset the delay chains back to zero if they have moved > 1
* (check for > 1 because loop will increase d even when pass in
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 102/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 5
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (100 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 101/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 4 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 103/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 6 Marek Vasut
` (71 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
This is kind of microseries-within-series indent cleanup.
This patch fixes the broken formatting strings in debug_cond()
invocations.
It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 2d16ce5..03cfefd 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2245,9 +2245,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
/* set a particular dqdqs phase */
scc_mgr_set_dqdqs_output_phase_all_ranks(read_group, p);
- debug_cond(DLEVEL == 1, "%s:%d calibrate_vfifo: g=%u \
- p=%u d=%u\n", __func__, __LINE__,
- read_group, p, d);
+ debug_cond(DLEVEL == 1,
+ "%s:%d calibrate_vfifo: g=%u p=%u d=%u\n",
+ __func__, __LINE__, read_group, p, d);
/*
* Load up the patterns used by read calibration
@@ -2257,10 +2257,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)) {
if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks
(read_group, 1, &bit_chk)) {
- debug_cond(DLEVEL == 1, "%s:%d Guaranteed read test failed:",
- __func__, __LINE__);
- debug_cond(DLEVEL == 1, " g=%u p=%u d=%u\n",
- read_group, p, d);
+ debug_cond(DLEVEL == 1,
+ "%s:%d Guaranteed read test failed: g=%u p=%u d=%u\n",
+ __func__, __LINE__, read_group, p, d);
break;
}
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 103/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 6
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (101 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 102/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 5 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 104/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 7 Marek Vasut
` (70 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
This is kind of microseries-within-series indent cleanup.
It is clear that the read_group and write_group variables
have the same value, to just make them into one variable
called rw_group. While doing this, constify the variables
as they are constant.
It is likely that this patch has checkpatch warnings, but
for the sake of not breaking the code, these are ignored.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 34 ++++++++++++++--------------------
1 file changed, 14 insertions(+), 20 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 03cfefd..6218341 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2201,30 +2201,25 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
* - DQS input phase and DQS input delay (DQ/DQS Centering)
* - we also do a per-bit deskew on the DQ lines.
*/
-static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
- uint32_t test_bgn)
+static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
{
uint32_t p, d, rank_bgn, sr;
uint32_t dtaps_per_ptap;
uint32_t bit_chk;
uint32_t grp_calibrated;
- uint32_t write_group, write_test_bgn;
uint32_t failed_substage;
- debug("%s:%d: %u %u\n", __func__, __LINE__, read_group, test_bgn);
+ debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
/* update info for sims */
reg_file_set_stage(CAL_STAGE_VFIFO);
- write_group = read_group;
- write_test_bgn = test_bgn;
-
/* USER Determine number of delay taps for each phase tap */
dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
/* update info for sims */
- reg_file_set_group(read_group);
+ reg_file_set_group(rw_group);
reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
@@ -2232,22 +2227,22 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
for (d = 0; d <= dtaps_per_ptap; d += 2) {
/*
* In RLDRAMX we may be messing the delay of pins in
- * the same write group but outside of the current read
- * the group, but that's ok because we haven't calibrated
+ * the same write rw_group but outside of the current read
+ * the rw_group, but that's ok because we haven't calibrated
* output side yet.
*/
if (d > 0) {
scc_mgr_apply_group_all_out_delay_add_all_ranks(
- write_group, d);
+ rw_group, d);
}
for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
/* set a particular dqdqs phase */
- scc_mgr_set_dqdqs_output_phase_all_ranks(read_group, p);
+ scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, p);
debug_cond(DLEVEL == 1,
"%s:%d calibrate_vfifo: g=%u p=%u d=%u\n",
- __func__, __LINE__, read_group, p, d);
+ __func__, __LINE__, rw_group, p, d);
/*
* Load up the patterns used by read calibration
@@ -2256,17 +2251,17 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
rw_mgr_mem_calibrate_read_load_patterns(0, 1);
if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)) {
if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks
- (read_group, 1, &bit_chk)) {
+ (rw_group, 1, &bit_chk)) {
debug_cond(DLEVEL == 1,
"%s:%d Guaranteed read test failed: g=%u p=%u d=%u\n",
- __func__, __LINE__, read_group, p, d);
+ __func__, __LINE__, rw_group, p, d);
break;
}
}
/* case:56390 */
if (!rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
- (write_group, read_group, test_bgn)) {
+ (rw_group, rw_group, test_bgn)) {
failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
continue;
}
@@ -2291,9 +2286,8 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
* FOM, now - do it then.
*/
if (rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
- write_group, read_group,
+ rw_group, rw_group,
test_bgn, 1, 0))
-
continue;
grp_calibrated = 0;
@@ -2306,7 +2300,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
}
/* Calibration Stage 1 failed. */
- set_failing_group_stage(write_group, CAL_STAGE_VFIFO, failed_substage);
+ set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
return 0;
/* Calibration Stage 1 completed OK. */
@@ -2317,7 +2311,7 @@ cal_done_ok:
* first case).
*/
if (d > 2)
- scc_mgr_zero_group(write_group, 1);
+ scc_mgr_zero_group(rw_group, 1);
return 1;
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 104/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 7
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (102 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 103/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 6 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 105/172] ddr: altera: Extract guaranteed write from rw_mgr_mem_calibrate_vfifo() Marek Vasut
` (69 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Mildly reorder the function so that the reg_file_set*() calls are
in the same place. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 6218341..48a90e9 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2211,19 +2211,17 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
- /* update info for sims */
+ /* Update info for sims */
+ reg_file_set_group(rw_group);
reg_file_set_stage(CAL_STAGE_VFIFO);
+ reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
- /* USER Determine number of delay taps for each phase tap */
+ failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
+
+ /* USER Determine number of delay taps for each phase tap. */
dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
- /* update info for sims */
- reg_file_set_group(rw_group);
-
- reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
- failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
-
for (d = 0; d <= dtaps_per_ptap; d += 2) {
/*
* In RLDRAMX we may be messing the delay of pins in
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 105/172] ddr: altera: Extract guaranteed write from rw_mgr_mem_calibrate_vfifo()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (103 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 104/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 7 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 106/172] ddr: altera: Extract DQS enable calibration " Marek Vasut
` (68 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Just extract this piece of functionality into separate function
to make the code better separated. This matches the division in
Altera documentation, Altera EMI_RM 2015.05.04 , section 1, the
UniPHY Calibration Stages.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 76 ++++++++++++++++++++++++++++++------------
1 file changed, 54 insertions(+), 22 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 48a90e9..57557d3 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sdram.h>
+#include <errno.h>
#include "sequencer.h"
#include "sequencer_auto.h"
#include "sequencer_auto_ac_init.h"
@@ -2187,6 +2188,53 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
}
/**
+ * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
+ * @rw_group: Read/Write Group
+ * @phase: DQ/DQS phase
+ *
+ * Because initially no communication ca be reliably performed with the memory
+ * device, the sequencer uses a guaranteed write mechanism to write data into
+ * the memory device.
+ */
+static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
+ const u32 phase)
+{
+ u32 bit_chk;
+ int ret;
+
+ /* Set a particular DQ/DQS phase. */
+ scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
+
+ debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
+ __func__, __LINE__, rw_group, phase);
+
+ /*
+ * Altera EMI_RM 2015.05.04 :: Figure 1-25
+ * Load up the patterns used by read calibration using the
+ * current DQDQS phase.
+ */
+ rw_mgr_mem_calibrate_read_load_patterns(0, 1);
+
+ if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
+ return 0;
+
+ /*
+ * Altera EMI_RM 2015.05.04 :: Figure 1-26
+ * Back-to-Back reads of the patterns used for calibration.
+ */
+ ret = rw_mgr_mem_calibrate_read_test_patterns_all_ranks(rw_group, 1,
+ &bit_chk);
+ if (!ret) { /* FIXME: 0 means failure in this old code :-( */
+ debug_cond(DLEVEL == 1,
+ "%s:%d Guaranteed read test failed: g=%u p=%u\n",
+ __func__, __LINE__, rw_group, phase);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+/**
* rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
* @rw_group: Read/Write Group
* @test_bgn: Rank at which the test begins
@@ -2205,10 +2253,11 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
{
uint32_t p, d, rank_bgn, sr;
uint32_t dtaps_per_ptap;
- uint32_t bit_chk;
uint32_t grp_calibrated;
uint32_t failed_substage;
+ int ret;
+
debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
/* Update info for sims */
@@ -2235,27 +2284,10 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
}
for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
- /* set a particular dqdqs phase */
- scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, p);
-
- debug_cond(DLEVEL == 1,
- "%s:%d calibrate_vfifo: g=%u p=%u d=%u\n",
- __func__, __LINE__, rw_group, p, d);
-
- /*
- * Load up the patterns used by read calibration
- * using current DQDQS phase.
- */
- rw_mgr_mem_calibrate_read_load_patterns(0, 1);
- if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)) {
- if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks
- (rw_group, 1, &bit_chk)) {
- debug_cond(DLEVEL == 1,
- "%s:%d Guaranteed read test failed: g=%u p=%u d=%u\n",
- __func__, __LINE__, rw_group, p, d);
- break;
- }
- }
+ /* 1) Guaranteed Write */
+ ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
+ if (ret)
+ break;
/* case:56390 */
if (!rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 106/172] ddr: altera: Extract DQS enable calibration from rw_mgr_mem_calibrate_vfifo()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (104 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 105/172] ddr: altera: Extract guaranteed write from rw_mgr_mem_calibrate_vfifo() Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 107/172] ddr: altera: Extract Centering DQ/DQS " Marek Vasut
` (67 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Just extract this piece of functionality into separate function
to make the code better separated. This matches the division in
Altera documentation, Altera EMI_RM 2015.05.04 , section 1, the
UniPHY Calibration Stages.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 32 +++++++++++++++++++++++++++++---
1 file changed, 29 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 57557d3..6fa07cf 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2235,6 +2235,31 @@ static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
}
/**
+ * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
+ * @rw_group: Read/Write Group
+ * @test_bgn: Rank at which the test begins
+ *
+ * DQS enable calibration ensures reliable capture of the DQ signal without
+ * glitches on the DQS line.
+ */
+static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
+ const u32 test_bgn)
+{
+ int ret;
+
+ /*
+ * Altera EMI_RM 2015.05.04 :: Figure 1-27
+ * DQS and DQS Eanble Signal Relationships.
+ */
+ ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay(
+ rw_group, rw_group, test_bgn);
+ if (!ret) /* FIXME: 0 means failure in this old code :-( */
+ return -EIO;
+
+ return 0;
+}
+
+/**
* rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
* @rw_group: Read/Write Group
* @test_bgn: Rank at which the test begins
@@ -2289,9 +2314,10 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
if (ret)
break;
- /* case:56390 */
- if (!rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
- (rw_group, rw_group, test_bgn)) {
+ /* 2) DQS Enable Calibration */
+ ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
+ test_bgn);
+ if (ret) {
failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
continue;
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 107/172] ddr: altera: Extract Centering DQ/DQS from rw_mgr_mem_calibrate_vfifo()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (105 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 106/172] ddr: altera: Extract DQS enable calibration " Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 108/172] ddr: altera: Minor rw_mgr_mem_calibrate_read_load_patterns() cleanup Marek Vasut
` (66 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Just extract this piece of functionality into separate function
to make the code better separated. This matches the division in
Altera documentation, Altera EMI_RM 2015.05.04 , section 1, the
UniPHY Calibration Stages.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 84 ++++++++++++++++++++++++++++--------------
1 file changed, 57 insertions(+), 27 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 6fa07cf..9c69857 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2260,6 +2260,53 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
}
/**
+ * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
+ * @rw_group: Read/Write Group
+ * @test_bgn: Rank at which the test begins
+ * @use_read_test: Perform a read test
+ * @update_fom: Update FOM
+ *
+ * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
+ * within a group.
+ */
+static int
+rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
+ const int use_read_test,
+ const int update_fom)
+
+{
+ int ret, grp_calibrated;
+ u32 rank_bgn, sr;
+
+ /*
+ * Altera EMI_RM 2015.05.04 :: Figure 1-28
+ * Read per-bit deskew can be done on a per shadow register basis.
+ */
+ grp_calibrated = 1;
+ for (rank_bgn = 0, sr = 0;
+ rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
+ rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
+ /* Check if this set of ranks should be skipped entirely. */
+ if (param->skip_shadow_regs[sr])
+ continue;
+
+ ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
+ rw_group, test_bgn,
+ use_read_test,
+ update_fom);
+ if (ret)
+ continue;
+
+ grp_calibrated = 0;
+ }
+
+ if (!grp_calibrated)
+ return -EIO;
+
+ return 0;
+}
+
+/**
* rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
* @rw_group: Read/Write Group
* @test_bgn: Rank at which the test begins
@@ -2276,9 +2323,8 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
*/
static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
{
- uint32_t p, d, rank_bgn, sr;
+ uint32_t p, d;
uint32_t dtaps_per_ptap;
- uint32_t grp_calibrated;
uint32_t failed_substage;
int ret;
@@ -2322,36 +2368,20 @@ static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
continue;
}
+ /* 3) Centering DQ/DQS */
/*
- * USER Read per-bit deskew can be done on a
- * per shadow register basis.
+ * If doing read after write calibration, do not update
+ * FOM now. Do it then.
*/
- grp_calibrated = 1;
- for (rank_bgn = 0, sr = 0;
- rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
- rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
- /*
- * Determine if this set of ranks
- * should be skipped entirely.
- */
- if (param->skip_shadow_regs[sr])
- continue;
- /*
- * If doing read after write
- * calibration, do not update
- * FOM, now - do it then.
- */
- if (rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
- rw_group, rw_group,
- test_bgn, 1, 0))
- continue;
-
- grp_calibrated = 0;
+ ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
+ test_bgn, 1, 0);
+ if (ret) {
failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
+ continue;
}
- if (grp_calibrated)
- goto cal_done_ok;
+ /* All done. */
+ goto cal_done_ok;
}
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 108/172] ddr: altera: Minor rw_mgr_mem_calibrate_read_load_patterns() cleanup
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (106 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 107/172] ddr: altera: Extract Centering DQ/DQS " Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 109/172] ddr: altera: Zap rw_mgr_mem_calibrate_read_test_patterns_all_ranks() Marek Vasut
` (65 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Just do an easy data type cleanup of this function, no functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 20 ++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 9c69857..a4cba69 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1114,15 +1114,23 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks
num_tries, bit_chk, 1);
}
-/* load up the patterns we are going to use during a read test */
-static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,
- uint32_t all_ranks)
+/**
+ * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
+ * @rank_bgn: Rank number
+ * @all_ranks: Test all ranks
+ *
+ * Load up the patterns we are going to use during a read test.
+ */
+static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
+ const int all_ranks)
{
- uint32_t r;
- uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
- (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
+ const u32 rank_end = all_ranks ?
+ RW_MGR_MEM_NUMBER_OF_RANKS :
+ (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
+ u32 r;
debug("%s:%d\n", __func__, __LINE__);
+
for (r = rank_bgn; r < rank_end; r++) {
if (param->skip_ranks[r])
/* request to skip the rank */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 109/172] ddr: altera: Zap rw_mgr_mem_calibrate_read_test_patterns_all_ranks()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (107 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 108/172] ddr: altera: Minor rw_mgr_mem_calibrate_read_load_patterns() cleanup Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 110/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_patterns() Marek Vasut
` (64 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
This function is called from one single place and it's sole purpose
is to call one single function with slightly modified arguments.
Zap this function to skip this useless intermediate step.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index a4cba69..e17e601 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1107,13 +1107,6 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
return *bit_chk == param->read_correct_mask;
}
-static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks
- (uint32_t group, uint32_t num_tries, uint32_t *bit_chk)
-{
- return rw_mgr_mem_calibrate_read_test_patterns(0, group,
- num_tries, bit_chk, 1);
-}
-
/**
* rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
* @rank_bgn: Rank number
@@ -2230,8 +2223,8 @@ static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
* Altera EMI_RM 2015.05.04 :: Figure 1-26
* Back-to-Back reads of the patterns used for calibration.
*/
- ret = rw_mgr_mem_calibrate_read_test_patterns_all_ranks(rw_group, 1,
- &bit_chk);
+ ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1,
+ &bit_chk, 1);
if (!ret) { /* FIXME: 0 means failure in this old code :-( */
debug_cond(DLEVEL == 1,
"%s:%d Guaranteed read test failed: g=%u p=%u\n",
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 110/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_patterns()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (108 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 109/172] ddr: altera: Zap rw_mgr_mem_calibrate_read_test_patterns_all_ranks() Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 111/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 1 Marek Vasut
` (63 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Rework this function such that the code is more readable. Zap
unused parameter "num_tries" while at it. Also wrap parameter
"bit_chk" into this function as it's value is not used outside.
Finally, fix the return value from this function to match the
common expectation, where 0 means success.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 96 ++++++++++++++++++++++--------------------
1 file changed, 50 insertions(+), 46 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index e17e601..8674a05 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1036,31 +1036,42 @@ static void rw_mgr_mem_handoff(void)
*/
}
-/*
- * performs a guaranteed read on the patterns we are going to use during a
- * read test to ensure memory works
+/**
+ * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
+ * @rank_bgn: Rank number
+ * @group: Read/Write Group
+ * @all_ranks: Test all ranks
+ *
+ * Performs a guaranteed read on the patterns we are going to use during a
+ * read test to ensure memory works.
*/
-static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
- uint32_t group, uint32_t num_tries, uint32_t *bit_chk,
- uint32_t all_ranks)
+static int
+rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
+ const u32 all_ranks)
{
- uint32_t r, vg;
- uint32_t correct_mask_vg;
- uint32_t tmp_bit_chk;
- uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
- (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
- uint32_t addr;
- uint32_t base_rw_mgr;
+ const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+ const u32 addr_offset =
+ (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
+ const u32 rank_end = all_ranks ?
+ RW_MGR_MEM_NUMBER_OF_RANKS :
+ (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
+ const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
+ const u32 correct_mask_vg = param->read_correct_mask_vg;
- *bit_chk = param->read_correct_mask;
- correct_mask_vg = param->read_correct_mask_vg;
+ u32 tmp_bit_chk, base_rw_mgr, bit_chk;
+ int vg, r;
+ int ret = 0;
+
+ bit_chk = param->read_correct_mask;
for (r = rank_bgn; r < rank_end; r++) {
+ /* Request to skip the rank */
if (param->skip_ranks[r])
- /* request to skip the rank */
continue;
- /* set rank */
+ /* Set rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
/* Load up a constant bursts of read commands */
@@ -1073,38 +1084,36 @@ static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
tmp_bit_chk = 0;
- for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
- /* reset the fifos to get pointers to known state */
-
+ for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
+ vg >= 0; vg--) {
+ /* Reset the FIFOs to get pointers to known state. */
writel(0, &phy_mgr_cmd->fifo_reset);
writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RESET_READ_DATAPATH_OFFSET);
-
- tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
- / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
-
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(RW_MGR_GUARANTEED_READ, addr +
- ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
- vg) << 2));
+ writel(RW_MGR_GUARANTEED_READ,
+ addr + addr_offset + (vg << 2));
base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
- tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
-
- if (vg == 0)
- break;
+ tmp_bit_chk <<= shift_ratio;
+ tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
}
- *bit_chk &= tmp_bit_chk;
+
+ bit_chk &= tmp_bit_chk;
}
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
- debug_cond(DLEVEL == 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) =>\
- %lu\n", __func__, __LINE__, group, *bit_chk, param->read_correct_mask,
- (long unsigned int)(*bit_chk == param->read_correct_mask));
- return *bit_chk == param->read_correct_mask;
+
+ if (bit_chk != param->read_correct_mask)
+ ret = -EIO;
+
+ debug_cond(DLEVEL == 1,
+ "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
+ __func__, __LINE__, group, bit_chk,
+ param->read_correct_mask, ret);
+
+ return ret;
}
/**
@@ -2200,7 +2209,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
const u32 phase)
{
- u32 bit_chk;
int ret;
/* Set a particular DQ/DQS phase. */
@@ -2223,16 +2231,12 @@ static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
* Altera EMI_RM 2015.05.04 :: Figure 1-26
* Back-to-Back reads of the patterns used for calibration.
*/
- ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1,
- &bit_chk, 1);
- if (!ret) { /* FIXME: 0 means failure in this old code :-( */
+ ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
+ if (ret)
debug_cond(DLEVEL == 1,
"%s:%d Guaranteed read test failed: g=%u p=%u\n",
__func__, __LINE__, rw_group, phase);
- return -EIO;
- }
-
- return 0;
+ return ret;
}
/**
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 111/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 1
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (109 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 110/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_patterns() Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 112/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 2 Marek Vasut
` (62 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Start cleaning up this function. In the first part, just fix
the incorrectly broken debug strings and fix return value to
respect the common convention.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 61 +++++++++++++++++++++---------------------
1 file changed, 30 insertions(+), 31 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 8674a05..c33a12a 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1770,57 +1770,59 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
* Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
* dq_in_delay values
*/
-static uint32_t
+static int
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
(uint32_t write_group, uint32_t read_group, uint32_t test_bgn)
{
- uint32_t found;
- uint32_t i;
- uint32_t p;
- uint32_t d;
- uint32_t r;
-
- const uint32_t delay_step = IO_IO_IN_DELAY_MAX /
- (RW_MGR_MEM_DQ_PER_READ_DQS-1);
- /* we start at zero, so have one less dq to devide among */
+ /* We start at zero, so have one less dq to devide among */
+ const u32 delay_step = IO_IO_IN_DELAY_MAX /
+ (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
+ int found;
+ u32 i, p, d, r;
- debug("%s:%d (%u,%u,%u)", __func__, __LINE__, write_group, read_group,
- test_bgn);
-
- /* try different dq_in_delays since the dq path is shorter than dqs */
+ debug("%s:%d (%u,%u,%u)\n", __func__, __LINE__,
+ write_group, read_group, test_bgn);
+ /* Try different dq_in_delays since the DQ path is shorter than DQS. */
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
- for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++, d += delay_step) {
- debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_\
- vfifo_find_dqs_", __func__, __LINE__);
- debug_cond(DLEVEL == 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
- write_group, read_group);
- debug_cond(DLEVEL == 1, "r=%u, i=%u p=%u d=%u\n", r, i , p, d);
+ for (i = 0, p = test_bgn, d = 0;
+ i < RW_MGR_MEM_DQ_PER_READ_DQS;
+ i++, p++, d += delay_step) {
+ debug_cond(DLEVEL == 1,
+ "%s:%d: g=%u/%u r=%u i=%u p=%u d=%u\n",
+ __func__, __LINE__, write_group, read_group,
+ r, i, p, d);
+
scc_mgr_set_dq_in_delay(p, d);
scc_mgr_load_dq(p);
}
+
writel(0, &sdr_scc_mgr->update);
}
found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
- debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_vfifo_find_dqs_\
- en_phase_sweep_dq", __func__, __LINE__);
- debug_cond(DLEVEL == 1, "_in_delay: g=%u/%u found=%u; Reseting delay \
- chain to zero\n", write_group, read_group, found);
+ debug_cond(DLEVEL == 1,
+ "%s:%d: g=%u/%u found=%u; Reseting delay chain to zero\n",
+ __func__, __LINE__, write_group, read_group, found);
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
- for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS;
- i++, p++) {
+ for (i = 0, p = test_bgn;
+ i < RW_MGR_MEM_DQ_PER_READ_DQS;
+ i++, p++) {
scc_mgr_set_dq_in_delay(p, 0);
scc_mgr_load_dq(p);
}
+
writel(0, &sdr_scc_mgr->update);
}
- return found;
+ if (!found)
+ return -EINVAL;
+
+ return 0;
}
/* per-bit deskew DQ and center */
@@ -2258,10 +2260,7 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
*/
ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay(
rw_group, rw_group, test_bgn);
- if (!ret) /* FIXME: 0 means failure in this old code :-( */
- return -EIO;
-
- return 0;
+ return ret;
}
/**
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 112/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 2
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (110 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 111/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 1 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 113/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 3 Marek Vasut
` (61 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
The read_group and write_group params have the same value for all (one)
invocations of this function, just merge them into a single param.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index c33a12a..a1be735 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1772,7 +1772,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
*/
static int
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
-(uint32_t write_group, uint32_t read_group, uint32_t test_bgn)
+(const u32 rw_group, const u32 test_bgn)
{
/* We start at zero, so have one less dq to devide among */
const u32 delay_step = IO_IO_IN_DELAY_MAX /
@@ -1780,8 +1780,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
int found;
u32 i, p, d, r;
- debug("%s:%d (%u,%u,%u)\n", __func__, __LINE__,
- write_group, read_group, test_bgn);
+ debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
/* Try different dq_in_delays since the DQ path is shorter than DQS. */
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
@@ -1790,9 +1789,8 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
i < RW_MGR_MEM_DQ_PER_READ_DQS;
i++, p++, d += delay_step) {
debug_cond(DLEVEL == 1,
- "%s:%d: g=%u/%u r=%u i=%u p=%u d=%u\n",
- __func__, __LINE__, write_group, read_group,
- r, i, p, d);
+ "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
+ __func__, __LINE__, rw_group, r, i, p, d);
scc_mgr_set_dq_in_delay(p, d);
scc_mgr_load_dq(p);
@@ -1801,11 +1799,11 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
writel(0, &sdr_scc_mgr->update);
}
- found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
+ found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
debug_cond(DLEVEL == 1,
- "%s:%d: g=%u/%u found=%u; Reseting delay chain to zero\n",
- __func__, __LINE__, write_group, read_group, found);
+ "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
+ __func__, __LINE__, rw_group, found);
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
@@ -2259,7 +2257,7 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
* DQS and DQS Eanble Signal Relationships.
*/
ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay(
- rw_group, rw_group, test_bgn);
+ rw_group, test_bgn);
return ret;
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 113/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 3
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (111 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 112/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 2 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 114/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 4 Marek Vasut
` (60 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Replace at least one of the loops in this function with call of a
standard function call instead of the ad-hoc implementation. The
other one cannot be replaced, since the delay is incremented for
each group.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index a1be735..6df534f 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1807,13 +1807,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
- for (i = 0, p = test_bgn;
- i < RW_MGR_MEM_DQ_PER_READ_DQS;
- i++, p++) {
- scc_mgr_set_dq_in_delay(p, 0);
- scc_mgr_load_dq(p);
- }
-
+ scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
writel(0, &sdr_scc_mgr->update);
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 114/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 4
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (112 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 113/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 3 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 115/172] ddr: altera: Clean up sdr_find_window_centre() part 1 Marek Vasut
` (59 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
This function is only invoked from rw_mgr_mem_calibrate_dqs_enable_calibration()
and at this point, it is just one level of indirection, so wrap the
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() into
rw_mgr_mem_calibrate_dqs_enable_calibration() to get rid of the level
of indirection.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 103 +++++++++++++++++++----------------------
1 file changed, 47 insertions(+), 56 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 6df534f..f696641 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1766,57 +1766,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
return 1;
}
-/*
- * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
- * dq_in_delay values
- */
-static int
-rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
-(const u32 rw_group, const u32 test_bgn)
-{
- /* We start at zero, so have one less dq to devide among */
- const u32 delay_step = IO_IO_IN_DELAY_MAX /
- (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
- int found;
- u32 i, p, d, r;
-
- debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
-
- /* Try different dq_in_delays since the DQ path is shorter than DQS. */
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
- r += NUM_RANKS_PER_SHADOW_REG) {
- for (i = 0, p = test_bgn, d = 0;
- i < RW_MGR_MEM_DQ_PER_READ_DQS;
- i++, p++, d += delay_step) {
- debug_cond(DLEVEL == 1,
- "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
- __func__, __LINE__, rw_group, r, i, p, d);
-
- scc_mgr_set_dq_in_delay(p, d);
- scc_mgr_load_dq(p);
- }
-
- writel(0, &sdr_scc_mgr->update);
- }
-
- found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
-
- debug_cond(DLEVEL == 1,
- "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
- __func__, __LINE__, rw_group, found);
-
- for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
- r += NUM_RANKS_PER_SHADOW_REG) {
- scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
- writel(0, &sdr_scc_mgr->update);
- }
-
- if (!found)
- return -EINVAL;
-
- return 0;
-}
-
/* per-bit deskew DQ and center */
static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
@@ -2244,15 +2193,57 @@ static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
const u32 test_bgn)
{
- int ret;
-
/*
* Altera EMI_RM 2015.05.04 :: Figure 1-27
* DQS and DQS Eanble Signal Relationships.
*/
- ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay(
- rw_group, test_bgn);
- return ret;
+
+ /* We start at zero, so have one less dq to devide among */
+ const u32 delay_step = IO_IO_IN_DELAY_MAX /
+ (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
+ int found;
+ u32 i, p, d, r;
+
+ debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
+
+ /* Try different dq_in_delays since the DQ path is shorter than DQS. */
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ r += NUM_RANKS_PER_SHADOW_REG) {
+ for (i = 0, p = test_bgn, d = 0;
+ i < RW_MGR_MEM_DQ_PER_READ_DQS;
+ i++, p++, d += delay_step) {
+ debug_cond(DLEVEL == 1,
+ "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
+ __func__, __LINE__, rw_group, r, i, p, d);
+
+ scc_mgr_set_dq_in_delay(p, d);
+ scc_mgr_load_dq(p);
+ }
+
+ writel(0, &sdr_scc_mgr->update);
+ }
+
+ /*
+ * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
+ * dq_in_delay values
+ */
+ found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
+
+ debug_cond(DLEVEL == 1,
+ "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
+ __func__, __LINE__, rw_group, found);
+
+ for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
+ r += NUM_RANKS_PER_SHADOW_REG) {
+ scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
+ writel(0, &sdr_scc_mgr->update);
+ }
+
+ if (!found)
+ return -EINVAL;
+
+ return 0;
+
}
/**
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 115/172] ddr: altera: Clean up sdr_find_window_centre() part 1
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (113 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 114/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 4 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 116/172] ddr: altera: Clean up sdr_find_window_centre() part 2 Marek Vasut
` (58 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Clean up the arguments of this function. Most of the pointers
passed into the function are either not needed at all, or can
be passed as value instead of reference. Also fix the broken
multiline debug strings. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 64 +++++++++++++++++++++---------------------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index f696641..4c4b36c 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1480,40 +1480,41 @@ static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
}
}
-static int sdr_find_window_centre(uint32_t *grp, uint32_t *bit_chk,
- uint32_t *work_bgn, uint32_t *v, uint32_t *d,
- uint32_t *p, uint32_t *work_mid,
- uint32_t *work_end)
+static int sdr_find_window_centre(const u32 grp, const u32 work_bgn,
+ const u32 work_end, const u32 val)
{
- int i;
+ u32 bit_chk, work_mid, v = val;
int tmp_delay = 0;
+ int i, p, d;
- *work_mid = (*work_bgn + *work_end) / 2;
+ work_mid = (work_bgn + work_end) / 2;
debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
- *work_bgn, *work_end, *work_mid);
+ work_bgn, work_end, work_mid);
/* Get the middle delay to be less than a VFIFO delay */
- for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX;
- (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
+ for (p = 0; p <= IO_DQS_EN_PHASE_MAX;
+ p++, tmp_delay += IO_DELAY_PER_OPA_TAP)
;
+
debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
- while (*work_mid > tmp_delay)
- *work_mid -= tmp_delay;
- debug_cond(DLEVEL == 2, "new work_mid %d\n", *work_mid);
+ while (work_mid > tmp_delay)
+ work_mid -= tmp_delay;
+ debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
tmp_delay = 0;
- for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX && tmp_delay < *work_mid;
- (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
+ for (p = 0; p <= IO_DQS_EN_PHASE_MAX && tmp_delay < work_mid;
+ p++, tmp_delay += IO_DELAY_PER_OPA_TAP)
;
tmp_delay -= IO_DELAY_PER_OPA_TAP;
- debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", (*p) - 1, tmp_delay);
- for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_mid; (*d)++,
- tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP)
+ debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p - 1, tmp_delay);
+
+ for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < work_mid;
+ d++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP)
;
- debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", *d, tmp_delay);
+ debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
- scc_mgr_set_dqs_en_phase_all_ranks(*grp, (*p) - 1);
- scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
+ scc_mgr_set_dqs_en_phase_all_ranks(grp, p - 1);
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
/*
* push vfifo until we can successfully calibrate. We can do this
@@ -1521,22 +1522,25 @@ static int sdr_find_window_centre(uint32_t *grp, uint32_t *bit_chk,
*/
for (i = 0; i < VFIFO_SIZE; i++) {
debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
- *v);
- if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
+ v);
+ if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT,
- bit_chk, 0)) {
+ &bit_chk, 0)) {
break;
}
/* fiddle with FIFO */
- rw_mgr_incr_vfifo(*grp, v);
+ rw_mgr_incr_vfifo(grp, &v);
}
if (i >= VFIFO_SIZE) {
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center: \
- failed\n", __func__, __LINE__);
+ debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
+ __func__, __LINE__);
return 0;
} else {
+ debug_cond(DLEVEL == 2,
+ "%s:%d center: found: vfifo=%u ptap=%u dtap=%u\n",
+ __func__, __LINE__, v, p - 1, d);
return 1;
}
}
@@ -1548,7 +1552,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
uint32_t max_working_cnt;
uint32_t bit_chk;
uint32_t dtaps_per_ptap;
- uint32_t work_bgn, work_mid, work_end;
+ uint32_t work_bgn, work_end;
uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
debug("%s:%d %u\n", __func__, __LINE__, grp);
@@ -1756,13 +1760,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* ******************************************** */
/* * step 6: Find the centre of the window * */
- if (sdr_find_window_centre(&grp, &bit_chk, &work_bgn, &v, &d, &p,
- &work_mid, &work_end) == 0)
+ if (sdr_find_window_centre(grp, work_bgn, work_end, v) == 0)
return 0;
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center found: \
- vfifo=%u ptap=%u dtap=%u\n", __func__, __LINE__,
- v, p-1, d);
return 1;
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 116/172] ddr: altera: Clean up sdr_find_window_centre() part 2
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (114 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 115/172] ddr: altera: Clean up sdr_find_window_centre() part 1 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 117/172] ddr: altera: Clean up sdr_find_window_centre() part 3 Marek Vasut
` (57 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
This function is a treasure trove of ad-hoc iterative
implementations of mathematical functions. Replace all
of those with their non-iterative counterpart.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 31 +++++++++++++++----------------
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 4c4b36c..eb246cc 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1492,28 +1492,27 @@ static int sdr_find_window_centre(const u32 grp, const u32 work_bgn,
debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
work_bgn, work_end, work_mid);
/* Get the middle delay to be less than a VFIFO delay */
- for (p = 0; p <= IO_DQS_EN_PHASE_MAX;
- p++, tmp_delay += IO_DELAY_PER_OPA_TAP)
- ;
+ tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
- while (work_mid > tmp_delay)
- work_mid -= tmp_delay;
+ work_mid %= tmp_delay;
debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
- tmp_delay = 0;
- for (p = 0; p <= IO_DQS_EN_PHASE_MAX && tmp_delay < work_mid;
- p++, tmp_delay += IO_DELAY_PER_OPA_TAP)
- ;
- tmp_delay -= IO_DELAY_PER_OPA_TAP;
- debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p - 1, tmp_delay);
+ tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
+ if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
+ tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
+ p = tmp_delay / IO_DELAY_PER_OPA_TAP;
+
+ debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
+
+ d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
+ if (d > IO_DQS_EN_DELAY_MAX)
+ d = IO_DQS_EN_DELAY_MAX;
+ tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
- for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < work_mid;
- d++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP)
- ;
debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
- scc_mgr_set_dqs_en_phase_all_ranks(grp, p - 1);
+ scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
/*
@@ -1540,7 +1539,7 @@ static int sdr_find_window_centre(const u32 grp, const u32 work_bgn,
} else {
debug_cond(DLEVEL == 2,
"%s:%d center: found: vfifo=%u ptap=%u dtap=%u\n",
- __func__, __LINE__, v, p - 1, d);
+ __func__, __LINE__, v, p, d);
return 1;
}
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 117/172] ddr: altera: Clean up sdr_find_window_centre() part 3
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (115 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 116/172] ddr: altera: Clean up sdr_find_window_centre() part 2 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 118/172] ddr: altera: Clean up sdr_*_phase() part 1 Marek Vasut
` (56 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Reorder the end of the function a little by moving the conditional
debug output around a little. Rename the function from _centre() to
_center(). Document the function in kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 35 ++++++++++++++++++++---------------
1 file changed, 20 insertions(+), 15 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index eb246cc..451e141 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1480,7 +1480,16 @@ static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
}
}
-static int sdr_find_window_centre(const u32 grp, const u32 work_bgn,
+/**
+ * sdr_find_window_center() - Find center of the working DQS window.
+ * @grp: Read/Write group
+ * @work_bgn: First working settings
+ * @work_end: Last working settings
+ * @val: VFIFO value
+ *
+ * Find center of the working DQS enable window.
+ */
+static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
const u32 work_end, const u32 val)
{
u32 bit_chk, work_mid, v = val;
@@ -1525,23 +1534,19 @@ static int sdr_find_window_centre(const u32 grp, const u32 work_bgn,
if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT,
&bit_chk, 0)) {
- break;
+ debug_cond(DLEVEL == 2,
+ "%s:%d center: found: vfifo=%u ptap=%u dtap=%u\n",
+ __func__, __LINE__, v, p, d);
+ return 0;
}
- /* fiddle with FIFO */
+ /* Fiddle with FIFO. */
rw_mgr_incr_vfifo(grp, &v);
}
- if (i >= VFIFO_SIZE) {
- debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
- __func__, __LINE__);
- return 0;
- } else {
- debug_cond(DLEVEL == 2,
- "%s:%d center: found: vfifo=%u ptap=%u dtap=%u\n",
- __func__, __LINE__, v, p, d);
- return 1;
- }
+ debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
+ __func__, __LINE__);
+ return -EINVAL;
}
/* find a good dqs enable to use */
@@ -1759,8 +1764,8 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* ******************************************** */
/* * step 6: Find the centre of the window * */
- if (sdr_find_window_centre(grp, work_bgn, work_end, v) == 0)
- return 0;
+ if (sdr_find_window_centre(grp, work_bgn, work_end, v))
+ return 0; /* FIXME: Old code, return 0 means failure :-( */
return 1;
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 118/172] ddr: altera: Clean up sdr_*_phase() part 1
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (116 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 117/172] ddr: altera: Clean up sdr_find_window_centre() part 3 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 119/172] ddr: altera: Clean up sdr_*_phase() part 2 Marek Vasut
` (55 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Rename find_working_phase() to sdr_working_phase() for the
sake of consistency.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 451e141..61ddc2c 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1332,7 +1332,7 @@ static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
}
}
-static int find_working_phase(uint32_t *grp, uint32_t *bit_chk,
+static int sdr_working_phase(uint32_t *grp, uint32_t *bit_chk,
uint32_t dtaps_per_ptap, uint32_t *work_bgn,
uint32_t *v, uint32_t *d, uint32_t *p,
uint32_t *i, uint32_t *max_working_cnt)
@@ -1579,8 +1579,8 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* ******************************************************** */
/* * step 2: find first working phase, increment in ptaps * */
work_bgn = 0;
- if (find_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
- &p, &i, &max_working_cnt) == 0)
+ if (sdr_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
+ &p, &i, &max_working_cnt) == 0)
return 0;
work_end = work_bgn;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 119/172] ddr: altera: Clean up sdr_*_phase() part 2
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (117 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 118/172] ddr: altera: Clean up sdr_*_phase() part 1 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 120/172] ddr: altera: Clean up sdr_*_phase() part 3 Marek Vasut
` (54 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Fix the arguments passed to these functions. The grp argument
does not have to be passed via reference, it's never modified
within either of those functions, so make it into a value.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 40 ++++++++++++++++++++--------------------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 61ddc2c..f4101b1 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1332,7 +1332,7 @@ static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
}
}
-static int sdr_working_phase(uint32_t *grp, uint32_t *bit_chk,
+static int sdr_working_phase(uint32_t grp, uint32_t *bit_chk,
uint32_t dtaps_per_ptap, uint32_t *work_bgn,
uint32_t *v, uint32_t *d, uint32_t *p,
uint32_t *i, uint32_t *max_working_cnt)
@@ -1344,16 +1344,16 @@ static int sdr_working_phase(uint32_t *grp, uint32_t *bit_chk,
for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
*work_bgn = tmp_delay;
- scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
IO_DELAY_PER_OPA_TAP) {
- scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
+ scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
test_status =
rw_mgr_mem_calibrate_read_test_all_ranks
- (*grp, 1, PASS_ONE_BIT, bit_chk, 0);
+ (grp, 1, PASS_ONE_BIT, bit_chk, 0);
if (test_status) {
*max_working_cnt = 1;
@@ -1367,7 +1367,7 @@ static int sdr_working_phase(uint32_t *grp, uint32_t *bit_chk,
if (*p > IO_DQS_EN_PHASE_MAX)
/* fiddle with FIFO */
- rw_mgr_incr_vfifo(*grp, v);
+ rw_mgr_incr_vfifo(grp, v);
}
if (found_begin)
@@ -1384,7 +1384,7 @@ static int sdr_working_phase(uint32_t *grp, uint32_t *bit_chk,
}
}
-static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
+static void sdr_backup_phase(uint32_t grp, uint32_t *bit_chk,
uint32_t *work_bgn, uint32_t *v, uint32_t *d,
uint32_t *p, uint32_t *max_working_cnt)
{
@@ -1394,18 +1394,18 @@ static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
/* Special case code for backing up a phase */
if (*p == 0) {
*p = IO_DQS_EN_PHASE_MAX;
- rw_mgr_decr_vfifo(*grp, v);
+ rw_mgr_decr_vfifo(grp, v);
} else {
(*p)--;
}
tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
- scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
+ scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
(*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
- scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
- if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
+ if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT,
bit_chk, 0)) {
found_begin = 1;
@@ -1425,13 +1425,13 @@ static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
(*p)++;
if (*p > IO_DQS_EN_PHASE_MAX) {
*p = 0;
- rw_mgr_incr_vfifo(*grp, v);
+ rw_mgr_incr_vfifo(grp, v);
}
- scc_mgr_set_dqs_en_delay_all_ranks(*grp, 0);
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
}
-static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
+static int sdr_nonworking_phase(uint32_t grp, uint32_t *bit_chk,
uint32_t *work_bgn, uint32_t *v, uint32_t *d,
uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
uint32_t *work_end)
@@ -1443,16 +1443,16 @@ static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
if (*p > IO_DQS_EN_PHASE_MAX) {
/* fiddle with FIFO */
*p = 0;
- rw_mgr_incr_vfifo(*grp, v);
+ rw_mgr_incr_vfifo(grp, v);
}
for (; *i < VFIFO_SIZE + 1; (*i)++) {
for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
+= IO_DELAY_PER_OPA_TAP) {
- scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
+ scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
if (!rw_mgr_mem_calibrate_read_test_all_ranks
- (*grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
+ (grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
found_end = 1;
break;
} else {
@@ -1465,7 +1465,7 @@ static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
if (*p > IO_DQS_EN_PHASE_MAX) {
/* fiddle with FIFO */
- rw_mgr_incr_vfifo(*grp, v);
+ rw_mgr_incr_vfifo(grp, v);
*p = 0;
}
}
@@ -1579,7 +1579,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* ******************************************************** */
/* * step 2: find first working phase, increment in ptaps * */
work_bgn = 0;
- if (sdr_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
+ if (sdr_working_phase(grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
&p, &i, &max_working_cnt) == 0)
return 0;
@@ -1595,13 +1595,13 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* * step 3a: if we have room, back off by one and
increment in dtaps * */
- sdr_backup_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
+ sdr_backup_phase(grp, &bit_chk, &work_bgn, &v, &d, &p,
&max_working_cnt);
/* ********************************************************* */
/* * step 4a: go forward from working phase to non working
phase, increment in ptaps * */
- if (sdr_nonworking_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
+ if (sdr_nonworking_phase(grp, &bit_chk, &work_bgn, &v, &d, &p,
&i, &max_working_cnt, &work_end) == 0)
return 0;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 120/172] ddr: altera: Clean up sdr_*_phase() part 3
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (118 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 119/172] ddr: altera: Clean up sdr_*_phase() part 2 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 121/172] ddr: altera: Clean up sdr_*_phase() part 4 Marek Vasut
` (53 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Fix the arguments passed to these functions. The bit_chk is
overriden by rw_mgr_mem_calibrate_read_test_all_ranks() which
is invoked by all three sdr_*_phase() functions, so just make
this into local variable.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 21 ++++++++++++---------
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index f4101b1..c62bec5 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1332,7 +1332,7 @@ static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
}
}
-static int sdr_working_phase(uint32_t grp, uint32_t *bit_chk,
+static int sdr_working_phase(uint32_t grp,
uint32_t dtaps_per_ptap, uint32_t *work_bgn,
uint32_t *v, uint32_t *d, uint32_t *p,
uint32_t *i, uint32_t *max_working_cnt)
@@ -1340,6 +1340,7 @@ static int sdr_working_phase(uint32_t grp, uint32_t *bit_chk,
uint32_t found_begin = 0;
uint32_t tmp_delay = 0;
uint32_t test_status;
+ u32 bit_chk;
for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
@@ -1353,7 +1354,7 @@ static int sdr_working_phase(uint32_t grp, uint32_t *bit_chk,
test_status =
rw_mgr_mem_calibrate_read_test_all_ranks
- (grp, 1, PASS_ONE_BIT, bit_chk, 0);
+ (grp, 1, PASS_ONE_BIT, &bit_chk, 0);
if (test_status) {
*max_working_cnt = 1;
@@ -1384,12 +1385,13 @@ static int sdr_working_phase(uint32_t grp, uint32_t *bit_chk,
}
}
-static void sdr_backup_phase(uint32_t grp, uint32_t *bit_chk,
+static void sdr_backup_phase(uint32_t grp,
uint32_t *work_bgn, uint32_t *v, uint32_t *d,
uint32_t *p, uint32_t *max_working_cnt)
{
uint32_t found_begin = 0;
uint32_t tmp_delay;
+ u32 bit_chk;
/* Special case code for backing up a phase */
if (*p == 0) {
@@ -1407,7 +1409,7 @@ static void sdr_backup_phase(uint32_t grp, uint32_t *bit_chk,
if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT,
- bit_chk, 0)) {
+ &bit_chk, 0)) {
found_begin = 1;
*work_bgn = tmp_delay;
break;
@@ -1431,12 +1433,13 @@ static void sdr_backup_phase(uint32_t grp, uint32_t *bit_chk,
scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
}
-static int sdr_nonworking_phase(uint32_t grp, uint32_t *bit_chk,
+static int sdr_nonworking_phase(uint32_t grp,
uint32_t *work_bgn, uint32_t *v, uint32_t *d,
uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
uint32_t *work_end)
{
uint32_t found_end = 0;
+ u32 bit_chk;
(*p)++;
*work_end += IO_DELAY_PER_OPA_TAP;
@@ -1452,7 +1455,7 @@ static int sdr_nonworking_phase(uint32_t grp, uint32_t *bit_chk,
scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
if (!rw_mgr_mem_calibrate_read_test_all_ranks
- (grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
+ (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
found_end = 1;
break;
} else {
@@ -1579,7 +1582,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* ******************************************************** */
/* * step 2: find first working phase, increment in ptaps * */
work_bgn = 0;
- if (sdr_working_phase(grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
+ if (sdr_working_phase(grp, dtaps_per_ptap, &work_bgn, &v, &d,
&p, &i, &max_working_cnt) == 0)
return 0;
@@ -1595,13 +1598,13 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* * step 3a: if we have room, back off by one and
increment in dtaps * */
- sdr_backup_phase(grp, &bit_chk, &work_bgn, &v, &d, &p,
+ sdr_backup_phase(grp, &work_bgn, &v, &d, &p,
&max_working_cnt);
/* ********************************************************* */
/* * step 4a: go forward from working phase to non working
phase, increment in ptaps * */
- if (sdr_nonworking_phase(grp, &bit_chk, &work_bgn, &v, &d, &p,
+ if (sdr_nonworking_phase(grp, &work_bgn, &v, &d, &p,
&i, &max_working_cnt, &work_end) == 0)
return 0;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 121/172] ddr: altera: Clean up sdr_*_phase() part 4
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (119 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 120/172] ddr: altera: Clean up sdr_*_phase() part 3 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 122/172] ddr: altera: Clean up sdr_*_phase() part 5 Marek Vasut
` (52 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Get rid of found_{begin,end} variables. Instead of breaking out
through all of the loops, just return when the begin/end of the
window is found and be done with it. Also clean up the trailing
conditional expression, which is now much easier.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 41 ++++++++++-------------------------------
1 file changed, 10 insertions(+), 31 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index c62bec5..df261ae 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1337,7 +1337,6 @@ static int sdr_working_phase(uint32_t grp,
uint32_t *v, uint32_t *d, uint32_t *p,
uint32_t *i, uint32_t *max_working_cnt)
{
- uint32_t found_begin = 0;
uint32_t tmp_delay = 0;
uint32_t test_status;
u32 bit_chk;
@@ -1358,31 +1357,20 @@ static int sdr_working_phase(uint32_t grp,
if (test_status) {
*max_working_cnt = 1;
- found_begin = 1;
- break;
+ return 1;
}
}
- if (found_begin)
- break;
-
if (*p > IO_DQS_EN_PHASE_MAX)
/* fiddle with FIFO */
rw_mgr_incr_vfifo(grp, v);
}
-
- if (found_begin)
- break;
}
- if (*i >= VFIFO_SIZE) {
- /* cannot find working solution */
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
- ptap/dtap\n", __func__, __LINE__);
- return 0;
- } else {
- return 1;
- }
+ /* Cannot find working solution */
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
+ ptap/dtap\n", __func__, __LINE__);
+ return 0;
}
static void sdr_backup_phase(uint32_t grp,
@@ -1438,7 +1426,6 @@ static int sdr_nonworking_phase(uint32_t grp,
uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
uint32_t *work_end)
{
- uint32_t found_end = 0;
u32 bit_chk;
(*p)++;
@@ -1456,16 +1443,12 @@ static int sdr_nonworking_phase(uint32_t grp,
if (!rw_mgr_mem_calibrate_read_test_all_ranks
(grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
- found_end = 1;
- break;
+ return 1;
} else {
(*max_working_cnt)++;
}
}
- if (found_end)
- break;
-
if (*p > IO_DQS_EN_PHASE_MAX) {
/* fiddle with FIFO */
rw_mgr_incr_vfifo(grp, v);
@@ -1473,14 +1456,10 @@ static int sdr_nonworking_phase(uint32_t grp,
}
}
- if (*i >= VFIFO_SIZE + 1) {
- /* cannot see edge of failing read */
- debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
- failed\n", __func__, __LINE__);
- return 0;
- } else {
- return 1;
- }
+ /* Cannot see edge of failing read. */
+ debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
+ failed\n", __func__, __LINE__);
+ return 0;
}
/**
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 122/172] ddr: altera: Clean up sdr_*_phase() part 5
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (120 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 121/172] ddr: altera: Clean up sdr_*_phase() part 4 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 123/172] ddr: altera: Clean up sdr_*_phase() part 6 Marek Vasut
` (51 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Pull out the loop for eaching working/non-working DQS enable phase
into a separate function, as this is mostly common code between.
Clean up sdr_working_phase() and sdr_nonworking_phase() while switching
these two functions to the common sdr_find_phase().
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 127 +++++++++++++++++++++++------------------
1 file changed, 72 insertions(+), 55 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index df261ae..c90bb9a 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1332,45 +1332,78 @@ static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
}
}
-static int sdr_working_phase(uint32_t grp,
- uint32_t dtaps_per_ptap, uint32_t *work_bgn,
- uint32_t *v, uint32_t *d, uint32_t *p,
- uint32_t *i, uint32_t *max_working_cnt)
+/**
+ * sdr_find_phase() - Find DQS enable phase
+ * @working: If 1, look for working phase, if 0, look for non-working phase
+ * @grp: Read/Write group
+ * @v: VFIFO value
+ * @work: Working window position
+ * @i: Iterator
+ * @p: DQS Phase Iterator
+ * @max_working_cnt: Counter
+ *
+ * Find working or non-working DQS enable phase setting.
+ */
+static int sdr_find_phase(int working, const u32 grp, u32 *v, u32 *work,
+ u32 *i, u32 *p, u32 *max_working_cnt)
{
- uint32_t tmp_delay = 0;
- uint32_t test_status;
- u32 bit_chk;
+ u32 ret, bit_chk;
+ const u32 end = VFIFO_SIZE + (working ? 0 : 1);
- for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
- IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
- *work_bgn = tmp_delay;
- scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
+ for (; *i < end; (*i)++) {
+ if (working)
+ *p = 0;
- for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
- for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
- IO_DELAY_PER_OPA_TAP) {
- scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
+ for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++) {
+ scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
- test_status =
- rw_mgr_mem_calibrate_read_test_all_ranks
- (grp, 1, PASS_ONE_BIT, &bit_chk, 0);
+ ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
+ PASS_ONE_BIT, &bit_chk, 0);
+ if (ret)
+ (*max_working_cnt)++;
- if (test_status) {
- *max_working_cnt = 1;
- return 1;
- }
- }
+ if (!working)
+ ret = !ret;
+
+ if (ret)
+ return 0;
- if (*p > IO_DQS_EN_PHASE_MAX)
- /* fiddle with FIFO */
- rw_mgr_incr_vfifo(grp, v);
+ *work += IO_DELAY_PER_OPA_TAP;
+ }
+
+ if (*p > IO_DQS_EN_PHASE_MAX) {
+ /* Fiddle with FIFO. */
+ rw_mgr_incr_vfifo(grp, v);
+ if (!working)
+ *p = 0;
}
}
+ return -EINVAL;
+}
+
+static int sdr_working_phase(uint32_t grp,
+ uint32_t dtaps_per_ptap, uint32_t *work_bgn,
+ uint32_t *v, uint32_t *d, uint32_t *p,
+ uint32_t *i, uint32_t *max_working_cnt)
+{
+ int ret;
+
+ *work_bgn = 0;
+
+ for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
+ *i = 0;
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
+ ret = sdr_find_phase(1, grp, v, work_bgn, i, p, max_working_cnt);
+ if (!ret)
+ return 0;
+ *work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+ }
+
/* Cannot find working solution */
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
- ptap/dtap\n", __func__, __LINE__);
- return 0;
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
+ __func__, __LINE__);
+ return -EINVAL;
}
static void sdr_backup_phase(uint32_t grp,
@@ -1426,40 +1459,24 @@ static int sdr_nonworking_phase(uint32_t grp,
uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
uint32_t *work_end)
{
- u32 bit_chk;
+ int ret;
(*p)++;
*work_end += IO_DELAY_PER_OPA_TAP;
if (*p > IO_DQS_EN_PHASE_MAX) {
- /* fiddle with FIFO */
+ /* Fiddle with FIFO. */
*p = 0;
rw_mgr_incr_vfifo(grp, v);
}
- for (; *i < VFIFO_SIZE + 1; (*i)++) {
- for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
- += IO_DELAY_PER_OPA_TAP) {
- scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
-
- if (!rw_mgr_mem_calibrate_read_test_all_ranks
- (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
- return 1;
- } else {
- (*max_working_cnt)++;
- }
- }
-
- if (*p > IO_DQS_EN_PHASE_MAX) {
- /* fiddle with FIFO */
- rw_mgr_incr_vfifo(grp, v);
- *p = 0;
- }
+ ret = sdr_find_phase(0, grp, v, work_end, i, p, max_working_cnt);
+ if (ret) {
+ /* Cannot see edge of failing read. */
+ debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
+ __func__, __LINE__);
}
- /* Cannot see edge of failing read. */
- debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
- failed\n", __func__, __LINE__);
- return 0;
+ return ret;
}
/**
@@ -1562,7 +1579,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* * step 2: find first working phase, increment in ptaps * */
work_bgn = 0;
if (sdr_working_phase(grp, dtaps_per_ptap, &work_bgn, &v, &d,
- &p, &i, &max_working_cnt) == 0)
+ &p, &i, &max_working_cnt))
return 0;
work_end = work_bgn;
@@ -1584,7 +1601,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* * step 4a: go forward from working phase to non working
phase, increment in ptaps * */
if (sdr_nonworking_phase(grp, &work_bgn, &v, &d, &p,
- &i, &max_working_cnt, &work_end) == 0)
+ &i, &max_working_cnt, &work_end))
return 0;
/* ********************************************************* */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 123/172] ddr: altera: Clean up sdr_*_phase() part 6
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (121 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 122/172] ddr: altera: Clean up sdr_*_phase() part 5 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 124/172] ddr: altera: Clean up sdr_*_phase() part 7 Marek Vasut
` (50 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
It is now clear that the max_working_cnt variable is totally unused.
Zap the variable and zap other variables which became unused due to
this change too.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 40 +++++++++-------------------------------
1 file changed, 9 insertions(+), 31 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index c90bb9a..75a0699 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1340,12 +1340,11 @@ static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
* @work: Working window position
* @i: Iterator
* @p: DQS Phase Iterator
- * @max_working_cnt: Counter
*
* Find working or non-working DQS enable phase setting.
*/
static int sdr_find_phase(int working, const u32 grp, u32 *v, u32 *work,
- u32 *i, u32 *p, u32 *max_working_cnt)
+ u32 *i, u32 *p)
{
u32 ret, bit_chk;
const u32 end = VFIFO_SIZE + (working ? 0 : 1);
@@ -1359,9 +1358,6 @@ static int sdr_find_phase(int working, const u32 grp, u32 *v, u32 *work,
ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT, &bit_chk, 0);
- if (ret)
- (*max_working_cnt)++;
-
if (!working)
ret = !ret;
@@ -1385,7 +1381,7 @@ static int sdr_find_phase(int working, const u32 grp, u32 *v, u32 *work,
static int sdr_working_phase(uint32_t grp,
uint32_t dtaps_per_ptap, uint32_t *work_bgn,
uint32_t *v, uint32_t *d, uint32_t *p,
- uint32_t *i, uint32_t *max_working_cnt)
+ uint32_t *i)
{
int ret;
@@ -1394,7 +1390,7 @@ static int sdr_working_phase(uint32_t grp,
for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
*i = 0;
scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
- ret = sdr_find_phase(1, grp, v, work_bgn, i, p, max_working_cnt);
+ ret = sdr_find_phase(1, grp, v, work_bgn, i, p);
if (!ret)
return 0;
*work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
@@ -1408,9 +1404,8 @@ static int sdr_working_phase(uint32_t grp,
static void sdr_backup_phase(uint32_t grp,
uint32_t *work_bgn, uint32_t *v, uint32_t *d,
- uint32_t *p, uint32_t *max_working_cnt)
+ uint32_t *p)
{
- uint32_t found_begin = 0;
uint32_t tmp_delay;
u32 bit_chk;
@@ -1431,16 +1426,11 @@ static void sdr_backup_phase(uint32_t grp,
if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT,
&bit_chk, 0)) {
- found_begin = 1;
*work_bgn = tmp_delay;
break;
}
}
- /* We have found a working dtap before the ptap found above */
- if (found_begin == 1)
- (*max_working_cnt)++;
-
/*
* Restore VFIFO to old state before we decremented it
* (if needed).
@@ -1456,7 +1446,7 @@ static void sdr_backup_phase(uint32_t grp,
static int sdr_nonworking_phase(uint32_t grp,
uint32_t *work_bgn, uint32_t *v, uint32_t *d,
- uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
+ uint32_t *p, uint32_t *i,
uint32_t *work_end)
{
int ret;
@@ -1469,7 +1459,7 @@ static int sdr_nonworking_phase(uint32_t grp,
rw_mgr_incr_vfifo(grp, v);
}
- ret = sdr_find_phase(0, grp, v, work_end, i, p, max_working_cnt);
+ ret = sdr_find_phase(0, grp, v, work_end, i, p);
if (ret) {
/* Cannot see edge of failing read. */
debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
@@ -1552,7 +1542,6 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
{
uint32_t v, d, p, i;
- uint32_t max_working_cnt;
uint32_t bit_chk;
uint32_t dtaps_per_ptap;
uint32_t work_bgn, work_end;
@@ -1573,13 +1562,10 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* * Step 1 : First push vfifo until we get a failing read * */
v = find_vfifo_read(grp, &bit_chk);
- max_working_cnt = 0;
-
/* ******************************************************** */
/* * step 2: find first working phase, increment in ptaps * */
work_bgn = 0;
- if (sdr_working_phase(grp, dtaps_per_ptap, &work_bgn, &v, &d,
- &p, &i, &max_working_cnt))
+ if (sdr_working_phase(grp, dtaps_per_ptap, &work_bgn, &v, &d, &p, &i))
return 0;
work_end = work_bgn;
@@ -1594,14 +1580,13 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* * step 3a: if we have room, back off by one and
increment in dtaps * */
- sdr_backup_phase(grp, &work_bgn, &v, &d, &p,
- &max_working_cnt);
+ sdr_backup_phase(grp, &work_bgn, &v, &d, &p);
/* ********************************************************* */
/* * step 4a: go forward from working phase to non working
phase, increment in ptaps * */
if (sdr_nonworking_phase(grp, &work_bgn, &v, &d, &p,
- &i, &max_working_cnt, &work_end))
+ &i, &work_end))
return 0;
/* ********************************************************* */
@@ -1634,13 +1619,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
v, p, d, work_bgn);
work_end = work_bgn;
-
- /* * The actual increment of dtaps is done outside of the
- if/else loop to share code */
-
- /* Only here to counterbalance a subtract later on which is
- not needed if this branch of the algorithm is taken */
- max_working_cnt++;
}
/* The dtap increment to find the failing edge is done here */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 124/172] ddr: altera: Clean up sdr_*_phase() part 7
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (122 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 123/172] ddr: altera: Clean up sdr_*_phase() part 6 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 125/172] ddr: altera: Clean up sdr_*_phase() part 8 Marek Vasut
` (49 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Wrap dtaps_per_ptap into the sdr_working_phase() function to trim
down the number of params. It's a constant too.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 75a0699..d93b5fe 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1378,11 +1378,12 @@ static int sdr_find_phase(int working, const u32 grp, u32 *v, u32 *work,
return -EINVAL;
}
-static int sdr_working_phase(uint32_t grp,
- uint32_t dtaps_per_ptap, uint32_t *work_bgn,
- uint32_t *v, uint32_t *d, uint32_t *p,
- uint32_t *i)
+static int sdr_working_phase(uint32_t grp, uint32_t *work_bgn,
+ uint32_t *v, uint32_t *d, uint32_t *p,
+ uint32_t *i)
{
+ const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
+ IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
int ret;
*work_bgn = 0;
@@ -1565,7 +1566,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* ******************************************************** */
/* * step 2: find first working phase, increment in ptaps * */
work_bgn = 0;
- if (sdr_working_phase(grp, dtaps_per_ptap, &work_bgn, &v, &d, &p, &i))
+ if (sdr_working_phase(grp, &work_bgn, &v, &d, &p, &i))
return 0;
work_end = work_bgn;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 125/172] ddr: altera: Clean up sdr_*_phase() part 8
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (123 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 124/172] ddr: altera: Clean up sdr_*_phase() part 7 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 126/172] ddr: altera: Clean up sdr_*_phase() part 9 Marek Vasut
` (48 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
The work_bgn parameter of sdr_nonworking_phase() is unused, zap it.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index d93b5fe..e6fb576 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1445,10 +1445,8 @@ static void sdr_backup_phase(uint32_t grp,
scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
}
-static int sdr_nonworking_phase(uint32_t grp,
- uint32_t *work_bgn, uint32_t *v, uint32_t *d,
- uint32_t *p, uint32_t *i,
- uint32_t *work_end)
+static int sdr_nonworking_phase(uint32_t grp, uint32_t *v, uint32_t *d,
+ uint32_t *p, uint32_t *i, uint32_t *work_end)
{
int ret;
@@ -1586,8 +1584,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* ********************************************************* */
/* * step 4a: go forward from working phase to non working
phase, increment in ptaps * */
- if (sdr_nonworking_phase(grp, &work_bgn, &v, &d, &p,
- &i, &work_end))
+ if (sdr_nonworking_phase(grp, &v, &d, &p, &i, &work_end))
return 0;
/* ********************************************************* */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 126/172] ddr: altera: Clean up sdr_*_phase() part 9
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (124 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 125/172] ddr: altera: Clean up sdr_*_phase() part 8 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 127/172] ddr: altera: Clean up sdr_*_phase() part 10 Marek Vasut
` (47 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
The "d" variable is set to 0 in sdr_backup_phase() and is not used
at all in sdr_nonworking_phase(). Make it local and zap it respectively.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index e6fb576..e5dd81b 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1403,12 +1403,11 @@ static int sdr_working_phase(uint32_t grp, uint32_t *work_bgn,
return -EINVAL;
}
-static void sdr_backup_phase(uint32_t grp,
- uint32_t *work_bgn, uint32_t *v, uint32_t *d,
- uint32_t *p)
+static void sdr_backup_phase(uint32_t grp, uint32_t *work_bgn,
+ uint32_t *v, uint32_t *p)
{
- uint32_t tmp_delay;
- u32 bit_chk;
+ u32 tmp_delay;
+ u32 bit_chk, d;
/* Special case code for backing up a phase */
if (*p == 0) {
@@ -1420,9 +1419,8 @@ static void sdr_backup_phase(uint32_t grp,
tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
- for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
- (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
- scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
+ for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn; d++) {
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT,
@@ -1430,6 +1428,8 @@ static void sdr_backup_phase(uint32_t grp,
*work_bgn = tmp_delay;
break;
}
+
+ tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
}
/*
@@ -1445,7 +1445,7 @@ static void sdr_backup_phase(uint32_t grp,
scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
}
-static int sdr_nonworking_phase(uint32_t grp, uint32_t *v, uint32_t *d,
+static int sdr_nonworking_phase(uint32_t grp, uint32_t *v,
uint32_t *p, uint32_t *i, uint32_t *work_end)
{
int ret;
@@ -1579,12 +1579,12 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* * step 3a: if we have room, back off by one and
increment in dtaps * */
- sdr_backup_phase(grp, &work_bgn, &v, &d, &p);
+ sdr_backup_phase(grp, &work_bgn, &v, &p);
/* ********************************************************* */
/* * step 4a: go forward from working phase to non working
phase, increment in ptaps * */
- if (sdr_nonworking_phase(grp, &v, &d, &p, &i, &work_end))
+ if (sdr_nonworking_phase(grp, &v, &p, &i, &work_end))
return 0;
/* ********************************************************* */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 127/172] ddr: altera: Clean up sdr_*_phase() part 10
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (125 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 126/172] ddr: altera: Clean up sdr_*_phase() part 9 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 128/172] ddr: altera: Clean up rw_mgr_*_vfifo() part 1 Marek Vasut
` (46 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Clean up data types, constify where applicable and document the
functions with kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 59 ++++++++++++++++++++++++++++++------------
1 file changed, 42 insertions(+), 17 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index e5dd81b..ff11702 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1378,9 +1378,19 @@ static int sdr_find_phase(int working, const u32 grp, u32 *v, u32 *work,
return -EINVAL;
}
-static int sdr_working_phase(uint32_t grp, uint32_t *work_bgn,
- uint32_t *v, uint32_t *d, uint32_t *p,
- uint32_t *i)
+/**
+ * sdr_working_phase() - Find working DQS enable phase
+ * @grp: Read/Write group
+ * @work_bgn: Working window start position
+ * @v: VFIFO value
+ * @d: dtaps output value
+ * @p: DQS Phase Iterator
+ * @i: Iterator
+ *
+ * Find working DQS enable phase setting.
+ */
+static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *v, u32 *d,
+ u32 *p, u32 *i)
{
const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
@@ -1403,11 +1413,19 @@ static int sdr_working_phase(uint32_t grp, uint32_t *work_bgn,
return -EINVAL;
}
-static void sdr_backup_phase(uint32_t grp, uint32_t *work_bgn,
- uint32_t *v, uint32_t *p)
+/**
+ * sdr_backup_phase() - Find DQS enable backup phase
+ * @grp: Read/Write group
+ * @work_bgn: Working window start position
+ * @v: VFIFO value
+ * @p: DQS Phase Iterator
+ *
+ * Find DQS enable backup phase setting.
+ */
+static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *v, u32 *p)
{
- u32 tmp_delay;
- u32 bit_chk, d;
+ u32 tmp_delay, bit_chk, d;
+ int ret;
/* Special case code for backing up a phase */
if (*p == 0) {
@@ -1422,9 +1440,9 @@ static void sdr_backup_phase(uint32_t grp, uint32_t *work_bgn,
for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn; d++) {
scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
- if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
- PASS_ONE_BIT,
- &bit_chk, 0)) {
+ ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
+ PASS_ONE_BIT, &bit_chk, 0);
+ if (ret) {
*work_bgn = tmp_delay;
break;
}
@@ -1432,10 +1450,7 @@ static void sdr_backup_phase(uint32_t grp, uint32_t *work_bgn,
tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
}
- /*
- * Restore VFIFO to old state before we decremented it
- * (if needed).
- */
+ /* Restore VFIFO to old state before we decremented it (if needed). */
(*p)++;
if (*p > IO_DQS_EN_PHASE_MAX) {
*p = 0;
@@ -1445,8 +1460,18 @@ static void sdr_backup_phase(uint32_t grp, uint32_t *work_bgn,
scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
}
-static int sdr_nonworking_phase(uint32_t grp, uint32_t *v,
- uint32_t *p, uint32_t *i, uint32_t *work_end)
+/**
+ * sdr_nonworking_phase() - Find non-working DQS enable phase
+ * @grp: Read/Write group
+ * @work_end: Working window end position
+ * @v: VFIFO value
+ * @p: DQS Phase Iterator
+ * @i: Iterator
+ *
+ * Find non-working DQS enable phase setting.
+ */
+static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *v,
+ u32 *p, u32 *i)
{
int ret;
@@ -1584,7 +1609,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* ********************************************************* */
/* * step 4a: go forward from working phase to non working
phase, increment in ptaps * */
- if (sdr_nonworking_phase(grp, &v, &p, &i, &work_end))
+ if (sdr_nonworking_phase(grp, &work_end, &v, &p, &i))
return 0;
/* ********************************************************* */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 128/172] ddr: altera: Clean up rw_mgr_*_vfifo() part 1
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (126 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 127/172] ddr: altera: Clean up sdr_*_phase() part 10 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 129/172] ddr: altera: Clean up rw_mgr_*_vfifo() part 2 Marek Vasut
` (45 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Perform minor cleanup, fix data types and constify where applicable.
Add kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index ff11702..3d0dc59 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1286,17 +1286,31 @@ static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
bit_chk, all_groups, 1);
}
-static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
+/**
+ * rw_mgr_incr_vfifo() - Increase VFIFO value
+ * @grp: Read/Write group
+ * @v: VFIFO value
+ *
+ * Increase VFIFO value.
+ */
+static void rw_mgr_incr_vfifo(const u32 grp, u32 *v)
{
writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
(*v)++;
}
-static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
+/**
+ * rw_mgr_decr_vfifo() - Decrease VFIFO value
+ * @grp: Read/Write group
+ * @v: VFIFO value
+ *
+ * Decrease VFIFO value.
+ */
+static void rw_mgr_decr_vfifo(const u32 grp, u32 *v)
{
- uint32_t i;
+ u32 i;
- for (i = 0; i < VFIFO_SIZE-1; i++)
+ for (i = 0; i < VFIFO_SIZE - 1; i++)
rw_mgr_incr_vfifo(grp, v);
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 129/172] ddr: altera: Clean up rw_mgr_*_vfifo() part 2
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (127 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 128/172] ddr: altera: Clean up rw_mgr_*_vfifo() part 1 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 130/172] ddr: altera: Clean up find_vfifo_read() Marek Vasut
` (44 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Pluck out all this VFIFO value counting, which turns out to be
completely unused. Thus, remove it to simplify the code.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 92 +++++++++++++++++++-----------------------
1 file changed, 41 insertions(+), 51 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 3d0dc59..50a5b8e 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1289,38 +1289,35 @@ static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
/**
* rw_mgr_incr_vfifo() - Increase VFIFO value
* @grp: Read/Write group
- * @v: VFIFO value
*
* Increase VFIFO value.
*/
-static void rw_mgr_incr_vfifo(const u32 grp, u32 *v)
+static void rw_mgr_incr_vfifo(const u32 grp)
{
writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
- (*v)++;
}
/**
* rw_mgr_decr_vfifo() - Decrease VFIFO value
* @grp: Read/Write group
- * @v: VFIFO value
*
* Decrease VFIFO value.
*/
-static void rw_mgr_decr_vfifo(const u32 grp, u32 *v)
+static void rw_mgr_decr_vfifo(const u32 grp)
{
u32 i;
for (i = 0; i < VFIFO_SIZE - 1; i++)
- rw_mgr_incr_vfifo(grp, v);
+ rw_mgr_incr_vfifo(grp);
}
static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
{
- uint32_t v;
+ uint32_t v;
uint32_t fail_cnt = 0;
uint32_t test_status;
- for (v = 0; v < VFIFO_SIZE; ) {
+ for (v = 0; v < VFIFO_SIZE; v++) {
debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
__func__, __LINE__, v);
test_status = rw_mgr_mem_calibrate_read_test_all_ranks
@@ -1333,7 +1330,7 @@ static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
}
/* fiddle with FIFO */
- rw_mgr_incr_vfifo(grp, &v);
+ rw_mgr_incr_vfifo(grp);
}
if (v >= VFIFO_SIZE) {
@@ -1350,14 +1347,13 @@ static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
* sdr_find_phase() - Find DQS enable phase
* @working: If 1, look for working phase, if 0, look for non-working phase
* @grp: Read/Write group
- * @v: VFIFO value
* @work: Working window position
* @i: Iterator
* @p: DQS Phase Iterator
*
* Find working or non-working DQS enable phase setting.
*/
-static int sdr_find_phase(int working, const u32 grp, u32 *v, u32 *work,
+static int sdr_find_phase(int working, const u32 grp, u32 *work,
u32 *i, u32 *p)
{
u32 ret, bit_chk;
@@ -1383,7 +1379,7 @@ static int sdr_find_phase(int working, const u32 grp, u32 *v, u32 *work,
if (*p > IO_DQS_EN_PHASE_MAX) {
/* Fiddle with FIFO. */
- rw_mgr_incr_vfifo(grp, v);
+ rw_mgr_incr_vfifo(grp);
if (!working)
*p = 0;
}
@@ -1396,14 +1392,13 @@ static int sdr_find_phase(int working, const u32 grp, u32 *v, u32 *work,
* sdr_working_phase() - Find working DQS enable phase
* @grp: Read/Write group
* @work_bgn: Working window start position
- * @v: VFIFO value
* @d: dtaps output value
* @p: DQS Phase Iterator
* @i: Iterator
*
* Find working DQS enable phase setting.
*/
-static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *v, u32 *d,
+static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
u32 *p, u32 *i)
{
const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
@@ -1415,7 +1410,7 @@ static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *v, u32 *d,
for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
*i = 0;
scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
- ret = sdr_find_phase(1, grp, v, work_bgn, i, p);
+ ret = sdr_find_phase(1, grp, work_bgn, i, p);
if (!ret)
return 0;
*work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
@@ -1431,12 +1426,11 @@ static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *v, u32 *d,
* sdr_backup_phase() - Find DQS enable backup phase
* @grp: Read/Write group
* @work_bgn: Working window start position
- * @v: VFIFO value
* @p: DQS Phase Iterator
*
* Find DQS enable backup phase setting.
*/
-static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *v, u32 *p)
+static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
{
u32 tmp_delay, bit_chk, d;
int ret;
@@ -1444,7 +1438,7 @@ static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *v, u32 *p)
/* Special case code for backing up a phase */
if (*p == 0) {
*p = IO_DQS_EN_PHASE_MAX;
- rw_mgr_decr_vfifo(grp, v);
+ rw_mgr_decr_vfifo(grp);
} else {
(*p)--;
}
@@ -1468,7 +1462,7 @@ static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *v, u32 *p)
(*p)++;
if (*p > IO_DQS_EN_PHASE_MAX) {
*p = 0;
- rw_mgr_incr_vfifo(grp, v);
+ rw_mgr_incr_vfifo(grp);
}
scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
@@ -1478,14 +1472,12 @@ static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *v, u32 *p)
* sdr_nonworking_phase() - Find non-working DQS enable phase
* @grp: Read/Write group
* @work_end: Working window end position
- * @v: VFIFO value
* @p: DQS Phase Iterator
* @i: Iterator
*
* Find non-working DQS enable phase setting.
*/
-static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *v,
- u32 *p, u32 *i)
+static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i)
{
int ret;
@@ -1494,10 +1486,10 @@ static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *v,
if (*p > IO_DQS_EN_PHASE_MAX) {
/* Fiddle with FIFO. */
*p = 0;
- rw_mgr_incr_vfifo(grp, v);
+ rw_mgr_incr_vfifo(grp);
}
- ret = sdr_find_phase(0, grp, v, work_end, i, p);
+ ret = sdr_find_phase(0, grp, work_end, i, p);
if (ret) {
/* Cannot see edge of failing read. */
debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
@@ -1512,14 +1504,13 @@ static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *v,
* @grp: Read/Write group
* @work_bgn: First working settings
* @work_end: Last working settings
- * @val: VFIFO value
*
* Find center of the working DQS enable window.
*/
static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
- const u32 work_end, const u32 val)
+ const u32 work_end)
{
- u32 bit_chk, work_mid, v = val;
+ u32 bit_chk, work_mid;
int tmp_delay = 0;
int i, p, d;
@@ -1556,19 +1547,18 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
* because the largest possible margin in 1 VFIFO cycle.
*/
for (i = 0; i < VFIFO_SIZE; i++) {
- debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
- v);
+ debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT,
&bit_chk, 0)) {
debug_cond(DLEVEL == 2,
- "%s:%d center: found: vfifo=%u ptap=%u dtap=%u\n",
- __func__, __LINE__, v, p, d);
+ "%s:%d center: found: ptap=%u dtap=%u\n",
+ __func__, __LINE__, p, d);
return 0;
}
/* Fiddle with FIFO. */
- rw_mgr_incr_vfifo(grp, &v);
+ rw_mgr_incr_vfifo(grp);
}
debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
@@ -1579,7 +1569,7 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
/* find a good dqs enable to use */
static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
{
- uint32_t v, d, p, i;
+ uint32_t d, p, i;
uint32_t bit_chk;
uint32_t dtaps_per_ptap;
uint32_t work_bgn, work_end;
@@ -1598,12 +1588,12 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* ********************************************************* */
/* * Step 1 : First push vfifo until we get a failing read * */
- v = find_vfifo_read(grp, &bit_chk);
+ find_vfifo_read(grp, &bit_chk);
/* ******************************************************** */
/* * step 2: find first working phase, increment in ptaps * */
work_bgn = 0;
- if (sdr_working_phase(grp, &work_bgn, &v, &d, &p, &i))
+ if (sdr_working_phase(grp, &work_bgn, &d, &p, &i))
return 0;
work_end = work_bgn;
@@ -1618,12 +1608,12 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* * step 3a: if we have room, back off by one and
increment in dtaps * */
- sdr_backup_phase(grp, &work_bgn, &v, &p);
+ sdr_backup_phase(grp, &work_bgn, &p);
/* ********************************************************* */
/* * step 4a: go forward from working phase to non working
phase, increment in ptaps * */
- if (sdr_nonworking_phase(grp, &work_end, &v, &p, &i))
+ if (sdr_nonworking_phase(grp, &work_end, &p, &i))
return 0;
/* ********************************************************* */
@@ -1632,7 +1622,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* Special case code for backing up a phase */
if (p == 0) {
p = IO_DQS_EN_PHASE_MAX;
- rw_mgr_decr_vfifo(grp, &v);
+ rw_mgr_decr_vfifo(grp);
} else {
p = p - 1;
}
@@ -1644,16 +1634,16 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
the if/else loop to share code */
d = 0;
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
- vfifo=%u ptap=%u\n", __func__, __LINE__,
- v, p);
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: p: \
+ ptap=%u\n", __func__, __LINE__,
+ p);
} else {
/* ******************************************************* */
/* * step 3-5b: Find the right edge of the window using
delay taps * */
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
- v, p, d, work_bgn);
+ p, d, work_bgn);
work_end = work_bgn;
}
@@ -1676,9 +1666,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
if (d != 0)
work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
+ debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: p/d: \
ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
- v, p, d-1, work_end);
+ p, d-1, work_end);
if (work_end < work_bgn) {
/* nil range */
@@ -1703,15 +1693,15 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* Special case code for backing up a phase */
if (p == 0) {
p = IO_DQS_EN_PHASE_MAX;
- rw_mgr_decr_vfifo(grp, &v);
+ rw_mgr_decr_vfifo(grp);
debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
- cycle/phase: v=%u p=%u\n", __func__, __LINE__,
- v, p);
+ cycle/phase: p=%u\n", __func__, __LINE__,
+ p);
} else {
p = p - 1;
debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
- phase only: v=%u p=%u", __func__, __LINE__,
- v, p);
+ phase only: p=%u", __func__, __LINE__,
+ p);
}
scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
@@ -1778,7 +1768,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* ******************************************** */
/* * step 6: Find the centre of the window * */
- if (sdr_find_window_centre(grp, work_bgn, work_end, v))
+ if (sdr_find_window_centre(grp, work_bgn, work_end))
return 0; /* FIXME: Old code, return 0 means failure :-( */
return 1;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 130/172] ddr: altera: Clean up find_vfifo_read()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (128 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 129/172] ddr: altera: Clean up rw_mgr_*_vfifo() part 2 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 131/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 1 Marek Vasut
` (43 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Fix data types, constify where applicable, fix comments and debug
strings. In case enough failing reads are detected, just return
right away instead of breaking from the loop. This lets us make
the error handling at the end much simpler.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 37 ++++++++++++++++++-------------------
1 file changed, 18 insertions(+), 19 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 50a5b8e..fbbf874 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1311,36 +1311,35 @@ static void rw_mgr_decr_vfifo(const u32 grp)
rw_mgr_incr_vfifo(grp);
}
-static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
+/**
+ * find_vfifo_failing_read() - Push VFIFO to get a failing read
+ * @grp: Read/Write group
+ *
+ * Push VFIFO until a failing read happens.
+ */
+static int find_vfifo_failing_read(const u32 grp)
{
- uint32_t v;
- uint32_t fail_cnt = 0;
- uint32_t test_status;
+ u32 v, ret, bit_chk, fail_cnt = 0;
for (v = 0; v < VFIFO_SIZE; v++) {
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
+ debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
__func__, __LINE__, v);
- test_status = rw_mgr_mem_calibrate_read_test_all_ranks
- (grp, 1, PASS_ONE_BIT, bit_chk, 0);
- if (!test_status) {
+ ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
+ PASS_ONE_BIT, &bit_chk, 0);
+ if (!ret) {
fail_cnt++;
if (fail_cnt == 2)
- break;
+ return v;
}
- /* fiddle with FIFO */
+ /* Fiddle with FIFO. */
rw_mgr_incr_vfifo(grp);
}
- if (v >= VFIFO_SIZE) {
- /* no failing read found!! Something must have gone wrong */
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
- __func__, __LINE__);
- return 0;
- } else {
- return v;
- }
+ /* No failing read found! Something must have gone wrong. */
+ debug_cond(DLEVEL == 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
+ return 0;
}
/**
@@ -1588,7 +1587,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
/* ********************************************************* */
/* * Step 1 : First push vfifo until we get a failing read * */
- find_vfifo_read(grp, &bit_chk);
+ find_vfifo_failing_read(grp);
/* ******************************************************** */
/* * step 2: find first working phase, increment in ptaps * */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 131/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 1
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (129 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 130/172] ddr: altera: Clean up find_vfifo_read() Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 132/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 2 Marek Vasut
` (42 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Fix broken multiline debug strings, fix comments.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 150 +++++++++++++++++++----------------------
1 file changed, 70 insertions(+), 80 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index fbbf874..a9f31d4 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1566,7 +1566,7 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
}
/* find a good dqs enable to use */
-static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
+static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(u32 grp)
{
uint32_t d, p, i;
uint32_t bit_chk;
@@ -1581,16 +1581,13 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
- /* ************************************************************** */
- /* * Step 0 : Determine number of delay taps for each phase tap * */
- dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
+ /* Step 0: Determine number of delay taps for each phase tap. */
+ dtaps_per_ptap = IO_DELAY_PER_OPA_TAP / IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
- /* ********************************************************* */
- /* * Step 1 : First push vfifo until we get a failing read * */
+ /* Step 1: First push vfifo until we get a failing read. */
find_vfifo_failing_read(grp);
- /* ******************************************************** */
- /* * step 2: find first working phase, increment in ptaps * */
+ /* Step 2: Find first working phase, increment in ptaps. */
work_bgn = 0;
if (sdr_working_phase(grp, &work_bgn, &d, &p, &i))
return 0;
@@ -1598,25 +1595,25 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
work_end = work_bgn;
/*
- * If d is 0 then the working window covers a phase tap and
- * we can follow the old procedure otherwise, we've found the beginning,
+ * If d is 0 then the working window covers a phase tap and we can
+ * follow the old procedure. Otherwise, we've found the beginning
* and we need to increment the dtaps until we find the end.
*/
if (d == 0) {
- /* ********************************************************* */
- /* * step 3a: if we have room, back off by one and
- increment in dtaps * */
-
+ /*
+ * Step 3a: If we have room, back off by one and
+ * increment in dtaps.
+ */
sdr_backup_phase(grp, &work_bgn, &p);
- /* ********************************************************* */
- /* * step 4a: go forward from working phase to non working
- phase, increment in ptaps * */
+ /*
+ * Step 4a: go forward from working phase to non working
+ * phase, increment in ptaps.
+ */
if (sdr_nonworking_phase(grp, &work_end, &p, &i))
return 0;
- /* ********************************************************* */
- /* * step 5a: back off one from last, increment in dtaps * */
+ /* Step 5a: Back off one from last, increment in dtaps. */
/* Special case code for backing up a phase */
if (p == 0) {
@@ -1629,97 +1626,92 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
work_end -= IO_DELAY_PER_OPA_TAP;
scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
- /* * The actual increment of dtaps is done outside of
- the if/else loop to share code */
d = 0;
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: p: \
- ptap=%u\n", __func__, __LINE__,
- p);
+ debug_cond(DLEVEL == 2, "%s:%d p: ptap=%u\n",
+ __func__, __LINE__, p);
} else {
- /* ******************************************************* */
- /* * step 3-5b: Find the right edge of the window using
- delay taps * */
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
- ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
- p, d, work_bgn);
+ /*
+ * Step 3-5b: Find the right edge of the window
+ * using delay taps.
+ */
+ debug_cond(DLEVEL == 2,
+ "%s:%d ptap=%u dtap=%u bgn=%u\n",
+ __func__, __LINE__, p, d, work_bgn);
work_end = work_bgn;
}
- /* The dtap increment to find the failing edge is done here */
- for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
- IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
- end-2: dtap=%u\n", __func__, __LINE__, d);
- scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
+ /* The dtap increment to find the failing edge is done here. */
+ for (; d <= IO_DQS_EN_DELAY_MAX;
+ d++, work_end += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
+ debug_cond(DLEVEL == 2, "%s:%d end-2: dtap=%u\n",
+ __func__, __LINE__, d);
- if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
- PASS_ONE_BIT,
- &bit_chk, 0)) {
- break;
- }
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
+
+ if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
+ PASS_ONE_BIT,
+ &bit_chk, 0)) {
+ break;
+ }
}
/* Go back to working dtap */
if (d != 0)
work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: p/d: \
- ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
- p, d-1, work_end);
+ debug_cond(DLEVEL == 2,
+ "%s:%d p/d: ptap=%u dtap=%u end=%u\n",
+ __func__, __LINE__, p, d - 1, work_end);
if (work_end < work_bgn) {
/* nil range */
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
- failed\n", __func__, __LINE__);
+ debug_cond(DLEVEL == 2, "%s:%d end-2: failed\n",
+ __func__, __LINE__);
return 0;
}
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
+ debug_cond(DLEVEL == 2, "%s:%d found range [%u,%u]\n",
__func__, __LINE__, work_bgn, work_end);
- /* *************************************************************** */
/*
- * * We need to calculate the number of dtaps that equal a ptap
- * * To do that we'll back up a ptap and re-find the edge of the
- * * window using dtaps
+ * We need to calculate the number of dtaps that equal a ptap.
+ * To do that we'll back up a ptap and re-find the edge of the
+ * window using dtaps
*/
-
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
- for tracking\n", __func__, __LINE__);
+ debug_cond(DLEVEL == 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
+ __func__, __LINE__);
/* Special case code for backing up a phase */
if (p == 0) {
p = IO_DQS_EN_PHASE_MAX;
rw_mgr_decr_vfifo(grp);
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
- cycle/phase: p=%u\n", __func__, __LINE__,
- p);
+ debug_cond(DLEVEL == 2, "%s:%d backedup cycle/phase: p=%u\n",
+ __func__, __LINE__, p);
} else {
p = p - 1;
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
- phase only: p=%u", __func__, __LINE__,
- p);
+ debug_cond(DLEVEL == 2, "%s:%d backedup phase only: p=%u",
+ __func__, __LINE__, p);
}
scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
/*
* Increase dtap until we first see a passing read (in case the
- * window is smaller than a ptap),
- * and then a failing read to mark the edge of the window again
+ * window is smaller than a ptap), and then a failing read to
+ * mark the edge of the window again.
*/
- /* Find a passing read */
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
+ /* Find a passing read. */
+ debug_cond(DLEVEL == 2, "%s:%d find passing read\n",
__func__, __LINE__);
found_passing_read = 0;
found_failing_read = 0;
initial_failing_dtap = d;
for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
- read d=%u\n", __func__, __LINE__, d);
+ debug_cond(DLEVEL == 2, "%s:%d testing read d=%u\n",
+ __func__, __LINE__, d);
scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
@@ -1731,12 +1723,12 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
}
if (found_passing_read) {
- /* Find a failing read */
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
- read\n", __func__, __LINE__);
+ /* Find a failing read. */
+ debug_cond(DLEVEL == 2, "%s:%d find failing read\n",
+ __func__, __LINE__);
for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
- testing read d=%u\n", __func__, __LINE__, d);
+ debug_cond(DLEVEL == 2, "%s:%d testing read d=%u\n",
+ __func__, __LINE__, d);
scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
if (!rw_mgr_mem_calibrate_read_test_all_ranks
@@ -1746,9 +1738,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
}
}
} else {
- debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
- calculate dtaps", __func__, __LINE__);
- debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
+ debug_cond(DLEVEL == 1,
+ "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
+ __func__, __LINE__);
}
/*
@@ -1761,14 +1753,12 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
dtaps_per_ptap = d - initial_failing_dtap;
writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
- debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
- - %u = %u", __func__, __LINE__, d,
- initial_failing_dtap, dtaps_per_ptap);
+ debug_cond(DLEVEL == 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
+ __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
- /* ******************************************** */
- /* * step 6: Find the centre of the window * */
+ /* Step 6: Find the centre of the window. */
if (sdr_find_window_centre(grp, work_bgn, work_end))
- return 0; /* FIXME: Old code, return 0 means failure :-( */
+ return 0;
return 1;
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 132/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 2
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (130 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 131/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 1 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 133/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 3 Marek Vasut
` (41 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
If d != 0 after sdr_working_phase() finishes, the else branch
of the condition has no impact on anything at all, since work_end
was already set independently of the value of "d" . Zap this
useless code.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index a9f31d4..16d09c1 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1630,16 +1630,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(u32 grp)
debug_cond(DLEVEL == 2, "%s:%d p: ptap=%u\n",
__func__, __LINE__, p);
- } else {
- /*
- * Step 3-5b: Find the right edge of the window
- * using delay taps.
- */
- debug_cond(DLEVEL == 2,
- "%s:%d ptap=%u dtap=%u bgn=%u\n",
- __func__, __LINE__, p, d, work_bgn);
-
- work_end = work_bgn;
}
/* The dtap increment to find the failing edge is done here. */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 133/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 3
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (131 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 132/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 2 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 134/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 4 Marek Vasut
` (40 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Clean up odd multiline loop, no functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 16d09c1..3d975f9 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1633,8 +1633,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(u32 grp)
}
/* The dtap increment to find the failing edge is done here. */
- for (; d <= IO_DQS_EN_DELAY_MAX;
- d++, work_end += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
+ for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
debug_cond(DLEVEL == 2, "%s:%d end-2: dtap=%u\n",
__func__, __LINE__, d);
@@ -1645,6 +1644,8 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(u32 grp)
&bit_chk, 0)) {
break;
}
+
+ work_end += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
}
/* Go back to working dtap */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 134/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 4
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (132 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 133/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 3 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 135/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 5 Marek Vasut
` (39 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Implement common sdr_find_phase_delay() function and convert all
places which use such code to this unified function. No functional
change to the code.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 103 ++++++++++++++++++++---------------------
1 file changed, 49 insertions(+), 54 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 3d975f9..e575c21 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1343,6 +1343,43 @@ static int find_vfifo_failing_read(const u32 grp)
}
/**
+ * sdr_find_phase_delay() - Find DQS enable phase or delay
+ * @working: If 1, look for working phase/delay, if 0, look for non-working
+ * @delay: If 1, look for delay, if 0, look for phase
+ * @grp: Read/Write group
+ * @work: Working window position
+ * @work_inc: Working window increment
+ * @pd: DQS Phase/Delay Iterator
+ *
+ * Find working or non-working DQS enable phase setting.
+ */
+static int sdr_find_phase_delay(int working, int delay, const u32 grp,
+ u32 *work, const u32 work_inc, u32 *pd)
+{
+ const u32 max = delay ? IO_DQS_EN_DELAY_MAX : IO_DQS_EN_PHASE_MAX;
+ u32 ret, bit_chk;
+
+ for (; *pd <= max; (*pd)++) {
+ if (delay)
+ scc_mgr_set_dqs_en_delay_all_ranks(grp, *pd);
+ else
+ scc_mgr_set_dqs_en_phase_all_ranks(grp, *pd);
+
+ ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
+ PASS_ONE_BIT, &bit_chk, 0);
+ if (!working)
+ ret = !ret;
+
+ if (ret)
+ return 0;
+
+ if (work)
+ *work += work_inc;
+ }
+
+ return -EINVAL;
+}
+/**
* sdr_find_phase() - Find DQS enable phase
* @working: If 1, look for working phase, if 0, look for non-working phase
* @grp: Read/Write group
@@ -1355,26 +1392,17 @@ static int find_vfifo_failing_read(const u32 grp)
static int sdr_find_phase(int working, const u32 grp, u32 *work,
u32 *i, u32 *p)
{
- u32 ret, bit_chk;
const u32 end = VFIFO_SIZE + (working ? 0 : 1);
+ int ret;
for (; *i < end; (*i)++) {
if (working)
*p = 0;
- for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++) {
- scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
-
- ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
- PASS_ONE_BIT, &bit_chk, 0);
- if (!working)
- ret = !ret;
-
- if (ret)
- return 0;
-
- *work += IO_DELAY_PER_OPA_TAP;
- }
+ ret = sdr_find_phase_delay(working, 0, grp, work,
+ IO_DELAY_PER_OPA_TAP, p);
+ if (!ret)
+ return 0;
if (*p > IO_DQS_EN_PHASE_MAX) {
/* Fiddle with FIFO. */
@@ -1569,7 +1597,6 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(u32 grp)
{
uint32_t d, p, i;
- uint32_t bit_chk;
uint32_t dtaps_per_ptap;
uint32_t work_bgn, work_end;
uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
@@ -1633,20 +1660,8 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(u32 grp)
}
/* The dtap increment to find the failing edge is done here. */
- for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
- debug_cond(DLEVEL == 2, "%s:%d end-2: dtap=%u\n",
- __func__, __LINE__, d);
-
- scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
-
- if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
- PASS_ONE_BIT,
- &bit_chk, 0)) {
- break;
- }
-
- work_end += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
- }
+ sdr_find_phase_delay(0, 1, grp, &work_end,
+ IO_DELAY_PER_DQS_EN_DCHAIN_TAP, &d);
/* Go back to working dtap */
if (d != 0)
@@ -1697,37 +1712,17 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(u32 grp)
/* Find a passing read. */
debug_cond(DLEVEL == 2, "%s:%d find passing read\n",
__func__, __LINE__);
- found_passing_read = 0;
- found_failing_read = 0;
- initial_failing_dtap = d;
- for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
- debug_cond(DLEVEL == 2, "%s:%d testing read d=%u\n",
- __func__, __LINE__, d);
- scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
- if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
- PASS_ONE_BIT,
- &bit_chk, 0)) {
- found_passing_read = 1;
- break;
- }
- }
+ initial_failing_dtap = d;
+ found_passing_read = !sdr_find_phase_delay(1, 1, grp, NULL, 0, &d);
if (found_passing_read) {
/* Find a failing read. */
debug_cond(DLEVEL == 2, "%s:%d find failing read\n",
__func__, __LINE__);
- for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
- debug_cond(DLEVEL == 2, "%s:%d testing read d=%u\n",
- __func__, __LINE__, d);
- scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
-
- if (!rw_mgr_mem_calibrate_read_test_all_ranks
- (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
- found_failing_read = 1;
- break;
- }
- }
+ d++;
+ found_failing_read = !sdr_find_phase_delay(0, 1, grp, NULL, 0,
+ &d);
} else {
debug_cond(DLEVEL == 1,
"%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 135/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 5
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (133 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 134/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 4 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 136/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 6 Marek Vasut
` (38 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Fix the data types, constify where applicable.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index e575c21..b700116 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1593,13 +1593,13 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
return -EINVAL;
}
-/* find a good dqs enable to use */
-static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(u32 grp)
+static u32 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
{
- uint32_t d, p, i;
- uint32_t dtaps_per_ptap;
- uint32_t work_bgn, work_end;
- uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
+ u32 d, p, i;
+ u32 dtaps_per_ptap;
+ u32 work_bgn, work_end;
+ u32 found_passing_read, found_failing_read, initial_failing_dtap;
+ int ret;
debug("%s:%d %u\n", __func__, __LINE__, grp);
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 136/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 6
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (134 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 135/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 5 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 137/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 7 Marek Vasut
` (37 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Fix the return value to match common conventions and propagate
this change through the code.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 31 ++++++++++++++-----------------
1 file changed, 14 insertions(+), 17 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index b700116..5f23777 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1593,7 +1593,7 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
return -EINVAL;
}
-static u32 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
+static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
{
u32 d, p, i;
u32 dtaps_per_ptap;
@@ -1616,8 +1616,9 @@ static u32 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
/* Step 2: Find first working phase, increment in ptaps. */
work_bgn = 0;
- if (sdr_working_phase(grp, &work_bgn, &d, &p, &i))
- return 0;
+ ret = sdr_working_phase(grp, &work_bgn, &d, &p, &i);
+ if (ret)
+ return ret;
work_end = work_bgn;
@@ -1637,8 +1638,9 @@ static u32 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
* Step 4a: go forward from working phase to non working
* phase, increment in ptaps.
*/
- if (sdr_nonworking_phase(grp, &work_end, &p, &i))
- return 0;
+ ret = sdr_nonworking_phase(grp, &work_end, &p, &i);
+ if (ret)
+ return ret;
/* Step 5a: Back off one from last, increment in dtaps. */
@@ -1675,7 +1677,7 @@ static u32 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
/* nil range */
debug_cond(DLEVEL == 2, "%s:%d end-2: failed\n",
__func__, __LINE__);
- return 0;
+ return -EINVAL;
}
debug_cond(DLEVEL == 2, "%s:%d found range [%u,%u]\n",
@@ -1743,10 +1745,9 @@ static u32 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
__func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
/* Step 6: Find the centre of the window. */
- if (sdr_find_window_centre(grp, work_bgn, work_end))
- return 0;
+ ret = sdr_find_window_center(grp, work_bgn, work_end);
- return 1;
+ return ret;
}
/* per-bit deskew DQ and center */
@@ -2184,7 +2185,7 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
/* We start at zero, so have one less dq to devide among */
const u32 delay_step = IO_IO_IN_DELAY_MAX /
(RW_MGR_MEM_DQ_PER_READ_DQS - 1);
- int found;
+ int ret;
u32 i, p, d, r;
debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
@@ -2210,11 +2211,11 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
* Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
* dq_in_delay values
*/
- found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
+ ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
debug_cond(DLEVEL == 1,
"%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
- __func__, __LINE__, rw_group, found);
+ __func__, __LINE__, rw_group, !ret);
for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
r += NUM_RANKS_PER_SHADOW_REG) {
@@ -2222,11 +2223,7 @@ static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
writel(0, &sdr_scc_mgr->update);
}
- if (!found)
- return -EINVAL;
-
- return 0;
-
+ return ret;
}
/**
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 137/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 7
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (135 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 136/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 6 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 138/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_all_ranks() Marek Vasut
` (36 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Add kerneldoc, no functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 5f23777..6999504 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1593,6 +1593,12 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
return -EINVAL;
}
+/**
+ * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to use
+ * @grp: Read/Write Group
+ *
+ * Find a good DQS enable to use.
+ */
static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
{
u32 d, p, i;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 138/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_all_ranks()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (136 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 137/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 7 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 139/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 1 Marek Vasut
` (35 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 40 +++++++++++++++++++++++++---------------
1 file changed, 25 insertions(+), 15 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 6999504..f7e2e40 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1278,12 +1278,23 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group
}
}
-static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
- uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
- uint32_t all_groups)
+/**
+ * rw_mgr_mem_calibrate_read_test_all_ranks() - Perform READ test on all ranks
+ * @grp: Read/Write group
+ * @num_tries: Number of retries of the test
+ * @all_correct: All bits must be correct in the mask
+ * @all_groups: Test all R/W groups
+ *
+ * Perform a READ test across all memory ranks.
+ */
+static int
+rw_mgr_mem_calibrate_read_test_all_ranks(const u32 grp, const u32 num_tries,
+ const u32 all_correct,
+ const u32 all_groups)
{
- return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
- bit_chk, all_groups, 1);
+ u32 bit_chk;
+ return rw_mgr_mem_calibrate_read_test(0, grp, num_tries, all_correct,
+ &bit_chk, all_groups, 1);
}
/**
@@ -1319,13 +1330,13 @@ static void rw_mgr_decr_vfifo(const u32 grp)
*/
static int find_vfifo_failing_read(const u32 grp)
{
- u32 v, ret, bit_chk, fail_cnt = 0;
+ u32 v, ret, fail_cnt = 0;
for (v = 0; v < VFIFO_SIZE; v++) {
debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
__func__, __LINE__, v);
ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
- PASS_ONE_BIT, &bit_chk, 0);
+ PASS_ONE_BIT, 0);
if (!ret) {
fail_cnt++;
@@ -1357,7 +1368,7 @@ static int sdr_find_phase_delay(int working, int delay, const u32 grp,
u32 *work, const u32 work_inc, u32 *pd)
{
const u32 max = delay ? IO_DQS_EN_DELAY_MAX : IO_DQS_EN_PHASE_MAX;
- u32 ret, bit_chk;
+ u32 ret;
for (; *pd <= max; (*pd)++) {
if (delay)
@@ -1366,7 +1377,7 @@ static int sdr_find_phase_delay(int working, int delay, const u32 grp,
scc_mgr_set_dqs_en_phase_all_ranks(grp, *pd);
ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
- PASS_ONE_BIT, &bit_chk, 0);
+ PASS_ONE_BIT, 0);
if (!working)
ret = !ret;
@@ -1459,7 +1470,7 @@ static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
*/
static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
{
- u32 tmp_delay, bit_chk, d;
+ u32 tmp_delay, d;
int ret;
/* Special case code for backing up a phase */
@@ -1476,7 +1487,7 @@ static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
- PASS_ONE_BIT, &bit_chk, 0);
+ PASS_ONE_BIT, 0);
if (ret) {
*work_bgn = tmp_delay;
break;
@@ -1537,7 +1548,7 @@ static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i)
static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
const u32 work_end)
{
- u32 bit_chk, work_mid;
+ u32 work_mid;
int tmp_delay = 0;
int i, p, d;
@@ -1577,7 +1588,7 @@ static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
PASS_ONE_BIT,
- &bit_chk, 0)) {
+ 0)) {
debug_cond(DLEVEL == 2,
"%s:%d center: found: ptap=%u dtap=%u\n",
__func__, __LINE__, p, d);
@@ -2427,7 +2438,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
static uint32_t rw_mgr_mem_calibrate_lfifo(void)
{
uint32_t found_one;
- uint32_t bit_chk;
debug("%s:%d\n", __func__, __LINE__);
@@ -2447,7 +2457,7 @@ static uint32_t rw_mgr_mem_calibrate_lfifo(void)
if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
NUM_READ_TESTS,
PASS_ALL_BITS,
- &bit_chk, 1)) {
+ 1)) {
break;
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 139/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 1
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (137 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 138/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_all_ranks() Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 140/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 2 Marek Vasut
` (34 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Clean up the debug output handling at the end of the function
and factor out common function call from the condition.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 29 ++++++++++++++++-------------
1 file changed, 16 insertions(+), 13 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index f7e2e40..c7ff863 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1189,6 +1189,8 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group
*bit_chk = param->read_correct_mask;
correct_mask_vg = param->read_correct_mask_vg;
+ int ret;
+
uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
@@ -1260,22 +1262,23 @@ static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group
addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
+ set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
+
if (all_correct) {
- set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
- debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
- (%u == %u) => %lu", __func__, __LINE__, group,
- all_groups, *bit_chk, param->read_correct_mask,
- (long unsigned int)(*bit_chk ==
- param->read_correct_mask));
- return *bit_chk == param->read_correct_mask;
+ ret = (*bit_chk == param->read_correct_mask);
+ debug_cond(DLEVEL == 2,
+ "%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n",
+ __func__, __LINE__, group, all_groups, *bit_chk,
+ param->read_correct_mask, ret);
} else {
- set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
- debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
- (%u != %lu) => %lu\n", __func__, __LINE__,
- group, all_groups, *bit_chk, (long unsigned int)0,
- (long unsigned int)(*bit_chk != 0x00));
- return *bit_chk != 0x00;
+ ret = (*bit_chk != 0x00);
+ debug_cond(DLEVEL == 2,
+ "%s:%d read_test(%u,ONE,%u) => (%u != %u) => %i\n",
+ __func__, __LINE__, group, all_groups, *bit_chk,
+ 0, ret);
}
+
+ return ret;
}
/**
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 140/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 2
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (138 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 139/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 1 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 141/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 3 Marek Vasut
` (33 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Clean up data types and constify where applicable. No function change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 30 +++++++++++++++---------------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index c7ff863..76d141a 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1174,25 +1174,25 @@ static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
* inserted into the mix used to align dqs enable. has more thorough checks
* than the regular read test.
*/
-static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
- uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
- uint32_t all_groups, uint32_t all_ranks)
+static int
+rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
+ const u32 num_tries, const u32 all_correct,
+ u32 *bit_chk,
+ const u32 all_groups, const u32 all_ranks)
{
- uint32_t r, vg;
- uint32_t correct_mask_vg;
- uint32_t tmp_bit_chk;
- uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
+ const u32 rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
(rank_bgn + NUM_RANKS_PER_SHADOW_REG);
- uint32_t addr;
- uint32_t base_rw_mgr;
+ const u32 quick_read_mode =
+ ((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) &&
+ ENABLE_SUPER_QUICK_CALIBRATION);
+ u32 correct_mask_vg = param->read_correct_mask_vg;
+ u32 tmp_bit_chk;
+ u32 base_rw_mgr;
+ u32 addr;
- *bit_chk = param->read_correct_mask;
- correct_mask_vg = param->read_correct_mask_vg;
+ int r, vg, ret;
- int ret;
-
- uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
- CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
+ *bit_chk = param->read_correct_mask;
for (r = rank_bgn; r < rank_end; r++) {
if (param->skip_ranks[r])
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 141/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 3
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (139 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 140/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 2 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 142/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 4 Marek Vasut
` (32 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
The C language has signed types, so make use of them. Fix this
obscene loop, which tries to do away with unsigned type, but
just makes the code more cryptic.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 76d141a..c03fae1 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1232,7 +1232,8 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
&sdr_rw_load_jump_mgr_regs->load_jump_add3);
tmp_bit_chk = 0;
- for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
+ for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1; vg >= 0;
+ vg--) {
/* reset the fifos to get pointers to known state */
writel(0, &phy_mgr_cmd->fifo_reset);
writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
@@ -1252,10 +1253,8 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
-
- if (vg == 0)
- break;
}
+
*bit_chk &= tmp_bit_chk;
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 142/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 4
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (140 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 141/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 3 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 143/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 5 Marek Vasut
` (31 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Clean up the inner loop a bit. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index c03fae1..4585e37 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1234,25 +1234,27 @@ rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
tmp_bit_chk = 0;
for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1; vg >= 0;
vg--) {
- /* reset the fifos to get pointers to known state */
+ /* Reset the FIFOs to get pointers to known state. */
writel(0, &phy_mgr_cmd->fifo_reset);
writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
RW_MGR_RESET_READ_DATAPATH_OFFSET);
- tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
- / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
-
- if (all_groups)
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
- else
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+ if (all_groups) {
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_ALL_GROUPS_OFFSET;
+ } else {
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+ }
writel(RW_MGR_READ_B2B, addr +
((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
vg) << 2));
base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
- tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
+ tmp_bit_chk <<= RW_MGR_MEM_DQ_PER_READ_DQS /
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
+ tmp_bit_chk |= correct_mask_vg & ~(base_rw_mgr);
}
*bit_chk &= tmp_bit_chk;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 143/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 5
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (141 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 142/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 4 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 144/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes() Marek Vasut
` (30 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Make the function documentation into kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 4585e37..0d1e6c8 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1169,10 +1169,19 @@ static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
}
-/*
- * try a read and see if it returns correct data back. has dummy reads
- * inserted into the mix used to align dqs enable. has more thorough checks
- * than the regular read test.
+/**
+ * rw_mgr_mem_calibrate_read_test() - Perform READ test on single rank
+ * @rank_bgn: Rank number
+ * @group: Read/Write group
+ * @num_tries: Number of retries of the test
+ * @all_correct: All bits must be correct in the mask
+ * @bit_chk: Resulting bit mask after the test
+ * @all_groups: Test all R/W groups
+ * @all_ranks: Test all ranks
+ *
+ * Try a read and see if it returns correct data back. Test has dummy reads
+ * inserted into the mix used to align DQS enable. Test has more thorough
+ * checks than the regular read test.
*/
static int
rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 144/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (142 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 143/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 5 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 145/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 1 Marek Vasut
` (29 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Reorder the content of the function a little and fix the comments
so they at least become full sentences. Constify function args.
Fix the return value to match the common convention of 0 meaning
success.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 36 ++++++++++++++++++++++++------------
1 file changed, 24 insertions(+), 12 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 0d1e6c8..714fdf0 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3160,25 +3160,37 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
}
-/* calibrate the write operations */
-static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
- uint32_t test_bgn)
+/**
+ * rw_mgr_mem_calibrate_writes() - Write Calibration Part One
+ * @rank_bgn: Rank number
+ * @group: Read/Write Group
+ * @test_bgn: Rank at which the test begins
+ *
+ * Stage 2: Write Calibration Part One.
+ *
+ * This function implements UniPHY calibration Stage 2, as explained in
+ * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
+ */
+static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group,
+ const u32 test_bgn)
{
- /* update info for sims */
- debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
+ int ret;
+
+ /* Update info for sims */
+ debug("%s:%d %u %u\n", __func__, __LINE__, group, test_bgn);
+ reg_file_set_group(group);
reg_file_set_stage(CAL_STAGE_WRITES);
reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
- reg_file_set_group(g);
-
- if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
- set_failing_group_stage(g, CAL_STAGE_WRITES,
+ ret = rw_mgr_mem_calibrate_writes_center(rank_bgn, group, test_bgn);
+ if (!ret) {
+ set_failing_group_stage(group, CAL_STAGE_WRITES,
CAL_SUBSTAGE_WRITES_CENTER);
- return 0;
+ return -EIO;
}
- return 1;
+ return 0;
}
/**
@@ -3472,7 +3484,7 @@ static uint32_t mem_calibrate(void)
continue;
/* Calibrate WRITEs */
- if (rw_mgr_mem_calibrate_writes(rank_bgn,
+ if (!rw_mgr_mem_calibrate_writes(rank_bgn,
write_group, write_test_bgn))
continue;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 145/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 1
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (143 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 144/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes() Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 146/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 2 Marek Vasut
` (28 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Factor out common code from rw_mgr_mem_calibrate_writes_center()
and rw_mgr_mem_calibrate_vfifo_center() for searching for the
right edge of the window. The code is almost identical, so pull
it into separate function and cater for the minor differences.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 418 +++++++++++++++++++----------------------
1 file changed, 197 insertions(+), 221 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 714fdf0..b175313 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1780,6 +1780,166 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
return ret;
}
+/**
+ * search_right_edge() - Find right edge of DQ/DQS working phase
+ * @write: Perform read (Stage 2) or write (Stage 3) calibration
+ * @rank_bgn: Rank number
+ * @write_group: Write Group
+ * @read_group: Read Group
+ * @start_dqs: DQS start phase
+ * @start_dqs_en: DQS enable start phase
+ * @bit_chk: Resulting bit mask after the test
+ * @sticky_bit_chk: Resulting sticky bit mask after the test
+ * @left_edge: Left edge of the DQ/DQS phase
+ * @right_edge: Right edge of the DQ/DQS phase
+ * @use_read_test: Perform read test
+ *
+ * Find right edge of DQ/DQS working phase.
+ */
+static int search_right_edge(const int write, const int rank_bgn,
+ const u32 write_group, const u32 read_group,
+ const int start_dqs, const int start_dqs_en,
+ u32 *bit_chk, u32 *sticky_bit_chk,
+ int *left_edge, int *right_edge, const u32 use_read_test)
+{
+ const u32 correct_mask = write ? param->write_correct_mask :
+ param->read_correct_mask;
+ const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
+ const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
+ const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
+ RW_MGR_MEM_DQ_PER_READ_DQS;
+ u32 stop;
+ int i, d;
+
+ for (d = 0; d <= dqs_max - start_dqs; d++) {
+ if (write) { /* WRITE-ONLY */
+ scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
+ d + start_dqs);
+ } else { /* READ-ONLY */
+ scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
+ if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
+ uint32_t delay = d + start_dqs_en;
+ if (delay > IO_DQS_EN_DELAY_MAX)
+ delay = IO_DQS_EN_DELAY_MAX;
+ scc_mgr_set_dqs_en_delay(read_group, delay);
+ }
+ scc_mgr_load_dqs(read_group);
+ }
+
+ writel(0, &sdr_scc_mgr->update);
+
+ /*
+ * Stop searching when the read test doesn't pass AND when
+ * we've seen a passing read on every bit.
+ */
+ if (write) { /* WRITE-ONLY */
+ stop = !rw_mgr_mem_calibrate_write_test(rank_bgn,
+ write_group,
+ 0, PASS_ONE_BIT,
+ bit_chk, 0);
+
+ } else if (use_read_test) { /* READ-ONLY */
+ stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
+ read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
+ bit_chk, 0, 0);
+ } else { /* READ-ONLY */
+ rw_mgr_mem_calibrate_write_test(rank_bgn,
+ write_group,
+ 0, PASS_ONE_BIT,
+ bit_chk, 0);
+ *bit_chk = *bit_chk >> (per_dqs *
+ (read_group - (write_group *
+ RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
+ stop = (*bit_chk == 0);
+ }
+ *sticky_bit_chk = *sticky_bit_chk | *bit_chk;
+ stop = stop && (*sticky_bit_chk == correct_mask);
+
+ debug_cond(DLEVEL == 2,
+ "%s:%d center(right): dtap=%u => %u == %u && %u", __func__, __LINE__, d,
+ *sticky_bit_chk, correct_mask, stop);
+
+ if (stop == 1) {
+ if (write && (d == 0)) { /* WRITE-ONLY */
+ for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
+ /*
+ * d = 0 failed, but it passed when
+ * testing the left edge, so it must be
+ * marginal, set it to -1
+ */
+ if (right_edge[i] == delay_max + 1 &&
+ left_edge[i] != delay_max + 1)
+ right_edge[i] = -1;
+ }
+ }
+ break;
+ }
+
+ /* stop != 1 */
+ for (i = 0; i < per_dqs; i++) {
+ if (*bit_chk & 1) {
+ /*
+ * Remember a passing test as
+ * the right_edge.
+ */
+ right_edge[i] = d;
+ } else {
+ if (d != 0) {
+ /*
+ * If a right edge has not
+ * been seen yet, then a future
+ * passing test will mark this
+ * edge as the left edge.
+ */
+ if (right_edge[i] == delay_max + 1)
+ left_edge[i] = -(d + 1);
+ } else {
+ /*
+ * d = 0 failed, but it passed
+ * when testing the left edge,
+ * so it must be marginal, set
+ * it to -1
+ */
+ if (right_edge[i] == delay_max + 1 &&
+ left_edge[i] != delay_max + 1)
+ right_edge[i] = -1;
+ /*
+ * If a right edge has not been
+ * seen yet, then a future
+ * passing test will mark this
+ * edge as the left edge.
+ */
+ else if (right_edge[i] == delay_max + 1)
+ left_edge[i] = -(d + 1);
+ }
+ }
+
+ debug_cond(DLEVEL == 2, "%s:%d center[r,d=%u]: ",
+ __func__, __LINE__, d);
+ debug_cond(DLEVEL == 2,
+ "bit_chk_test=%i left_edge[%u]: %d ",
+ *bit_chk & 1, i, left_edge[i]);
+ debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
+ right_edge[i]);
+ *bit_chk = *bit_chk >> 1;
+ }
+ }
+
+ /* Check that all bits have a window */
+ for (i = 0; i < per_dqs; i++) {
+ debug_cond(DLEVEL == 2,
+ "%s:%d write_center: left_edge[%u]: %d right_edge[%u]: %d",
+ __func__, __LINE__, i, left_edge[i],
+ i, right_edge[i]);
+ if ((left_edge[i] == dqs_max + 1) ||
+ (right_edge[i] == dqs_max + 1))
+ return i + 1; /* FIXME: If we fail, retval > 0 */
+ }
+
+ return 0;
+}
+
/* per-bit deskew DQ and center */
static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
@@ -1803,6 +1963,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
uint32_t stop;
uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
uint32_t addr;
+ int ret;
debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
@@ -1909,132 +2070,38 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
}
/* Search for the right edge of the window for each bit */
- for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
- scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
- if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
- uint32_t delay = d + start_dqs_en;
- if (delay > IO_DQS_EN_DELAY_MAX)
- delay = IO_DQS_EN_DELAY_MAX;
- scc_mgr_set_dqs_en_delay(read_group, delay);
- }
- scc_mgr_load_dqs(read_group);
-
- writel(0, &sdr_scc_mgr->update);
-
+ ret = search_right_edge(0, rank_bgn, write_group, read_group,
+ start_dqs, start_dqs_en,
+ &bit_chk, &sticky_bit_chk,
+ left_edge, right_edge, use_read_test);
+ if (ret) {
/*
- * Stop searching when the read test doesn't pass AND when
- * we've seen a passing read on every bit.
+ * Restore delay chain settings before letting the loop
+ * in rw_mgr_mem_calibrate_vfifo to retry different
+ * dqs/ck relationships.
*/
- if (use_read_test) {
- stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
- read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
- &bit_chk, 0, 0);
- } else {
- rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
- 0, PASS_ONE_BIT,
- &bit_chk, 0);
- bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
- (read_group - (write_group *
- RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
- stop = (bit_chk == 0);
- }
- sticky_bit_chk = sticky_bit_chk | bit_chk;
- stop = stop && (sticky_bit_chk == param->read_correct_mask);
+ scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
+ if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
+ scc_mgr_set_dqs_en_delay(read_group, start_dqs_en);
- debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
- %u && %u", __func__, __LINE__, d,
- sticky_bit_chk, param->read_correct_mask, stop);
+ scc_mgr_load_dqs(read_group);
+ writel(0, &sdr_scc_mgr->update);
- if (stop == 1) {
- break;
+ debug_cond(DLEVEL == 1,
+ "%s:%d vfifo_center: failed to find edge [%u]: %d %d",
+ __func__, __LINE__, i, left_edge[i], right_edge[i]);
+ if (use_read_test) {
+ set_failing_group_stage(read_group *
+ RW_MGR_MEM_DQ_PER_READ_DQS + i,
+ CAL_STAGE_VFIFO,
+ CAL_SUBSTAGE_VFIFO_CENTER);
} else {
- for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
- if (bit_chk & 1) {
- /* Remember a passing test as
- the right_edge */
- right_edge[i] = d;
- } else {
- if (d != 0) {
- /* If a right edge has not been
- seen yet, then a future passing
- test will mark this edge as the
- left edge */
- if (right_edge[i] ==
- IO_IO_IN_DELAY_MAX + 1) {
- left_edge[i] = -(d + 1);
- }
- } else {
- /* d = 0 failed, but it passed
- when testing the left edge,
- so it must be marginal,
- set it to -1 */
- if (right_edge[i] ==
- IO_IO_IN_DELAY_MAX + 1 &&
- left_edge[i] !=
- IO_IO_IN_DELAY_MAX
- + 1) {
- right_edge[i] = -1;
- }
- /* If a right edge has not been
- seen yet, then a future passing
- test will mark this edge as the
- left edge */
- else if (right_edge[i] ==
- IO_IO_IN_DELAY_MAX +
- 1) {
- left_edge[i] = -(d + 1);
- }
- }
- }
-
- debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
- d=%u]: ", __func__, __LINE__, d);
- debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
- (int)(bit_chk & 1), i, left_edge[i]);
- debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
- right_edge[i]);
- bit_chk = bit_chk >> 1;
- }
- }
- }
-
- /* Check that all bits have a window */
- for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
- debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
- %d right_edge[%u]: %d", __func__, __LINE__,
- i, left_edge[i], i, right_edge[i]);
- if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
- == IO_IO_IN_DELAY_MAX + 1)) {
- /*
- * Restore delay chain settings before letting the loop
- * in rw_mgr_mem_calibrate_vfifo to retry different
- * dqs/ck relationships.
- */
- scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
- if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
- scc_mgr_set_dqs_en_delay(read_group,
- start_dqs_en);
- }
- scc_mgr_load_dqs(read_group);
- writel(0, &sdr_scc_mgr->update);
-
- debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
- find edge [%u]: %d %d", __func__, __LINE__,
- i, left_edge[i], right_edge[i]);
- if (use_read_test) {
- set_failing_group_stage(read_group *
- RW_MGR_MEM_DQ_PER_READ_DQS + i,
- CAL_STAGE_VFIFO,
- CAL_SUBSTAGE_VFIFO_CENTER);
- } else {
- set_failing_group_stage(read_group *
- RW_MGR_MEM_DQ_PER_READ_DQS + i,
- CAL_STAGE_VFIFO_AFTER_WRITES,
- CAL_SUBSTAGE_VFIFO_CENTER);
- }
- return 0;
+ set_failing_group_stage(read_group *
+ RW_MGR_MEM_DQ_PER_READ_DQS + i,
+ CAL_STAGE_VFIFO_AFTER_WRITES,
+ CAL_SUBSTAGE_VFIFO_CENTER);
}
+ return 0;
}
/* Find middle of window for each DQ bit */
@@ -2729,6 +2796,8 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
uint32_t temp_dq_out1_delay;
uint32_t addr;
+ int ret;
+
debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
dm_margin = 0;
@@ -2833,107 +2902,14 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
}
/* Search for the right edge of the window for each bit */
- for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
- scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
- d + start_dqs);
-
- writel(0, &sdr_scc_mgr->update);
-
- /*
- * Stop searching when the read test doesn't pass AND when
- * we've seen a passing read on every bit.
- */
- stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
- 0, PASS_ONE_BIT, &bit_chk, 0);
-
- sticky_bit_chk = sticky_bit_chk | bit_chk;
- stop = stop && (sticky_bit_chk == param->write_correct_mask);
-
- debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
- %u && %u\n", d, sticky_bit_chk,
- param->write_correct_mask, stop);
-
- if (stop == 1) {
- if (d == 0) {
- for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
- i++) {
- /* d = 0 failed, but it passed when
- testing the left edge, so it must be
- marginal, set it to -1 */
- if (right_edge[i] ==
- IO_IO_OUT1_DELAY_MAX + 1 &&
- left_edge[i] !=
- IO_IO_OUT1_DELAY_MAX + 1) {
- right_edge[i] = -1;
- }
- }
- }
- break;
- } else {
- for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
- if (bit_chk & 1) {
- /*
- * Remember a passing test as
- * the right_edge.
- */
- right_edge[i] = d;
- } else {
- if (d != 0) {
- /*
- * If a right edge has not
- * been seen yet, then a future
- * passing test will mark this
- * edge as the left edge.
- */
- if (right_edge[i] ==
- IO_IO_OUT1_DELAY_MAX + 1)
- left_edge[i] = -(d + 1);
- } else {
- /*
- * d = 0 failed, but it passed
- * when testing the left edge,
- * so it must be marginal, set
- * it to -1.
- */
- if (right_edge[i] ==
- IO_IO_OUT1_DELAY_MAX + 1 &&
- left_edge[i] !=
- IO_IO_OUT1_DELAY_MAX + 1)
- right_edge[i] = -1;
- /*
- * If a right edge has not been
- * seen yet, then a future
- * passing test will mark this
- * edge as the left edge.
- */
- else if (right_edge[i] ==
- IO_IO_OUT1_DELAY_MAX +
- 1)
- left_edge[i] = -(d + 1);
- }
- }
- debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
- debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
- (int)(bit_chk & 1), i, left_edge[i]);
- debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
- right_edge[i]);
- bit_chk = bit_chk >> 1;
- }
- }
- }
-
- /* Check that all bits have a window */
- for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
- debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
- %d right_edge[%u]: %d", __func__, __LINE__,
- i, left_edge[i], i, right_edge[i]);
- if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
- (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
- set_failing_group_stage(test_bgn + i,
- CAL_STAGE_WRITES,
- CAL_SUBSTAGE_WRITES_CENTER);
- return 0;
- }
+ ret = search_right_edge(1, rank_bgn, write_group, 0,
+ start_dqs, 0,
+ &bit_chk, &sticky_bit_chk,
+ left_edge, right_edge, 0);
+ if (ret) {
+ set_failing_group_stage(test_bgn + ret - 1, CAL_STAGE_WRITES,
+ CAL_SUBSTAGE_WRITES_CENTER);
+ return 0;
}
/* Find middle of window for each DQ bit */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 146/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 2
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (144 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 145/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 1 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 147/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 3 Marek Vasut
` (27 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Factor out common code from rw_mgr_mem_calibrate_writes_center()
and rw_mgr_mem_calibrate_vfifo_center() for searching for the
left edge of the window. The code is almost identical, so pull
it into separate function and cater for the minor differences.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 316 +++++++++++++++++++----------------------
1 file changed, 146 insertions(+), 170 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index b175313..8f55e44 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1781,6 +1781,145 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
}
/**
+ * search_left_edge() - Find left edge of DQ/DQS working phase
+ * @write: Perform read (Stage 2) or write (Stage 3) calibration
+ * @rank_bgn: Rank number
+ * @write_group: Write Group
+ * @read_group: Read Group
+ * @test_bgn: Rank number to begin the test
+ * @bit_chk: Resulting bit mask after the test
+ * @sticky_bit_chk: Resulting sticky bit mask after the test
+ * @left_edge: Left edge of the DQ/DQS phase
+ * @right_edge: Right edge of the DQ/DQS phase
+ * @use_read_test: Perform read test
+ *
+ * Find left edge of DQ/DQS working phase.
+ */
+static void search_left_edge(const int write, const int rank_bgn,
+ const u32 write_group, const u32 read_group, const u32 test_bgn,
+ u32 *bit_chk, u32 *sticky_bit_chk,
+ int *left_edge, int *right_edge, const u32 use_read_test)
+{
+ const u32 correct_mask = write ? param->write_correct_mask :
+ param->read_correct_mask;
+ const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
+ const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
+ const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
+ RW_MGR_MEM_DQ_PER_READ_DQS;
+ u32 stop;
+ int i, d;
+
+ for (d = 0; d <= dqs_max; d++) {
+ if (write)
+ scc_mgr_apply_group_dq_out1_delay(d);
+ else
+ scc_mgr_apply_group_dq_in_delay(test_bgn, d);
+
+ writel(0, &sdr_scc_mgr->update);
+
+ /*
+ * Stop searching when the read test doesn't pass AND when
+ * we've seen a passing read on every bit.
+ */
+ if (write) { /* WRITE-ONLY */
+ stop = !rw_mgr_mem_calibrate_write_test(rank_bgn,
+ write_group,
+ 0, PASS_ONE_BIT,
+ bit_chk, 0);
+ } else if (use_read_test) { /* READ-ONLY */
+ stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
+ read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
+ bit_chk, 0, 0);
+ } else { /* READ-ONLY */
+ rw_mgr_mem_calibrate_write_test(rank_bgn,
+ write_group,
+ 0, PASS_ONE_BIT,
+ bit_chk, 0);
+ *bit_chk = *bit_chk >> (per_dqs *
+ (read_group - (write_group *
+ RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
+ stop = (*bit_chk == 0);
+ }
+ *sticky_bit_chk = *sticky_bit_chk | *bit_chk;
+ stop = stop && (*sticky_bit_chk == correct_mask);
+ debug_cond(DLEVEL == 2,
+ "%s:%d center(left): dtap=%u => %u == %u && %u", __func__, __LINE__, d,
+ *sticky_bit_chk, correct_mask, stop);
+
+ if (stop == 1)
+ break;
+
+ /* stop != 1 */
+ for (i = 0; i < per_dqs; i++) {
+ if (*bit_chk & 1) {
+ /*
+ * Remember a passing test as
+ * the left_edge.
+ */
+ left_edge[i] = d;
+ } else {
+ /*
+ * If a left edge has not been seen
+ * yet, then a future passing test
+ * will mark this edge as the right
+ * edge.
+ */
+ if (left_edge[i] == delay_max + 1)
+ right_edge[i] = -(d + 1);
+ }
+ *bit_chk = *bit_chk >> 1;
+ }
+ }
+
+ /* Reset DQ delay chains to 0 */
+ if (write)
+ scc_mgr_apply_group_dq_out1_delay(0);
+ else
+ scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
+
+ *sticky_bit_chk = 0;
+ for (i = per_dqs - 1; i >= 0; i--) {
+ debug_cond(DLEVEL == 2,
+ "%s:%d vfifo_center: left_edge[%u]: %d right_edge[%u]: %d\n",
+ __func__, __LINE__, i, left_edge[i],
+ i, right_edge[i]);
+
+ /*
+ * Check for cases where we haven't found the left edge,
+ * which makes our assignment of the the right edge invalid.
+ * Reset it to the illegal value.
+ */
+ if ((left_edge[i] == delay_max + 1) &&
+ (right_edge[i] != delay_max + 1)) {
+ right_edge[i] = delay_max + 1;
+ debug_cond(DLEVEL == 2,
+ "%s:%d vfifo_center: reset right_edge[%u]: %d\n",
+ __func__, __LINE__, i, right_edge[i]);
+ }
+
+ /*
+ * Reset sticky bit
+ * READ: except for bits where we have seen both
+ * the left and right edge.
+ * WRITE: except for bits where we have seen the
+ * left edge.
+ */
+ *sticky_bit_chk <<= 1;
+ if (write) {
+ if (left_edge[i] != delay_max + 1)
+ *sticky_bit_chk |= 1;
+ } else {
+ if ((left_edge[i] != delay_max + 1) &&
+ (right_edge[i] != delay_max + 1))
+ *sticky_bit_chk |= 1;
+ }
+ }
+
+
+}
+
+/**
* search_right_edge() - Find right edge of DQ/DQS working phase
* @write: Perform read (Stage 2) or write (Stage 3) calibration
* @rank_bgn: Rank number
@@ -1945,7 +2084,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
uint32_t use_read_test, uint32_t update_fom)
{
- uint32_t i, p, d, min_index;
+ uint32_t i, p, min_index;
/*
* Store these as signed since there are comparisons with
* signed numbers.
@@ -1960,7 +2099,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
final_dqs_en;
int32_t dq_margin, dqs_margin;
- uint32_t stop;
uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
uint32_t addr;
int ret;
@@ -1982,92 +2120,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
}
/* Search for the left edge of the window for each bit */
- for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
- scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
-
- writel(0, &sdr_scc_mgr->update);
-
- /*
- * Stop searching when the read test doesn't pass AND when
- * we've seen a passing read on every bit.
- */
- if (use_read_test) {
- stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
- read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
- &bit_chk, 0, 0);
- } else {
- rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
- 0, PASS_ONE_BIT,
- &bit_chk, 0);
- bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
- (read_group - (write_group *
- RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
- stop = (bit_chk == 0);
- }
- sticky_bit_chk = sticky_bit_chk | bit_chk;
- stop = stop && (sticky_bit_chk == param->read_correct_mask);
- debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
- && %u", __func__, __LINE__, d,
- sticky_bit_chk,
- param->read_correct_mask, stop);
-
- if (stop == 1) {
- break;
- } else {
- for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
- if (bit_chk & 1) {
- /* Remember a passing test as the
- left_edge */
- left_edge[i] = d;
- } else {
- /* If a left edge has not been seen yet,
- then a future passing test will mark
- this edge as the right edge */
- if (left_edge[i] ==
- IO_IO_IN_DELAY_MAX + 1) {
- right_edge[i] = -(d + 1);
- }
- }
- bit_chk = bit_chk >> 1;
- }
- }
- }
-
- /* Reset DQ delay chains to 0 */
- scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
- sticky_bit_chk = 0;
- for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
- debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
- %d right_edge[%u]: %d\n", __func__, __LINE__,
- i, left_edge[i], i, right_edge[i]);
-
- /*
- * Check for cases where we haven't found the left edge,
- * which makes our assignment of the the right edge invalid.
- * Reset it to the illegal value.
- */
- if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
- right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
- right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
- debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
- right_edge[%u]: %d\n", __func__, __LINE__,
- i, right_edge[i]);
- }
-
- /*
- * Reset sticky bit (except for bits where we have seen
- * both the left and right edge).
- */
- sticky_bit_chk = sticky_bit_chk << 1;
- if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
- (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
- sticky_bit_chk = sticky_bit_chk | 1;
- }
-
- if (i == 0)
- break;
- }
+ search_left_edge(0, rank_bgn, write_group, read_group, test_bgn,
+ &bit_chk, &sticky_bit_chk,
+ left_edge, right_edge, use_read_test);
/* Search for the right edge of the window for each bit */
ret = search_right_edge(0, rank_bgn, write_group, read_group,
@@ -2792,7 +2847,6 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
int32_t mid_min, orig_mid_min;
int32_t new_dqs, start_dqs, shift_dq;
int32_t dq_margin, dqs_margin, dm_margin;
- uint32_t stop;
uint32_t temp_dq_out1_delay;
uint32_t addr;
@@ -2819,87 +2873,9 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
}
/* Search for the left edge of the window for each bit */
- for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
- scc_mgr_apply_group_dq_out1_delay(write_group, d);
-
- writel(0, &sdr_scc_mgr->update);
-
- /*
- * Stop searching when the read test doesn't pass AND when
- * we've seen a passing read on every bit.
- */
- stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
- 0, PASS_ONE_BIT, &bit_chk, 0);
- sticky_bit_chk = sticky_bit_chk | bit_chk;
- stop = stop && (sticky_bit_chk == param->write_correct_mask);
- debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
- == %u && %u [bit_chk= %u ]\n",
- d, sticky_bit_chk, param->write_correct_mask,
- stop, bit_chk);
-
- if (stop == 1) {
- break;
- } else {
- for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
- if (bit_chk & 1) {
- /*
- * Remember a passing test as the
- * left_edge.
- */
- left_edge[i] = d;
- } else {
- /*
- * If a left edge has not been seen
- * yet, then a future passing test will
- * mark this edge as the right edge.
- */
- if (left_edge[i] ==
- IO_IO_OUT1_DELAY_MAX + 1) {
- right_edge[i] = -(d + 1);
- }
- }
- debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
- debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
- (int)(bit_chk & 1), i, left_edge[i]);
- debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
- right_edge[i]);
- bit_chk = bit_chk >> 1;
- }
- }
- }
-
- /* Reset DQ delay chains to 0 */
- scc_mgr_apply_group_dq_out1_delay(0);
- sticky_bit_chk = 0;
- for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
- debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
- %d right_edge[%u]: %d\n", __func__, __LINE__,
- i, left_edge[i], i, right_edge[i]);
-
- /*
- * Check for cases where we haven't found the left edge,
- * which makes our assignment of the the right edge invalid.
- * Reset it to the illegal value.
- */
- if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
- (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
- right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
- debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
- right_edge[%u]: %d\n", __func__, __LINE__,
- i, right_edge[i]);
- }
-
- /*
- * Reset sticky bit (except for bits where we have
- * seen the left edge).
- */
- sticky_bit_chk = sticky_bit_chk << 1;
- if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
- sticky_bit_chk = sticky_bit_chk | 1;
-
- if (i == 0)
- break;
- }
+ search_left_edge(1, rank_bgn, write_group, 0, test_bgn,
+ &bit_chk, &sticky_bit_chk,
+ left_edge, right_edge, 0);
/* Search for the right edge of the window for each bit */
ret = search_right_edge(1, rank_bgn, write_group, 0,
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 147/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 3
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (145 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 146/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 2 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 148/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 4 Marek Vasut
` (26 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Factor out common code from search_left_edge() and search_right_edge()
which checks whether searching for the window edge should stop. The
code is almost identical, so pull it into separate function and cater
for the minor differences.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 126 ++++++++++++++++++++---------------------
1 file changed, 60 insertions(+), 66 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 8f55e44..2ecf6b8 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1781,6 +1781,60 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
}
/**
+ * search_stop_check() - Check if the detected edge is valid
+ * @write: Perform read (Stage 2) or write (Stage 3) calibration
+ * @d: DQS delay
+ * @rank_bgn: Rank number
+ * @write_group: Write Group
+ * @read_group: Read Group
+ * @bit_chk: Resulting bit mask after the test
+ * @sticky_bit_chk: Resulting sticky bit mask after the test
+ * @use_read_test: Perform read test
+ *
+ * Test if the found edge is valid.
+ */
+static u32 search_stop_check(const int write, const int d, const int rank_bgn,
+ const u32 write_group, const u32 read_group,
+ u32 *bit_chk, u32 *sticky_bit_chk,
+ const u32 use_read_test)
+{
+ const u32 ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
+ RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
+ const u32 correct_mask = write ? param->write_correct_mask :
+ param->read_correct_mask;
+ const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
+ RW_MGR_MEM_DQ_PER_READ_DQS;
+ u32 ret;
+ /*
+ * Stop searching when the read test doesn't pass AND when
+ * we've seen a passing read on every bit.
+ */
+ if (write) { /* WRITE-ONLY */
+ ret = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
+ 0, PASS_ONE_BIT,
+ bit_chk, 0);
+ } else if (use_read_test) { /* READ-ONLY */
+ ret = !rw_mgr_mem_calibrate_read_test(rank_bgn, read_group,
+ NUM_READ_PB_TESTS,
+ PASS_ONE_BIT, bit_chk,
+ 0, 0);
+ } else { /* READ-ONLY */
+ rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 0,
+ PASS_ONE_BIT, bit_chk, 0);
+ *bit_chk = *bit_chk >> (per_dqs *
+ (read_group - (write_group * ratio)));
+ ret = (*bit_chk == 0);
+ }
+ *sticky_bit_chk = *sticky_bit_chk | *bit_chk;
+ ret = ret && (*sticky_bit_chk == correct_mask);
+ debug_cond(DLEVEL == 2,
+ "%s:%d center(left): dtap=%u => %u == %u && %u",
+ __func__, __LINE__, d,
+ *sticky_bit_chk, correct_mask, ret);
+ return ret;
+}
+
+/**
* search_left_edge() - Find left edge of DQ/DQS working phase
* @write: Perform read (Stage 2) or write (Stage 3) calibration
* @rank_bgn: Rank number
@@ -1800,8 +1854,6 @@ static void search_left_edge(const int write, const int rank_bgn,
u32 *bit_chk, u32 *sticky_bit_chk,
int *left_edge, int *right_edge, const u32 use_read_test)
{
- const u32 correct_mask = write ? param->write_correct_mask :
- param->read_correct_mask;
const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
@@ -1817,36 +1869,9 @@ static void search_left_edge(const int write, const int rank_bgn,
writel(0, &sdr_scc_mgr->update);
- /*
- * Stop searching when the read test doesn't pass AND when
- * we've seen a passing read on every bit.
- */
- if (write) { /* WRITE-ONLY */
- stop = !rw_mgr_mem_calibrate_write_test(rank_bgn,
- write_group,
- 0, PASS_ONE_BIT,
- bit_chk, 0);
- } else if (use_read_test) { /* READ-ONLY */
- stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
- read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
- bit_chk, 0, 0);
- } else { /* READ-ONLY */
- rw_mgr_mem_calibrate_write_test(rank_bgn,
- write_group,
- 0, PASS_ONE_BIT,
- bit_chk, 0);
- *bit_chk = *bit_chk >> (per_dqs *
- (read_group - (write_group *
- RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
- stop = (*bit_chk == 0);
- }
- *sticky_bit_chk = *sticky_bit_chk | *bit_chk;
- stop = stop && (*sticky_bit_chk == correct_mask);
- debug_cond(DLEVEL == 2,
- "%s:%d center(left): dtap=%u => %u == %u && %u", __func__, __LINE__, d,
- *sticky_bit_chk, correct_mask, stop);
-
+ stop = search_stop_check(write, d, rank_bgn, write_group,
+ read_group, bit_chk, sticky_bit_chk,
+ use_read_test);
if (stop == 1)
break;
@@ -1941,8 +1966,6 @@ static int search_right_edge(const int write, const int rank_bgn,
u32 *bit_chk, u32 *sticky_bit_chk,
int *left_edge, int *right_edge, const u32 use_read_test)
{
- const u32 correct_mask = write ? param->write_correct_mask :
- param->read_correct_mask;
const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
@@ -1967,38 +1990,9 @@ static int search_right_edge(const int write, const int rank_bgn,
writel(0, &sdr_scc_mgr->update);
- /*
- * Stop searching when the read test doesn't pass AND when
- * we've seen a passing read on every bit.
- */
- if (write) { /* WRITE-ONLY */
- stop = !rw_mgr_mem_calibrate_write_test(rank_bgn,
- write_group,
- 0, PASS_ONE_BIT,
- bit_chk, 0);
-
- } else if (use_read_test) { /* READ-ONLY */
- stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
- read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
- bit_chk, 0, 0);
- } else { /* READ-ONLY */
- rw_mgr_mem_calibrate_write_test(rank_bgn,
- write_group,
- 0, PASS_ONE_BIT,
- bit_chk, 0);
- *bit_chk = *bit_chk >> (per_dqs *
- (read_group - (write_group *
- RW_MGR_MEM_IF_READ_DQS_WIDTH /
- RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
- stop = (*bit_chk == 0);
- }
- *sticky_bit_chk = *sticky_bit_chk | *bit_chk;
- stop = stop && (*sticky_bit_chk == correct_mask);
-
- debug_cond(DLEVEL == 2,
- "%s:%d center(right): dtap=%u => %u == %u && %u", __func__, __LINE__, d,
- *sticky_bit_chk, correct_mask, stop);
-
+ stop = search_stop_check(write, d, rank_bgn, write_group,
+ read_group, bit_chk, sticky_bit_chk,
+ use_read_test);
if (stop == 1) {
if (write && (d == 0)) { /* WRITE-ONLY */
for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 148/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 4
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (146 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 147/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 3 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 149/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 5 Marek Vasut
` (25 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
First of all, don't break strings in the debug_cond() calls across
multiple lines. Next, zap a couple of really odd casts in the code.
Finally, make i into a signed variable, so it is possible to avoid
constructs of the form:
for (i = FOO;; i--) { <code>; if (i == 0) break; }.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 40 +++++++++++++++++++++++-----------------
1 file changed, 23 insertions(+), 17 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 2ecf6b8..3db226d 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2078,7 +2078,8 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
uint32_t use_read_test, uint32_t update_fom)
{
- uint32_t i, p, min_index;
+ uint32_t p, min_index;
+ int i;
/*
* Store these as signed since there are comparisons with
* signed numbers.
@@ -2118,6 +2119,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
&bit_chk, &sticky_bit_chk,
left_edge, right_edge, use_read_test);
+
/* Search for the right edge of the window for each bit */
ret = search_right_edge(0, rank_bgn, write_group, read_group,
start_dqs, start_dqs_en,
@@ -2198,8 +2200,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
}
new_dqs = start_dqs - mid_min;
- debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
- new_dqs=%d mid_min=%d\n", start_dqs,
+ debug_cond(DLEVEL == 1,
+ "vfifo_center: start_dqs=%d start_dqs_en=%d new_dqs=%d mid_min=%d\n",
+ start_dqs,
IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
new_dqs, mid_min);
@@ -2214,28 +2217,31 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
(left_edge[min_index] - right_edge[min_index]))/2 +
(orig_mid_min - mid_min);
- debug_cond(DLEVEL == 2, "vfifo_center: before: \
- shift_dq[%u]=%d\n", i, shift_dq);
+ debug_cond(DLEVEL == 2,
+ "vfifo_center: before: shift_dq[%u]=%d\n",
+ i, shift_dq);
addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
temp_dq_in_delay1 = readl(addr + (p << 2));
temp_dq_in_delay2 = readl(addr + (i << 2));
- if (shift_dq + (int32_t)temp_dq_in_delay1 >
- (int32_t)IO_IO_IN_DELAY_MAX) {
- shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
- } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
- shift_dq = -(int32_t)temp_dq_in_delay1;
- }
- debug_cond(DLEVEL == 2, "vfifo_center: after: \
- shift_dq[%u]=%d\n", i, shift_dq);
+ if (shift_dq + temp_dq_in_delay1 > IO_IO_IN_DELAY_MAX)
+ shift_dq = IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
+ else if (shift_dq + temp_dq_in_delay1 < 0)
+ shift_dq = -temp_dq_in_delay1;
+
+ debug_cond(DLEVEL == 2,
+ "vfifo_center: after: shift_dq[%u]=%d\n",
+ i, shift_dq);
final_dq[i] = temp_dq_in_delay1 + shift_dq;
scc_mgr_set_dq_in_delay(p, final_dq[i]);
scc_mgr_load_dq(p);
- debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
+ debug_cond(DLEVEL == 2,
+ "vfifo_center: margin[%u]=[%d,%d]\n", i,
left_edge[i] - shift_dq + (-mid_min),
right_edge[i] + shift_dq - (-mid_min));
+
/* To determine values for export structures */
if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
dq_margin = left_edge[i] - shift_dq + (-mid_min);
@@ -2257,9 +2263,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
/* Move DQS */
scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
scc_mgr_load_dqs(read_group);
- debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
- dqs_margin=%d", __func__, __LINE__,
- dq_margin, dqs_margin);
+ debug_cond(DLEVEL == 2,
+ "%s:%d vfifo_center: dq_margin=%d dqs_margin=%d",
+ __func__, __LINE__, dq_margin, dqs_margin);
/*
* Do not remove this line as it makes sure all of our decisions
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 149/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 5
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (147 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 148/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 4 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 150/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 6 Marek Vasut
` (24 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Factor out the get_window_mid_index() for finding the best DQ
window centering. This is again code common to two stages, so
pull it out.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 90 +++++++++++++++++++++---------------------
1 file changed, 44 insertions(+), 46 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 3db226d..d6b96f4 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2073,6 +2073,48 @@ static int search_right_edge(const int write, const int rank_bgn,
return 0;
}
+/**
+ * get_window_mid_index() - Find the best middle setting of DQ/DQS phase
+ * @write: Perform read (Stage 2) or write (Stage 3) calibration
+ * @left_edge: Left edge of the DQ/DQS phase
+ * @right_edge: Right edge of the DQ/DQS phase
+ * @mid_min: Best DQ/DQS phase middle setting
+ *
+ * Find index and value of the middle of the DQ/DQS working phase.
+ */
+static int get_window_mid_index(const int write, int *left_edge,
+ int *right_edge, int *mid_min)
+{
+ const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
+ RW_MGR_MEM_DQ_PER_READ_DQS;
+ int i, mid, min_index;
+
+ /* Find middle of window for each DQ bit */
+ *mid_min = left_edge[0] - right_edge[0];
+ min_index = 0;
+ for (i = 1; i < per_dqs; i++) {
+ mid = left_edge[i] - right_edge[i];
+ if (mid < *mid_min) {
+ *mid_min = mid;
+ min_index = i;
+ }
+ }
+
+ /*
+ * -mid_min/2 represents the amount that we need to move DQS.
+ * If mid_min is odd and positive we'll need to add one to make
+ * sure the rounding in further calculations is correct (always
+ * bias to the right), so just add 1 for all positive values.
+ */
+ if (*mid_min > 0)
+ (*mid_min)++;
+ *mid_min = *mid_min / 2;
+
+ debug_cond(DLEVEL == 1, "%s:%d vfifo_center: *mid_min=%d (index=%u)\n",
+ __func__, __LINE__, *mid_min, min_index);
+ return min_index;
+}
+
/* per-bit deskew DQ and center */
static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
@@ -2155,30 +2197,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
return 0;
}
- /* Find middle of window for each DQ bit */
- mid_min = left_edge[0] - right_edge[0];
- min_index = 0;
- for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
- mid = left_edge[i] - right_edge[i];
- if (mid < mid_min) {
- mid_min = mid;
- min_index = i;
- }
- }
-
- /*
- * -mid_min/2 represents the amount that we need to move DQS.
- * If mid_min is odd and positive we'll need to add one to
- * make sure the rounding in further calculations is correct
- * (always bias to the right), so just add 1 for all positive values.
- */
- if (mid_min > 0)
- mid_min++;
-
- mid_min = mid_min / 2;
-
- debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
- __func__, __LINE__, mid_min, min_index);
+ min_index = get_window_mid_index(0, left_edge, right_edge, &mid_min);
/* Determine the amount we can change DQS (which is -mid_min) */
orig_mid_min = mid_min;
@@ -2888,28 +2907,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
return 0;
}
- /* Find middle of window for each DQ bit */
- mid_min = left_edge[0] - right_edge[0];
- min_index = 0;
- for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
- mid = left_edge[i] - right_edge[i];
- if (mid < mid_min) {
- mid_min = mid;
- min_index = i;
- }
- }
-
- /*
- * -mid_min/2 represents the amount that we need to move DQS.
- * If mid_min is odd and positive we'll need to add one to
- * make sure the rounding in further calculations is correct
- * (always bias to the right), so just add 1 for all positive values.
- */
- if (mid_min > 0)
- mid_min++;
- mid_min = mid_min / 2;
- debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
- __LINE__, mid_min);
+ min_index = get_window_mid_index(1, left_edge, right_edge, &mid_min);
/* Determine the amount we can change DQS (which is -mid_min) */
orig_mid_min = mid_min;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 150/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 6
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (148 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 149/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 5 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 151/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 7 Marek Vasut
` (23 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Factor out center_dq_windows(), which is common code between
stage 2 and stage 3 of the calibration again and cater for
the minor differences.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 177 ++++++++++++++++++++---------------------
1 file changed, 88 insertions(+), 89 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index d6b96f4..e3cd8a9 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2115,13 +2115,90 @@ static int get_window_mid_index(const int write, int *left_edge,
return min_index;
}
+/**
+ * center_dq_windows() - Center the DQ/DQS windows
+ * @write: Perform read (Stage 2) or write (Stage 3) calibration
+ * @left_edge: Left edge of the DQ/DQS phase
+ * @right_edge: Right edge of the DQ/DQS phase
+ * @mid_min: Adjusted DQ/DQS phase middle setting
+ * @orig_mid_min: Original DQ/DQS phase middle setting
+ * @min_index: DQ/DQS phase middle setting index
+ * @test_bgn: Rank number to begin the test
+ * @dq_margin: Amount of shift for the DQ
+ * @dqs_margin: Amount of shift for the DQS
+ *
+ * Align the DQ/DQS windows in each group.
+ */
+static void center_dq_windows(const int write, int *left_edge, int *right_edge,
+ const int mid_min, const int orig_mid_min,
+ const int min_index, const int test_bgn,
+ int *dq_margin, int *dqs_margin)
+{
+ const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
+ const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
+ RW_MGR_MEM_DQ_PER_READ_DQS;
+ const u32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
+ SCC_MGR_IO_IN_DELAY_OFFSET;
+ const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off;
+
+ u32 temp_dq_io_delay1, temp_dq_io_delay2;
+ int shift_dq, i, p;
+
+ /* Initialize data for export structures */
+ *dqs_margin = delay_max + 1;
+ *dq_margin = delay_max + 1;
+
+ /* add delay to bring centre of all DQ windows to the same "level" */
+ for (i = 0, p = test_bgn; i < per_dqs; i++, p++) {
+ /* Use values before divide by 2 to reduce round off error */
+ shift_dq = (left_edge[i] - right_edge[i] -
+ (left_edge[min_index] - right_edge[min_index]))/2 +
+ (orig_mid_min - mid_min);
+
+ debug_cond(DLEVEL == 2,
+ "vfifo_center: before: shift_dq[%u]=%d\n",
+ i, shift_dq);
+
+ temp_dq_io_delay1 = readl(addr + (p << 2));
+ temp_dq_io_delay2 = readl(addr + (i << 2));
+
+ if (shift_dq + temp_dq_io_delay1 > delay_max)
+ shift_dq = delay_max - temp_dq_io_delay2;
+ else if (shift_dq + temp_dq_io_delay1 < 0)
+ shift_dq = -temp_dq_io_delay1;
+
+ debug_cond(DLEVEL == 2,
+ "vfifo_center: after: shift_dq[%u]=%d\n",
+ i, shift_dq);
+
+ if (write)
+ scc_mgr_set_dq_out1_delay(i, temp_dq_io_delay1 + shift_dq);
+ else
+ scc_mgr_set_dq_in_delay(p, temp_dq_io_delay1 + shift_dq);
+
+ scc_mgr_load_dq(p);
+
+ debug_cond(DLEVEL == 2,
+ "vfifo_center: margin[%u]=[%d,%d]\n", i,
+ left_edge[i] - shift_dq + (-mid_min),
+ right_edge[i] + shift_dq - (-mid_min));
+
+ /* To determine values for export structures */
+ if (left_edge[i] - shift_dq + (-mid_min) < *dq_margin)
+ *dq_margin = left_edge[i] - shift_dq + (-mid_min);
+
+ if (right_edge[i] + shift_dq - (-mid_min) < *dqs_margin)
+ *dqs_margin = right_edge[i] + shift_dq - (-mid_min);
+ }
+
+}
+
/* per-bit deskew DQ and center */
static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
uint32_t use_read_test, uint32_t update_fom)
{
- uint32_t p, min_index;
- int i;
+ int i, min_index;
/*
* Store these as signed since there are comparisons with
* signed numbers.
@@ -2130,13 +2207,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
uint32_t sticky_bit_chk;
int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
- int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
- int32_t mid;
int32_t orig_mid_min, mid_min;
- int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
- final_dqs_en;
+ int32_t new_dqs, start_dqs, start_dqs_en, final_dqs, final_dqs_en;
int32_t dq_margin, dqs_margin;
- uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
uint32_t addr;
int ret;
@@ -2225,49 +2298,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
new_dqs, mid_min);
- /* Initialize data for export structures */
- dqs_margin = IO_IO_IN_DELAY_MAX + 1;
- dq_margin = IO_IO_IN_DELAY_MAX + 1;
-
- /* add delay to bring centre of all DQ windows to the same "level" */
- for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
- /* Use values before divide by 2 to reduce round off error */
- shift_dq = (left_edge[i] - right_edge[i] -
- (left_edge[min_index] - right_edge[min_index]))/2 +
- (orig_mid_min - mid_min);
-
- debug_cond(DLEVEL == 2,
- "vfifo_center: before: shift_dq[%u]=%d\n",
- i, shift_dq);
-
- addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
- temp_dq_in_delay1 = readl(addr + (p << 2));
- temp_dq_in_delay2 = readl(addr + (i << 2));
-
- if (shift_dq + temp_dq_in_delay1 > IO_IO_IN_DELAY_MAX)
- shift_dq = IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
- else if (shift_dq + temp_dq_in_delay1 < 0)
- shift_dq = -temp_dq_in_delay1;
-
- debug_cond(DLEVEL == 2,
- "vfifo_center: after: shift_dq[%u]=%d\n",
- i, shift_dq);
- final_dq[i] = temp_dq_in_delay1 + shift_dq;
- scc_mgr_set_dq_in_delay(p, final_dq[i]);
- scc_mgr_load_dq(p);
-
- debug_cond(DLEVEL == 2,
- "vfifo_center: margin[%u]=[%d,%d]\n", i,
- left_edge[i] - shift_dq + (-mid_min),
- right_edge[i] + shift_dq - (-mid_min));
-
- /* To determine values for export structures */
- if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
- dq_margin = left_edge[i] - shift_dq + (-mid_min);
-
- if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
- dqs_margin = right_edge[i] + shift_dq - (-mid_min);
- }
+ /* Add delay to bring centre of all DQ windows to the same "level". */
+ center_dq_windows(0, left_edge, right_edge, mid_min, orig_mid_min,
+ min_index, test_bgn, &dq_margin, &dqs_margin);
final_dqs = new_dqs;
if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
@@ -2852,7 +2885,7 @@ static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
uint32_t write_group, uint32_t test_bgn)
{
- uint32_t i, p, min_index;
+ uint32_t i, min_index;
int32_t d;
/*
* Store these as signed since there are comparisons with
@@ -2864,9 +2897,8 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
int32_t mid;
int32_t mid_min, orig_mid_min;
- int32_t new_dqs, start_dqs, shift_dq;
+ int32_t new_dqs, start_dqs;
int32_t dq_margin, dqs_margin, dm_margin;
- uint32_t temp_dq_out1_delay;
uint32_t addr;
int ret;
@@ -2915,43 +2947,10 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
mid_min = 0;
debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
- /* Initialize data for export structures */
- dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
- dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
-
- /* add delay to bring centre of all DQ windows to the same "level" */
- for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
- /* Use values before divide by 2 to reduce round off error */
- shift_dq = (left_edge[i] - right_edge[i] -
- (left_edge[min_index] - right_edge[min_index]))/2 +
- (orig_mid_min - mid_min);
-
- debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
- [%u]=%d\n", __func__, __LINE__, i, shift_dq);
-
- addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
- temp_dq_out1_delay = readl(addr + (i << 2));
- if (shift_dq + (int32_t)temp_dq_out1_delay >
- (int32_t)IO_IO_OUT1_DELAY_MAX) {
- shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
- } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
- shift_dq = -(int32_t)temp_dq_out1_delay;
- }
- debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
- i, shift_dq);
- scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
- scc_mgr_load_dq(i);
- debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
- left_edge[i] - shift_dq + (-mid_min),
- right_edge[i] + shift_dq - (-mid_min));
- /* To determine values for export structures */
- if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
- dq_margin = left_edge[i] - shift_dq + (-mid_min);
-
- if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
- dqs_margin = right_edge[i] + shift_dq - (-mid_min);
- }
+ /* Add delay to bring centre of all DQ windows to the same "level". */
+ center_dq_windows(1, left_edge, right_edge, mid_min, orig_mid_min,
+ min_index, 0, &dq_margin, &dqs_margin);
/* Move DQS */
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 151/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 7
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (149 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 150/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 6 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 152/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 8 Marek Vasut
` (22 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Perform minor reordering of the function to make the code more
organised, no functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index e3cd8a9..eadf39b 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2198,7 +2198,9 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
uint32_t use_read_test, uint32_t update_fom)
{
- int i, min_index;
+ const u32 addr =
+ SDR_PHYGRP_SCCGRP_ADDRESS + SCC_MGR_DQS_IN_DELAY_OFFSET +
+ (read_group << 2);
/*
* Store these as signed since there are comparisons with
* signed numbers.
@@ -2208,18 +2210,16 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
int32_t orig_mid_min, mid_min;
- int32_t new_dqs, start_dqs, start_dqs_en, final_dqs, final_dqs_en;
+ int32_t new_dqs, start_dqs, start_dqs_en, final_dqs_en;
int32_t dq_margin, dqs_margin;
- uint32_t addr;
+ int i, min_index;
int ret;
debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
- addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
- start_dqs = readl(addr + (read_group << 2));
+ start_dqs = readl(addr);
if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
- start_dqs_en = readl(addr + ((read_group << 2)
- - IO_DQS_EN_DELAY_OFFSET));
+ start_dqs_en = readl(addr - IO_DQS_EN_DELAY_OFFSET);
/* set the left and right edge of each bit to an illegal value */
/* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
@@ -2302,18 +2302,15 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
center_dq_windows(0, left_edge, right_edge, mid_min, orig_mid_min,
min_index, test_bgn, &dq_margin, &dqs_margin);
- final_dqs = new_dqs;
- if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
- final_dqs_en = start_dqs_en - mid_min;
-
/* Move DQS-en */
if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
+ final_dqs_en = start_dqs_en - mid_min;
scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
scc_mgr_load_dqs(read_group);
}
/* Move DQS */
- scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
+ scc_mgr_set_dqs_bus_in_delay(read_group, new_dqs);
scc_mgr_load_dqs(read_group);
debug_cond(DLEVEL == 2,
"%s:%d vfifo_center: dq_margin=%d dqs_margin=%d",
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 152/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 8
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (150 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 151/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 7 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 153/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 9 Marek Vasut
` (21 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
The search_stop_check() always resets the bit_chk to a new value,
so bit_chk will never survive between search_left_edge() and
search_right_edge() invocation. There is thus no need to pass
it into these functions, so make bit_chk local to them.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 33 +++++++++++++++------------------
1 file changed, 15 insertions(+), 18 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index eadf39b..a01a2dc 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1841,7 +1841,6 @@ static u32 search_stop_check(const int write, const int d, const int rank_bgn,
* @write_group: Write Group
* @read_group: Read Group
* @test_bgn: Rank number to begin the test
- * @bit_chk: Resulting bit mask after the test
* @sticky_bit_chk: Resulting sticky bit mask after the test
* @left_edge: Left edge of the DQ/DQS phase
* @right_edge: Right edge of the DQ/DQS phase
@@ -1851,14 +1850,14 @@ static u32 search_stop_check(const int write, const int d, const int rank_bgn,
*/
static void search_left_edge(const int write, const int rank_bgn,
const u32 write_group, const u32 read_group, const u32 test_bgn,
- u32 *bit_chk, u32 *sticky_bit_chk,
+ u32 *sticky_bit_chk,
int *left_edge, int *right_edge, const u32 use_read_test)
{
const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
RW_MGR_MEM_DQ_PER_READ_DQS;
- u32 stop;
+ u32 stop, bit_chk;
int i, d;
for (d = 0; d <= dqs_max; d++) {
@@ -1870,14 +1869,14 @@ static void search_left_edge(const int write, const int rank_bgn,
writel(0, &sdr_scc_mgr->update);
stop = search_stop_check(write, d, rank_bgn, write_group,
- read_group, bit_chk, sticky_bit_chk,
+ read_group, &bit_chk, sticky_bit_chk,
use_read_test);
if (stop == 1)
break;
/* stop != 1 */
for (i = 0; i < per_dqs; i++) {
- if (*bit_chk & 1) {
+ if (bit_chk & 1) {
/*
* Remember a passing test as
* the left_edge.
@@ -1893,7 +1892,7 @@ static void search_left_edge(const int write, const int rank_bgn,
if (left_edge[i] == delay_max + 1)
right_edge[i] = -(d + 1);
}
- *bit_chk = *bit_chk >> 1;
+ bit_chk >>= 1;
}
}
@@ -1952,7 +1951,6 @@ static void search_left_edge(const int write, const int rank_bgn,
* @read_group: Read Group
* @start_dqs: DQS start phase
* @start_dqs_en: DQS enable start phase
- * @bit_chk: Resulting bit mask after the test
* @sticky_bit_chk: Resulting sticky bit mask after the test
* @left_edge: Left edge of the DQ/DQS phase
* @right_edge: Right edge of the DQ/DQS phase
@@ -1963,14 +1961,14 @@ static void search_left_edge(const int write, const int rank_bgn,
static int search_right_edge(const int write, const int rank_bgn,
const u32 write_group, const u32 read_group,
const int start_dqs, const int start_dqs_en,
- u32 *bit_chk, u32 *sticky_bit_chk,
+ u32 *sticky_bit_chk,
int *left_edge, int *right_edge, const u32 use_read_test)
{
const u32 delay_max = write ? IO_IO_OUT1_DELAY_MAX : IO_IO_IN_DELAY_MAX;
const u32 dqs_max = write ? IO_IO_OUT1_DELAY_MAX : IO_DQS_IN_DELAY_MAX;
const u32 per_dqs = write ? RW_MGR_MEM_DQ_PER_WRITE_DQS :
RW_MGR_MEM_DQ_PER_READ_DQS;
- u32 stop;
+ u32 stop, bit_chk;
int i, d;
for (d = 0; d <= dqs_max - start_dqs; d++) {
@@ -1991,7 +1989,7 @@ static int search_right_edge(const int write, const int rank_bgn,
writel(0, &sdr_scc_mgr->update);
stop = search_stop_check(write, d, rank_bgn, write_group,
- read_group, bit_chk, sticky_bit_chk,
+ read_group, &bit_chk, sticky_bit_chk,
use_read_test);
if (stop == 1) {
if (write && (d == 0)) { /* WRITE-ONLY */
@@ -2011,7 +2009,7 @@ static int search_right_edge(const int write, const int rank_bgn,
/* stop != 1 */
for (i = 0; i < per_dqs; i++) {
- if (*bit_chk & 1) {
+ if (bit_chk & 1) {
/*
* Remember a passing test as
* the right_edge.
@@ -2052,10 +2050,10 @@ static int search_right_edge(const int write, const int rank_bgn,
__func__, __LINE__, d);
debug_cond(DLEVEL == 2,
"bit_chk_test=%i left_edge[%u]: %d ",
- *bit_chk & 1, i, left_edge[i]);
+ bit_chk & 1, i, left_edge[i]);
debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
right_edge[i]);
- *bit_chk = *bit_chk >> 1;
+ bit_chk >>= 1;
}
}
@@ -2205,7 +2203,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
* Store these as signed since there are comparisons with
* signed numbers.
*/
- uint32_t bit_chk;
uint32_t sticky_bit_chk;
int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
@@ -2231,14 +2228,14 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
/* Search for the left edge of the window for each bit */
search_left_edge(0, rank_bgn, write_group, read_group, test_bgn,
- &bit_chk, &sticky_bit_chk,
+ &sticky_bit_chk,
left_edge, right_edge, use_read_test);
/* Search for the right edge of the window for each bit */
ret = search_right_edge(0, rank_bgn, write_group, read_group,
start_dqs, start_dqs_en,
- &bit_chk, &sticky_bit_chk,
+ &sticky_bit_chk,
left_edge, right_edge, use_read_test);
if (ret) {
/*
@@ -2922,13 +2919,13 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
/* Search for the left edge of the window for each bit */
search_left_edge(1, rank_bgn, write_group, 0, test_bgn,
- &bit_chk, &sticky_bit_chk,
+ &sticky_bit_chk,
left_edge, right_edge, 0);
/* Search for the right edge of the window for each bit */
ret = search_right_edge(1, rank_bgn, write_group, 0,
start_dqs, 0,
- &bit_chk, &sticky_bit_chk,
+ &sticky_bit_chk,
left_edge, right_edge, 0);
if (ret) {
set_failing_group_stage(test_bgn + ret - 1, CAL_STAGE_WRITES,
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 153/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 9
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (151 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 152/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 8 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 154/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 10 Marek Vasut
` (20 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
The read_group and write_group arguments are the same in all
cases when this function is invoked, just merge them into one
rw_group argument. Also, clean up the function argument data
types and constify them.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 35 +++++++++++++++++------------------
1 file changed, 17 insertions(+), 18 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index a01a2dc..ee541ce 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2192,13 +2192,13 @@ static void center_dq_windows(const int write, int *left_edge, int *right_edge,
}
/* per-bit deskew DQ and center */
-static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
- uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
- uint32_t use_read_test, uint32_t update_fom)
+static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
+ const u32 rw_group, const u32 test_bgn,
+ const int use_read_test, const int update_fom)
{
const u32 addr =
SDR_PHYGRP_SCCGRP_ADDRESS + SCC_MGR_DQS_IN_DELAY_OFFSET +
- (read_group << 2);
+ (rw_group << 2);
/*
* Store these as signed since there are comparisons with
* signed numbers.
@@ -2212,7 +2212,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
int i, min_index;
int ret;
- debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
+ debug("%s:%d: %u %u", __func__, __LINE__, rw_group, test_bgn);
start_dqs = readl(addr);
if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
@@ -2227,13 +2227,13 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
}
/* Search for the left edge of the window for each bit */
- search_left_edge(0, rank_bgn, write_group, read_group, test_bgn,
+ search_left_edge(0, rank_bgn, rw_group, rw_group, test_bgn,
&sticky_bit_chk,
left_edge, right_edge, use_read_test);
/* Search for the right edge of the window for each bit */
- ret = search_right_edge(0, rank_bgn, write_group, read_group,
+ ret = search_right_edge(0, rank_bgn, rw_group, rw_group,
start_dqs, start_dqs_en,
&sticky_bit_chk,
left_edge, right_edge, use_read_test);
@@ -2243,23 +2243,23 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
* in rw_mgr_mem_calibrate_vfifo to retry different
* dqs/ck relationships.
*/
- scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
+ scc_mgr_set_dqs_bus_in_delay(rw_group, start_dqs);
if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
- scc_mgr_set_dqs_en_delay(read_group, start_dqs_en);
+ scc_mgr_set_dqs_en_delay(rw_group, start_dqs_en);
- scc_mgr_load_dqs(read_group);
+ scc_mgr_load_dqs(rw_group);
writel(0, &sdr_scc_mgr->update);
debug_cond(DLEVEL == 1,
"%s:%d vfifo_center: failed to find edge [%u]: %d %d",
__func__, __LINE__, i, left_edge[i], right_edge[i]);
if (use_read_test) {
- set_failing_group_stage(read_group *
+ set_failing_group_stage(rw_group *
RW_MGR_MEM_DQ_PER_READ_DQS + i,
CAL_STAGE_VFIFO,
CAL_SUBSTAGE_VFIFO_CENTER);
} else {
- set_failing_group_stage(read_group *
+ set_failing_group_stage(rw_group *
RW_MGR_MEM_DQ_PER_READ_DQS + i,
CAL_STAGE_VFIFO_AFTER_WRITES,
CAL_SUBSTAGE_VFIFO_CENTER);
@@ -2302,13 +2302,13 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
/* Move DQS-en */
if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
final_dqs_en = start_dqs_en - mid_min;
- scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
- scc_mgr_load_dqs(read_group);
+ scc_mgr_set_dqs_en_delay(rw_group, final_dqs_en);
+ scc_mgr_load_dqs(rw_group);
}
/* Move DQS */
- scc_mgr_set_dqs_bus_in_delay(read_group, new_dqs);
- scc_mgr_load_dqs(read_group);
+ scc_mgr_set_dqs_bus_in_delay(rw_group, new_dqs);
+ scc_mgr_load_dqs(rw_group);
debug_cond(DLEVEL == 2,
"%s:%d vfifo_center: dq_margin=%d dqs_margin=%d",
__func__, __LINE__, dq_margin, dqs_margin);
@@ -2456,7 +2456,7 @@ rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
continue;
ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
- rw_group, test_bgn,
+ test_bgn,
use_read_test,
update_fom);
if (ret)
@@ -2595,7 +2595,6 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
if (!param->skip_shadow_regs[sr]) {
/* This is the last calibration round, update FOM here */
if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
- write_group,
read_group,
test_bgn, 0,
1)) {
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 154/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 10
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (152 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 153/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 9 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 155/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 11 Marek Vasut
` (19 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Fix the return value of the function to match common convention
where 0 means success and negative means error. Fix the return
values in case of an error to use errno.h codes.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index ee541ce..efcf283 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2264,7 +2264,7 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
CAL_STAGE_VFIFO_AFTER_WRITES,
CAL_SUBSTAGE_VFIFO_CENTER);
}
- return 0;
+ return -EIO;
}
min_index = get_window_mid_index(0, left_edge, right_edge, &mid_min);
@@ -2319,7 +2319,10 @@ static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
*/
writel(0, &sdr_scc_mgr->update);
- return (dq_margin >= 0) && (dqs_margin >= 0);
+ if ((dq_margin < 0) || (dqs_margin < 0))
+ return -EINVAL;
+
+ return 0;
}
/**
@@ -2459,7 +2462,7 @@ rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
test_bgn,
use_read_test,
update_fom);
- if (ret)
+ if (!ret)
continue;
grp_calibrated = 0;
@@ -2594,7 +2597,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
/* Determine if this set of ranks should be skipped entirely */
if (!param->skip_shadow_regs[sr]) {
/* This is the last calibration round, update FOM here */
- if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
+ if (rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
read_group,
test_bgn, 0,
1)) {
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 155/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 11
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (153 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 154/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 10 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 156/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1 Marek Vasut
` (18 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Add kerneldoc, no functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index efcf283..b81fc8c 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2191,7 +2191,16 @@ static void center_dq_windows(const int write, int *left_edge, int *right_edge,
}
-/* per-bit deskew DQ and center */
+/**
+ * rw_mgr_mem_calibrate_vfifo_center() - Per-bit deskew DQ and centering
+ * @rank_bgn: Rank number
+ * @rw_group: Read/Write Group
+ * @test_bgn: Rank at which the test begins
+ * @use_read_test: Perform a read test
+ * @update_fom: Update FOM
+ *
+ * Per-bit deskew DQ and centering.
+ */
static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
const u32 rw_group, const u32 test_bgn,
const int use_read_test, const int update_fom)
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 156/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (154 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 155/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 11 Marek Vasut
@ 2015-07-27 20:51 ` Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 157/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 2 Marek Vasut
` (17 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:51 UTC (permalink / raw)
To: u-boot
Fix data types and constify where applicable, fix broken multiline
debug strings and fix comments. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 124 +++++++++++++++++++++--------------------
1 file changed, 63 insertions(+), 61 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index b81fc8c..e99ecb4 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2887,24 +2887,26 @@ static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
* center all windows. do per-bit-deskew to possibly increase size of
* certain windows.
*/
-static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
- uint32_t write_group, uint32_t test_bgn)
+static int
+rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
+ const u32 test_bgn)
{
- uint32_t i, min_index;
- int32_t d;
- /*
- * Store these as signed since there are comparisons with
- * signed numbers.
- */
- uint32_t bit_chk;
- uint32_t sticky_bit_chk;
- int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
- int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
- int32_t mid;
- int32_t mid_min, orig_mid_min;
- int32_t new_dqs, start_dqs;
- int32_t dq_margin, dqs_margin, dm_margin;
- uint32_t addr;
+ int i, d;
+ u32 bit_chk;
+ u32 sticky_bit_chk;
+ u32 min_index;
+ u32 addr;
+ int left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
+ int right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
+ int mid;
+ int mid_min, orig_mid_min;
+ int new_dqs, start_dqs;
+ int dq_margin, dqs_margin, dm_margin;
+ int bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
+ int end_curr = IO_IO_OUT1_DELAY_MAX + 1;
+ int bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
+ int end_best = IO_IO_OUT1_DELAY_MAX + 1;
+ int win_best = 0;
int ret;
@@ -2916,11 +2918,11 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
start_dqs = readl(addr +
(RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
- /* per-bit deskew */
+ /* Per-bit deskew. */
/*
- * set the left and right edge of each bit to an illegal value
- * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
+ * Set the left and right edge of each bit to an illegal value.
+ * Use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
*/
sticky_bit_chk = 0;
for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
@@ -2928,12 +2930,12 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
}
- /* Search for the left edge of the window for each bit */
+ /* Search for the left edge of the window for each bit. */
search_left_edge(1, rank_bgn, write_group, 0, test_bgn,
&sticky_bit_chk,
left_edge, right_edge, 0);
- /* Search for the right edge of the window for each bit */
+ /* Search for the right edge of the window for each bit. */
ret = search_right_edge(1, rank_bgn, write_group, 0,
start_dqs, 0,
&sticky_bit_chk,
@@ -2946,12 +2948,13 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
min_index = get_window_mid_index(1, left_edge, right_edge, &mid_min);
- /* Determine the amount we can change DQS (which is -mid_min) */
+ /* Determine the amount we can change DQS (which is -mid_min). */
orig_mid_min = mid_min;
new_dqs = start_dqs;
mid_min = 0;
- debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
- mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
+ debug_cond(DLEVEL == 1,
+ "%s:%d write_center: start_dqs=%d new_dqs=%d mid_min=%d\n",
+ __func__, __LINE__, start_dqs, new_dqs, mid_min);
/* Add delay to bring centre of all DQ windows to the same "level". */
center_dq_windows(1, left_edge, right_edge, mid_min, orig_mid_min,
@@ -2965,18 +2968,13 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
/*
- * set the left and right edge of each bit to an illegal value,
- * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
+ * Set the left and right edge of each bit to an illegal value.
+ * Use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
*/
left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
- int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
- int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
- int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
- int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
- int32_t win_best = 0;
- /* Search for the/part of the window with DM shift */
+ /* Search for the/part of the window with DM shift. */
for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
scc_mgr_apply_group_dm_out1_delay(d);
writel(0, &sdr_scc_mgr->update);
@@ -2984,7 +2982,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
PASS_ALL_BITS, &bit_chk,
0)) {
- /* USE Set current end of the window */
+ /* Set current end of the window. */
end_curr = -d;
/*
* If a starting edge of our window has not been seen
@@ -3003,26 +3001,26 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
end_best = end_curr;
}
} else {
- /* We just saw a failing test. Reset temp edge */
+ /* We just saw a failing test. Reset temp edge. */
bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
end_curr = IO_IO_OUT1_DELAY_MAX + 1;
- }
}
+ }
-
- /* Reset DM delay chains to 0 */
+ /* Reset DM delay chains to 0. */
scc_mgr_apply_group_dm_out1_delay(0);
/*
* Check to see if the current window nudges up aganist 0 delay.
* If so we need to continue the search by shifting DQS otherwise DQS
- * search begins as a new search. */
+ * search begins as a new search.
+ */
if (end_curr != 0) {
bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
end_curr = IO_IO_OUT1_DELAY_MAX + 1;
}
- /* Search for the/part of the window with DQS shifts */
+ /* Search for the/part of the window with DQS shifts. */
for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
/*
* Note: This only shifts DQS, so are we limiting ourselve to
@@ -3035,7 +3033,7 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
PASS_ALL_BITS, &bit_chk,
0)) {
- /* USE Set current end of the window */
+ /* Set current end of the window. */
end_curr = d;
/*
* If a beginning edge of our window has not been seen
@@ -3054,40 +3052,42 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
end_best = end_curr;
}
} else {
- /* We just saw a failing test. Reset temp edge */
+ /* We just saw a failing test. Reset temp edge. */
bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
end_curr = IO_IO_OUT1_DELAY_MAX + 1;
- /* Early exit optimization: if ther remaining delay
- chain space is less than already seen largest window
- we can exit */
+ /*
+ * Early exit optimization: if the remaining delay
+ * chain space is less than already seen largest
+ * window we can exit.
+ */
if ((win_best-1) >
(IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
break;
- }
}
}
+ }
- /* assign left and right edge for cal and reporting; */
- left_edge[0] = -1*bgn_best;
+ /* Assign left and right edge for cal and reporting. */
+ left_edge[0] = -1 * bgn_best;
right_edge[0] = end_best;
- debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
- __LINE__, left_edge[0], right_edge[0]);
+ debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n",
+ __func__, __LINE__, left_edge[0], right_edge[0]);
- /* Move DQS (back to orig) */
+ /* Move DQS (back to orig). */
scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
/* Move DM */
- /* Find middle of window for the DM bit */
+ /* Find middle of window for the DM bit. */
mid = (left_edge[0] - right_edge[0]) / 2;
- /* only move right, since we are not moving DQS/DQ */
+ /* Only move right, since we are not moving DQS/DQ. */
if (mid < 0)
mid = 0;
- /* dm_marign should fail if we never find a window */
+ /* dm_marign should fail if we never find a window. */
if (win_best == 0)
dm_margin = -1;
else
@@ -3096,21 +3096,23 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
scc_mgr_apply_group_dm_out1_delay(mid);
writel(0, &sdr_scc_mgr->update);
- debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
- dm_margin=%d\n", __func__, __LINE__, left_edge[0],
- right_edge[0], mid, dm_margin);
- /* Export values */
+ debug_cond(DLEVEL == 2,
+ "%s:%d dm_calib: left=%d right=%d mid=%d dm_margin=%d\n",
+ __func__, __LINE__, left_edge[0], right_edge[0],
+ mid, dm_margin);
+ /* Export values. */
gbl->fom_out += dq_margin + dqs_margin;
- debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
- dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
- dq_margin, dqs_margin, dm_margin);
+ debug_cond(DLEVEL == 2,
+ "%s:%d write_center: dq_margin=%d dqs_margin=%d dm_margin=%d\n",
+ __func__, __LINE__, dq_margin, dqs_margin, dm_margin);
/*
* Do not remove this line as it makes sure all of our
* decisions have been applied.
*/
writel(0, &sdr_scc_mgr->update);
+
return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 157/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 2
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (155 preceding siblings ...)
2015-07-27 20:51 ` [U-Boot] [PATCH 156/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1 Marek Vasut
@ 2015-07-27 20:52 ` Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 158/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3 Marek Vasut
` (16 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:52 UTC (permalink / raw)
To: u-boot
Factor out common code for searching best DM/DQS window.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 167 ++++++++++++++++++++++-------------------
1 file changed, 88 insertions(+), 79 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index e99ecb4..cc5db16 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2883,6 +2883,89 @@ static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
}
}
+/**
+ * search_window() - Search for the/part of the window with DM/DQS shift
+ * @search_dm: If 1, search for the DM shift, if 0, search for DQS shift
+ * @rank_bgn: Rank number
+ * @write_group: Write Group
+ * @bgn_curr: Current window begin
+ * @end_curr: Current window end
+ * @bgn_best: Current best window begin
+ * @end_best: Current best window end
+ * @win_best: Size of the best window
+ * @new_dqs: New DQS value (only applicable if search_dm = 0).
+ *
+ * Search for the/part of the window with DM/DQS shift.
+ */
+static void search_window(const int search_dm,
+ const u32 rank_bgn, const u32 write_group,
+ int *bgn_curr, int *end_curr, int *bgn_best,
+ int *end_best, int *win_best, int new_dqs)
+{
+ u32 bit_chk;
+ const int max = IO_IO_OUT1_DELAY_MAX - new_dqs;
+ int d, di;
+
+ /* Search for the/part of the window with DM/DQS shift. */
+ for (di = max; di >= 0; di -= DELTA_D) {
+ if (search_dm) {
+ d = di;
+ scc_mgr_apply_group_dm_out1_delay(d);
+ } else {
+ /* For DQS, we go from 0...max */
+ d = max - di;
+ /*
+ * Note: This only shifts DQS, so are we limiting ourselve to
+ * width of DQ unnecessarily.
+ */
+ scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
+ d + new_dqs);
+ }
+
+ writel(0, &sdr_scc_mgr->update);
+
+ if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
+ PASS_ALL_BITS, &bit_chk,
+ 0)) {
+ /* Set current end of the window. */
+ *end_curr = search_dm ? -d : d;
+
+ /*
+ * If a starting edge of our window has not been seen
+ * this is our current start of the DM window.
+ */
+ if (*bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
+ *bgn_curr = search_dm ? -d : d;
+
+ /*
+ * If current window is bigger than best seen.
+ * Set best seen to be current window.
+ */
+ if ((*end_curr - *bgn_curr + 1) > *win_best) {
+ *win_best = *end_curr - *bgn_curr + 1;
+ *bgn_best = *bgn_curr;
+ *end_best = *end_curr;
+ }
+ } else {
+ /* We just saw a failing test. Reset temp edge. */
+ *bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
+ *end_curr = IO_IO_OUT1_DELAY_MAX + 1;
+
+ /* Early exit is only applicable to DQS. */
+ if (search_dm)
+ continue;
+
+ /*
+ * Early exit optimization: if the remaining delay
+ * chain space is less than already seen largest
+ * window we can exit.
+ */
+ if (*win_best - 1 > IO_IO_OUT1_DELAY_MAX - new_dqs - d)
+ break;
+ }
+ }
+}
+
/*
* center all windows. do per-bit-deskew to possibly increase size of
* certain windows.
@@ -2891,8 +2974,7 @@ static int
rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
const u32 test_bgn)
{
- int i, d;
- u32 bit_chk;
+ int i;
u32 sticky_bit_chk;
u32 min_index;
u32 addr;
@@ -2975,37 +3057,8 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
/* Search for the/part of the window with DM shift. */
- for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
- scc_mgr_apply_group_dm_out1_delay(d);
- writel(0, &sdr_scc_mgr->update);
-
- if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
- PASS_ALL_BITS, &bit_chk,
- 0)) {
- /* Set current end of the window. */
- end_curr = -d;
- /*
- * If a starting edge of our window has not been seen
- * this is our current start of the DM window.
- */
- if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
- bgn_curr = -d;
-
- /*
- * If current window is bigger than best seen.
- * Set best seen to be current window.
- */
- if ((end_curr-bgn_curr+1) > win_best) {
- win_best = end_curr-bgn_curr+1;
- bgn_best = bgn_curr;
- end_best = end_curr;
- }
- } else {
- /* We just saw a failing test. Reset temp edge. */
- bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
- end_curr = IO_IO_OUT1_DELAY_MAX + 1;
- }
- }
+ search_window(1, rank_bgn, write_group, &bgn_curr, &end_curr,
+ &bgn_best, &end_best, &win_best, 0);
/* Reset DM delay chains to 0. */
scc_mgr_apply_group_dm_out1_delay(0);
@@ -3021,52 +3074,8 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
}
/* Search for the/part of the window with DQS shifts. */
- for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
- /*
- * Note: This only shifts DQS, so are we limiting ourselve to
- * width of DQ unnecessarily.
- */
- scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
- d + new_dqs);
-
- writel(0, &sdr_scc_mgr->update);
- if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
- PASS_ALL_BITS, &bit_chk,
- 0)) {
- /* Set current end of the window. */
- end_curr = d;
- /*
- * If a beginning edge of our window has not been seen
- * this is our current begin of the DM window.
- */
- if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
- bgn_curr = d;
-
- /*
- * If current window is bigger than best seen. Set best
- * seen to be current window.
- */
- if ((end_curr-bgn_curr+1) > win_best) {
- win_best = end_curr-bgn_curr+1;
- bgn_best = bgn_curr;
- end_best = end_curr;
- }
- } else {
- /* We just saw a failing test. Reset temp edge. */
- bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
- end_curr = IO_IO_OUT1_DELAY_MAX + 1;
-
- /*
- * Early exit optimization: if the remaining delay
- * chain space is less than already seen largest
- * window we can exit.
- */
- if ((win_best-1) >
- (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
- break;
- }
- }
- }
+ search_window(0, rank_bgn, write_group, &bgn_curr, &end_curr,
+ &bgn_best, &end_best, &win_best, new_dqs);
/* Assign left and right edge for cal and reporting. */
left_edge[0] = -1 * bgn_best;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 158/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (156 preceding siblings ...)
2015-07-27 20:52 ` [U-Boot] [PATCH 157/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 2 Marek Vasut
@ 2015-07-27 20:52 ` Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 159/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 4 Marek Vasut
` (15 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:52 UTC (permalink / raw)
To: u-boot
Zap the useless addr variable.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index cc5db16..986f088 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2977,7 +2977,6 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
int i;
u32 sticky_bit_chk;
u32 min_index;
- u32 addr;
int left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
int right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
int mid;
@@ -2996,8 +2995,8 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
dm_margin = 0;
- addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
- start_dqs = readl(addr +
+ start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS |
+ SCC_MGR_IO_OUT1_DELAY_OFFSET) +
(RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
/* Per-bit deskew. */
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 159/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 4
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (157 preceding siblings ...)
2015-07-27 20:52 ` [U-Boot] [PATCH 158/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3 Marek Vasut
@ 2015-07-27 20:52 ` Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 160/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 5 Marek Vasut
` (14 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:52 UTC (permalink / raw)
To: u-boot
Fix return values to match the common return value convention.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 986f088..9cf2a1a 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3024,7 +3024,7 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
if (ret) {
set_failing_group_stage(test_bgn + ret - 1, CAL_STAGE_WRITES,
CAL_SUBSTAGE_WRITES_CENTER);
- return 0;
+ return -EINVAL;
}
min_index = get_window_mid_index(1, left_edge, right_edge, &mid_min);
@@ -3121,7 +3121,10 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
*/
writel(0, &sdr_scc_mgr->update);
- return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
+ if ((dq_margin < 0) || (dqs_margin < 0) || (dm_margin < 0))
+ return -EINVAL;
+
+ return 0;
}
/**
@@ -3148,13 +3151,11 @@ static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group,
reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
ret = rw_mgr_mem_calibrate_writes_center(rank_bgn, group, test_bgn);
- if (!ret) {
+ if (ret)
set_failing_group_stage(group, CAL_STAGE_WRITES,
CAL_SUBSTAGE_WRITES_CENTER);
- return -EIO;
- }
- return 0;
+ return ret;
}
/**
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 160/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 5
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (158 preceding siblings ...)
2015-07-27 20:52 ` [U-Boot] [PATCH 159/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 4 Marek Vasut
@ 2015-07-27 20:52 ` Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 161/172] ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 1 Marek Vasut
` (13 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:52 UTC (permalink / raw)
To: u-boot
Add kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 9cf2a1a..99cd2b2 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2967,7 +2967,12 @@ static void search_window(const int search_dm,
}
/*
- * center all windows. do per-bit-deskew to possibly increase size of
+ * rw_mgr_mem_calibrate_writes_center() - Center all windows
+ * @rank_bgn: Rank number
+ * @write_group: Write group
+ * @test_bgn: Rank at which the test begins
+ *
+ * Center all windows. Do per-bit-deskew to possibly increase size of
* certain windows.
*/
static int
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 161/172] ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 1
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (159 preceding siblings ...)
2015-07-27 20:52 ` [U-Boot] [PATCH 160/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 5 Marek Vasut
@ 2015-07-27 20:52 ` Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 162/172] ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 2 Marek Vasut
` (12 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:52 UTC (permalink / raw)
To: u-boot
Move code around to get rid of the forward declaration. No change
to the actual code.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 406 ++++++++++++++++++++---------------------
1 file changed, 201 insertions(+), 205 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 99cd2b2..659c0d8 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -80,10 +80,6 @@ struct gbl_type *gbl;
struct param_type *param;
uint32_t curr_shadow_reg;
-static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
- uint32_t write_group, uint32_t use_dm,
- uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
-
static void set_failing_group_stage(uint32_t group, uint32_t stage,
uint32_t substage)
{
@@ -1036,6 +1032,207 @@ static void rw_mgr_mem_handoff(void)
*/
}
+/*
+ * issue write test command.
+ * two variants are provided. one that just tests a write pattern and
+ * another that tests datamask functionality.
+ */
+static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
+ uint32_t test_dm)
+{
+ uint32_t mcc_instruction;
+ uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
+ ENABLE_SUPER_QUICK_CALIBRATION);
+ uint32_t rw_wl_nop_cycles;
+ uint32_t addr;
+
+ /*
+ * Set counter and jump addresses for the right
+ * number of NOP cycles.
+ * The number of supported NOP cycles can range from -1 to infinity
+ * Three different cases are handled:
+ *
+ * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
+ * mechanism will be used to insert the right number of NOPs
+ *
+ * 2. For a number of NOP cycles equals to 0, the micro-instruction
+ * issuing the write command will jump straight to the
+ * micro-instruction that turns on DQS (for DDRx), or outputs write
+ * data (for RLD), skipping
+ * the NOP micro-instruction all together
+ *
+ * 3. A number of NOP cycles equal to -1 indicates that DQS must be
+ * turned on in the same micro-instruction that issues the write
+ * command. Then we need
+ * to directly jump to the micro-instruction that sends out the data
+ *
+ * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
+ * (2 and 3). One jump-counter (0) is used to perform multiple
+ * write-read operations.
+ * one counter left to issue this command in "multiple-group" mode
+ */
+
+ rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
+
+ if (rw_wl_nop_cycles == -1) {
+ /*
+ * CNTR 2 - We want to execute the special write operation that
+ * turns on DQS right away and then skip directly to the
+ * instruction that sends out the data. We set the counter to a
+ * large number so that the jump is always taken.
+ */
+ writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
+
+ /* CNTR 3 - Not used */
+ if (test_dm) {
+ mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
+ writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ } else {
+ mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ }
+ } else if (rw_wl_nop_cycles == 0) {
+ /*
+ * CNTR 2 - We want to skip the NOP operation and go straight
+ * to the DQS enable instruction. We set the counter to a large
+ * number so that the jump is always taken.
+ */
+ writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
+
+ /* CNTR 3 - Not used */
+ if (test_dm) {
+ mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
+ writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ } else {
+ mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+ }
+ } else {
+ /*
+ * CNTR 2 - In this case we want to execute the next instruction
+ * and NOT take the jump. So we set the counter to 0. The jump
+ * address doesn't count.
+ */
+ writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
+ writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
+
+ /*
+ * CNTR 3 - Set the nop counter to the number of cycles we
+ * need to loop for, minus 1.
+ */
+ writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
+ if (test_dm) {
+ mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
+ writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ } else {
+ mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add3);
+ }
+ }
+
+ writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RESET_READ_DATAPATH_OFFSET);
+
+ if (quick_write_mode)
+ writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
+ else
+ writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
+
+ writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
+
+ /*
+ * CNTR 1 - This is used to ensure enough time elapses
+ * for read data to come back.
+ */
+ writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
+
+ if (test_dm) {
+ writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ } else {
+ writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
+ &sdr_rw_load_jump_mgr_regs->load_jump_add1);
+ }
+
+ addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
+ writel(mcc_instruction, addr + (group << 2));
+}
+
+/* Test writes, can check for a single bit pass or multiple bit pass */
+static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
+ uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
+ uint32_t *bit_chk, uint32_t all_ranks)
+{
+ uint32_t r;
+ uint32_t correct_mask_vg;
+ uint32_t tmp_bit_chk;
+ uint32_t vg;
+ uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
+ (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
+ uint32_t addr_rw_mgr;
+ uint32_t base_rw_mgr;
+
+ *bit_chk = param->write_correct_mask;
+ correct_mask_vg = param->write_correct_mask_vg;
+
+ for (r = rank_bgn; r < rank_end; r++) {
+ if (param->skip_ranks[r]) {
+ /* request to skip the rank */
+ continue;
+ }
+
+ /* set rank */
+ set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
+
+ tmp_bit_chk = 0;
+ addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
+ for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
+ /* reset the fifos to get pointers to known state */
+ writel(0, &phy_mgr_cmd->fifo_reset);
+
+ tmp_bit_chk = tmp_bit_chk <<
+ (RW_MGR_MEM_DQ_PER_WRITE_DQS /
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
+ rw_mgr_mem_calibrate_write_test_issue(write_group *
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
+ use_dm);
+
+ base_rw_mgr = readl(addr_rw_mgr);
+ tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
+ if (vg == 0)
+ break;
+ }
+ *bit_chk &= tmp_bit_chk;
+ }
+
+ if (all_correct) {
+ set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
+ debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
+ %u => %lu", write_group, use_dm,
+ *bit_chk, param->write_correct_mask,
+ (long unsigned int)(*bit_chk ==
+ param->write_correct_mask));
+ return *bit_chk == param->write_correct_mask;
+ } else {
+ set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
+ debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
+ write_group, use_dm, *bit_chk);
+ debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
+ (long unsigned int)(*bit_chk != 0));
+ return *bit_chk != 0x00;
+ }
+}
+
/**
* rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
* @rank_bgn: Rank number
@@ -2682,207 +2879,6 @@ static uint32_t rw_mgr_mem_calibrate_lfifo(void)
}
}
-/*
- * issue write test command.
- * two variants are provided. one that just tests a write pattern and
- * another that tests datamask functionality.
- */
-static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
- uint32_t test_dm)
-{
- uint32_t mcc_instruction;
- uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
- ENABLE_SUPER_QUICK_CALIBRATION);
- uint32_t rw_wl_nop_cycles;
- uint32_t addr;
-
- /*
- * Set counter and jump addresses for the right
- * number of NOP cycles.
- * The number of supported NOP cycles can range from -1 to infinity
- * Three different cases are handled:
- *
- * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
- * mechanism will be used to insert the right number of NOPs
- *
- * 2. For a number of NOP cycles equals to 0, the micro-instruction
- * issuing the write command will jump straight to the
- * micro-instruction that turns on DQS (for DDRx), or outputs write
- * data (for RLD), skipping
- * the NOP micro-instruction all together
- *
- * 3. A number of NOP cycles equal to -1 indicates that DQS must be
- * turned on in the same micro-instruction that issues the write
- * command. Then we need
- * to directly jump to the micro-instruction that sends out the data
- *
- * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
- * (2 and 3). One jump-counter (0) is used to perform multiple
- * write-read operations.
- * one counter left to issue this command in "multiple-group" mode
- */
-
- rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
-
- if (rw_wl_nop_cycles == -1) {
- /*
- * CNTR 2 - We want to execute the special write operation that
- * turns on DQS right away and then skip directly to the
- * instruction that sends out the data. We set the counter to a
- * large number so that the jump is always taken.
- */
- writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
-
- /* CNTR 3 - Not used */
- if (test_dm) {
- mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
- &sdr_rw_load_jump_mgr_regs->load_jump_add2);
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
- &sdr_rw_load_jump_mgr_regs->load_jump_add3);
- } else {
- mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
- &sdr_rw_load_jump_mgr_regs->load_jump_add2);
- writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
- &sdr_rw_load_jump_mgr_regs->load_jump_add3);
- }
- } else if (rw_wl_nop_cycles == 0) {
- /*
- * CNTR 2 - We want to skip the NOP operation and go straight
- * to the DQS enable instruction. We set the counter to a large
- * number so that the jump is always taken.
- */
- writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
-
- /* CNTR 3 - Not used */
- if (test_dm) {
- mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
- &sdr_rw_load_jump_mgr_regs->load_jump_add2);
- } else {
- mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
- &sdr_rw_load_jump_mgr_regs->load_jump_add2);
- }
- } else {
- /*
- * CNTR 2 - In this case we want to execute the next instruction
- * and NOT take the jump. So we set the counter to 0. The jump
- * address doesn't count.
- */
- writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
- writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
-
- /*
- * CNTR 3 - Set the nop counter to the number of cycles we
- * need to loop for, minus 1.
- */
- writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
- if (test_dm) {
- mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
- &sdr_rw_load_jump_mgr_regs->load_jump_add3);
- } else {
- mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
- writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
- &sdr_rw_load_jump_mgr_regs->load_jump_add3);
- }
- }
-
- writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
- RW_MGR_RESET_READ_DATAPATH_OFFSET);
-
- if (quick_write_mode)
- writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
- else
- writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
-
- writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
-
- /*
- * CNTR 1 - This is used to ensure enough time elapses
- * for read data to come back.
- */
- writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
-
- if (test_dm) {
- writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
- } else {
- writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
- &sdr_rw_load_jump_mgr_regs->load_jump_add1);
- }
-
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(mcc_instruction, addr + (group << 2));
-}
-
-/* Test writes, can check for a single bit pass or multiple bit pass */
-static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
- uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
- uint32_t *bit_chk, uint32_t all_ranks)
-{
- uint32_t r;
- uint32_t correct_mask_vg;
- uint32_t tmp_bit_chk;
- uint32_t vg;
- uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
- (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
- uint32_t addr_rw_mgr;
- uint32_t base_rw_mgr;
-
- *bit_chk = param->write_correct_mask;
- correct_mask_vg = param->write_correct_mask_vg;
-
- for (r = rank_bgn; r < rank_end; r++) {
- if (param->skip_ranks[r]) {
- /* request to skip the rank */
- continue;
- }
-
- /* set rank */
- set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
-
- tmp_bit_chk = 0;
- addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
- for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
- /* reset the fifos to get pointers to known state */
- writel(0, &phy_mgr_cmd->fifo_reset);
-
- tmp_bit_chk = tmp_bit_chk <<
- (RW_MGR_MEM_DQ_PER_WRITE_DQS /
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
- rw_mgr_mem_calibrate_write_test_issue(write_group *
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
- use_dm);
-
- base_rw_mgr = readl(addr_rw_mgr);
- tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
- if (vg == 0)
- break;
- }
- *bit_chk &= tmp_bit_chk;
- }
-
- if (all_correct) {
- set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
- debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
- %u => %lu", write_group, use_dm,
- *bit_chk, param->write_correct_mask,
- (long unsigned int)(*bit_chk ==
- param->write_correct_mask));
- return *bit_chk == param->write_correct_mask;
- } else {
- set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
- debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
- write_group, use_dm, *bit_chk);
- debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
- (long unsigned int)(*bit_chk != 0));
- return *bit_chk != 0x00;
- }
-}
-
/**
* search_window() - Search for the/part of the window with DM/DQS shift
* @search_dm: If 1, search for the DM shift, if 0, search for DQS shift
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 162/172] ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 2
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (160 preceding siblings ...)
2015-07-27 20:52 ` [U-Boot] [PATCH 161/172] ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 1 Marek Vasut
@ 2015-07-27 20:52 ` Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 163/172] ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 3 Marek Vasut
` (11 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:52 UTC (permalink / raw)
To: u-boot
Clean up coding style, mostly broken multiline formatting strings
in debug output. Also clean up data types and constify where applicable.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 75 ++++++++++++++++++++----------------------
1 file changed, 36 insertions(+), 39 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 659c0d8..dd1ce85 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1169,66 +1169,63 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
}
/* Test writes, can check for a single bit pass or multiple bit pass */
-static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
- uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
- uint32_t *bit_chk, uint32_t all_ranks)
-{
- uint32_t r;
- uint32_t correct_mask_vg;
- uint32_t tmp_bit_chk;
- uint32_t vg;
- uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
- (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
- uint32_t addr_rw_mgr;
- uint32_t base_rw_mgr;
+static int
+rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group,
+ const u32 use_dm, const u32 all_correct,
+ u32 *bit_chk, const u32 all_ranks)
+{
+ const u32 rank_end = all_ranks ?
+ RW_MGR_MEM_NUMBER_OF_RANKS :
+ (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
+ const u32 shift_ratio = RW_MGR_MEM_DQ_PER_WRITE_DQS /
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS;
+ const u32 correct_mask_vg = param->write_correct_mask_vg;
+
+ u32 tmp_bit_chk, base_rw_mgr;
+ int vg, r;
*bit_chk = param->write_correct_mask;
- correct_mask_vg = param->write_correct_mask_vg;
for (r = rank_bgn; r < rank_end; r++) {
- if (param->skip_ranks[r]) {
- /* request to skip the rank */
+ /* Request to skip the rank */
+ if (param->skip_ranks[r])
continue;
- }
- /* set rank */
+ /* Set rank */
set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
tmp_bit_chk = 0;
- addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
- for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
- /* reset the fifos to get pointers to known state */
+ for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS - 1;
+ vg >= 0; vg--) {
+ /* Reset the FIFOs to get pointers to known state. */
writel(0, &phy_mgr_cmd->fifo_reset);
- tmp_bit_chk = tmp_bit_chk <<
- (RW_MGR_MEM_DQ_PER_WRITE_DQS /
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
- rw_mgr_mem_calibrate_write_test_issue(write_group *
- RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
+ rw_mgr_mem_calibrate_write_test_issue(
+ write_group *
+ RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS + vg,
use_dm);
- base_rw_mgr = readl(addr_rw_mgr);
- tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
- if (vg == 0)
- break;
+ base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
+ tmp_bit_chk <<= shift_ratio;
+ tmp_bit_chk |= (correct_mask_vg & ~(base_rw_mgr));
}
+
*bit_chk &= tmp_bit_chk;
}
+ set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
if (all_correct) {
- set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
- debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
- %u => %lu", write_group, use_dm,
- *bit_chk, param->write_correct_mask,
- (long unsigned int)(*bit_chk ==
- param->write_correct_mask));
+ debug_cond(DLEVEL == 2,
+ "write_test(%u,%u,ALL) : %u == %u => %i\n",
+ write_group, use_dm, *bit_chk,
+ param->write_correct_mask,
+ *bit_chk == param->write_correct_mask);
return *bit_chk == param->write_correct_mask;
} else {
set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
- debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
- write_group, use_dm, *bit_chk);
- debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
- (long unsigned int)(*bit_chk != 0));
+ debug_cond(DLEVEL == 2,
+ "write_test(%u,%u,ONE) : %u != %i => %i\n",
+ write_group, use_dm, *bit_chk, 0, *bit_chk != 0);
return *bit_chk != 0x00;
}
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 163/172] ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 3
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (161 preceding siblings ...)
2015-07-27 20:52 ` [U-Boot] [PATCH 162/172] ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 2 Marek Vasut
@ 2015-07-27 20:52 ` Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 164/172] ddr: altera: Clean up rw_mgr_mem_calibrate_write_test_issue() Marek Vasut
` (10 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:52 UTC (permalink / raw)
To: u-boot
Add kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index dd1ce85..ce53800 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1168,7 +1168,17 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
writel(mcc_instruction, addr + (group << 2));
}
-/* Test writes, can check for a single bit pass or multiple bit pass */
+/**
+ * rw_mgr_mem_calibrate_write_test() - Test writes, check for single/multiple pass
+ * @rank_bgn: Rank number
+ * @write_group: Write Group
+ * @use_dm: Use DM
+ * @all_correct: All bits must be correct in the mask
+ * @bit_chk: Resulting bit mask after the test
+ * @all_ranks: Test all ranks
+ *
+ * Test writes, can check for a single bit pass or multiple bit pass.
+ */
static int
rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group,
const u32 use_dm, const u32 all_correct,
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 164/172] ddr: altera: Clean up rw_mgr_mem_calibrate_write_test_issue()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (162 preceding siblings ...)
2015-07-27 20:52 ` [U-Boot] [PATCH 163/172] ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 3 Marek Vasut
@ 2015-07-27 20:52 ` Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 165/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_end() Marek Vasut
` (9 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:52 UTC (permalink / raw)
To: u-boot
Brief clean, add kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 31 ++++++++++++++++++-------------
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index ce53800..6ae8a65 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1032,19 +1032,23 @@ static void rw_mgr_mem_handoff(void)
*/
}
-/*
- * issue write test command.
- * two variants are provided. one that just tests a write pattern and
- * another that tests datamask functionality.
+
+/**
+ * rw_mgr_mem_calibrate_write_test_issue() - Issue write test command
+ * @group: Write Group
+ * @use_dm: Use DM
+ *
+ * Issue write test command. Two variants are provided, one that just tests
+ * a write pattern and another that tests datamask functionality.
*/
-static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
- uint32_t test_dm)
+static void rw_mgr_mem_calibrate_write_test_issue(u32 group,
+ u32 test_dm)
{
- uint32_t mcc_instruction;
- uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
- ENABLE_SUPER_QUICK_CALIBRATION);
- uint32_t rw_wl_nop_cycles;
- uint32_t addr;
+ const u32 quick_write_mode =
+ (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) &&
+ ENABLE_SUPER_QUICK_CALIBRATION;
+ u32 mcc_instruction;
+ u32 rw_wl_nop_cycles;
/*
* Set counter and jump addresses for the right
@@ -1164,8 +1168,9 @@ static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
}
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(mcc_instruction, addr + (group << 2));
+ writel(mcc_instruction, (SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET) +
+ (group << 2));
}
/**
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 165/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_end()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (163 preceding siblings ...)
2015-07-27 20:52 ` [U-Boot] [PATCH 164/172] ddr: altera: Clean up rw_mgr_mem_calibrate_write_test_issue() Marek Vasut
@ 2015-07-27 20:52 ` Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 166/172] ddr: altera: Clean up rw_mgr_mem_calibrate_lfifo() Marek Vasut
` (8 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:52 UTC (permalink / raw)
To: u-boot
This function is implementing the DDR calibration Stage 3 as
described in Altera EMI_RM 2015.05.04 . The main body of this
function is almost identical to Stage 1.3 (DQ/DQS centering)
for all but two flags -- use_read_test and update_fom. Convert
this function to call rw_mgr_mem_calibrate_dq_dqs_centering()
with the correct flags set to trim down the code duplication.
Moreover, reorder the remnants in the function a little and
convert the function to return either 0 or -EIO in case of
success and failure respectively, to match the common return
value convention.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 59 +++++++++++++++---------------------------
1 file changed, 21 insertions(+), 38 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 6ae8a65..2baf77d 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2788,51 +2788,34 @@ cal_done_ok:
return 1;
}
-/* VFIFO Calibration -- Read Deskew Calibration after write deskew */
-static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
- uint32_t test_bgn)
+/**
+ * rw_mgr_mem_calibrate_vfifo_end() - DQ/DQS Centering.
+ * @rw_group: Read/Write Group
+ * @test_bgn: Rank at which the test begins
+ *
+ * Stage 3: DQ/DQS Centering.
+ *
+ * This function implements UniPHY calibration Stage 3, as explained in
+ * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
+ */
+static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group,
+ const u32 test_bgn)
{
- uint32_t rank_bgn, sr;
- uint32_t grp_calibrated;
- uint32_t write_group;
-
- debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
+ int ret;
- /* update info for sims */
+ debug("%s:%d %u %u", __func__, __LINE__, rw_group, test_bgn);
+ /* Update info for sims. */
+ reg_file_set_group(rw_group);
reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
- write_group = read_group;
-
- /* update info for sims */
- reg_file_set_group(read_group);
-
- grp_calibrated = 1;
- /* Read per-bit deskew can be done on a per shadow register basis */
- for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
- rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
- /* Determine if this set of ranks should be skipped entirely */
- if (!param->skip_shadow_regs[sr]) {
- /* This is the last calibration round, update FOM here */
- if (rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
- read_group,
- test_bgn, 0,
- 1)) {
- grp_calibrated = 0;
- }
- }
- }
-
-
- if (grp_calibrated == 0) {
- set_failing_group_stage(write_group,
+ ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group, test_bgn, 0, 1);
+ if (ret)
+ set_failing_group_stage(rw_group,
CAL_STAGE_VFIFO_AFTER_WRITES,
CAL_SUBSTAGE_VFIFO_CENTER);
- return 0;
- }
-
- return 1;
+ return ret;
}
/* Calibrate LFIFO to find smallest read latency */
@@ -3483,7 +3466,7 @@ static uint32_t mem_calibrate(void)
if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
continue;
- if (rw_mgr_mem_calibrate_vfifo_end(read_group,
+ if (!rw_mgr_mem_calibrate_vfifo_end(read_group,
read_test_bgn))
continue;
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 166/172] ddr: altera: Clean up rw_mgr_mem_calibrate_lfifo()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (164 preceding siblings ...)
2015-07-27 20:52 ` [U-Boot] [PATCH 165/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_end() Marek Vasut
@ 2015-07-27 20:52 ` Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 167/172] ddr: altera: Minor clean up of rw_mgr_mem_handoff() Marek Vasut
` (7 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:52 UTC (permalink / raw)
To: u-boot
Minor coding style cleanup, add kerneldoc. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 49 +++++++++++++++++++++++-------------------
1 file changed, 27 insertions(+), 22 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 2baf77d..eb0e8cf 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -2818,60 +2818,65 @@ static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group,
return ret;
}
-/* Calibrate LFIFO to find smallest read latency */
+/**
+ * rw_mgr_mem_calibrate_lfifo() - Minimize latency
+ *
+ * Stage 4: Minimize latency.
+ *
+ * This function implements UniPHY calibration Stage 4, as explained in
+ * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
+ * Calibrate LFIFO to find smallest read latency.
+ */
static uint32_t rw_mgr_mem_calibrate_lfifo(void)
{
- uint32_t found_one;
+ int found_one = 0;
debug("%s:%d\n", __func__, __LINE__);
- /* update info for sims */
+ /* Update info for sims. */
reg_file_set_stage(CAL_STAGE_LFIFO);
reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
/* Load up the patterns used by read calibration for all ranks */
rw_mgr_mem_calibrate_read_load_patterns(0, 1);
- found_one = 0;
do {
writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
__func__, __LINE__, gbl->curr_read_lat);
- if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
- NUM_READ_TESTS,
- PASS_ALL_BITS,
- 1)) {
+ if (!rw_mgr_mem_calibrate_read_test_all_ranks(0, NUM_READ_TESTS,
+ PASS_ALL_BITS, 1))
break;
- }
found_one = 1;
- /* reduce read latency and see if things are working */
- /* correctly */
+ /*
+ * Reduce read latency and see if things are
+ * working correctly.
+ */
gbl->curr_read_lat--;
} while (gbl->curr_read_lat > 0);
- /* reset the fifos to get pointers to known state */
-
+ /* Reset the fifos to get pointers to known state. */
writel(0, &phy_mgr_cmd->fifo_reset);
if (found_one) {
- /* add a fudge factor to the read latency that was determined */
+ /* Add a fudge factor to the read latency that was determined */
gbl->curr_read_lat += 2;
writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
- debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
- read_lat=%u\n", __func__, __LINE__,
- gbl->curr_read_lat);
- return 1;
+ debug_cond(DLEVEL == 2,
+ "%s:%d lfifo: success: using read_lat=%u\n",
+ __func__, __LINE__, gbl->curr_read_lat);
} else {
set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
CAL_SUBSTAGE_READ_LATENCY);
- debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
- read_lat=%u\n", __func__, __LINE__,
- gbl->curr_read_lat);
- return 0;
+ debug_cond(DLEVEL == 2,
+ "%s:%d lfifo: failed at initial read_lat=%u\n",
+ __func__, __LINE__, gbl->curr_read_lat);
}
+
+ return found_one;
}
/**
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 167/172] ddr: altera: Minor clean up of rw_mgr_mem_handoff()
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (165 preceding siblings ...)
2015-07-27 20:52 ` [U-Boot] [PATCH 166/172] ddr: altera: Clean up rw_mgr_mem_calibrate_lfifo() Marek Vasut
@ 2015-07-27 20:52 ` Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 168/172] ddr: altera: Clean up of delay_for_n_mem_clocks() part 1 Marek Vasut
` (6 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:52 UTC (permalink / raw)
To: u-boot
Add kerneldoc and perform a minor comment cleanup.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index eb0e8cf..9470aca 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -1018,21 +1018,22 @@ static void rw_mgr_mem_initialize(void)
0);
}
-/*
- * At the end of calibration we have to program the user settings in, and
- * USER hand off the memory to the user.
+/**
+ * rw_mgr_mem_handoff() - Hand off the memory to user
+ *
+ * At the end of calibration we have to program the user settings in
+ * and hand off the memory to the user.
*/
static void rw_mgr_mem_handoff(void)
{
rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
/*
- * USER need to wait tMOD (12CK or 15ns) time before issuing
- * other commands, but we will have plenty of NIOS cycles before
- * actual handoff so its okay.
+ * Need to wait tMOD (12CK or 15ns) time before issuing other
+ * commands, but we will have plenty of NIOS cycles before actual
+ * handoff so its okay.
*/
}
-
/**
* rw_mgr_mem_calibrate_write_test_issue() - Issue write test command
* @group: Write Group
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 168/172] ddr: altera: Clean up of delay_for_n_mem_clocks() part 1
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (166 preceding siblings ...)
2015-07-27 20:52 ` [U-Boot] [PATCH 167/172] ddr: altera: Minor clean up of rw_mgr_mem_handoff() Marek Vasut
@ 2015-07-27 20:52 ` Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 169/172] ddr: altera: Clean up of delay_for_n_mem_clocks() part 2 Marek Vasut
` (5 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:52 UTC (permalink / raw)
To: u-boot
Fix data types, clean up comments a bit and fix coding style a bit.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 27 +++++++++++++--------------
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 9470aca..5a6c991 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -758,40 +758,39 @@ static void set_jump_as_return(void)
* should always use constants as argument to ensure all computations are
* performed at compile time
*/
-static void delay_for_n_mem_clocks(const uint32_t clocks)
+static void delay_for_n_mem_clocks(const u32 clocks)
{
- uint32_t afi_clocks;
- uint8_t inner = 0;
- uint8_t outer = 0;
- uint16_t c_loop = 0;
+ u32 afi_clocks;
+ u16 c_loop = 0;
+ u8 inner = 0;
+ u8 outer = 0;
debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
-
- afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
/* scale (rounding up) to get afi clocks */
+ afi_clocks = DIV_ROUND_UP(clocks, AFI_RATE_RATIO);
/*
- * Note, we don't bother accounting for being off a little bit
- * because of a few extra instructions in outer loops
- * Note, the loops have a test at the end, and do the test before
- * the decrement, and so always perform the loop
+ * Note, we don't bother accounting for being off a little
+ * bit because of a few extra instructions in outer loops.
+ * Note, the loops have a test at the end, and do the test
+ * before the decrement, and so always perform the loop
* 1 time more than the counter value
*/
if (afi_clocks == 0) {
;
} else if (afi_clocks <= 0x100) {
- inner = afi_clocks-1;
+ inner = afi_clocks - 1;
outer = 0;
c_loop = 0;
} else if (afi_clocks <= 0x10000) {
inner = 0xff;
- outer = (afi_clocks-1) >> 8;
+ outer = (afi_clocks - 1) >> 8;
c_loop = 0;
} else {
inner = 0xff;
outer = 0xff;
- c_loop = (afi_clocks-1) >> 16;
+ c_loop = (afi_clocks - 1) >> 16;
}
/*
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 169/172] ddr: altera: Clean up of delay_for_n_mem_clocks() part 2
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (167 preceding siblings ...)
2015-07-27 20:52 ` [U-Boot] [PATCH 168/172] ddr: altera: Clean up of delay_for_n_mem_clocks() part 1 Marek Vasut
@ 2015-07-27 20:52 ` Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 170/172] ddr: altera: Clean up of delay_for_n_mem_clocks() part 3 Marek Vasut
` (4 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:52 UTC (permalink / raw)
To: u-boot
Factor out (afi_clocks - 1) into a single place instead of having it
all around the function.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 5a6c991..25de209 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -767,8 +767,10 @@ static void delay_for_n_mem_clocks(const u32 clocks)
debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
- /* scale (rounding up) to get afi clocks */
+ /* Scale (rounding up) to get afi clocks. */
afi_clocks = DIV_ROUND_UP(clocks, AFI_RATE_RATIO);
+ if (afi_clocks) /* Temporary underflow protection */
+ afi_clocks--;
/*
* Note, we don't bother accounting for being off a little
@@ -779,18 +781,18 @@ static void delay_for_n_mem_clocks(const u32 clocks)
*/
if (afi_clocks == 0) {
;
- } else if (afi_clocks <= 0x100) {
- inner = afi_clocks - 1;
+ } else if (afi_clocks < 0x100) {
+ inner = afi_clocks;
outer = 0;
c_loop = 0;
- } else if (afi_clocks <= 0x10000) {
+ } else if (afi_clocks < 0x10000) {
inner = 0xff;
- outer = (afi_clocks - 1) >> 8;
+ outer = afi_clocks >> 8;
c_loop = 0;
- } else {
+ } else { /* >= 0x10000 */
inner = 0xff;
outer = 0xff;
- c_loop = (afi_clocks - 1) >> 16;
+ c_loop = afi_clocks >> 16;
}
/*
@@ -810,7 +812,7 @@ static void delay_for_n_mem_clocks(const u32 clocks)
* and sequencer rom and keeps the delays more accurate and reduces
* overhead
*/
- if (afi_clocks <= 0x100) {
+ if (afi_clocks < 0x100) {
writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
&sdr_rw_load_mgr_regs->load_cntr1);
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 170/172] ddr: altera: Clean up of delay_for_n_mem_clocks() part 3
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (168 preceding siblings ...)
2015-07-27 20:52 ` [U-Boot] [PATCH 169/172] ddr: altera: Clean up of delay_for_n_mem_clocks() part 2 Marek Vasut
@ 2015-07-27 20:52 ` Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 171/172] ddr: altera: Clean up of delay_for_n_mem_clocks() part 4 Marek Vasut
` (3 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:52 UTC (permalink / raw)
To: u-boot
Clean up the computation of c_loop, outer and inner variables.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 24 ++++++------------------
1 file changed, 6 insertions(+), 18 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 25de209..ed4d791 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -761,9 +761,9 @@ static void set_jump_as_return(void)
static void delay_for_n_mem_clocks(const u32 clocks)
{
u32 afi_clocks;
- u16 c_loop = 0;
- u8 inner = 0;
- u8 outer = 0;
+ u16 c_loop;
+ u8 inner;
+ u8 outer;
debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
@@ -779,21 +779,9 @@ static void delay_for_n_mem_clocks(const u32 clocks)
* before the decrement, and so always perform the loop
* 1 time more than the counter value
*/
- if (afi_clocks == 0) {
- ;
- } else if (afi_clocks < 0x100) {
- inner = afi_clocks;
- outer = 0;
- c_loop = 0;
- } else if (afi_clocks < 0x10000) {
- inner = 0xff;
- outer = afi_clocks >> 8;
- c_loop = 0;
- } else { /* >= 0x10000 */
- inner = 0xff;
- outer = 0xff;
- c_loop = afi_clocks >> 16;
- }
+ c_loop = afi_clocks >> 16;
+ outer = c_loop ? 0xff : (afi_clocks >> 8);
+ inner = outer ? 0xff : afi_clocks;
/*
* rom instructions are structured as follows:
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 171/172] ddr: altera: Clean up of delay_for_n_mem_clocks() part 4
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (169 preceding siblings ...)
2015-07-27 20:52 ` [U-Boot] [PATCH 170/172] ddr: altera: Clean up of delay_for_n_mem_clocks() part 3 Marek Vasut
@ 2015-07-27 20:52 ` Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 172/172] ddr: altera: Clean up of delay_for_n_mem_clocks() part 5 Marek Vasut
` (2 subsequent siblings)
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:52 UTC (permalink / raw)
To: u-boot
Simplify the loop code, optimizing compiler can deal with this.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 17 +++++------------
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index ed4d791..d4e720f 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -822,18 +822,11 @@ static void delay_for_n_mem_clocks(const u32 clocks)
writel(RW_MGR_IDLE_LOOP2,
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
- /* hack to get around compiler not being smart enough */
- if (afi_clocks <= 0x10000) {
- /* only need to run once */
- writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
- RW_MGR_RUN_SINGLE_GROUP_OFFSET);
- } else {
- do {
- writel(RW_MGR_IDLE_LOOP2,
- SDR_PHYGRP_RWMGRGRP_ADDRESS |
- RW_MGR_RUN_SINGLE_GROUP_OFFSET);
- } while (c_loop-- != 0);
- }
+ do {
+ writel(RW_MGR_IDLE_LOOP2,
+ SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET);
+ } while (c_loop-- != 0);
}
debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
}
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 172/172] ddr: altera: Clean up of delay_for_n_mem_clocks() part 5
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (170 preceding siblings ...)
2015-07-27 20:52 ` [U-Boot] [PATCH 171/172] ddr: altera: Clean up of delay_for_n_mem_clocks() part 4 Marek Vasut
@ 2015-07-27 20:52 ` Marek Vasut
2015-07-28 13:13 ` [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Pavel Machek
2015-08-03 15:16 ` Dinh Nguyen
173 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-27 20:52 UTC (permalink / raw)
To: u-boot
Add kerneldoc.
Signed-off-by: Marek Vasut <marex@denx.de>
---
drivers/ddr/altera/sequencer.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index d4e720f..37f7354 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -754,9 +754,11 @@ static void set_jump_as_return(void)
writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
}
-/*
- * should always use constants as argument to ensure all computations are
- * performed at compile time
+/**
+ * delay_for_n_mem_clocks() - Delay for N memory clocks
+ * @clocks: Length of the delay
+ *
+ * Delay for N memory clocks.
*/
static void delay_for_n_mem_clocks(const u32 clocks)
{
--
2.1.4
^ permalink raw reply related [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (171 preceding siblings ...)
2015-07-27 20:52 ` [U-Boot] [PATCH 172/172] ddr: altera: Clean up of delay_for_n_mem_clocks() part 5 Marek Vasut
@ 2015-07-28 13:13 ` Pavel Machek
2015-07-28 13:30 ` Marek Vasut
2015-08-03 15:16 ` Dinh Nguyen
173 siblings, 1 reply; 185+ messages in thread
From: Pavel Machek @ 2015-07-28 13:13 UTC (permalink / raw)
To: u-boot
Hi!
> This series fixes the SPL support on SoCFPGA and cleans up the DDR
> init code such that it is becoming remotely mainlinable. After this
> series, the SPL is capable of booting from both SD/MMC and QSPI NOR.
>
> There is still work to be done, but I'd like to start picking it up
> so it can land in 2015.10 . Reviews and comments are welcome.
Do you have series in git somewhere? I guess I'd like to review
different diffs than these...
Thanks,
Pavel
> Dinh Nguyen (3):
> driver/ddr/altera: Add DDR driver for Altera's SDRAM controller
> driver/ddr/altera: Add the sdram calibration portion
> arm: socfpga: enable the Altera SDRAM controller driver
>
> Marek Vasut (169):
> arm: socfpga: Move sdram_config.h to board dir
> ddr: altera: Move struct sdram_prot_rule prototype
> ddr: altera: Fix typo in mp_threshold1 programming
> ddr: altera: Fix debug message format in sequencer
> arm: socfpga: reset: Add missing reset manager regs
> arm: socfpga: reset: Start reworking the SoCFPGA reset manager
> arm: socfpga: reset: Implement unified function to toggle reset
> arm: socfpga: reset: Replace ad-hoc reset functions
> arm: socfpga: reset: Repair bridge reset handling
> arm: socfpga: reset: Add function to reset add peripherals
> arm: socfpga: reset: Add SDMMC, QSPI and DMA defines
> arm: socfpga: clock: Get rid of cm_config_t typedef
> arm: socfpga: clock: Clean up pll_config.h
> arm: socfpga: scan: Staticize scan_mgr_io_scan_chain_prg()
> arm: socfpga: scan: Zap redundant params in
> scan_mgr_io_scan_chain_prg()
> arm: socfpga: scan: Zap iocsr_scan_chain*_table()
> arm: socfpga: system: Rework sysmgr_enable_warmrstcfgio()
> arm: socfpga: system: Clean up pinmux_config.c
> arm: socfpga: spl: Toggle warm reset config I/O bit
> arm: socfpga: spl: Configure SCU and NIC-301 early
> arm: socfpga: spl: Add missing reset logic
> arm: socfpga: spl: Merge spl_board_init() into board_init_f()
> arm: socfpga: spl: Remove custom linker script
> arm: socfpga: spl: Add support for booting from SD/MMC
> arm: socfpga: spl: Add support for booting from QSPI
> arm: socfpga: spl: Add support for selecting boot device from BSEL
> arm: socfpga: misc: Fix warm reset
> arm: socfpga: misc: Add support for printing boot mode
> arm: socfpga: misc: Export bootmode into environment variable
> arm: socfpga: misc: Probe ethernet GMAC from OF
> arm: socfpga: misc: Reset ethernet from OF
> arm: socfpga: config: Move SPL GD and malloc to RAM
> arm: socfpga: config: Zap incorrect config options
> arm: socfpga: config: Exclude CONFIG_SPI_FLASH_MTD from SPL build
> arm: socfpga: config: Enable CONFIG_SPI_FLASH_BAR
> arm: socfpga: config: Fix LOADADDR
> arm: socfpga: config: Make CONFIG_SPI_FLASH_MTD useful
> Makefile: Add target for building bootable SPL image for SoCFPGA
> ddr: altera: Minor indent fix in set_rank_and_odt_mask()
> ddr: altera: Clean up ugly casts in sdram_calibration_full()
> ddr: altera: Zap invocation of sdr_get_addr((u32 *)BASE_RW_MGR)"
> ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_reg_file->.*)
> ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_scc_mgr->.*)
> ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_rw_load.*->.*)
> ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_mgr_.*->.*)
> ddr: altera: Pluck out remaining sdr_get_addr() calls
> ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESS
> ddr: altera: Stop using SDR_CTRLGRP_ADDRESS directly
> ddr: altera: Massage addr into I/O accessors
> ddr: altera: Clean up hc_initialize_rom_data()
> ddr: altera: Clean up initialize_reg_file()
> ddr: altera: Clean up initialize_hps_phy()
> ddr: altera: Clean up reg_file_set*()
> ddr: altera: Clean up scc manager function args
> ddr: altera: Reorder scc manager functions
> ddr: altera: Implement universal scc manager config function
> ddr: altera: Clean up scc_mgr_initialize()
> ddr: altera: Shuffle around scc_mgr_set_*all_ranks()
> ddr: altera: Implement universal scc_mgr_set_all_ranks()
> ddr: altera: Clean up scc_mgr_load_dqs_for_write_group()
> ddr: altera: Clean up scc_set_bypass_mode()
> ddr: altera: Clean up scc_mgr_set_oct_out1_delay()
> ddr: altera: Clean up scc_mgr_apply_group_dq_out1_delay()
> ddr: altera: Clean up scc_mgr_*_delay() args
> ddr: altera: Clean up scc_mgr_set_hhp_extras()
> ddr: altera: Extract scc_mgr_set_hhp_extras()
> ddr: altera: Clean up scc_mgr_zero_all()
> ddr: altera: Clean up scc_mgr_zero_group()
> FIXME: ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add()
> cleanup part 1
> ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add() cleanup
> part 2
> ddr: altera: Clean up
> scc_mgr_apply_group_all_out_delay_add_all_ranks()
> ddr: altera: Factor out instruction loading from
> rw_mgr_mem_initialize()
> ddr: altera: Factor out common code
> ddr: altera: Minor clean up of set_jump_as_return()
> ddr: altera: Fix ad-hoc iterative division implementation
> ddr: altera: Rework initialize_tracking()
> ddr: altera: Init my_param and my_gbl
> ddr: altera: Rename initialize() to phy_mgr_initialize()
> ddr: altera: Clean up run_mem_calibrate()
> ddr: altera: Clean up phy_mgr_initialize()
> ddr: altera: Clean up mem_config()
> ddr: altera: Clean up mem_precharge_and_activate()
> ddr: altera: Clean up set_rank_and_odt_mask() part 1
> ddr: altera: Clean up set_rank_and_odt_mask() part 2
> ddr: altera: Clean up set_rank_and_odt_mask() part 3
> ddr: altera: Minor clean up of mem_skip_calibrate()
> ddr: altera: Trivial mem_calibrate() indent cleanup
> ddr: altera: Internal mem_calibrate() cleanup part 1
> ddr: altera: Internal mem_calibrate() cleanup part 2
> ddr: altera: Internal mem_calibrate() cleanup part 3
> ddr: altera: Internal mem_calibrate() cleanup part 4
> ddr: altera: Internal mem_calibrate() cleanup part 5
> ddr: altera: Internal mem_calibrate() cleanup part 6
> ddr: altera: Minor clean up of rw_mgr_mem_initialize()
> ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 1
> ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 2
> ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 3
> ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 4
> ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 5
> ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 6
> ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 7
> ddr: altera: Extract guaranteed write from
> rw_mgr_mem_calibrate_vfifo()
> ddr: altera: Extract DQS enable calibration from
> rw_mgr_mem_calibrate_vfifo()
> ddr: altera: Extract Centering DQ/DQS from
> rw_mgr_mem_calibrate_vfifo()
> ddr: altera: Minor rw_mgr_mem_calibrate_read_load_patterns() cleanup
> ddr: altera: Zap rw_mgr_mem_calibrate_read_test_patterns_all_ranks()
> ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_patterns()
> ddr: altera: Clean up
> rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay()
> part 1
> ddr: altera: Clean up
> rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay()
> part 2
> ddr: altera: Clean up
> rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay()
> part 3
> ddr: altera: Clean up
> rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay()
> part 4
> ddr: altera: Clean up sdr_find_window_centre() part 1
> ddr: altera: Clean up sdr_find_window_centre() part 2
> ddr: altera: Clean up sdr_find_window_centre() part 3
> ddr: altera: Clean up sdr_*_phase() part 1
> ddr: altera: Clean up sdr_*_phase() part 2
> ddr: altera: Clean up sdr_*_phase() part 3
> ddr: altera: Clean up sdr_*_phase() part 4
> ddr: altera: Clean up sdr_*_phase() part 5
> ddr: altera: Clean up sdr_*_phase() part 6
> ddr: altera: Clean up sdr_*_phase() part 7
> ddr: altera: Clean up sdr_*_phase() part 8
> ddr: altera: Clean up sdr_*_phase() part 9
> ddr: altera: Clean up sdr_*_phase() part 10
> ddr: altera: Clean up rw_mgr_*_vfifo() part 1
> ddr: altera: Clean up rw_mgr_*_vfifo() part 2
> ddr: altera: Clean up find_vfifo_read()
> ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
> part 1
> ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
> part 2
> ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
> part 3
> ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
> part 4
> ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
> part 5
> ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
> part 6
> ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase()
> part 7
> ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_all_ranks()
> ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 1
> ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 2
> ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 3
> ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 4
> ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 5
> ddr: altera: Clean up rw_mgr_mem_calibrate_writes()
> ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 1
> ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 2
> ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 3
> ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 4
> ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 5
> ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 6
> ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 7
> ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 8
> ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 9
> ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 10
> ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 11
> ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1
> ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 2
> ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3
> ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 4
> ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 5
> ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 1
> ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 2
> ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 3
> ddr: altera: Clean up rw_mgr_mem_calibrate_write_test_issue()
> ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_end()
> ddr: altera: Clean up rw_mgr_mem_calibrate_lfifo()
> ddr: altera: Minor clean up of rw_mgr_mem_handoff()
> ddr: altera: Clean up of delay_for_n_mem_clocks() part 1
> ddr: altera: Clean up of delay_for_n_mem_clocks() part 2
> ddr: altera: Clean up of delay_for_n_mem_clocks() part 3
> ddr: altera: Clean up of delay_for_n_mem_clocks() part 4
> ddr: altera: Clean up of delay_for_n_mem_clocks() part 5
>
> Makefile | 13 +
> arch/arm/mach-socfpga/clock_manager.c | 28 +-
> arch/arm/mach-socfpga/include/mach/clock_manager.h | 12 +-
> arch/arm/mach-socfpga/include/mach/reset_manager.h | 60 +-
> arch/arm/mach-socfpga/include/mach/scan_manager.h | 23 +-
> arch/arm/mach-socfpga/include/mach/sdram.h | 298 +-
> .../arm/mach-socfpga/include/mach/system_manager.h | 7 +-
> arch/arm/mach-socfpga/misc.c | 115 +-
> arch/arm/mach-socfpga/reset_manager.c | 99 +-
> arch/arm/mach-socfpga/scan_manager.c | 31 +-
> arch/arm/mach-socfpga/spl.c | 220 +-
> arch/arm/mach-socfpga/system_manager.c | 16 +-
> arch/arm/mach-socfpga/u-boot-spl.lds | 45 -
> board/altera/socfpga/Makefile | 4 +-
> board/altera/socfpga/qts/Makefile | 7 -
> board/altera/socfpga/qts/sdram_config.h | 100 +
> board/altera/socfpga/wrap_iocsr_config.c | 41 +
> board/altera/socfpga/wrap_pinmux_config.c | 35 +
> board/altera/socfpga/wrap_pll_config.c | 144 +
> configs/socfpga_arria5_defconfig | 9 +
> configs/socfpga_cyclone5_defconfig | 10 +
> configs/socfpga_socrates_defconfig | 11 +-
> drivers/ddr/altera/Makefile | 11 +
> drivers/ddr/altera/sdram.c | 817 +++++
> drivers/ddr/altera/sequencer.c | 3806 ++++++++++++++++++++
> drivers/ddr/altera/sequencer.h | 299 ++
> drivers/ddr/altera/sequencer_auto.h | 128 +
> drivers/ddr/altera/sequencer_auto_ac_init.h | 84 +
> drivers/ddr/altera/sequencer_auto_inst_init.h | 268 ++
> drivers/ddr/altera/sequencer_defines.h | 121 +
> include/configs/socfpga_arria5.h | 7 +-
> include/configs/socfpga_common.h | 63 +-
> include/configs/socfpga_cyclone5.h | 7 +-
> include/fdtdec.h | 1 +
> lib/fdtdec.c | 1 +
> scripts/Makefile.spl | 11 +
> 36 files changed, 6566 insertions(+), 386 deletions(-)
> delete mode 100644 arch/arm/mach-socfpga/u-boot-spl.lds
> delete mode 100644 board/altera/socfpga/qts/Makefile
> create mode 100644 board/altera/socfpga/qts/sdram_config.h
> create mode 100644 board/altera/socfpga/wrap_iocsr_config.c
> create mode 100644 board/altera/socfpga/wrap_pinmux_config.c
> create mode 100644 board/altera/socfpga/wrap_pll_config.c
> create mode 100644 drivers/ddr/altera/Makefile
> create mode 100644 drivers/ddr/altera/sdram.c
> create mode 100644 drivers/ddr/altera/sequencer.c
> create mode 100644 drivers/ddr/altera/sequencer.h
> create mode 100644 drivers/ddr/altera/sequencer_auto.h
> create mode 100644 drivers/ddr/altera/sequencer_auto_ac_init.h
> create mode 100644 drivers/ddr/altera/sequencer_auto_inst_init.h
> create mode 100644 drivers/ddr/altera/sequencer_defines.h
>
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init
2015-07-28 13:13 ` [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Pavel Machek
@ 2015-07-28 13:30 ` Marek Vasut
2015-07-28 13:58 ` Pavel Machek
0 siblings, 1 reply; 185+ messages in thread
From: Marek Vasut @ 2015-07-28 13:30 UTC (permalink / raw)
To: u-boot
On Tuesday, July 28, 2015 at 03:13:09 PM, Pavel Machek wrote:
> Hi!
>
> > This series fixes the SPL support on SoCFPGA and cleans up the DDR
> > init code such that it is becoming remotely mainlinable. After this
> > series, the SPL is capable of booting from both SD/MMC and QSPI NOR.
> >
> > There is still work to be done, but I'd like to start picking it up
> > so it can land in 2015.10 . Reviews and comments are welcome.
>
> Do you have series in git somewhere? I guess I'd like to review
> different diffs than these...
>
Here is what you'd probably make most use of -- complete sockit support:
http://git.denx.de/?p=u-boot/u-boot-
socfpga.git;a=shortlog;h=refs/heads/wip/sockit
The sub-series are in branches with 01...05-* names.
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init
2015-07-28 13:30 ` Marek Vasut
@ 2015-07-28 13:58 ` Pavel Machek
2015-07-28 14:58 ` Marek Vasut
0 siblings, 1 reply; 185+ messages in thread
From: Pavel Machek @ 2015-07-28 13:58 UTC (permalink / raw)
To: u-boot
On Tue 2015-07-28 15:30:06, Marek Vasut wrote:
> On Tuesday, July 28, 2015 at 03:13:09 PM, Pavel Machek wrote:
> > Hi!
> >
> > > This series fixes the SPL support on SoCFPGA and cleans up the DDR
> > > init code such that it is becoming remotely mainlinable. After this
> > > series, the SPL is capable of booting from both SD/MMC and QSPI NOR.
> > >
> > > There is still work to be done, but I'd like to start picking it up
> > > so it can land in 2015.10 . Reviews and comments are welcome.
> >
> > Do you have series in git somewhere? I guess I'd like to review
> > different diffs than these...
> >
>
> Here is what you'd probably make most use of -- complete sockit support:
> http://git.denx.de/?p=u-boot/u-boot-
> socfpga.git;a=shortlog;h=refs/heads/wip/sockit
Thanks!
Random notes:
+static int check_cache_range(unsigned long start, unsigned long stop)
+{
+ int ok = 1;
+
+ if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
+ ok = 0;
+
+ if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
+ ok = 0;
+
+ if (!ok)
+ debug("CACHE: Misaligned operation at range [%08lx,
%08lx]\n",
+ start, stop);
+
if ((start | end) & (...))
debug()
..and you get rid of a variable.
+int iocsr_get_config_table(const unsigned int chain_id,
+ const unsigned long **table,
+ unsigned int *table_len)
+{
+ switch (chain_id) {
+ case 0:
+ *table = iocsr_scan_chain0_table;
+ *table_len = CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH;
+ break;
+ case 1:
+ *table = iocsr_scan_chain1_table;
+ *table_len = CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH;
+ break;
+ case 2:
+ *table = iocsr_scan_chain2_table;
+ *table_len = CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH;
+ break;
+ case 3:
+ *table = iocsr_scan_chain3_table;
+ *table_len = CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH;
+ break;
+ default:
+ return -EINVAL;
I'd do *table = NULL, *table_len = 0 here, to catch any mistakes.
+static void sdram_set_rule(struct sdram_prot_rule *prule)
+{
+ uint32_t lo_addr_bits;
+ uint32_t hi_addr_bits;
Can we do u32 here, and in other places like this?
+ rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER,
1);
+ /*
+ * Need to wait tMOD (12CK or 15ns) time before issuing other
+ * commands, but we will have plenty of NIOS cycles before
actual
+ * handoff so its okay.
+ */
I don't understand this comment.
+ return 0;
+
+ /* Calibration Stage 1 completed OK. */
+cal_done_ok:
+ /*
+ * Reset the delay chains back to zero if they have moved > 1
+ * (check for > 1 because loop will increase d even when pass
in
+ * first case).
+ */
+ if (d > 2)
+ scc_mgr_zero_group(rw_group, 1);
+
+ return 1;
+}
Other functions use 0/-EIO protocol here, so it would be good to be
consistent.
It looks much better now, thanks,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init
2015-07-28 13:58 ` Pavel Machek
@ 2015-07-28 14:58 ` Marek Vasut
2015-07-28 20:28 ` Pavel Machek
0 siblings, 1 reply; 185+ messages in thread
From: Marek Vasut @ 2015-07-28 14:58 UTC (permalink / raw)
To: u-boot
On Tuesday, July 28, 2015 at 03:58:34 PM, Pavel Machek wrote:
> On Tue 2015-07-28 15:30:06, Marek Vasut wrote:
> > On Tuesday, July 28, 2015 at 03:13:09 PM, Pavel Machek wrote:
> > > Hi!
> > >
> > > > This series fixes the SPL support on SoCFPGA and cleans up the DDR
> > > > init code such that it is becoming remotely mainlinable. After this
> > > > series, the SPL is capable of booting from both SD/MMC and QSPI NOR.
> > > >
> > > > There is still work to be done, but I'd like to start picking it up
> > > > so it can land in 2015.10 . Reviews and comments are welcome.
> > >
> > > Do you have series in git somewhere? I guess I'd like to review
> > > different diffs than these...
> >
> > Here is what you'd probably make most use of -- complete sockit support:
> > http://git.denx.de/?p=u-boot/u-boot-
> > socfpga.git;a=shortlog;h=refs/heads/wip/sockit
>
> Thanks!
>
> Random notes:
>
> +static int check_cache_range(unsigned long start, unsigned long stop)
> +{
> + int ok = 1;
> +
> + if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
> + ok = 0;
> +
> + if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
> + ok = 0;
> +
> + if (!ok)
> + debug("CACHE: Misaligned operation at range [%08lx,
> %08lx]\n",
> + start, stop);
> +
>
> if ((start | end) & (...))
> debug()
>
> ..and you get rid of a variable.
This is what I was afraid of -- you not commenting on a specific patch,
but at bulk on a series which doesn't even contain the patch :'-(
I'd like to get some feedback on that patch from Albert/Tom though.
> +int iocsr_get_config_table(const unsigned int chain_id,
> + const unsigned long **table,
> + unsigned int *table_len)
> +{
> + switch (chain_id) {
> + case 0:
> + *table = iocsr_scan_chain0_table;
> + *table_len = CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH;
> + break;
> + case 1:
> + *table = iocsr_scan_chain1_table;
> + *table_len = CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH;
> + break;
> + case 2:
> + *table = iocsr_scan_chain2_table;
> + *table_len = CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH;
> + break;
> + case 3:
> + *table = iocsr_scan_chain3_table;
> + *table_len = CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH;
> + break;
> + default:
> + return -EINVAL;
>
> I'd do *table = NULL, *table_len = 0 here, to catch any mistakes.
You can check the return value of the function, I explicitly don't want
to modify the output args in case of a failure :)
> +static void sdram_set_rule(struct sdram_prot_rule *prule)
> +{
> + uint32_t lo_addr_bits;
> + uint32_t hi_addr_bits;
>
> Can we do u32 here, and in other places like this?
Yes, linting the rest for proper types is on my list, there is much more
than these two variables.
> + rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER,
> 1);
> + /*
> + * Need to wait tMOD (12CK or 15ns) time before issuing other
> + * commands, but we will have plenty of NIOS cycles before
> actual
> + * handoff so its okay.
> + */
>
> I don't understand this comment.
There's plenty of code between issuing the above instruction and triggering
the mem handoff, so we don't need to add explicit delay into this function.
Also, 15nS is like 15 instructions on the SoCFPGA, so there is zero chance
we will trigger the handoff too early.
> + return 0;
> +
> + /* Calibration Stage 1 completed OK. */
> +cal_done_ok:
> + /*
> + * Reset the delay chains back to zero if they have moved > 1
> + * (check for > 1 because loop will increase d even when pass
> in
> + * first case).
> + */
> + if (d > 2)
> + scc_mgr_zero_group(rw_group, 1);
> +
> + return 1;
> +}
>
> Other functions use 0/-EIO protocol here, so it would be good to be
> consistent.
This is also on my list and will do that after the series is in -- this
and the type cleanup.
> It looks much better now, thanks,
It's far from good though and there will be another series after this one
I'm afraid. It might be even heftier, but I want to open the door to proper
SoCFPGA support this MW even if it means blowing them to shreds ...
^ permalink raw reply [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 011/172] arm: socfpga: reset: Replace ad-hoc reset functions
2015-07-27 20:49 ` [U-Boot] [PATCH 011/172] arm: socfpga: reset: Replace ad-hoc reset functions Marek Vasut
@ 2015-07-28 19:12 ` Dinh Nguyen
2015-07-28 19:26 ` Marek Vasut
0 siblings, 1 reply; 185+ messages in thread
From: Dinh Nguyen @ 2015-07-28 19:12 UTC (permalink / raw)
To: u-boot
On 7/27/15 3:49 PM, Marek Vasut wrote:
> Replace all those ad-hoc reset functions, which were all copies
> of the same invocation of clrbits_le32() anyway, with one single
> unified function, socfpga_per_reset(), with necessary parameters.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> ---
> arch/arm/mach-socfpga/include/mach/reset_manager.h | 7 ---
> arch/arm/mach-socfpga/misc.c | 14 ++++--
> arch/arm/mach-socfpga/reset_manager.c | 50 ----------------------
> arch/arm/mach-socfpga/spl.c | 6 +--
> 4 files changed, 13 insertions(+), 64 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> index 56509c2..97f155d 100644
> --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> @@ -14,13 +14,6 @@ void socfpga_bridges_reset(int enable);
>
> void socfpga_per_reset(u32 reset, int set);
>
> -void socfpga_emac_reset(int enable);
> -void socfpga_watchdog_reset(void);
> -void socfpga_spim_enable(void);
> -void socfpga_uart0_enable(void);
> -void socfpga_sdram_enable(void);
> -void socfpga_osc1timer_enable(void);
> -
> struct socfpga_reset_manager {
> u32 status;
> u32 ctrl;
> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> index 3ddac4c..f03689c 100644
> --- a/arch/arm/mach-socfpga/misc.c
> +++ b/arch/arm/mach-socfpga/misc.c
> @@ -54,8 +54,10 @@ int cpu_eth_init(bd_t *bis)
> {
> #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
> const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
> + const u32 reset = SOCFPGA_RESET(EMAC0);
> #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
> const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
> + const u32 reset = SOCFPGA_RESET(EMAC1);
> #else
> #error "Incorrect CONFIG_EMAC_BASE value!"
> #endif
> @@ -66,7 +68,8 @@ int cpu_eth_init(bd_t *bis)
> * Putting the EMAC controller to reset when configuring the PHY
> * interface select at System Manager
> */
> - socfpga_emac_reset(1);
> + socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
> + socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
Couldn't you just use the 'reset' variable here?
This my only comment on this patch, no need to resend if it's the only one.
Thanks,
Dinh
^ permalink raw reply [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 012/172] arm: socfpga: reset: Repair bridge reset handling
2015-07-27 20:49 ` [U-Boot] [PATCH 012/172] arm: socfpga: reset: Repair bridge reset handling Marek Vasut
@ 2015-07-28 19:21 ` Dinh Nguyen
2015-07-30 11:28 ` Marek Vasut
0 siblings, 1 reply; 185+ messages in thread
From: Dinh Nguyen @ 2015-07-28 19:21 UTC (permalink / raw)
To: u-boot
On 7/27/15 3:49 PM, Marek Vasut wrote:
> The current bridge reset code, which de-asserted the bridge reset,
> was activelly polling whether the FPGA is programmed and ready and
s/activelly/actively
Again...only comment for this patch, no need to resend.
Dinh
^ permalink raw reply [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 011/172] arm: socfpga: reset: Replace ad-hoc reset functions
2015-07-28 19:12 ` Dinh Nguyen
@ 2015-07-28 19:26 ` Marek Vasut
0 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-28 19:26 UTC (permalink / raw)
To: u-boot
On Tuesday, July 28, 2015 at 09:12:50 PM, Dinh Nguyen wrote:
Hi!
> > @@ -66,7 +68,8 @@ int cpu_eth_init(bd_t *bis)
> >
> > * Putting the EMAC controller to reset when configuring the PHY
> > * interface select at System Manager
> > */
> >
> > - socfpga_emac_reset(1);
> > + socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
> > + socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
>
> Couldn't you just use the 'reset' variable here?
Actually, the answer is no. The logic here is such, that you put both GMAC into
reset state, but release from reset only the GMAC which is useful to you. The
rest remains in reset indefinitelly, so it doesn't consume power etc.
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init
2015-07-28 14:58 ` Marek Vasut
@ 2015-07-28 20:28 ` Pavel Machek
2015-07-28 21:08 ` Marek Vasut
0 siblings, 1 reply; 185+ messages in thread
From: Pavel Machek @ 2015-07-28 20:28 UTC (permalink / raw)
To: u-boot
Hi!
> > + rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER,
> > 1);
> > + /*
> > + * Need to wait tMOD (12CK or 15ns) time before issuing other
> > + * commands, but we will have plenty of NIOS cycles before
> > actual
> > + * handoff so its okay.
> > + */
> >
> > I don't understand this comment.
>
> There's plenty of code between issuing the above instruction and triggering
> the mem handoff, so we don't need to add explicit delay into this function.
> Also, 15nS is like 15 instructions on the SoCFPGA, so there is zero chance
> we will trigger the handoff too early.
What does this have to do with NIOS? CPU cores in FPGA are not
mandatory, AFAICT.
> > It looks much better now, thanks,
>
> It's far from good though and there will be another series after this one
> I'm afraid. It might be even heftier, but I want to open the door to proper
> SoCFPGA support this MW even if it means blowing them to shreds ...
MW?
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
^ permalink raw reply [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init
2015-07-28 20:28 ` Pavel Machek
@ 2015-07-28 21:08 ` Marek Vasut
0 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-28 21:08 UTC (permalink / raw)
To: u-boot
On Tuesday, July 28, 2015 at 10:28:39 PM, Pavel Machek wrote:
> Hi!
>
> > > + rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER,
> > > 1);
> > > + /*
> > > + * Need to wait tMOD (12CK or 15ns) time before issuing other
> > > + * commands, but we will have plenty of NIOS cycles before
> > > actual
> > > + * handoff so its okay.
> > > + */
> > >
> > > I don't understand this comment.
> >
> > There's plenty of code between issuing the above instruction and
> > triggering the mem handoff, so we don't need to add explicit delay into
> > this function. Also, 15nS is like 15 instructions on the SoCFPGA, so
> > there is zero chance we will trigger the handoff too early.
>
> What does this have to do with NIOS? CPU cores in FPGA are not
> mandatory, AFAICT.
I think the UniPHY has a NIOS in it, but Dinh might be able to clarify.
> > > It looks much better now, thanks,
> >
> > It's far from good though and there will be another series after this one
> > I'm afraid. It might be even heftier, but I want to open the door to
> > proper SoCFPGA support this MW even if it means blowing them to shreds
> > ...
>
> MW?
Merge Window.
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 012/172] arm: socfpga: reset: Repair bridge reset handling
2015-07-28 19:21 ` Dinh Nguyen
@ 2015-07-30 11:28 ` Marek Vasut
0 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-07-30 11:28 UTC (permalink / raw)
To: u-boot
On Tuesday, July 28, 2015 at 09:21:50 PM, Dinh Nguyen wrote:
> On 7/27/15 3:49 PM, Marek Vasut wrote:
> > The current bridge reset code, which de-asserted the bridge reset,
> > was activelly polling whether the FPGA is programmed and ready and
>
> s/activelly/actively
>
> Again...only comment for this patch, no need to resend.
Fixed, thanks!
Sorry about the blast of patches . How far are you with the review please? :)
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
` (172 preceding siblings ...)
2015-07-28 13:13 ` [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Pavel Machek
@ 2015-08-03 15:16 ` Dinh Nguyen
2015-08-03 16:23 ` Marek Vasut
173 siblings, 1 reply; 185+ messages in thread
From: Dinh Nguyen @ 2015-08-03 15:16 UTC (permalink / raw)
To: u-boot
On 07/27/2015 03:49 PM, Marek Vasut wrote:
> This series fixes the SPL support on SoCFPGA and cleans up the DDR
> init code such that it is becoming remotely mainlinable. After this
> series, the SPL is capable of booting from both SD/MMC and QSPI NOR.
>
> There is still work to be done, but I'd like to start picking it up
> so it can land in 2015.10 . Reviews and comments are welcome.
>
Thank you so much for putting this series together! For the whole series:
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Dinh
^ permalink raw reply [flat|nested] 185+ messages in thread
* [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init
2015-08-03 15:16 ` Dinh Nguyen
@ 2015-08-03 16:23 ` Marek Vasut
0 siblings, 0 replies; 185+ messages in thread
From: Marek Vasut @ 2015-08-03 16:23 UTC (permalink / raw)
To: u-boot
On Monday, August 03, 2015 at 05:16:29 PM, Dinh Nguyen wrote:
> On 07/27/2015 03:49 PM, Marek Vasut wrote:
> > This series fixes the SPL support on SoCFPGA and cleans up the DDR
> > init code such that it is becoming remotely mainlinable. After this
> > series, the SPL is capable of booting from both SD/MMC and QSPI NOR.
> >
> > There is still work to be done, but I'd like to start picking it up
> > so it can land in 2015.10 . Reviews and comments are welcome.
>
> Thank you so much for putting this series together! For the whole series:
>
> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Applied all to u-boot-socfpga/master, thanks!
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 185+ messages in thread
end of thread, other threads:[~2015-08-03 16:23 UTC | newest]
Thread overview: 185+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-07-27 20:49 [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 001/172] driver/ddr/altera: Add DDR driver for Altera's SDRAM controller Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 002/172] driver/ddr/altera: Add the sdram calibration portion Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 003/172] arm: socfpga: enable the Altera SDRAM controller driver Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 004/172] arm: socfpga: Move sdram_config.h to board dir Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 005/172] ddr: altera: Move struct sdram_prot_rule prototype Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 006/172] ddr: altera: Fix typo in mp_threshold1 programming Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 007/172] ddr: altera: Fix debug message format in sequencer Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 008/172] arm: socfpga: reset: Add missing reset manager regs Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 009/172] arm: socfpga: reset: Start reworking the SoCFPGA reset manager Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 010/172] arm: socfpga: reset: Implement unified function to toggle reset Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 011/172] arm: socfpga: reset: Replace ad-hoc reset functions Marek Vasut
2015-07-28 19:12 ` Dinh Nguyen
2015-07-28 19:26 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 012/172] arm: socfpga: reset: Repair bridge reset handling Marek Vasut
2015-07-28 19:21 ` Dinh Nguyen
2015-07-30 11:28 ` Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 013/172] arm: socfpga: reset: Add function to reset add peripherals Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 014/172] arm: socfpga: reset: Add SDMMC, QSPI and DMA defines Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 015/172] arm: socfpga: clock: Get rid of cm_config_t typedef Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 016/172] arm: socfpga: clock: Clean up pll_config.h Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 017/172] arm: socfpga: scan: Staticize scan_mgr_io_scan_chain_prg() Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 018/172] arm: socfpga: scan: Zap redundant params in scan_mgr_io_scan_chain_prg() Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 019/172] arm: socfpga: scan: Zap iocsr_scan_chain*_table() Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 020/172] arm: socfpga: system: Rework sysmgr_enable_warmrstcfgio() Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 021/172] arm: socfpga: system: Clean up pinmux_config.c Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 022/172] arm: socfpga: spl: Toggle warm reset config I/O bit Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 023/172] arm: socfpga: spl: Configure SCU and NIC-301 early Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 024/172] arm: socfpga: spl: Add missing reset logic Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 025/172] arm: socfpga: spl: Merge spl_board_init() into board_init_f() Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 026/172] arm: socfpga: spl: Remove custom linker script Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 027/172] arm: socfpga: spl: Add support for booting from SD/MMC Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 028/172] arm: socfpga: spl: Add support for booting from QSPI Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 029/172] arm: socfpga: spl: Add support for selecting boot device from BSEL Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 030/172] arm: socfpga: misc: Fix warm reset Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 031/172] arm: socfpga: misc: Add support for printing boot mode Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 032/172] arm: socfpga: misc: Export bootmode into environment variable Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 033/172] arm: socfpga: misc: Probe ethernet GMAC from OF Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 034/172] arm: socfpga: misc: Reset ethernet " Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 035/172] arm: socfpga: config: Move SPL GD and malloc to RAM Marek Vasut
2015-07-27 20:49 ` [U-Boot] [PATCH 036/172] arm: socfpga: config: Zap incorrect config options Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 037/172] arm: socfpga: config: Exclude CONFIG_SPI_FLASH_MTD from SPL build Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 038/172] arm: socfpga: config: Enable CONFIG_SPI_FLASH_BAR Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 039/172] arm: socfpga: config: Fix LOADADDR Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 040/172] arm: socfpga: config: Make CONFIG_SPI_FLASH_MTD useful Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 041/172] Makefile: Add target for building bootable SPL image for SoCFPGA Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 042/172] ddr: altera: Minor indent fix in set_rank_and_odt_mask() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 043/172] ddr: altera: Clean up ugly casts in sdram_calibration_full() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 044/172] ddr: altera: Zap invocation of sdr_get_addr((u32 *)BASE_RW_MGR)" Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 045/172] ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_reg_file->.*) Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 046/172] ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_scc_mgr->.*) Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 047/172] ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_rw_load.*->.*) Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 048/172] ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_mgr_.*->.*) Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 049/172] ddr: altera: Pluck out remaining sdr_get_addr() calls Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 050/172] ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESS Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 051/172] ddr: altera: Stop using SDR_CTRLGRP_ADDRESS directly Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 052/172] ddr: altera: Massage addr into I/O accessors Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 053/172] ddr: altera: Clean up hc_initialize_rom_data() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 054/172] ddr: altera: Clean up initialize_reg_file() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 055/172] ddr: altera: Clean up initialize_hps_phy() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 056/172] ddr: altera: Clean up reg_file_set*() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 057/172] ddr: altera: Clean up scc manager function args Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 058/172] ddr: altera: Reorder scc manager functions Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 059/172] ddr: altera: Implement universal scc manager config function Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 060/172] ddr: altera: Clean up scc_mgr_initialize() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 061/172] ddr: altera: Shuffle around scc_mgr_set_*all_ranks() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 062/172] ddr: altera: Implement universal scc_mgr_set_all_ranks() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 063/172] ddr: altera: Clean up scc_mgr_load_dqs_for_write_group() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 064/172] ddr: altera: Clean up scc_set_bypass_mode() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 065/172] ddr: altera: Clean up scc_mgr_set_oct_out1_delay() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 066/172] ddr: altera: Clean up scc_mgr_apply_group_dq_out1_delay() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 067/172] ddr: altera: Clean up scc_mgr_*_delay() args Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 068/172] ddr: altera: Clean up scc_mgr_set_hhp_extras() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 069/172] ddr: altera: Extract scc_mgr_set_hhp_extras() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 070/172] ddr: altera: Clean up scc_mgr_zero_all() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 071/172] ddr: altera: Clean up scc_mgr_zero_group() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 072/172] FIXME: ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add() cleanup part 1 Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 073/172] ddr: altera: Internal scc_mgr_apply_group_all_out_delay_add() cleanup part 2 Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 074/172] ddr: altera: Clean up scc_mgr_apply_group_all_out_delay_add_all_ranks() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 075/172] ddr: altera: Factor out instruction loading from rw_mgr_mem_initialize() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 076/172] ddr: altera: Factor out common code Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 077/172] ddr: altera: Minor clean up of set_jump_as_return() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 078/172] ddr: altera: Fix ad-hoc iterative division implementation Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 079/172] ddr: altera: Rework initialize_tracking() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 080/172] ddr: altera: Init my_param and my_gbl Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 081/172] ddr: altera: Rename initialize() to phy_mgr_initialize() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 082/172] ddr: altera: Clean up run_mem_calibrate() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 083/172] ddr: altera: Clean up phy_mgr_initialize() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 084/172] ddr: altera: Clean up mem_config() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 085/172] ddr: altera: Clean up mem_precharge_and_activate() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 086/172] ddr: altera: Clean up set_rank_and_odt_mask() part 1 Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 087/172] ddr: altera: Clean up set_rank_and_odt_mask() part 2 Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 088/172] ddr: altera: Clean up set_rank_and_odt_mask() part 3 Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 089/172] ddr: altera: Minor clean up of mem_skip_calibrate() Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 090/172] ddr: altera: Trivial mem_calibrate() indent cleanup Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 091/172] ddr: altera: Internal mem_calibrate() cleanup part 1 Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 092/172] ddr: altera: Internal mem_calibrate() cleanup part 2 Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 093/172] ddr: altera: Internal mem_calibrate() cleanup part 3 Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 094/172] ddr: altera: Internal mem_calibrate() cleanup part 4 Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 095/172] ddr: altera: Internal mem_calibrate() cleanup part 5 Marek Vasut
2015-07-27 20:50 ` [U-Boot] [PATCH 096/172] ddr: altera: Internal mem_calibrate() cleanup part 6 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 097/172] ddr: altera: Minor clean up of rw_mgr_mem_initialize() Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 098/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 1 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 099/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 2 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 100/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 3 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 101/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 4 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 102/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 5 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 103/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 6 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 104/172] ddr: altera: Internal rw_mgr_mem_calibrate_vfifo() cleanup part 7 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 105/172] ddr: altera: Extract guaranteed write from rw_mgr_mem_calibrate_vfifo() Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 106/172] ddr: altera: Extract DQS enable calibration " Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 107/172] ddr: altera: Extract Centering DQ/DQS " Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 108/172] ddr: altera: Minor rw_mgr_mem_calibrate_read_load_patterns() cleanup Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 109/172] ddr: altera: Zap rw_mgr_mem_calibrate_read_test_patterns_all_ranks() Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 110/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_patterns() Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 111/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 1 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 112/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 2 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 113/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 3 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 114/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 4 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 115/172] ddr: altera: Clean up sdr_find_window_centre() part 1 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 116/172] ddr: altera: Clean up sdr_find_window_centre() part 2 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 117/172] ddr: altera: Clean up sdr_find_window_centre() part 3 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 118/172] ddr: altera: Clean up sdr_*_phase() part 1 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 119/172] ddr: altera: Clean up sdr_*_phase() part 2 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 120/172] ddr: altera: Clean up sdr_*_phase() part 3 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 121/172] ddr: altera: Clean up sdr_*_phase() part 4 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 122/172] ddr: altera: Clean up sdr_*_phase() part 5 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 123/172] ddr: altera: Clean up sdr_*_phase() part 6 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 124/172] ddr: altera: Clean up sdr_*_phase() part 7 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 125/172] ddr: altera: Clean up sdr_*_phase() part 8 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 126/172] ddr: altera: Clean up sdr_*_phase() part 9 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 127/172] ddr: altera: Clean up sdr_*_phase() part 10 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 128/172] ddr: altera: Clean up rw_mgr_*_vfifo() part 1 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 129/172] ddr: altera: Clean up rw_mgr_*_vfifo() part 2 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 130/172] ddr: altera: Clean up find_vfifo_read() Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 131/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 1 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 132/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 2 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 133/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 3 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 134/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 4 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 135/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 5 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 136/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 6 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 137/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 7 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 138/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_all_ranks() Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 139/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 1 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 140/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 2 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 141/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 3 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 142/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 4 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 143/172] ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 5 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 144/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes() Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 145/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 1 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 146/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 2 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 147/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 3 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 148/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 4 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 149/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 5 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 150/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 6 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 151/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 7 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 152/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 8 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 153/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 9 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 154/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 10 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 155/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 11 Marek Vasut
2015-07-27 20:51 ` [U-Boot] [PATCH 156/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1 Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 157/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 2 Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 158/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3 Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 159/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 4 Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 160/172] ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 5 Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 161/172] ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 1 Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 162/172] ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 2 Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 163/172] ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 3 Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 164/172] ddr: altera: Clean up rw_mgr_mem_calibrate_write_test_issue() Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 165/172] ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_end() Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 166/172] ddr: altera: Clean up rw_mgr_mem_calibrate_lfifo() Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 167/172] ddr: altera: Minor clean up of rw_mgr_mem_handoff() Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 168/172] ddr: altera: Clean up of delay_for_n_mem_clocks() part 1 Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 169/172] ddr: altera: Clean up of delay_for_n_mem_clocks() part 2 Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 170/172] ddr: altera: Clean up of delay_for_n_mem_clocks() part 3 Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 171/172] ddr: altera: Clean up of delay_for_n_mem_clocks() part 4 Marek Vasut
2015-07-27 20:52 ` [U-Boot] [PATCH 172/172] ddr: altera: Clean up of delay_for_n_mem_clocks() part 5 Marek Vasut
2015-07-28 13:13 ` [U-Boot] [PATCH 000/172] socfpga: SPL and DDR init Pavel Machek
2015-07-28 13:30 ` Marek Vasut
2015-07-28 13:58 ` Pavel Machek
2015-07-28 14:58 ` Marek Vasut
2015-07-28 20:28 ` Pavel Machek
2015-07-28 21:08 ` Marek Vasut
2015-08-03 15:16 ` Dinh Nguyen
2015-08-03 16:23 ` Marek Vasut
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all data and code used by this external index.