[U-Boot] [PATCH V2 0/3] ARM: DRA74x: Provide support for ARM erratum 801819

[U-Boot] [PATCH V2 0/3] ARM: DRA74x: Provide support for ARM erratum 801819

[Nishanth Menon]

Provide support ARM erratum 801819 with capability to disable write streaming.

Obvioulsy on SMP systems such as DRA74x/OMAP5, this will benefit only
CPU0. CPU1 when made online in HLOS such as linux kernel will need
similar workaround as well.


Ignoring v1 of the patch completely here.

Nishanth Menon (3):
  ARM: Introduce erratum workaround for 801819
  ARM: DRA7/ OMAP5: implement Auxiliary Control Register configuration
  ARM: DRA72: disable workaround for 801819

 README                                      |  1 +
 arch/arm/cpu/armv7/omap5/hwinit.c           | 17 +++++++++++++++++
 arch/arm/cpu/armv7/start.S                  | 21 +++++++++++++++++++++
 arch/arm/include/asm/arch-omap5/sys_proto.h |  1 +
 4 files changed, 40 insertions(+)

-- 
2.1.4

[U-Boot] [PATCH V2 1/3] ARM: Introduce erratum workaround for 801819

[Nishanth Menon]

Add workaround for Cortex-A15 ARM erratum 801819 which says in summary
that "A livelock can occur in the L2 cache arbitration that might
prevent a snoop from completing. Under certain conditions this can
cause the system to deadlock. "

Recommended workaround is as follows:
Do both of the following:

1) Do not use the write-back no-allocate memory type.
2) Do not issue write-back cacheable stores at any time when the cache
is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it
is implementation defined whether cacheable stores update the cache when
the cache is disabled it is not expected that any portable code will
execute cacheable stores when the cache is disabled.

For implementations of Cortex-A15 configured without the ?L2 arbitration
register slice? option (typically one or two core systems), you must
also do the following:

3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111

So, we provide an option to disable write streaming on OMAP5 and DRA7.
It is a rare condition to occur and may be enabled selectively based
on platform acceptance of risk.

Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3]
is set to 0.

Note: certain unicore SoCs *might* not have REVIDR[3] not set, but
might not meet the condition for the erratum to occur when they donot
have ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
Extensions). Such SoCs will need the work around handled in the SoC
specific manner, since there is no ARM generic manner to detect such
configurations.

Based on ARM errata Document revision 18.0 (22 Nov 2013)

Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Reviewed-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 README                     |  1 +
 arch/arm/cpu/armv7/start.S | 21 +++++++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/README b/README
index 4e0ff9f74e59..55834ee3c465 100644
--- a/README
+++ b/README
@@ -705,6 +705,7 @@ The following options need to be configured:
 		CONFIG_ARM_ERRATA_454179
 		CONFIG_ARM_ERRATA_621766
 		CONFIG_ARM_ERRATA_798870
+		CONFIG_ARM_ERRATA_801819
 
 - Tegra SoC options:
 		CONFIG_TEGRA_SUPPORT_NON_SECURE
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 1c7e6f01f941..b18094447b06 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -187,6 +187,27 @@ ENTRY(cpu_init_cp15)
 skip_errata_798870:
 #endif
 
+#ifdef CONFIG_ARM_ERRATA_801819
+	cmp	r2, #0x24		@ Applies to lt including R2p4
+	bgt	skip_errata_801819      @ skip if not affected rev
+	cmp	r2, #0x20		@ Applies to including and above R2p0
+	blt	skip_errata_801819      @ skip if not affected rev
+	mrc	p15, 0, r0, c0, c0, 6	@ pick up REVIDR reg
+	and	r0, r0, #1 << 3		@ check REVIDR[3]
+	cmp	r0, #1 << 3
+	beq	skip_errata_801819	@ skip erratum if REVIDR[3] is set
+
+	mrc	p15, 0, r0, c1, c0, 1	@ read auxilary control register
+	orr	r0, r0, #3 << 27	@ Disables streaming. All write-allocate
+					@ lines allocate in the L1 or L2 cache.
+	orr	r0, r0, #3 << 25	@ Disables streaming. All write-allocate
+					@ lines allocate in the L1 cache.
+	push	{r1-r5}			@ Save the cpu info registers
+	bl	v7_arch_cp15_set_acr
+	pop	{r1-r5}			@ Restore the cpu info - fall through
+skip_errata_801819:
+#endif
+
 #ifdef CONFIG_ARM_ERRATA_454179
 	cmp	r2, #0x21		@ Only on < r2p1
 	bge	skip_errata_454179
-- 
2.1.4

[U-Boot] [PATCH V2 2/3] ARM: DRA7/ OMAP5: implement Auxiliary Control Register configuration

[Nishanth Menon]

Implement logic for ACR(Auxiliary Control Register) configuration using
ROM Code smc service.

Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Reviewed-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/cpu/armv7/omap5/hwinit.c           | 6 ++++++
 arch/arm/include/asm/arch-omap5/sys_proto.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index 39f8d0d5e200..bc19aebc6db7 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -418,3 +418,9 @@ void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
 {
 	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
 }
+
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+			  u32 cpu_variant, u32 cpu_rev)
+{
+	omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
+}
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 6da8297c7292..7fcb78389403 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -81,5 +81,6 @@ static inline u32 usec_to_32k(u32 usec)
 }
 
 #define OMAP5_SERVICE_L2ACTLR_SET    0x104
+#define OMAP5_SERVICE_ACR_SET        0x107
 
 #endif
-- 
2.1.4

[U-Boot] [PATCH V2 3/3] ARM: DRA72: disable workaround for 801819

[Nishanth Menon]

DRA72x processor variants are single core and it does not export ACP[1].
Hence, we have no source for generating an external snoop requests which
appear to be key to the deadlock in DRA72x design.

Since we build the same image for DRA74x and DRA72x platforms, lets
runtime detect and disable the workaround (in favor of performance) on
DRA72x platforms.

[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438i/BABIAJAG.html

Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Reviewed-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/cpu/armv7/omap5/hwinit.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index bc19aebc6db7..22e0829a6a0c 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -422,5 +422,16 @@ void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
 void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
 			  u32 cpu_variant, u32 cpu_rev)
 {
+
+#ifdef CONFIG_ARM_ERRATA_801819
+	/*
+	 * DRA72x processors are uniprocessors and DONOT have
+	 * ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
+	 * Extensions) Hence the erratum workaround is not applicable for
+	 * DRA72x processors.
+	 */
+	if (is_dra72x())
+		acr &= ~((0x3 << 23) | (0x3 << 25));
+#endif
 	omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
 }
-- 
2.1.4

[U-Boot] [U-Boot, V2, 1/3] ARM: Introduce erratum workaround for 801819

[Tom Rini]

On Mon, Jul 27, 2015 at 04:26:05PM -0500, Nishanth Menon wrote:

> Add workaround for Cortex-A15 ARM erratum 801819 which says in summary
> that "A livelock can occur in the L2 cache arbitration that might
> prevent a snoop from completing. Under certain conditions this can
> cause the system to deadlock. "
> 
> Recommended workaround is as follows:
> Do both of the following:
> 
> 1) Do not use the write-back no-allocate memory type.
> 2) Do not issue write-back cacheable stores at any time when the cache
> is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it
> is implementation defined whether cacheable stores update the cache when
> the cache is disabled it is not expected that any portable code will
> execute cacheable stores when the cache is disabled.
> 
> For implementations of Cortex-A15 configured without the ?L2 arbitration
> register slice? option (typically one or two core systems), you must
> also do the following:
> 
> 3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111
> 
> So, we provide an option to disable write streaming on OMAP5 and DRA7.
> It is a rare condition to occur and may be enabled selectively based
> on platform acceptance of risk.
> 
> Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3]
> is set to 0.
> 
> Note: certain unicore SoCs *might* not have REVIDR[3] not set, but
> might not meet the condition for the erratum to occur when they donot
> have ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
> Extensions). Such SoCs will need the work around handled in the SoC
> specific manner, since there is no ARM generic manner to detect such
> configurations.
> 
> Based on ARM errata Document revision 18.0 (22 Nov 2013)
> 
> Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
> Suggested-by: Brad Griffis <bgriffis@ti.com>
> Reviewed-by: Brad Griffis <bgriffis@ti.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, V2, 2/3] ARM: DRA7/ OMAP5: implement Auxiliary Control Register configuration

[Tom Rini]

On Mon, Jul 27, 2015 at 04:26:06PM -0500, Nishanth Menon wrote:

> Implement logic for ACR(Auxiliary Control Register) configuration using
> ROM Code smc service.
> 
> Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
> Suggested-by: Brad Griffis <bgriffis@ti.com>
> Reviewed-by: Brad Griffis <bgriffis@ti.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>

Applied to u-boot/master, thanks!

-- 
Tom
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[U-Boot] [U-Boot, V2, 3/3] ARM: DRA72: disable workaround for 801819

[Tom Rini]

On Mon, Jul 27, 2015 at 04:26:07PM -0500, Nishanth Menon wrote:

> DRA72x processor variants are single core and it does not export ACP[1].
> Hence, we have no source for generating an external snoop requests which
> appear to be key to the deadlock in DRA72x design.
> 
> Since we build the same image for DRA74x and DRA72x platforms, lets
> runtime detect and disable the workaround (in favor of performance) on
> DRA72x platforms.
> 
> [1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438i/BABIAJAG.html
> 
> Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
> Suggested-by: Brad Griffis <bgriffis@ti.com>
> Reviewed-by: Brad Griffis <bgriffis@ti.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>

Applied to u-boot/master, thanks!

-- 
Tom
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