[PATCH v3 0/3] x86/pci/intel-mid-pci: fix to get eMMC detected

[PATCH v3 0/3] x86/pci/intel-mid-pci: fix to get eMMC detected

[Andy Shevchenko]

On Intel Edison we have an interesting implementation of x86 platform without
legacy PIC and with specific PCI. There are devices which are not using
interrupt line 0, but have it assigned in the PCI configuration. By default
first come gets it, though the first eMMC host controller is the actual user
for IRQ0. 

So, this series provides a quirk (patch 1) to resolve the issue, a small fix of
error code (patch 2), and a sparse warning fix (patch 3).

Changelog v3:
- address Thomas' comments
- massage changelog (what Thomas proposed)

Changelog v2:
- rearrange patches 1 and 2 to provide fix first with Fixes: tag
- append patch 3
- rebase on top of recent linux-next

Andy Shevchenko (3):
  x86/pci/intel_mid_pci: work around for IRQ0 assignment
  x86/pci/intel_mid_pci: propagate actual return code
  x86/pci/intel_mid_pci: fix a sparse warning

 arch/x86/pci/intel_mid_pci.c | 32 +++++++++++++++++++++++++++-----
 1 file changed, 27 insertions(+), 5 deletions(-)

-- 
2.4.6

[PATCH v3 1/3] x86/pci/intel_mid_pci: work around for IRQ0 assignment

[Andy Shevchenko]

On Intel Tangier the MMC host controller is wired up to irq 0. But several
other devices have irq 0 associated as well due to a bogus PCI configuration.

The first initialized driver will acquire irq 0 and make it unavailable for
other devices. If the sdhci driver is not the first one it will fail to acquire
the interrupt and therefor be non functional.

Add a quirk to the pci irq enable function which denies irq 0 to anything else
than the MMC host controller driver on Tangier platforms.

Fixes: 90b9aacf912a (serial: 8250_pci: add Intel Tangier support)
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 arch/x86/pci/intel_mid_pci.c | 24 ++++++++++++++++++++++--
 1 file changed, 22 insertions(+), 2 deletions(-)

diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index 2706230..7553921 100644
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -35,6 +35,9 @@
 
 #define PCIE_CAP_OFFSET	0x100
 
+/* Quirks for the listed devices */
+#define PCI_DEVICE_ID_INTEL_MRFL_MMC	0x1190
+
 /* Fixed BAR fields */
 #define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00	/* Fixed BAR (TBD) */
 #define PCI_FIXED_BAR_0_SIZE	0x04
@@ -214,10 +217,27 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
 	if (dev->irq_managed && dev->irq > 0)
 		return 0;
 
-	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
+	switch (intel_mid_identify_cpu()) {
+	case INTEL_MID_CPU_CHIP_TANGIER:
 		polarity = 0; /* active high */
-	else
+
+		/* Special treatment for IRQ0 */
+		if (dev->irq == 0) {
+			/*
+			 * TNG has IRQ0 assigned to eMMC controller. But there
+			 * are also other devices with bogus PCI configuration
+			 * that have IRQ0 assigned. This check ensures that
+			 * eMMC gets it.
+			 */
+			if (dev->device != PCI_DEVICE_ID_INTEL_MRFL_MMC)
+				return -EBUSY;
+		}
+		break;
+	default:
 		polarity = 1; /* active low */
+		break;
+	}
+
 	ioapic_set_alloc_attr(&info, dev_to_node(&dev->dev), 1, polarity);
 
 	/*
-- 
2.4.6

[PATCH v3 2/3] x86/pci/intel_mid_pci: propagate actual return code

[Andy Shevchenko]

mp_map_gsi_to_irq() returns different codes if it fails.
intel_mid_pci_irq_enable() hides this under -EBUSY. The patch replaces it by
what is actually returned.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 arch/x86/pci/intel_mid_pci.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index 7553921..3361f0a 100644
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -213,6 +213,7 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
 {
 	struct irq_alloc_info info;
 	int polarity;
+	int ret;
 
 	if (dev->irq_managed && dev->irq > 0)
 		return 0;
@@ -244,8 +245,9 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
 	 * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
 	 * IOAPIC RTE entries, so we just enable RTE for the device.
 	 */
-	if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info) < 0)
-		return -EBUSY;
+	ret = mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info);
+	if (ret < 0)
+		return ret;
 
 	dev->irq_managed = 1;
 
-- 
2.4.6

[PATCH v3 3/3] x86/pci/intel_mid_pci: fix a sparse warning

[Andy Shevchenko]

This fixes the following sparse warning.
arch/x86/pci/intel_mid_pci.c:265:16: warning: symbol 'intel_mid_pci_ops' was not declared. Should it be static?

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 arch/x86/pci/intel_mid_pci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index 3361f0a..b096da5 100644
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -263,7 +263,7 @@ static void intel_mid_pci_irq_disable(struct pci_dev *dev)
 	}
 }
 
-struct pci_ops intel_mid_pci_ops = {
+static struct pci_ops intel_mid_pci_ops = {
 	.read = pci_read,
 	.write = pci_write,
 };
-- 
2.4.6

Re: [PATCH v3 0/3] x86/pci/intel-mid-pci: fix to get eMMC detected

[Thomas Gleixner]

On Wed, 29 Jul 2015, Andy Shevchenko wrote:

> On Intel Edison we have an interesting implementation of x86 platform without
> legacy PIC and with specific PCI. There are devices which are not using
> interrupt line 0, but have it assigned in the PCI configuration. By default
> first come gets it, though the first eMMC host controller is the actual user
> for IRQ0. 
> 
> So, this series provides a quirk (patch 1) to resolve the issue, a small fix of
> error code (patch 2), and a sparse warning fix (patch 3).
> 
> Changelog v3:
> - address Thomas' comments
> - massage changelog (what Thomas proposed)
> 
> Andy Shevchenko (3):
>   x86/pci/intel_mid_pci: work around for IRQ0 assignment
>   x86/pci/intel_mid_pci: propagate actual return code
>   x86/pci/intel_mid_pci: fix a sparse warning

I've picked them up. If you get the tip-bot mails, you might notice a
few edits on the changelogs. 

    - Sentence starts with an upper case letter.

    - You cannot fix a sparse warning.

    - "This patch does ...." is just horrible. When one reads a patch
      he already knows that it is a patch.

Please avoid these things in the future.

Thanks,

	tglx

[tip:x86/platform] x86/pci/intel_mid_pci: Work around for IRQ0 assignment

[tip-bot for Andy Shevchenko]

Commit-ID:  39d9b77b8debb4746e189aa5b61ae6e81ec5eab8
Gitweb:     http://git.kernel.org/tip/39d9b77b8debb4746e189aa5b61ae6e81ec5eab8
Author:     Andy Shevchenko <andriy.shevchenko@linux.intel.com>
AuthorDate: Wed, 29 Jul 2015 12:16:47 +0300
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Wed, 29 Jul 2015 21:23:50 +0200

x86/pci/intel_mid_pci: Work around for IRQ0 assignment

On Intel Tangier the MMC host controller is wired up to irq 0. But
several other devices have irq 0 associated as well due to a bogus PCI
configuration.

The first initialized driver will acquire irq 0 and make it
unavailable for other devices. If the sdhci driver is not the first
one it will fail to acquire the interrupt and therefor be non
functional.

Add a quirk to the pci irq enable function which denies irq 0 to
anything else than the MMC host controller driver on Tangier
platforms.

Fixes: 90b9aacf912a (serial: 8250_pci: add Intel Tangier support)
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Link: http://lkml.kernel.org/r/1438161409-4671-2-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
 arch/x86/pci/intel_mid_pci.c | 24 ++++++++++++++++++++++--
 1 file changed, 22 insertions(+), 2 deletions(-)

diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index 2706230..7553921 100644
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -35,6 +35,9 @@
 
 #define PCIE_CAP_OFFSET	0x100
 
+/* Quirks for the listed devices */
+#define PCI_DEVICE_ID_INTEL_MRFL_MMC	0x1190
+
 /* Fixed BAR fields */
 #define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00	/* Fixed BAR (TBD) */
 #define PCI_FIXED_BAR_0_SIZE	0x04
@@ -214,10 +217,27 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
 	if (dev->irq_managed && dev->irq > 0)
 		return 0;
 
-	if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
+	switch (intel_mid_identify_cpu()) {
+	case INTEL_MID_CPU_CHIP_TANGIER:
 		polarity = 0; /* active high */
-	else
+
+		/* Special treatment for IRQ0 */
+		if (dev->irq == 0) {
+			/*
+			 * TNG has IRQ0 assigned to eMMC controller. But there
+			 * are also other devices with bogus PCI configuration
+			 * that have IRQ0 assigned. This check ensures that
+			 * eMMC gets it.
+			 */
+			if (dev->device != PCI_DEVICE_ID_INTEL_MRFL_MMC)
+				return -EBUSY;
+		}
+		break;
+	default:
 		polarity = 1; /* active low */
+		break;
+	}
+
 	ioapic_set_alloc_attr(&info, dev_to_node(&dev->dev), 1, polarity);
 
 	/*

[tip:x86/platform] x86/pci/intel_mid_pci: Propagate actual return code

[tip-bot for Andy Shevchenko]

Commit-ID:  2a61c8eaf1879db99286c3f5fe5e78086c7edb85
Gitweb:     http://git.kernel.org/tip/2a61c8eaf1879db99286c3f5fe5e78086c7edb85
Author:     Andy Shevchenko <andriy.shevchenko@linux.intel.com>
AuthorDate: Wed, 29 Jul 2015 12:16:48 +0300
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Wed, 29 Jul 2015 21:23:50 +0200

x86/pci/intel_mid_pci: Propagate actual return code

mp_map_gsi_to_irq() returns different codes if it fails.
intel_mid_pci_irq_enable() hides this under -EBUSY.

Return the actual failure code.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Link: http://lkml.kernel.org/r/1438161409-4671-3-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
 arch/x86/pci/intel_mid_pci.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index 7553921..3361f0a 100644
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -213,6 +213,7 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
 {
 	struct irq_alloc_info info;
 	int polarity;
+	int ret;
 
 	if (dev->irq_managed && dev->irq > 0)
 		return 0;
@@ -244,8 +245,9 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
 	 * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
 	 * IOAPIC RTE entries, so we just enable RTE for the device.
 	 */
-	if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info) < 0)
-		return -EBUSY;
+	ret = mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info);
+	if (ret < 0)
+		return ret;
 
 	dev->irq_managed = 1;
 

[tip:x86/platform] x86/pci/intel_mid_pci: Make intel_mid_pci_ops static

[tip-bot for Andy Shevchenko]

Commit-ID:  0abbdea1e9592fba120521ce22c6c26301e72761
Gitweb:     http://git.kernel.org/tip/0abbdea1e9592fba120521ce22c6c26301e72761
Author:     Andy Shevchenko <andriy.shevchenko@linux.intel.com>
AuthorDate: Wed, 29 Jul 2015 12:16:49 +0300
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Wed, 29 Jul 2015 21:23:50 +0200

x86/pci/intel_mid_pci: Make intel_mid_pci_ops static

This fixes the following sparse warning.
arch/x86/pci/intel_mid_pci.c:265:16: warning: symbol 'intel_mid_pci_ops' was not declared. Should it be static?

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Link: http://lkml.kernel.org/r/1438161409-4671-4-git-send-email-andriy.shevchenko@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
 arch/x86/pci/intel_mid_pci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index 3361f0a..b096da5 100644
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -263,7 +263,7 @@ static void intel_mid_pci_irq_disable(struct pci_dev *dev)
 	}
 }
 
-struct pci_ops intel_mid_pci_ops = {
+static struct pci_ops intel_mid_pci_ops = {
 	.read = pci_read,
 	.write = pci_write,
 };