* [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
This patch series adds Clock Domain support to the Clock Pulse Generator
(CPG) Module Stop (MSTP) Clocks driver using the generic PM Domain, to
be used on shmobile SoCs without device power domains (R-Car Gen1 and
Gen2, RZ). This allows to power-manage the module clocks of SoC devices
that are part of the CPG/MSTP Clock Domain using Runtime PM, or for
system suspend/resume, similar to SoCs with device power domains
(SH-Mobile and R-Mobile).
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock are tagged in DT with a proper
"power-domains" property, also serving as a visual clue. This applies to
most on-SoC devices, which have a one-to-one mapping from SoC device to
DT device node. Notable exceptions are "display" and "sound" device
nodes, which represent multiple SoC devices, each having their own MSTP
clocks. Hence drivers for such devices still have to manage their
(multiple module) clocks themselves.
The (MSTP) clock to use for power-management is found by scanning for
clocks that are compatible with "renesas,cpg-mstp-clocks".
In V1, the "first" clock tied to each device (con_id NULL) was used,
being a bit ad-hoc. It was suggested to use the "fck" clock instead,
but this may conflict with DT bindings for devices we don't control
(e.g. GIC-400 plans to mandate "clk" for the clk-name of its single
clock). Looking for real MSTP clocks avoids this problem.
Logically, the CPG/MSTP Clock Domain operates on the SoC CPG/MSTP block.
As there's no single device node in DT representing this block (there
are separate device nodes for the CPG and for the individual MSTP
clocks), I bound the logic to the CPG device node. Perhaps this is
something we should change for future SoCs?
Finally, the legacy default PM domain hack in drivers/sh/pm_runtime.c
is no longer needed when running an ARM multi-platform kernel on an
shmobile SoC with genpd support. Please note that this hack is still
needed for legacy (SH/ARM) platforms, and for the CONFIG_PM=n case.
Perhaps we should unconditionally enable PM when building shmobile
multi-platform kernels?
Compared to the legacy default PM domain hack, the CPG/MSTP Clock Domain
has several advantages:
- It only affects on-SoC devices, not all platform devices,
- It only affects the on-SoC devices we want, as specified in DT,
- Allmost all module clocks of all on-SoC devices (barring devices
needed for wake-up) are now gated during s2ram, saving more power.
By adding a small quirk to the CPG/MSTP Clock Domain code, its functions
to attach/detach devices to a PM Domain can be reused by the pm-rmobile
driver, reducing code duplication.
Here's a list of all devices in the CPG/MSTP Clock Domain on r8a7791:
root@koelsch:~# cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
domain status slaves
/device runtime status
----------------------------------------------------------------------
cpg_clocks on
/devices/platform/e61c0000.interrupt-controller active
/devices/platform/e60b0000.i2c suspended
/devices/platform/ffca0000.timer suspended
/devices/platform/e6590100.usb-phy unsupported
/devices/platform/e6050000.gpio active
/devices/platform/e6051000.gpio active
/devices/platform/e6052000.gpio active
/devices/platform/e6053000.gpio active
/devices/platform/e6054000.gpio active
/devices/platform/e6055000.gpio active
/devices/platform/e6055400.gpio active
/devices/platform/e6055800.gpio active
/devices/platform/ee090000.pci active
/devices/platform/ee0d0000.pci active
/devices/platform/fe000000.pcie unsupported
/devices/platform/e6700000.dma-controller active
/devices/platform/e6720000.dma-controller active
/devices/platform/ec700000.dma-controller active
/devices/platform/ec720000.dma-controller suspended
/devices/platform/e65a0000.dma-controller suspended
/devices/platform/e65b0000.dma-controller suspended
/devices/platform/e6e60000.serial active
/devices/platform/e6e68000.serial active
/devices/platform/ee300000.sata unsupported
/devices/platform/e6b10000.spi suspended
/devices/platform/e6e20000.spi suspended
/devices/platform/ee700000.ethernet active
/devices/platform/e6530000.i2c suspended
/devices/platform/e6ef1000.video suspended
/devices/platform/e61f0000.thermal active
/devices/platform/ee100000.sd active
/devices/platform/ee140000.sd active
/devices/platform/ee160000.sd active
root@koelsch:~#
Patch overview:
- Patch 1 adds the core CPG/MSTP Clock Domain code to the CPG MSTP
driver,
- Patches 2-5 adds CPG/MSTP Clock Domain driver support for all
Renesas SoCs that have MSTP clocks, but no device power domains, and
updates the DT binding documentation accordingly,
- Patches 6-12 add CPG/MSTP Clock Domains to the dtsi files,
- Patches 13 and 14 disable the legacy default PM domain hack on all
ARM multi-platform builds with genpd support, now it's no longer
needed nor wanted,
- Patch 15 adds a quirk for r8a73a4 and sh73a0, where the Bus State
Controller is not power-managed by an MSTP clock, but by a plain
CPG clock,
- Patch 16 makes the R-Mobile PM Domain driver use the CPG/MSTP Clock
Domain attach/detach helpers, as they're more future-proof, and to
reduce code duplication.
Changes compared to v3 ("[PATCH v3 00/16] ARM: shmobile: Add CPG/MSTP
Clock Domain", https://lkml.org/lkml/2015/7/1/408):
- clk-mstp.c needs to #include <linux/clk.h> due to recent
<linux/clk*.h> shuffling,
- Add "power-domains" properties to recently introduced device nodes
(jpu, mmcif0),
- Consistently add "power-domains" properties after clock and dma
properties,
- Add Reviewed-by,
Changes compared to v2 ("[PATCH v2 00/14] ARM: shmobile: Add CPG Clock
Domains", https://lkml.org/lkml/2015/5/28/590):
- Add Acked-by,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
- Drop bogus addition of #includes to clk-rcar-gen2.c,
- Call pm_clk_destroy() from cpg_mstp_detach_dev() only if
cpg_mstp_attach_dev() actually added a clock,
- Add "power-domains" property to recently introduced Ethernet AVB
device node,
- Add CPG/MSTP Clock Domain to recently introduced r8a7793 SoC,
- The legacy default PM Domain runtime check must stay for the ARM
multiplatform CONFIG_PM=n case, to prevent the code from running on
non-shmobile machines,
- Provide backwards-compatibility with old DTs (mainly for R-Car
Gen2),
- Extract EMMA Mobile EV2 removal into a separate patch,
- Replace explicit platform checks in the legacy default PM Domain
code by a check for the presence of MSTP clocks,
- Drop references to legacy r8a7740/sh73a0, which are gone.
Changes compared to v1 ("[PATCH/RFC 0/5] ARM: shmobile: rcar-gen2: Add
CPG Clock Domain",
https://www.marc.info/?l=linux-pm&m\x142670805530085&w=3):
- Add Acked-by and Reviewed-by.
- Move core CPG Clock Domain code from the R-Car Gen2 driver to the
CPG MSTP Clocks driver, as it's generic, and can be used on other
Renesas SoCs that have a CPG/MSTP block,
- Scan for an MSTP clock instead of using the first clock tied to the
device (con_id NULL),
- Add support for R-Car Gen1 and RZ, in addition to R-Car Gen2,
allowing to drop the legacy default PM domain hack completely in
multi-platform builds,
- Reuse the CPG Clock Domain attach/detach helpers for pm-rmobile.
More detailed change logs are available in the individual patches.
Dependencies:
- This series is against renesas-devel-20150803-v4.2-rc5 (not
renesas-drivers-2015-08-04-v4.2-rc5, as that tree has more changes
to the .dtsi files),
- As usual when involving clocks and/or PM Domains, there are stringent
dependencies between the (subsets of) patches:
- Patches 2-5 depend on patch 1,
- Patches 6-12 depend on patches 2-5,
- Patch 14 depends on patches 6-13,
- Patch 15 depends on patch 1 only,
- Patch 16 depends on patch 15.
All of this was tested on:
- r8a73a4/ape6evm,
- r8a7740/armadillo,
- r8a7791/koelsch (with and without CONFIG_PM),
- sh73a0/kzm9g.
Testing on other shmobile platforms (esp. R-Car Gen1 and RZ) would be
appreciated.
I think this series goes best in through Simon's shmobile tree.
Thanks for applying!
Geert Uytterhoeven (16):
clk: shmobile: Add CPG/MSTP Clock Domain support
clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
clk: shmobile: rz: Add CPG/MSTP Clock Domain support
ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
drivers: sh: Disable legacy default PM Domain on emev2
drivers: sh: Disable PM runtime for multi-platform ARM with genpd
clk: shmobile: mstp: Consider "zb_clk" suitable for power management
ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach
helpers
.../bindings/clock/renesas,r8a7778-cpg-clocks.txt | 29 ++++++-
.../bindings/clock/renesas,r8a7779-cpg-clocks.txt | 30 ++++++-
.../clock/renesas,rcar-gen2-cpg-clocks.txt | 26 ++++++-
.../bindings/clock/renesas,rz-cpg-clocks.txt | 29 ++++++-
arch/arm/boot/dts/r7s72100.dtsi | 19 +++++
arch/arm/boot/dts/r8a7778.dtsi | 22 ++++++
arch/arm/boot/dts/r8a7779.dtsi | 23 ++++++
arch/arm/boot/dts/r8a7790.dtsi | 86 +++++++++++++++++---
arch/arm/boot/dts/r8a7791.dtsi | 88 +++++++++++++++++++--
arch/arm/boot/dts/r8a7793.dtsi | 7 ++
arch/arm/boot/dts/r8a7794.dtsi | 29 +++++++
arch/arm/mach-shmobile/Kconfig | 2 +
arch/arm/mach-shmobile/pm-rmobile.c | 35 +--------
drivers/clk/shmobile/clk-mstp.c | 91 ++++++++++++++++++++++
drivers/clk/shmobile/clk-r8a7778.c | 2 +
drivers/clk/shmobile/clk-r8a7779.c | 2 +
drivers/clk/shmobile/clk-rcar-gen2.c | 2 +
drivers/clk/shmobile/clk-rz.c | 3 +
drivers/sh/pm_runtime.c | 19 ++---
include/linux/clk/shmobile.h | 12 +++
20 files changed, 482 insertions(+), 74 deletions(-)
--
1.9.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: linux-clk, linux-pm, linux-sh, linux-arm-kernel, devicetree,
linux-kernel, Geert Uytterhoeven
Hi all,
This patch series adds Clock Domain support to the Clock Pulse Generator
(CPG) Module Stop (MSTP) Clocks driver using the generic PM Domain, to
be used on shmobile SoCs without device power domains (R-Car Gen1 and
Gen2, RZ). This allows to power-manage the module clocks of SoC devices
that are part of the CPG/MSTP Clock Domain using Runtime PM, or for
system suspend/resume, similar to SoCs with device power domains
(SH-Mobile and R-Mobile).
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock are tagged in DT with a proper
"power-domains" property, also serving as a visual clue. This applies to
most on-SoC devices, which have a one-to-one mapping from SoC device to
DT device node. Notable exceptions are "display" and "sound" device
nodes, which represent multiple SoC devices, each having their own MSTP
clocks. Hence drivers for such devices still have to manage their
(multiple module) clocks themselves.
The (MSTP) clock to use for power-management is found by scanning for
clocks that are compatible with "renesas,cpg-mstp-clocks".
In V1, the "first" clock tied to each device (con_id NULL) was used,
being a bit ad-hoc. It was suggested to use the "fck" clock instead,
but this may conflict with DT bindings for devices we don't control
(e.g. GIC-400 plans to mandate "clk" for the clk-name of its single
clock). Looking for real MSTP clocks avoids this problem.
Logically, the CPG/MSTP Clock Domain operates on the SoC CPG/MSTP block.
As there's no single device node in DT representing this block (there
are separate device nodes for the CPG and for the individual MSTP
clocks), I bound the logic to the CPG device node. Perhaps this is
something we should change for future SoCs?
Finally, the legacy default PM domain hack in drivers/sh/pm_runtime.c
is no longer needed when running an ARM multi-platform kernel on an
shmobile SoC with genpd support. Please note that this hack is still
needed for legacy (SH/ARM) platforms, and for the CONFIG_PM=n case.
Perhaps we should unconditionally enable PM when building shmobile
multi-platform kernels?
Compared to the legacy default PM domain hack, the CPG/MSTP Clock Domain
has several advantages:
- It only affects on-SoC devices, not all platform devices,
- It only affects the on-SoC devices we want, as specified in DT,
- Allmost all module clocks of all on-SoC devices (barring devices
needed for wake-up) are now gated during s2ram, saving more power.
By adding a small quirk to the CPG/MSTP Clock Domain code, its functions
to attach/detach devices to a PM Domain can be reused by the pm-rmobile
driver, reducing code duplication.
Here's a list of all devices in the CPG/MSTP Clock Domain on r8a7791:
root@koelsch:~# cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
domain status slaves
/device runtime status
----------------------------------------------------------------------
cpg_clocks on
/devices/platform/e61c0000.interrupt-controller active
/devices/platform/e60b0000.i2c suspended
/devices/platform/ffca0000.timer suspended
/devices/platform/e6590100.usb-phy unsupported
/devices/platform/e6050000.gpio active
/devices/platform/e6051000.gpio active
/devices/platform/e6052000.gpio active
/devices/platform/e6053000.gpio active
/devices/platform/e6054000.gpio active
/devices/platform/e6055000.gpio active
/devices/platform/e6055400.gpio active
/devices/platform/e6055800.gpio active
/devices/platform/ee090000.pci active
/devices/platform/ee0d0000.pci active
/devices/platform/fe000000.pcie unsupported
/devices/platform/e6700000.dma-controller active
/devices/platform/e6720000.dma-controller active
/devices/platform/ec700000.dma-controller active
/devices/platform/ec720000.dma-controller suspended
/devices/platform/e65a0000.dma-controller suspended
/devices/platform/e65b0000.dma-controller suspended
/devices/platform/e6e60000.serial active
/devices/platform/e6e68000.serial active
/devices/platform/ee300000.sata unsupported
/devices/platform/e6b10000.spi suspended
/devices/platform/e6e20000.spi suspended
/devices/platform/ee700000.ethernet active
/devices/platform/e6530000.i2c suspended
/devices/platform/e6ef1000.video suspended
/devices/platform/e61f0000.thermal active
/devices/platform/ee100000.sd active
/devices/platform/ee140000.sd active
/devices/platform/ee160000.sd active
root@koelsch:~#
Patch overview:
- Patch 1 adds the core CPG/MSTP Clock Domain code to the CPG MSTP
driver,
- Patches 2-5 adds CPG/MSTP Clock Domain driver support for all
Renesas SoCs that have MSTP clocks, but no device power domains, and
updates the DT binding documentation accordingly,
- Patches 6-12 add CPG/MSTP Clock Domains to the dtsi files,
- Patches 13 and 14 disable the legacy default PM domain hack on all
ARM multi-platform builds with genpd support, now it's no longer
needed nor wanted,
- Patch 15 adds a quirk for r8a73a4 and sh73a0, where the Bus State
Controller is not power-managed by an MSTP clock, but by a plain
CPG clock,
- Patch 16 makes the R-Mobile PM Domain driver use the CPG/MSTP Clock
Domain attach/detach helpers, as they're more future-proof, and to
reduce code duplication.
Changes compared to v3 ("[PATCH v3 00/16] ARM: shmobile: Add CPG/MSTP
Clock Domain", https://lkml.org/lkml/2015/7/1/408):
- clk-mstp.c needs to #include <linux/clk.h> due to recent
<linux/clk*.h> shuffling,
- Add "power-domains" properties to recently introduced device nodes
(jpu, mmcif0),
- Consistently add "power-domains" properties after clock and dma
properties,
- Add Reviewed-by,
Changes compared to v2 ("[PATCH v2 00/14] ARM: shmobile: Add CPG Clock
Domains", https://lkml.org/lkml/2015/5/28/590):
- Add Acked-by,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
- Drop bogus addition of #includes to clk-rcar-gen2.c,
- Call pm_clk_destroy() from cpg_mstp_detach_dev() only if
cpg_mstp_attach_dev() actually added a clock,
- Add "power-domains" property to recently introduced Ethernet AVB
device node,
- Add CPG/MSTP Clock Domain to recently introduced r8a7793 SoC,
- The legacy default PM Domain runtime check must stay for the ARM
multiplatform CONFIG_PM=n case, to prevent the code from running on
non-shmobile machines,
- Provide backwards-compatibility with old DTs (mainly for R-Car
Gen2),
- Extract EMMA Mobile EV2 removal into a separate patch,
- Replace explicit platform checks in the legacy default PM Domain
code by a check for the presence of MSTP clocks,
- Drop references to legacy r8a7740/sh73a0, which are gone.
Changes compared to v1 ("[PATCH/RFC 0/5] ARM: shmobile: rcar-gen2: Add
CPG Clock Domain",
https://www.marc.info/?l=linux-pm&m=142670805530085&w=3):
- Add Acked-by and Reviewed-by.
- Move core CPG Clock Domain code from the R-Car Gen2 driver to the
CPG MSTP Clocks driver, as it's generic, and can be used on other
Renesas SoCs that have a CPG/MSTP block,
- Scan for an MSTP clock instead of using the first clock tied to the
device (con_id NULL),
- Add support for R-Car Gen1 and RZ, in addition to R-Car Gen2,
allowing to drop the legacy default PM domain hack completely in
multi-platform builds,
- Reuse the CPG Clock Domain attach/detach helpers for pm-rmobile.
More detailed change logs are available in the individual patches.
Dependencies:
- This series is against renesas-devel-20150803-v4.2-rc5 (not
renesas-drivers-2015-08-04-v4.2-rc5, as that tree has more changes
to the .dtsi files),
- As usual when involving clocks and/or PM Domains, there are stringent
dependencies between the (subsets of) patches:
- Patches 2-5 depend on patch 1,
- Patches 6-12 depend on patches 2-5,
- Patch 14 depends on patches 6-13,
- Patch 15 depends on patch 1 only,
- Patch 16 depends on patch 15.
All of this was tested on:
- r8a73a4/ape6evm,
- r8a7740/armadillo,
- r8a7791/koelsch (with and without CONFIG_PM),
- sh73a0/kzm9g.
Testing on other shmobile platforms (esp. R-Car Gen1 and RZ) would be
appreciated.
I think this series goes best in through Simon's shmobile tree.
Thanks for applying!
Geert Uytterhoeven (16):
clk: shmobile: Add CPG/MSTP Clock Domain support
clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
clk: shmobile: rz: Add CPG/MSTP Clock Domain support
ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
drivers: sh: Disable legacy default PM Domain on emev2
drivers: sh: Disable PM runtime for multi-platform ARM with genpd
clk: shmobile: mstp: Consider "zb_clk" suitable for power management
ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach
helpers
.../bindings/clock/renesas,r8a7778-cpg-clocks.txt | 29 ++++++-
.../bindings/clock/renesas,r8a7779-cpg-clocks.txt | 30 ++++++-
.../clock/renesas,rcar-gen2-cpg-clocks.txt | 26 ++++++-
.../bindings/clock/renesas,rz-cpg-clocks.txt | 29 ++++++-
arch/arm/boot/dts/r7s72100.dtsi | 19 +++++
arch/arm/boot/dts/r8a7778.dtsi | 22 ++++++
arch/arm/boot/dts/r8a7779.dtsi | 23 ++++++
arch/arm/boot/dts/r8a7790.dtsi | 86 +++++++++++++++++---
arch/arm/boot/dts/r8a7791.dtsi | 88 +++++++++++++++++++--
arch/arm/boot/dts/r8a7793.dtsi | 7 ++
arch/arm/boot/dts/r8a7794.dtsi | 29 +++++++
arch/arm/mach-shmobile/Kconfig | 2 +
arch/arm/mach-shmobile/pm-rmobile.c | 35 +--------
drivers/clk/shmobile/clk-mstp.c | 91 ++++++++++++++++++++++
drivers/clk/shmobile/clk-r8a7778.c | 2 +
drivers/clk/shmobile/clk-r8a7779.c | 2 +
drivers/clk/shmobile/clk-rcar-gen2.c | 2 +
drivers/clk/shmobile/clk-rz.c | 3 +
drivers/sh/pm_runtime.c | 19 ++---
include/linux/clk/shmobile.h | 12 +++
20 files changed, 482 insertions(+), 74 deletions(-)
--
1.9.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
This patch series adds Clock Domain support to the Clock Pulse Generator
(CPG) Module Stop (MSTP) Clocks driver using the generic PM Domain, to
be used on shmobile SoCs without device power domains (R-Car Gen1 and
Gen2, RZ). This allows to power-manage the module clocks of SoC devices
that are part of the CPG/MSTP Clock Domain using Runtime PM, or for
system suspend/resume, similar to SoCs with device power domains
(SH-Mobile and R-Mobile).
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock are tagged in DT with a proper
"power-domains" property, also serving as a visual clue. This applies to
most on-SoC devices, which have a one-to-one mapping from SoC device to
DT device node. Notable exceptions are "display" and "sound" device
nodes, which represent multiple SoC devices, each having their own MSTP
clocks. Hence drivers for such devices still have to manage their
(multiple module) clocks themselves.
The (MSTP) clock to use for power-management is found by scanning for
clocks that are compatible with "renesas,cpg-mstp-clocks".
In V1, the "first" clock tied to each device (con_id NULL) was used,
being a bit ad-hoc. It was suggested to use the "fck" clock instead,
but this may conflict with DT bindings for devices we don't control
(e.g. GIC-400 plans to mandate "clk" for the clk-name of its single
clock). Looking for real MSTP clocks avoids this problem.
Logically, the CPG/MSTP Clock Domain operates on the SoC CPG/MSTP block.
As there's no single device node in DT representing this block (there
are separate device nodes for the CPG and for the individual MSTP
clocks), I bound the logic to the CPG device node. Perhaps this is
something we should change for future SoCs?
Finally, the legacy default PM domain hack in drivers/sh/pm_runtime.c
is no longer needed when running an ARM multi-platform kernel on an
shmobile SoC with genpd support. Please note that this hack is still
needed for legacy (SH/ARM) platforms, and for the CONFIG_PM=n case.
Perhaps we should unconditionally enable PM when building shmobile
multi-platform kernels?
Compared to the legacy default PM domain hack, the CPG/MSTP Clock Domain
has several advantages:
- It only affects on-SoC devices, not all platform devices,
- It only affects the on-SoC devices we want, as specified in DT,
- Allmost all module clocks of all on-SoC devices (barring devices
needed for wake-up) are now gated during s2ram, saving more power.
By adding a small quirk to the CPG/MSTP Clock Domain code, its functions
to attach/detach devices to a PM Domain can be reused by the pm-rmobile
driver, reducing code duplication.
Here's a list of all devices in the CPG/MSTP Clock Domain on r8a7791:
root at koelsch:~# cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
domain status slaves
/device runtime status
----------------------------------------------------------------------
cpg_clocks on
/devices/platform/e61c0000.interrupt-controller active
/devices/platform/e60b0000.i2c suspended
/devices/platform/ffca0000.timer suspended
/devices/platform/e6590100.usb-phy unsupported
/devices/platform/e6050000.gpio active
/devices/platform/e6051000.gpio active
/devices/platform/e6052000.gpio active
/devices/platform/e6053000.gpio active
/devices/platform/e6054000.gpio active
/devices/platform/e6055000.gpio active
/devices/platform/e6055400.gpio active
/devices/platform/e6055800.gpio active
/devices/platform/ee090000.pci active
/devices/platform/ee0d0000.pci active
/devices/platform/fe000000.pcie unsupported
/devices/platform/e6700000.dma-controller active
/devices/platform/e6720000.dma-controller active
/devices/platform/ec700000.dma-controller active
/devices/platform/ec720000.dma-controller suspended
/devices/platform/e65a0000.dma-controller suspended
/devices/platform/e65b0000.dma-controller suspended
/devices/platform/e6e60000.serial active
/devices/platform/e6e68000.serial active
/devices/platform/ee300000.sata unsupported
/devices/platform/e6b10000.spi suspended
/devices/platform/e6e20000.spi suspended
/devices/platform/ee700000.ethernet active
/devices/platform/e6530000.i2c suspended
/devices/platform/e6ef1000.video suspended
/devices/platform/e61f0000.thermal active
/devices/platform/ee100000.sd active
/devices/platform/ee140000.sd active
/devices/platform/ee160000.sd active
root at koelsch:~#
Patch overview:
- Patch 1 adds the core CPG/MSTP Clock Domain code to the CPG MSTP
driver,
- Patches 2-5 adds CPG/MSTP Clock Domain driver support for all
Renesas SoCs that have MSTP clocks, but no device power domains, and
updates the DT binding documentation accordingly,
- Patches 6-12 add CPG/MSTP Clock Domains to the dtsi files,
- Patches 13 and 14 disable the legacy default PM domain hack on all
ARM multi-platform builds with genpd support, now it's no longer
needed nor wanted,
- Patch 15 adds a quirk for r8a73a4 and sh73a0, where the Bus State
Controller is not power-managed by an MSTP clock, but by a plain
CPG clock,
- Patch 16 makes the R-Mobile PM Domain driver use the CPG/MSTP Clock
Domain attach/detach helpers, as they're more future-proof, and to
reduce code duplication.
Changes compared to v3 ("[PATCH v3 00/16] ARM: shmobile: Add CPG/MSTP
Clock Domain", https://lkml.org/lkml/2015/7/1/408):
- clk-mstp.c needs to #include <linux/clk.h> due to recent
<linux/clk*.h> shuffling,
- Add "power-domains" properties to recently introduced device nodes
(jpu, mmcif0),
- Consistently add "power-domains" properties after clock and dma
properties,
- Add Reviewed-by,
Changes compared to v2 ("[PATCH v2 00/14] ARM: shmobile: Add CPG Clock
Domains", https://lkml.org/lkml/2015/5/28/590):
- Add Acked-by,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
- Drop bogus addition of #includes to clk-rcar-gen2.c,
- Call pm_clk_destroy() from cpg_mstp_detach_dev() only if
cpg_mstp_attach_dev() actually added a clock,
- Add "power-domains" property to recently introduced Ethernet AVB
device node,
- Add CPG/MSTP Clock Domain to recently introduced r8a7793 SoC,
- The legacy default PM Domain runtime check must stay for the ARM
multiplatform CONFIG_PM=n case, to prevent the code from running on
non-shmobile machines,
- Provide backwards-compatibility with old DTs (mainly for R-Car
Gen2),
- Extract EMMA Mobile EV2 removal into a separate patch,
- Replace explicit platform checks in the legacy default PM Domain
code by a check for the presence of MSTP clocks,
- Drop references to legacy r8a7740/sh73a0, which are gone.
Changes compared to v1 ("[PATCH/RFC 0/5] ARM: shmobile: rcar-gen2: Add
CPG Clock Domain",
https://www.marc.info/?l=linux-pm&m=142670805530085&w=3):
- Add Acked-by and Reviewed-by.
- Move core CPG Clock Domain code from the R-Car Gen2 driver to the
CPG MSTP Clocks driver, as it's generic, and can be used on other
Renesas SoCs that have a CPG/MSTP block,
- Scan for an MSTP clock instead of using the first clock tied to the
device (con_id NULL),
- Add support for R-Car Gen1 and RZ, in addition to R-Car Gen2,
allowing to drop the legacy default PM domain hack completely in
multi-platform builds,
- Reuse the CPG Clock Domain attach/detach helpers for pm-rmobile.
More detailed change logs are available in the individual patches.
Dependencies:
- This series is against renesas-devel-20150803-v4.2-rc5 (not
renesas-drivers-2015-08-04-v4.2-rc5, as that tree has more changes
to the .dtsi files),
- As usual when involving clocks and/or PM Domains, there are stringent
dependencies between the (subsets of) patches:
- Patches 2-5 depend on patch 1,
- Patches 6-12 depend on patches 2-5,
- Patch 14 depends on patches 6-13,
- Patch 15 depends on patch 1 only,
- Patch 16 depends on patch 15.
All of this was tested on:
- r8a73a4/ape6evm,
- r8a7740/armadillo,
- r8a7791/koelsch (with and without CONFIG_PM),
- sh73a0/kzm9g.
Testing on other shmobile platforms (esp. R-Car Gen1 and RZ) would be
appreciated.
I think this series goes best in through Simon's shmobile tree.
Thanks for applying!
Geert Uytterhoeven (16):
clk: shmobile: Add CPG/MSTP Clock Domain support
clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
clk: shmobile: rz: Add CPG/MSTP Clock Domain support
ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
drivers: sh: Disable legacy default PM Domain on emev2
drivers: sh: Disable PM runtime for multi-platform ARM with genpd
clk: shmobile: mstp: Consider "zb_clk" suitable for power management
ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach
helpers
.../bindings/clock/renesas,r8a7778-cpg-clocks.txt | 29 ++++++-
.../bindings/clock/renesas,r8a7779-cpg-clocks.txt | 30 ++++++-
.../clock/renesas,rcar-gen2-cpg-clocks.txt | 26 ++++++-
.../bindings/clock/renesas,rz-cpg-clocks.txt | 29 ++++++-
arch/arm/boot/dts/r7s72100.dtsi | 19 +++++
arch/arm/boot/dts/r8a7778.dtsi | 22 ++++++
arch/arm/boot/dts/r8a7779.dtsi | 23 ++++++
arch/arm/boot/dts/r8a7790.dtsi | 86 +++++++++++++++++---
arch/arm/boot/dts/r8a7791.dtsi | 88 +++++++++++++++++++--
arch/arm/boot/dts/r8a7793.dtsi | 7 ++
arch/arm/boot/dts/r8a7794.dtsi | 29 +++++++
arch/arm/mach-shmobile/Kconfig | 2 +
arch/arm/mach-shmobile/pm-rmobile.c | 35 +--------
drivers/clk/shmobile/clk-mstp.c | 91 ++++++++++++++++++++++
drivers/clk/shmobile/clk-r8a7778.c | 2 +
drivers/clk/shmobile/clk-r8a7779.c | 2 +
drivers/clk/shmobile/clk-rcar-gen2.c | 2 +
drivers/clk/shmobile/clk-rz.c | 3 +
drivers/sh/pm_runtime.c | 19 ++---
include/linux/clk/shmobile.h | 12 +++
20 files changed, 482 insertions(+), 74 deletions(-)
--
1.9.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* [PATCH v4 01/16] clk: shmobile: Add CPG/MSTP Clock Domain support
2015-08-04 12:28 ` Geert Uytterhoeven
(?)
@ 2015-08-04 12:28 ` Geert Uytterhoeven
-1 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add Clock Domain support to the Clock Pulse Generator (CPG) Module Stop
(MSTP) Clocks driver using the generic PM Domain. This allows to
power-manage the module clocks of SoC devices that are part of the
CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a
proper "power-domains" property.
The CPG/MSTP Clock Domain code will scan such devices for clocks that
are suitable for power-managing the device, by looking for a clock that
is compatible with "renesas,cpg-mstp-clocks".
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
---
v4:
- clk-mstp.c needs to #include <linux/clk.h> due to recent
<linux/clk*.h> shuffling,
v3:
- Add Acked-by,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
- Drop bogus addition of #includes to clk-rcar-gen2.c,
- Call pm_clk_destroy() from cpg_mstp_detach_dev() only if
cpg_mstp_attach_dev() actually added a clock,
v2:
- Add Acked-by and Reviewed-by,
- Move core CPG Clock Domain code from the R-Car Gen2 driver to the
CPG MSTP Clock driver, as it's generic, and can be used on other
Renesas SoCs that have a CPG/MSTP block,
- Scan for an MSTP clock instead of using the first clock tied to the
device (con_id NULL),
- Extract R-Car Gen2 specifics to a separate patch.
---
drivers/clk/shmobile/clk-mstp.c | 87 +++++++++++++++++++++++++++++++++++++++++
include/linux/clk/shmobile.h | 12 ++++++
2 files changed, 99 insertions(+)
diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
index 2d2fe773ac8168f9..b1df7b2f1e970adb 100644
--- a/drivers/clk/shmobile/clk-mstp.c
+++ b/drivers/clk/shmobile/clk-mstp.c
@@ -2,6 +2,7 @@
* R-Car MSTP clocks
*
* Copyright (C) 2013 Ideas On Board SPRL
+ * Copyright (C) 2015 Glider bvba
*
* Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
*
@@ -10,11 +11,16 @@
* the Free Software Foundation; version 2 of the License.
*/
+#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
+#include <linux/clk/shmobile.h>
+#include <linux/device.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_domain.h>
#include <linux/spinlock.h>
/*
@@ -236,3 +242,84 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
}
CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
+
+
+#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
+int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
+{
+ struct device_node *np = dev->of_node;
+ struct of_phandle_args clkspec;
+ struct clk *clk;
+ int i = 0;
+ int error;
+
+ while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
+ &clkspec)) {
+ if (of_device_is_compatible(clkspec.np,
+ "renesas,cpg-mstp-clocks"))
+ goto found;
+
+ of_node_put(clkspec.np);
+ i++;
+ }
+
+ return 0;
+
+found:
+ clk = of_clk_get_from_provider(&clkspec);
+ of_node_put(clkspec.np);
+
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ error = pm_clk_create(dev);
+ if (error) {
+ dev_err(dev, "pm_clk_create failed %d\n", error);
+ goto fail_put;
+ }
+
+ error = pm_clk_add_clk(dev, clk);
+ if (error) {
+ dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
+ goto fail_destroy;
+ }
+
+ return 0;
+
+fail_destroy:
+ pm_clk_destroy(dev);
+fail_put:
+ clk_put(clk);
+ return error;
+}
+
+void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev)
+{
+ if (!list_empty(&dev->power.subsys_data->clock_list))
+ pm_clk_destroy(dev);
+}
+
+void __init cpg_mstp_add_clk_domain(struct device_node *np)
+{
+ struct generic_pm_domain *pd;
+ u32 ncells;
+
+ if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
+ pr_warn("%s lacks #power-domain-cells\n", np->full_name);
+ return;
+ }
+
+ pd = kzalloc(sizeof(*pd), GFP_KERNEL);
+ if (!pd)
+ return;
+
+ pd->name = np->name;
+
+ pd->flags = GENPD_FLAG_PM_CLK;
+ pm_genpd_init(pd, &simple_qos_governor, false);
+ pd->attach_dev = cpg_mstp_attach_dev;
+ pd->detach_dev = cpg_mstp_detach_dev;
+
+ of_genpd_add_provider_simple(np, pd);
+}
+#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */
diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
index 63a8159c4e64153d..cb19cc1865ca5cfb 100644
--- a/include/linux/clk/shmobile.h
+++ b/include/linux/clk/shmobile.h
@@ -16,8 +16,20 @@
#include <linux/types.h>
+struct device;
+struct device_node;
+struct generic_pm_domain;
+
void r8a7778_clocks_init(u32 mode);
void r8a7779_clocks_init(u32 mode);
void rcar_gen2_clocks_init(u32 mode);
+#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
+void cpg_mstp_add_clk_domain(struct device_node *np);
+int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev);
+void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev);
+#else
+static inline void cpg_mstp_add_clk_domain(struct device_node *np) {}
+#endif
+
#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 01/16] clk: shmobile: Add CPG/MSTP Clock Domain support
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: linux-clk, linux-pm, linux-sh, linux-arm-kernel, devicetree,
linux-kernel, Geert Uytterhoeven
Add Clock Domain support to the Clock Pulse Generator (CPG) Module Stop
(MSTP) Clocks driver using the generic PM Domain. This allows to
power-manage the module clocks of SoC devices that are part of the
CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a
proper "power-domains" property.
The CPG/MSTP Clock Domain code will scan such devices for clocks that
are suitable for power-managing the device, by looking for a clock that
is compatible with "renesas,cpg-mstp-clocks".
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
---
v4:
- clk-mstp.c needs to #include <linux/clk.h> due to recent
<linux/clk*.h> shuffling,
v3:
- Add Acked-by,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
- Drop bogus addition of #includes to clk-rcar-gen2.c,
- Call pm_clk_destroy() from cpg_mstp_detach_dev() only if
cpg_mstp_attach_dev() actually added a clock,
v2:
- Add Acked-by and Reviewed-by,
- Move core CPG Clock Domain code from the R-Car Gen2 driver to the
CPG MSTP Clock driver, as it's generic, and can be used on other
Renesas SoCs that have a CPG/MSTP block,
- Scan for an MSTP clock instead of using the first clock tied to the
device (con_id NULL),
- Extract R-Car Gen2 specifics to a separate patch.
---
drivers/clk/shmobile/clk-mstp.c | 87 +++++++++++++++++++++++++++++++++++++++++
include/linux/clk/shmobile.h | 12 ++++++
2 files changed, 99 insertions(+)
diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
index 2d2fe773ac8168f9..b1df7b2f1e970adb 100644
--- a/drivers/clk/shmobile/clk-mstp.c
+++ b/drivers/clk/shmobile/clk-mstp.c
@@ -2,6 +2,7 @@
* R-Car MSTP clocks
*
* Copyright (C) 2013 Ideas On Board SPRL
+ * Copyright (C) 2015 Glider bvba
*
* Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
*
@@ -10,11 +11,16 @@
* the Free Software Foundation; version 2 of the License.
*/
+#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
+#include <linux/clk/shmobile.h>
+#include <linux/device.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_domain.h>
#include <linux/spinlock.h>
/*
@@ -236,3 +242,84 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
}
CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
+
+
+#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
+int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
+{
+ struct device_node *np = dev->of_node;
+ struct of_phandle_args clkspec;
+ struct clk *clk;
+ int i = 0;
+ int error;
+
+ while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
+ &clkspec)) {
+ if (of_device_is_compatible(clkspec.np,
+ "renesas,cpg-mstp-clocks"))
+ goto found;
+
+ of_node_put(clkspec.np);
+ i++;
+ }
+
+ return 0;
+
+found:
+ clk = of_clk_get_from_provider(&clkspec);
+ of_node_put(clkspec.np);
+
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ error = pm_clk_create(dev);
+ if (error) {
+ dev_err(dev, "pm_clk_create failed %d\n", error);
+ goto fail_put;
+ }
+
+ error = pm_clk_add_clk(dev, clk);
+ if (error) {
+ dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
+ goto fail_destroy;
+ }
+
+ return 0;
+
+fail_destroy:
+ pm_clk_destroy(dev);
+fail_put:
+ clk_put(clk);
+ return error;
+}
+
+void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev)
+{
+ if (!list_empty(&dev->power.subsys_data->clock_list))
+ pm_clk_destroy(dev);
+}
+
+void __init cpg_mstp_add_clk_domain(struct device_node *np)
+{
+ struct generic_pm_domain *pd;
+ u32 ncells;
+
+ if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
+ pr_warn("%s lacks #power-domain-cells\n", np->full_name);
+ return;
+ }
+
+ pd = kzalloc(sizeof(*pd), GFP_KERNEL);
+ if (!pd)
+ return;
+
+ pd->name = np->name;
+
+ pd->flags = GENPD_FLAG_PM_CLK;
+ pm_genpd_init(pd, &simple_qos_governor, false);
+ pd->attach_dev = cpg_mstp_attach_dev;
+ pd->detach_dev = cpg_mstp_detach_dev;
+
+ of_genpd_add_provider_simple(np, pd);
+}
+#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */
diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
index 63a8159c4e64153d..cb19cc1865ca5cfb 100644
--- a/include/linux/clk/shmobile.h
+++ b/include/linux/clk/shmobile.h
@@ -16,8 +16,20 @@
#include <linux/types.h>
+struct device;
+struct device_node;
+struct generic_pm_domain;
+
void r8a7778_clocks_init(u32 mode);
void r8a7779_clocks_init(u32 mode);
void rcar_gen2_clocks_init(u32 mode);
+#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
+void cpg_mstp_add_clk_domain(struct device_node *np);
+int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev);
+void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev);
+#else
+static inline void cpg_mstp_add_clk_domain(struct device_node *np) {}
+#endif
+
#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 01/16] clk: shmobile: Add CPG/MSTP Clock Domain support
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add Clock Domain support to the Clock Pulse Generator (CPG) Module Stop
(MSTP) Clocks driver using the generic PM Domain. This allows to
power-manage the module clocks of SoC devices that are part of the
CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a
proper "power-domains" property.
The CPG/MSTP Clock Domain code will scan such devices for clocks that
are suitable for power-managing the device, by looking for a clock that
is compatible with "renesas,cpg-mstp-clocks".
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
---
v4:
- clk-mstp.c needs to #include <linux/clk.h> due to recent
<linux/clk*.h> shuffling,
v3:
- Add Acked-by,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
- Drop bogus addition of #includes to clk-rcar-gen2.c,
- Call pm_clk_destroy() from cpg_mstp_detach_dev() only if
cpg_mstp_attach_dev() actually added a clock,
v2:
- Add Acked-by and Reviewed-by,
- Move core CPG Clock Domain code from the R-Car Gen2 driver to the
CPG MSTP Clock driver, as it's generic, and can be used on other
Renesas SoCs that have a CPG/MSTP block,
- Scan for an MSTP clock instead of using the first clock tied to the
device (con_id NULL),
- Extract R-Car Gen2 specifics to a separate patch.
---
drivers/clk/shmobile/clk-mstp.c | 87 +++++++++++++++++++++++++++++++++++++++++
include/linux/clk/shmobile.h | 12 ++++++
2 files changed, 99 insertions(+)
diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
index 2d2fe773ac8168f9..b1df7b2f1e970adb 100644
--- a/drivers/clk/shmobile/clk-mstp.c
+++ b/drivers/clk/shmobile/clk-mstp.c
@@ -2,6 +2,7 @@
* R-Car MSTP clocks
*
* Copyright (C) 2013 Ideas On Board SPRL
+ * Copyright (C) 2015 Glider bvba
*
* Contact: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
*
@@ -10,11 +11,16 @@
* the Free Software Foundation; version 2 of the License.
*/
+#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
+#include <linux/clk/shmobile.h>
+#include <linux/device.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_domain.h>
#include <linux/spinlock.h>
/*
@@ -236,3 +242,84 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
of_clk_add_provider(np, of_clk_src_onecell_get, &group->data);
}
CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);
+
+
+#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
+int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
+{
+ struct device_node *np = dev->of_node;
+ struct of_phandle_args clkspec;
+ struct clk *clk;
+ int i = 0;
+ int error;
+
+ while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
+ &clkspec)) {
+ if (of_device_is_compatible(clkspec.np,
+ "renesas,cpg-mstp-clocks"))
+ goto found;
+
+ of_node_put(clkspec.np);
+ i++;
+ }
+
+ return 0;
+
+found:
+ clk = of_clk_get_from_provider(&clkspec);
+ of_node_put(clkspec.np);
+
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ error = pm_clk_create(dev);
+ if (error) {
+ dev_err(dev, "pm_clk_create failed %d\n", error);
+ goto fail_put;
+ }
+
+ error = pm_clk_add_clk(dev, clk);
+ if (error) {
+ dev_err(dev, "pm_clk_add_clk %pC failed %d\n", clk, error);
+ goto fail_destroy;
+ }
+
+ return 0;
+
+fail_destroy:
+ pm_clk_destroy(dev);
+fail_put:
+ clk_put(clk);
+ return error;
+}
+
+void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev)
+{
+ if (!list_empty(&dev->power.subsys_data->clock_list))
+ pm_clk_destroy(dev);
+}
+
+void __init cpg_mstp_add_clk_domain(struct device_node *np)
+{
+ struct generic_pm_domain *pd;
+ u32 ncells;
+
+ if (of_property_read_u32(np, "#power-domain-cells", &ncells)) {
+ pr_warn("%s lacks #power-domain-cells\n", np->full_name);
+ return;
+ }
+
+ pd = kzalloc(sizeof(*pd), GFP_KERNEL);
+ if (!pd)
+ return;
+
+ pd->name = np->name;
+
+ pd->flags = GENPD_FLAG_PM_CLK;
+ pm_genpd_init(pd, &simple_qos_governor, false);
+ pd->attach_dev = cpg_mstp_attach_dev;
+ pd->detach_dev = cpg_mstp_detach_dev;
+
+ of_genpd_add_provider_simple(np, pd);
+}
+#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */
diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
index 63a8159c4e64153d..cb19cc1865ca5cfb 100644
--- a/include/linux/clk/shmobile.h
+++ b/include/linux/clk/shmobile.h
@@ -16,8 +16,20 @@
#include <linux/types.h>
+struct device;
+struct device_node;
+struct generic_pm_domain;
+
void r8a7778_clocks_init(u32 mode);
void r8a7779_clocks_init(u32 mode);
void rcar_gen2_clocks_init(u32 mode);
+#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
+void cpg_mstp_add_clk_domain(struct device_node *np);
+int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev);
+void cpg_mstp_detach_dev(struct generic_pm_domain *domain, struct device *dev);
+#else
+static inline void cpg_mstp_add_clk_domain(struct device_node *np) {}
+#endif
+
#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 02/16] clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
2015-08-04 12:28 ` Geert Uytterhoeven
(?)
@ 2015-08-04 12:28 ` Geert Uytterhoeven
-1 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add Clock Domain support to the R-Car M1A Clock Pulse Generator (CPG)
driver using the generic PM Domain. This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Add Acked-by,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
.../bindings/clock/renesas,r8a7778-cpg-clocks.txt | 29 +++++++++++++++++++---
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/clk/shmobile/clk-r8a7778.c | 2 ++
3 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
index 2f3747fdcf1c5305..e4cdaf1cb3333012 100644
--- a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
@@ -1,7 +1,9 @@
* Renesas R8A7778 Clock Pulse Generator (CPG)
The CPG generates core clocks for the R8A7778. It includes two PLLs and
-several fixed ratio dividers
+several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
Required Properties:
@@ -10,10 +12,18 @@ Required Properties:
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are
"plla", "pllb", "b", "out", "p", "s", and "s1".
+ - #power-domain-cells: Must be 0
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
-Example
--------
+
+Examples
+--------
+
+ - CPG device node:
cpg_clocks: cpg_clocks@ffc80000 {
compatible = "renesas,r8a7778-cpg-clocks";
@@ -22,4 +32,17 @@ Example
clocks = <&extal_clk>;
clock-output-names = "plla", "pllb", "b",
"out", "p", "s", "s1";
+ #power-domain-cells = <0>;
+ };
+
+
+ - CPG/MSTP Clock Domain member device node:
+
+ sdhi0: sd@ffe4c000 {
+ compatible = "renesas,sdhi-r8a7778";
+ reg = <0xffe4c000 0x100>;
+ interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
};
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index aa38a438af8990ef..5b1f9eca7c871aee 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -4,6 +4,7 @@ config ARCH_SHMOBILE
config PM_RCAR
bool
+ select PM_GENERIC_DOMAINS if PM
config PM_RMOBILE
bool
diff --git a/drivers/clk/shmobile/clk-r8a7778.c b/drivers/clk/shmobile/clk-r8a7778.c
index e97e28fcfc13d102..87c1d2f2fb57a46c 100644
--- a/drivers/clk/shmobile/clk-r8a7778.c
+++ b/drivers/clk/shmobile/clk-r8a7778.c
@@ -124,6 +124,8 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np)
}
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+ cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks",
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 02/16] clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: linux-clk, linux-pm, linux-sh, linux-arm-kernel, devicetree,
linux-kernel, Geert Uytterhoeven
Add Clock Domain support to the R-Car M1A Clock Pulse Generator (CPG)
driver using the generic PM Domain. This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Add Acked-by,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
.../bindings/clock/renesas,r8a7778-cpg-clocks.txt | 29 +++++++++++++++++++---
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/clk/shmobile/clk-r8a7778.c | 2 ++
3 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
index 2f3747fdcf1c5305..e4cdaf1cb3333012 100644
--- a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
@@ -1,7 +1,9 @@
* Renesas R8A7778 Clock Pulse Generator (CPG)
The CPG generates core clocks for the R8A7778. It includes two PLLs and
-several fixed ratio dividers
+several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
Required Properties:
@@ -10,10 +12,18 @@ Required Properties:
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are
"plla", "pllb", "b", "out", "p", "s", and "s1".
+ - #power-domain-cells: Must be 0
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
-Example
--------
+
+Examples
+--------
+
+ - CPG device node:
cpg_clocks: cpg_clocks@ffc80000 {
compatible = "renesas,r8a7778-cpg-clocks";
@@ -22,4 +32,17 @@ Example
clocks = <&extal_clk>;
clock-output-names = "plla", "pllb", "b",
"out", "p", "s", "s1";
+ #power-domain-cells = <0>;
+ };
+
+
+ - CPG/MSTP Clock Domain member device node:
+
+ sdhi0: sd@ffe4c000 {
+ compatible = "renesas,sdhi-r8a7778";
+ reg = <0xffe4c000 0x100>;
+ interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
};
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index aa38a438af8990ef..5b1f9eca7c871aee 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -4,6 +4,7 @@ config ARCH_SHMOBILE
config PM_RCAR
bool
+ select PM_GENERIC_DOMAINS if PM
config PM_RMOBILE
bool
diff --git a/drivers/clk/shmobile/clk-r8a7778.c b/drivers/clk/shmobile/clk-r8a7778.c
index e97e28fcfc13d102..87c1d2f2fb57a46c 100644
--- a/drivers/clk/shmobile/clk-r8a7778.c
+++ b/drivers/clk/shmobile/clk-r8a7778.c
@@ -124,6 +124,8 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np)
}
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+ cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks",
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 02/16] clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add Clock Domain support to the R-Car M1A Clock Pulse Generator (CPG)
driver using the generic PM Domain. This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Add Acked-by,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
.../bindings/clock/renesas,r8a7778-cpg-clocks.txt | 29 +++++++++++++++++++---
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/clk/shmobile/clk-r8a7778.c | 2 ++
3 files changed, 29 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
index 2f3747fdcf1c5305..e4cdaf1cb3333012 100644
--- a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
@@ -1,7 +1,9 @@
* Renesas R8A7778 Clock Pulse Generator (CPG)
The CPG generates core clocks for the R8A7778. It includes two PLLs and
-several fixed ratio dividers
+several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
Required Properties:
@@ -10,10 +12,18 @@ Required Properties:
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are
"plla", "pllb", "b", "out", "p", "s", and "s1".
+ - #power-domain-cells: Must be 0
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
-Example
--------
+
+Examples
+--------
+
+ - CPG device node:
cpg_clocks: cpg_clocks at ffc80000 {
compatible = "renesas,r8a7778-cpg-clocks";
@@ -22,4 +32,17 @@ Example
clocks = <&extal_clk>;
clock-output-names = "plla", "pllb", "b",
"out", "p", "s", "s1";
+ #power-domain-cells = <0>;
+ };
+
+
+ - CPG/MSTP Clock Domain member device node:
+
+ sdhi0: sd at ffe4c000 {
+ compatible = "renesas,sdhi-r8a7778";
+ reg = <0xffe4c000 0x100>;
+ interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
};
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index aa38a438af8990ef..5b1f9eca7c871aee 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -4,6 +4,7 @@ config ARCH_SHMOBILE
config PM_RCAR
bool
+ select PM_GENERIC_DOMAINS if PM
config PM_RMOBILE
bool
diff --git a/drivers/clk/shmobile/clk-r8a7778.c b/drivers/clk/shmobile/clk-r8a7778.c
index e97e28fcfc13d102..87c1d2f2fb57a46c 100644
--- a/drivers/clk/shmobile/clk-r8a7778.c
+++ b/drivers/clk/shmobile/clk-r8a7778.c
@@ -124,6 +124,8 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np)
}
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+ cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks",
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 03/16] clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
2015-08-04 12:28 ` Geert Uytterhoeven
(?)
@ 2015-08-04 12:28 ` Geert Uytterhoeven
-1 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add Clock Domain support to the R-Car H1 Clock Pulse Generator (CPG)
driver using the generic PM Domain. This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Also update the reg property in the DT binding doc example to match the
actual dtsi, which uses #address-cells and #size-cells = 1, not 2.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Add Acked-by,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
.../bindings/clock/renesas,r8a7779-cpg-clocks.txt | 30 +++++++++++++++++++---
drivers/clk/shmobile/clk-r8a7779.c | 2 ++
2 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
index ed3c8cb12f4eb699..8c81547c29f568e8 100644
--- a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
@@ -1,7 +1,9 @@
* Renesas R8A7779 Clock Pulse Generator (CPG)
The CPG generates core clocks for the R8A7779. It includes one PLL and
-several fixed ratio dividers
+several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
Required Properties:
@@ -12,16 +14,36 @@ Required Properties:
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are "plla",
"z", "zs", "s", "s1", "p", "b", "out".
+ - #power-domain-cells: Must be 0
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
-Example
--------
+
+Examples
+--------
+
+ - CPG device node:
cpg_clocks: cpg_clocks@ffc80000 {
compatible = "renesas,r8a7779-cpg-clocks";
- reg = <0 0xffc80000 0 0x30>;
+ reg = <0xffc80000 0x30>;
clocks = <&extal_clk>;
#clock-cells = <1>;
clock-output-names = "plla", "z", "zs", "s", "s1", "p",
"b", "out";
+ #power-domain-cells = <0>;
+ };
+
+
+ - CPG/MSTP Clock Domain member device node:
+
+ sata: sata@fc600000 {
+ compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
+ reg = <0xfc600000 0x2000>;
+ interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp1_clks R8A7779_CLK_SATA>;
+ power-domains = <&cpg_clocks>;
};
diff --git a/drivers/clk/shmobile/clk-r8a7779.c b/drivers/clk/shmobile/clk-r8a7779.c
index af297963489f473d..92275c5f2c60303e 100644
--- a/drivers/clk/shmobile/clk-r8a7779.c
+++ b/drivers/clk/shmobile/clk-r8a7779.c
@@ -168,6 +168,8 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np)
}
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+ cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
r8a7779_cpg_clocks_init);
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 03/16] clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: linux-clk, linux-pm, linux-sh, linux-arm-kernel, devicetree,
linux-kernel, Geert Uytterhoeven
Add Clock Domain support to the R-Car H1 Clock Pulse Generator (CPG)
driver using the generic PM Domain. This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Also update the reg property in the DT binding doc example to match the
actual dtsi, which uses #address-cells and #size-cells == 1, not 2.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Add Acked-by,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
.../bindings/clock/renesas,r8a7779-cpg-clocks.txt | 30 +++++++++++++++++++---
drivers/clk/shmobile/clk-r8a7779.c | 2 ++
2 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
index ed3c8cb12f4eb699..8c81547c29f568e8 100644
--- a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
@@ -1,7 +1,9 @@
* Renesas R8A7779 Clock Pulse Generator (CPG)
The CPG generates core clocks for the R8A7779. It includes one PLL and
-several fixed ratio dividers
+several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
Required Properties:
@@ -12,16 +14,36 @@ Required Properties:
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are "plla",
"z", "zs", "s", "s1", "p", "b", "out".
+ - #power-domain-cells: Must be 0
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
-Example
--------
+
+Examples
+--------
+
+ - CPG device node:
cpg_clocks: cpg_clocks@ffc80000 {
compatible = "renesas,r8a7779-cpg-clocks";
- reg = <0 0xffc80000 0 0x30>;
+ reg = <0xffc80000 0x30>;
clocks = <&extal_clk>;
#clock-cells = <1>;
clock-output-names = "plla", "z", "zs", "s", "s1", "p",
"b", "out";
+ #power-domain-cells = <0>;
+ };
+
+
+ - CPG/MSTP Clock Domain member device node:
+
+ sata: sata@fc600000 {
+ compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
+ reg = <0xfc600000 0x2000>;
+ interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp1_clks R8A7779_CLK_SATA>;
+ power-domains = <&cpg_clocks>;
};
diff --git a/drivers/clk/shmobile/clk-r8a7779.c b/drivers/clk/shmobile/clk-r8a7779.c
index af297963489f473d..92275c5f2c60303e 100644
--- a/drivers/clk/shmobile/clk-r8a7779.c
+++ b/drivers/clk/shmobile/clk-r8a7779.c
@@ -168,6 +168,8 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np)
}
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+ cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
r8a7779_cpg_clocks_init);
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 03/16] clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add Clock Domain support to the R-Car H1 Clock Pulse Generator (CPG)
driver using the generic PM Domain. This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Also update the reg property in the DT binding doc example to match the
actual dtsi, which uses #address-cells and #size-cells == 1, not 2.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Add Acked-by,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
.../bindings/clock/renesas,r8a7779-cpg-clocks.txt | 30 +++++++++++++++++++---
drivers/clk/shmobile/clk-r8a7779.c | 2 ++
2 files changed, 28 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
index ed3c8cb12f4eb699..8c81547c29f568e8 100644
--- a/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a7779-cpg-clocks.txt
@@ -1,7 +1,9 @@
* Renesas R8A7779 Clock Pulse Generator (CPG)
The CPG generates core clocks for the R8A7779. It includes one PLL and
-several fixed ratio dividers
+several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
Required Properties:
@@ -12,16 +14,36 @@ Required Properties:
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are "plla",
"z", "zs", "s", "s1", "p", "b", "out".
+ - #power-domain-cells: Must be 0
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
-Example
--------
+
+Examples
+--------
+
+ - CPG device node:
cpg_clocks: cpg_clocks at ffc80000 {
compatible = "renesas,r8a7779-cpg-clocks";
- reg = <0 0xffc80000 0 0x30>;
+ reg = <0xffc80000 0x30>;
clocks = <&extal_clk>;
#clock-cells = <1>;
clock-output-names = "plla", "z", "zs", "s", "s1", "p",
"b", "out";
+ #power-domain-cells = <0>;
+ };
+
+
+ - CPG/MSTP Clock Domain member device node:
+
+ sata: sata at fc600000 {
+ compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
+ reg = <0xfc600000 0x2000>;
+ interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp1_clks R8A7779_CLK_SATA>;
+ power-domains = <&cpg_clocks>;
};
diff --git a/drivers/clk/shmobile/clk-r8a7779.c b/drivers/clk/shmobile/clk-r8a7779.c
index af297963489f473d..92275c5f2c60303e 100644
--- a/drivers/clk/shmobile/clk-r8a7779.c
+++ b/drivers/clk/shmobile/clk-r8a7779.c
@@ -168,6 +168,8 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np)
}
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+ cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(r8a7779_cpg_clks, "renesas,r8a7779-cpg-clocks",
r8a7779_cpg_clocks_init);
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 04/16] clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
2015-08-04 12:28 ` Geert Uytterhoeven
(?)
@ 2015-08-04 12:28 ` Geert Uytterhoeven
-1 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG)
driver using the generic PM Domain. This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Add Acked-by,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- Add Acked-by and Reviewed-by,
- Move core CPG Clock Domain code from the R-Car Gen2 driver to the
CPG MSTP Clocks driver, as it's generic, and can be used on other
Renesas SoCs that have a CPG/MSTP block,
- Scan for an MSTP clock instead of using the first clock tied to the
device (con_id NULL),
- Extract R-Car Gen2 specifics from "[PATCH/RFC 1/5] clk: shmobile:
rcar-gen2: Add CPG Clock Domain support" into this patch.
---
.../clock/renesas,rcar-gen2-cpg-clocks.txt | 26 ++++++++++++++++++++--
drivers/clk/shmobile/clk-rcar-gen2.c | 2 ++
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
index 56f111bd3e456619..2a9a8edc8f3547b0 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
@@ -2,6 +2,8 @@
The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
and several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
Required Properties:
@@ -20,10 +22,18 @@ Required Properties:
- clock-output-names: The names of the clocks. Supported clocks are "main",
"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
"adsp"
+ - #power-domain-cells: Must be 0
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
-Example
--------
+
+Examples
+--------
+
+ - CPG device node:
cpg_clocks: cpg_clocks@e6150000 {
compatible = "renesas,r8a7790-cpg-clocks",
@@ -34,4 +44,16 @@ Example
clock-output-names = "main", "pll0, "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "sd1", "z",
"rcan", "adsp";
+ #power-domain-cells = <0>;
+ };
+
+
+ - CPG/MSTP Clock Domain member device node:
+
+ thermal@e61f0000 {
+ compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
+ reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+ interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
+ power-domains = <&cpg_clocks>;
};
diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c
index 9233ebf8cc49f933..745496f7ee9c7402 100644
--- a/drivers/clk/shmobile/clk-rcar-gen2.c
+++ b/drivers/clk/shmobile/clk-rcar-gen2.c
@@ -415,6 +415,8 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
}
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+ cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
rcar_gen2_cpg_clocks_init);
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 04/16] clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: linux-clk, linux-pm, linux-sh, linux-arm-kernel, devicetree,
linux-kernel, Geert Uytterhoeven
Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG)
driver using the generic PM Domain. This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Add Acked-by,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- Add Acked-by and Reviewed-by,
- Move core CPG Clock Domain code from the R-Car Gen2 driver to the
CPG MSTP Clocks driver, as it's generic, and can be used on other
Renesas SoCs that have a CPG/MSTP block,
- Scan for an MSTP clock instead of using the first clock tied to the
device (con_id NULL),
- Extract R-Car Gen2 specifics from "[PATCH/RFC 1/5] clk: shmobile:
rcar-gen2: Add CPG Clock Domain support" into this patch.
---
.../clock/renesas,rcar-gen2-cpg-clocks.txt | 26 ++++++++++++++++++++--
drivers/clk/shmobile/clk-rcar-gen2.c | 2 ++
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
index 56f111bd3e456619..2a9a8edc8f3547b0 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
@@ -2,6 +2,8 @@
The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
and several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
Required Properties:
@@ -20,10 +22,18 @@ Required Properties:
- clock-output-names: The names of the clocks. Supported clocks are "main",
"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
"adsp"
+ - #power-domain-cells: Must be 0
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
-Example
--------
+
+Examples
+--------
+
+ - CPG device node:
cpg_clocks: cpg_clocks@e6150000 {
compatible = "renesas,r8a7790-cpg-clocks",
@@ -34,4 +44,16 @@ Example
clock-output-names = "main", "pll0, "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "sd1", "z",
"rcan", "adsp";
+ #power-domain-cells = <0>;
+ };
+
+
+ - CPG/MSTP Clock Domain member device node:
+
+ thermal@e61f0000 {
+ compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
+ reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+ interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
+ power-domains = <&cpg_clocks>;
};
diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c
index 9233ebf8cc49f933..745496f7ee9c7402 100644
--- a/drivers/clk/shmobile/clk-rcar-gen2.c
+++ b/drivers/clk/shmobile/clk-rcar-gen2.c
@@ -415,6 +415,8 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
}
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+ cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
rcar_gen2_cpg_clocks_init);
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 04/16] clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG)
driver using the generic PM Domain. This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Add Acked-by,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- Add Acked-by and Reviewed-by,
- Move core CPG Clock Domain code from the R-Car Gen2 driver to the
CPG MSTP Clocks driver, as it's generic, and can be used on other
Renesas SoCs that have a CPG/MSTP block,
- Scan for an MSTP clock instead of using the first clock tied to the
device (con_id NULL),
- Extract R-Car Gen2 specifics from "[PATCH/RFC 1/5] clk: shmobile:
rcar-gen2: Add CPG Clock Domain support" into this patch.
---
.../clock/renesas,rcar-gen2-cpg-clocks.txt | 26 ++++++++++++++++++++--
drivers/clk/shmobile/clk-rcar-gen2.c | 2 ++
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
index 56f111bd3e456619..2a9a8edc8f3547b0 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
@@ -2,6 +2,8 @@
The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
and several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
Required Properties:
@@ -20,10 +22,18 @@ Required Properties:
- clock-output-names: The names of the clocks. Supported clocks are "main",
"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
"adsp"
+ - #power-domain-cells: Must be 0
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
-Example
--------
+
+Examples
+--------
+
+ - CPG device node:
cpg_clocks: cpg_clocks at e6150000 {
compatible = "renesas,r8a7790-cpg-clocks",
@@ -34,4 +44,16 @@ Example
clock-output-names = "main", "pll0, "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "sd1", "z",
"rcan", "adsp";
+ #power-domain-cells = <0>;
+ };
+
+
+ - CPG/MSTP Clock Domain member device node:
+
+ thermal at e61f0000 {
+ compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
+ reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+ interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
+ power-domains = <&cpg_clocks>;
};
diff --git a/drivers/clk/shmobile/clk-rcar-gen2.c b/drivers/clk/shmobile/clk-rcar-gen2.c
index 9233ebf8cc49f933..745496f7ee9c7402 100644
--- a/drivers/clk/shmobile/clk-rcar-gen2.c
+++ b/drivers/clk/shmobile/clk-rcar-gen2.c
@@ -415,6 +415,8 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
}
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+ cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(rcar_gen2_cpg_clks, "renesas,rcar-gen2-cpg-clocks",
rcar_gen2_cpg_clocks_init);
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 05/16] clk: shmobile: rz: Add CPG/MSTP Clock Domain support
2015-08-04 12:28 ` Geert Uytterhoeven
(?)
(?)
@ 2015-08-04 12:28 ` Geert Uytterhoeven
-1 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add Clock Domain support to the RZ Clock Pulse Generator (CPG) driver
using the generic PM Domain. This allows to power-manage the module
clocks of SoC devices that are part of the CPG/MSTP Clock Domain using
Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Add Acked-by,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
.../bindings/clock/renesas,rz-cpg-clocks.txt | 29 ++++++++++++++++++++--
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/clk/shmobile/clk-rz.c | 3 +++
3 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
index b0f7ddb8cdb13750..bb51a33a1fbfbc97 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
@@ -2,6 +2,8 @@
The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
CPU and GPU clocks, and several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
Required Properties:
@@ -14,10 +16,18 @@ Required Properties:
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are "pll",
"i", and "g"
+ - #power-domain-cells: Must be 0
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
-Example
--------
+
+Examples
+--------
+
+ - CPG device node:
cpg_clocks: cpg_clocks@fcfe0000 {
#clock-cells = <1>;
@@ -26,4 +36,19 @@ Example
reg = <0xfcfe0000 0x18>;
clocks = <&extal_clk>, <&usb_x1_clk>;
clock-output-names = "pll", "i", "g";
+ #power-domain-cells = <0>;
+ };
+
+
+ - CPG/MSTP Clock Domain member device node:
+
+ mtu2: timer@fcff0000 {
+ compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
+ reg = <0xfcff0000 0x400>;
+ interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tgi0a";
+ clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
};
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 5b1f9eca7c871aee..926e336d6aeb7181 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -51,6 +51,7 @@ config ARCH_EMEV2
config ARCH_R7S72100
bool "RZ/A1H (R7S72100)"
+ select PM_GENERIC_DOMAINS if PM
select SYS_SUPPORTS_SH_MTU2
config ARCH_R8A73A4
diff --git a/drivers/clk/shmobile/clk-rz.c b/drivers/clk/shmobile/clk-rz.c
index 7e68e86309625c9e..9766e3cb595fd257 100644
--- a/drivers/clk/shmobile/clk-rz.c
+++ b/drivers/clk/shmobile/clk-rz.c
@@ -10,6 +10,7 @@
*/
#include <linux/clk-provider.h>
+#include <linux/clk/shmobile.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
@@ -99,5 +100,7 @@ static void __init rz_cpg_clocks_init(struct device_node *np)
}
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+ cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 05/16] clk: shmobile: rz: Add CPG/MSTP Clock Domain support
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: linux-clk, linux-pm, linux-sh, linux-arm-kernel, devicetree,
linux-kernel, Geert Uytterhoeven
Add Clock Domain support to the RZ Clock Pulse Generator (CPG) driver
using the generic PM Domain. This allows to power-manage the module
clocks of SoC devices that are part of the CPG/MSTP Clock Domain using
Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Add Acked-by,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
.../bindings/clock/renesas,rz-cpg-clocks.txt | 29 ++++++++++++++++++++--
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/clk/shmobile/clk-rz.c | 3 +++
3 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
index b0f7ddb8cdb13750..bb51a33a1fbfbc97 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
@@ -2,6 +2,8 @@
The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
CPU and GPU clocks, and several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
Required Properties:
@@ -14,10 +16,18 @@ Required Properties:
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are "pll",
"i", and "g"
+ - #power-domain-cells: Must be 0
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
-Example
--------
+
+Examples
+--------
+
+ - CPG device node:
cpg_clocks: cpg_clocks@fcfe0000 {
#clock-cells = <1>;
@@ -26,4 +36,19 @@ Example
reg = <0xfcfe0000 0x18>;
clocks = <&extal_clk>, <&usb_x1_clk>;
clock-output-names = "pll", "i", "g";
+ #power-domain-cells = <0>;
+ };
+
+
+ - CPG/MSTP Clock Domain member device node:
+
+ mtu2: timer@fcff0000 {
+ compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
+ reg = <0xfcff0000 0x400>;
+ interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tgi0a";
+ clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
};
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 5b1f9eca7c871aee..926e336d6aeb7181 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -51,6 +51,7 @@ config ARCH_EMEV2
config ARCH_R7S72100
bool "RZ/A1H (R7S72100)"
+ select PM_GENERIC_DOMAINS if PM
select SYS_SUPPORTS_SH_MTU2
config ARCH_R8A73A4
diff --git a/drivers/clk/shmobile/clk-rz.c b/drivers/clk/shmobile/clk-rz.c
index 7e68e86309625c9e..9766e3cb595fd257 100644
--- a/drivers/clk/shmobile/clk-rz.c
+++ b/drivers/clk/shmobile/clk-rz.c
@@ -10,6 +10,7 @@
*/
#include <linux/clk-provider.h>
+#include <linux/clk/shmobile.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
@@ -99,5 +100,7 @@ static void __init rz_cpg_clocks_init(struct device_node *np)
}
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+ cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 05/16] clk: shmobile: rz: Add CPG/MSTP Clock Domain support
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA, linux-sh-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Geert Uytterhoeven
Add Clock Domain support to the RZ Clock Pulse Generator (CPG) driver
using the generic PM Domain. This allows to power-manage the module
clocks of SoC devices that are part of the CPG/MSTP Clock Domain using
Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
Acked-by: Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Reviewed-by: Ulf Hansson <ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
v4:
- Add Reviewed-by,
v3:
- Add Acked-by,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
.../bindings/clock/renesas,rz-cpg-clocks.txt | 29 ++++++++++++++++++++--
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/clk/shmobile/clk-rz.c | 3 +++
3 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
index b0f7ddb8cdb13750..bb51a33a1fbfbc97 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
@@ -2,6 +2,8 @@
The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
CPU and GPU clocks, and several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
Required Properties:
@@ -14,10 +16,18 @@ Required Properties:
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are "pll",
"i", and "g"
+ - #power-domain-cells: Must be 0
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
-Example
--------
+
+Examples
+--------
+
+ - CPG device node:
cpg_clocks: cpg_clocks@fcfe0000 {
#clock-cells = <1>;
@@ -26,4 +36,19 @@ Example
reg = <0xfcfe0000 0x18>;
clocks = <&extal_clk>, <&usb_x1_clk>;
clock-output-names = "pll", "i", "g";
+ #power-domain-cells = <0>;
+ };
+
+
+ - CPG/MSTP Clock Domain member device node:
+
+ mtu2: timer@fcff0000 {
+ compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
+ reg = <0xfcff0000 0x400>;
+ interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tgi0a";
+ clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
};
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 5b1f9eca7c871aee..926e336d6aeb7181 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -51,6 +51,7 @@ config ARCH_EMEV2
config ARCH_R7S72100
bool "RZ/A1H (R7S72100)"
+ select PM_GENERIC_DOMAINS if PM
select SYS_SUPPORTS_SH_MTU2
config ARCH_R8A73A4
diff --git a/drivers/clk/shmobile/clk-rz.c b/drivers/clk/shmobile/clk-rz.c
index 7e68e86309625c9e..9766e3cb595fd257 100644
--- a/drivers/clk/shmobile/clk-rz.c
+++ b/drivers/clk/shmobile/clk-rz.c
@@ -10,6 +10,7 @@
*/
#include <linux/clk-provider.h>
+#include <linux/clk/shmobile.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
@@ -99,5 +100,7 @@ static void __init rz_cpg_clocks_init(struct device_node *np)
}
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+ cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 05/16] clk: shmobile: rz: Add CPG/MSTP Clock Domain support
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add Clock Domain support to the RZ Clock Pulse Generator (CPG) driver
using the generic PM Domain. This allows to power-manage the module
clocks of SoC devices that are part of the CPG/MSTP Clock Domain using
Runtime PM, or for system suspend/resume.
SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Add Acked-by,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
.../bindings/clock/renesas,rz-cpg-clocks.txt | 29 ++++++++++++++++++++--
arch/arm/mach-shmobile/Kconfig | 1 +
drivers/clk/shmobile/clk-rz.c | 3 +++
3 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
index b0f7ddb8cdb13750..bb51a33a1fbfbc97 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
@@ -2,6 +2,8 @@
The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
CPU and GPU clocks, and several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
Required Properties:
@@ -14,10 +16,18 @@ Required Properties:
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are "pll",
"i", and "g"
+ - #power-domain-cells: Must be 0
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
-Example
--------
+
+Examples
+--------
+
+ - CPG device node:
cpg_clocks: cpg_clocks at fcfe0000 {
#clock-cells = <1>;
@@ -26,4 +36,19 @@ Example
reg = <0xfcfe0000 0x18>;
clocks = <&extal_clk>, <&usb_x1_clk>;
clock-output-names = "pll", "i", "g";
+ #power-domain-cells = <0>;
+ };
+
+
+ - CPG/MSTP Clock Domain member device node:
+
+ mtu2: timer at fcff0000 {
+ compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
+ reg = <0xfcff0000 0x400>;
+ interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tgi0a";
+ clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
};
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 5b1f9eca7c871aee..926e336d6aeb7181 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -51,6 +51,7 @@ config ARCH_EMEV2
config ARCH_R7S72100
bool "RZ/A1H (R7S72100)"
+ select PM_GENERIC_DOMAINS if PM
select SYS_SUPPORTS_SH_MTU2
config ARCH_R8A73A4
diff --git a/drivers/clk/shmobile/clk-rz.c b/drivers/clk/shmobile/clk-rz.c
index 7e68e86309625c9e..9766e3cb595fd257 100644
--- a/drivers/clk/shmobile/clk-rz.c
+++ b/drivers/clk/shmobile/clk-rz.c
@@ -10,6 +10,7 @@
*/
#include <linux/clk-provider.h>
+#include <linux/clk/shmobile.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
@@ -99,5 +100,7 @@ static void __init rz_cpg_clocks_init(struct device_node *np)
}
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
+
+ cpg_mstp_add_clk_domain(np);
}
CLK_OF_DECLARE(rz_cpg_clks, "renesas,rz-cpg-clocks", rz_cpg_clocks_init);
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 06/16] ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
2015-08-04 12:28 ` Geert Uytterhoeven
(?)
@ 2015-08-04 12:28 ` Geert Uytterhoeven
-1 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
arch/arm/boot/dts/r7s72100.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 277e73c110e5d40c..060c32cbd66923ed 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -86,6 +86,7 @@
reg = <0xfcfe0000 0x18>;
clocks = <&extal_clk>, <&usb_x1_clk>;
clock-output-names = "pll", "i", "g";
+ #power-domain-cells = <0>;
};
/* MSTP clocks */
@@ -157,6 +158,7 @@
<0 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -169,6 +171,7 @@
<0 193 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -181,6 +184,7 @@
<0 197 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -193,6 +197,7 @@
<0 201 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -205,6 +210,7 @@
<0 205 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -217,6 +223,7 @@
<0 209 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -229,6 +236,7 @@
<0 213 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -241,6 +249,7 @@
<0 217 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -252,6 +261,7 @@
<0 240 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -266,6 +276,7 @@
<0 243 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -280,6 +291,7 @@
<0 246 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -294,6 +306,7 @@
<0 249 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -308,6 +321,7 @@
<0 252 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -338,6 +352,7 @@
<0 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
clock-frequency = <100000>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -356,6 +371,7 @@
<0 172 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
clock-frequency = <100000>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -374,6 +390,7 @@
<0 180 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
clock-frequency = <100000>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -392,6 +409,7 @@
<0 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
clock-frequency = <100000>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -402,6 +420,7 @@
interrupt-names = "tgi0a";
clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 06/16] ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: linux-clk, linux-pm, linux-sh, linux-arm-kernel, devicetree,
linux-kernel, Geert Uytterhoeven
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
arch/arm/boot/dts/r7s72100.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 277e73c110e5d40c..060c32cbd66923ed 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -86,6 +86,7 @@
reg = <0xfcfe0000 0x18>;
clocks = <&extal_clk>, <&usb_x1_clk>;
clock-output-names = "pll", "i", "g";
+ #power-domain-cells = <0>;
};
/* MSTP clocks */
@@ -157,6 +158,7 @@
<0 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -169,6 +171,7 @@
<0 193 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -181,6 +184,7 @@
<0 197 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -193,6 +197,7 @@
<0 201 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -205,6 +210,7 @@
<0 205 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -217,6 +223,7 @@
<0 209 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -229,6 +236,7 @@
<0 213 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -241,6 +249,7 @@
<0 217 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -252,6 +261,7 @@
<0 240 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -266,6 +276,7 @@
<0 243 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -280,6 +291,7 @@
<0 246 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -294,6 +306,7 @@
<0 249 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -308,6 +321,7 @@
<0 252 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -338,6 +352,7 @@
<0 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
clock-frequency = <100000>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -356,6 +371,7 @@
<0 172 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
clock-frequency = <100000>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -374,6 +390,7 @@
<0 180 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
clock-frequency = <100000>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -392,6 +409,7 @@
<0 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
clock-frequency = <100000>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -402,6 +420,7 @@
interrupt-names = "tgi0a";
clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 06/16] ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
arch/arm/boot/dts/r7s72100.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 277e73c110e5d40c..060c32cbd66923ed 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -86,6 +86,7 @@
reg = <0xfcfe0000 0x18>;
clocks = <&extal_clk>, <&usb_x1_clk>;
clock-output-names = "pll", "i", "g";
+ #power-domain-cells = <0>;
};
/* MSTP clocks */
@@ -157,6 +158,7 @@
<0 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -169,6 +171,7 @@
<0 193 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -181,6 +184,7 @@
<0 197 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -193,6 +197,7 @@
<0 201 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -205,6 +210,7 @@
<0 205 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -217,6 +223,7 @@
<0 209 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -229,6 +236,7 @@
<0 213 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -241,6 +249,7 @@
<0 217 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -252,6 +261,7 @@
<0 240 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -266,6 +276,7 @@
<0 243 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -280,6 +291,7 @@
<0 246 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -294,6 +306,7 @@
<0 249 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -308,6 +321,7 @@
<0 252 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -338,6 +352,7 @@
<0 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
clock-frequency = <100000>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -356,6 +371,7 @@
<0 172 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
clock-frequency = <100000>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -374,6 +390,7 @@
<0 180 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
clock-frequency = <100000>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -392,6 +409,7 @@
<0 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
clock-frequency = <100000>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -402,6 +420,7 @@
interrupt-names = "tgi0a";
clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 07/16] ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
2015-08-04 12:28 ` Geert Uytterhoeven
(?)
(?)
@ 2015-08-04 12:28 ` Geert Uytterhoeven
-1 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node. A notable
exception is the "sound" node, which represents multiple SoC devices,
each having their own MSTP clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
arch/arm/boot/dts/r8a7778.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 7ce9f5fd586504f2..4b1fa9f42ad5457b 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -53,6 +53,7 @@
reg = <0xfde00000 0x400>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
+ power-domains = <&cpg_clocks>;
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
@@ -152,6 +153,7 @@
reg = <0xffc70000 0x1000>;
interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -162,6 +164,7 @@
reg = <0xffc71000 0x1000>;
interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -172,6 +175,7 @@
reg = <0xffc72000 0x1000>;
interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -182,6 +186,7 @@
reg = <0xffc73000 0x1000>;
interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -193,6 +198,7 @@
<0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -207,6 +213,7 @@
<0 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -221,6 +228,7 @@
<0 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -288,6 +296,7 @@
interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -297,6 +306,7 @@
interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -306,6 +316,7 @@
interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -315,6 +326,7 @@
interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -324,6 +336,7 @@
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -333,6 +346,7 @@
interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -341,6 +355,7 @@
reg = <0xffe4e000 0x100>;
interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_MMC>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -349,6 +364,7 @@
reg = <0xffe4c000 0x100>;
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -357,6 +373,7 @@
reg = <0xffe4d000 0x100>;
interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -365,6 +382,7 @@
reg = <0xffe4f000 0x100>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -373,6 +391,7 @@
reg = <0xfffc7000 0x18>;
interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -383,6 +402,7 @@
reg = <0xfffc8000 0x18>;
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -393,6 +413,7 @@
reg = <0xfffc6000 0x18>;
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -419,6 +440,7 @@
clocks = <&extal_clk>;
clock-output-names = "plla", "pllb", "b",
"out", "p", "s", "s1";
+ #power-domain-cells = <0>;
};
/* Audio clocks; frequencies are set by boards if applicable. */
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 07/16] ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: linux-clk, linux-pm, linux-sh, linux-arm-kernel, devicetree,
linux-kernel, Geert Uytterhoeven
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node. A notable
exception is the "sound" node, which represents multiple SoC devices,
each having their own MSTP clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
arch/arm/boot/dts/r8a7778.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 7ce9f5fd586504f2..4b1fa9f42ad5457b 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -53,6 +53,7 @@
reg = <0xfde00000 0x400>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
+ power-domains = <&cpg_clocks>;
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
@@ -152,6 +153,7 @@
reg = <0xffc70000 0x1000>;
interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -162,6 +164,7 @@
reg = <0xffc71000 0x1000>;
interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -172,6 +175,7 @@
reg = <0xffc72000 0x1000>;
interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -182,6 +186,7 @@
reg = <0xffc73000 0x1000>;
interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -193,6 +198,7 @@
<0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -207,6 +213,7 @@
<0 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -221,6 +228,7 @@
<0 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -288,6 +296,7 @@
interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -297,6 +306,7 @@
interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -306,6 +316,7 @@
interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -315,6 +326,7 @@
interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -324,6 +336,7 @@
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -333,6 +346,7 @@
interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -341,6 +355,7 @@
reg = <0xffe4e000 0x100>;
interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_MMC>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -349,6 +364,7 @@
reg = <0xffe4c000 0x100>;
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -357,6 +373,7 @@
reg = <0xffe4d000 0x100>;
interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -365,6 +382,7 @@
reg = <0xffe4f000 0x100>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -373,6 +391,7 @@
reg = <0xfffc7000 0x18>;
interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -383,6 +402,7 @@
reg = <0xfffc8000 0x18>;
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -393,6 +413,7 @@
reg = <0xfffc6000 0x18>;
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -419,6 +440,7 @@
clocks = <&extal_clk>;
clock-output-names = "plla", "pllb", "b",
"out", "p", "s", "s1";
+ #power-domain-cells = <0>;
};
/* Audio clocks; frequencies are set by boards if applicable. */
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 07/16] ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: devicetree, Geert Uytterhoeven, linux-sh, linux-pm, linux-kernel,
linux-clk, linux-arm-kernel
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node. A notable
exception is the "sound" node, which represents multiple SoC devices,
each having their own MSTP clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
arch/arm/boot/dts/r8a7778.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 7ce9f5fd586504f2..4b1fa9f42ad5457b 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -53,6 +53,7 @@
reg = <0xfde00000 0x400>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
+ power-domains = <&cpg_clocks>;
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
@@ -152,6 +153,7 @@
reg = <0xffc70000 0x1000>;
interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -162,6 +164,7 @@
reg = <0xffc71000 0x1000>;
interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -172,6 +175,7 @@
reg = <0xffc72000 0x1000>;
interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -182,6 +186,7 @@
reg = <0xffc73000 0x1000>;
interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -193,6 +198,7 @@
<0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -207,6 +213,7 @@
<0 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -221,6 +228,7 @@
<0 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -288,6 +296,7 @@
interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -297,6 +306,7 @@
interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -306,6 +316,7 @@
interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -315,6 +326,7 @@
interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -324,6 +336,7 @@
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -333,6 +346,7 @@
interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -341,6 +355,7 @@
reg = <0xffe4e000 0x100>;
interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_MMC>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -349,6 +364,7 @@
reg = <0xffe4c000 0x100>;
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -357,6 +373,7 @@
reg = <0xffe4d000 0x100>;
interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -365,6 +382,7 @@
reg = <0xffe4f000 0x100>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -373,6 +391,7 @@
reg = <0xfffc7000 0x18>;
interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -383,6 +402,7 @@
reg = <0xfffc8000 0x18>;
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -393,6 +413,7 @@
reg = <0xfffc6000 0x18>;
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -419,6 +440,7 @@
clocks = <&extal_clk>;
clock-output-names = "plla", "pllb", "b",
"out", "p", "s", "s1";
+ #power-domain-cells = <0>;
};
/* Audio clocks; frequencies are set by boards if applicable. */
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 07/16] ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node. A notable
exception is the "sound" node, which represents multiple SoC devices,
each having their own MSTP clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
arch/arm/boot/dts/r8a7778.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 7ce9f5fd586504f2..4b1fa9f42ad5457b 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -53,6 +53,7 @@
reg = <0xfde00000 0x400>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
+ power-domains = <&cpg_clocks>;
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
@@ -152,6 +153,7 @@
reg = <0xffc70000 0x1000>;
interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -162,6 +164,7 @@
reg = <0xffc71000 0x1000>;
interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -172,6 +175,7 @@
reg = <0xffc72000 0x1000>;
interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -182,6 +186,7 @@
reg = <0xffc73000 0x1000>;
interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -193,6 +198,7 @@
<0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -207,6 +213,7 @@
<0 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -221,6 +228,7 @@
<0 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -288,6 +296,7 @@
interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -297,6 +306,7 @@
interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -306,6 +316,7 @@
interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -315,6 +326,7 @@
interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -324,6 +336,7 @@
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -333,6 +346,7 @@
interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -341,6 +355,7 @@
reg = <0xffe4e000 0x100>;
interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_MMC>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -349,6 +364,7 @@
reg = <0xffe4c000 0x100>;
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -357,6 +373,7 @@
reg = <0xffe4d000 0x100>;
interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -365,6 +382,7 @@
reg = <0xffe4f000 0x100>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -373,6 +391,7 @@
reg = <0xfffc7000 0x18>;
interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -383,6 +402,7 @@
reg = <0xfffc8000 0x18>;
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -393,6 +413,7 @@
reg = <0xfffc6000 0x18>;
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -419,6 +440,7 @@
clocks = <&extal_clk>;
clock-output-names = "plla", "pllb", "b",
"out", "p", "s", "s1";
+ #power-domain-cells = <0>;
};
/* Audio clocks; frequencies are set by boards if applicable. */
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 08/16] ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
2015-08-04 12:28 ` Geert Uytterhoeven
(?)
@ 2015-08-04 12:28 ` Geert Uytterhoeven
-1 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
arch/arm/boot/dts/r8a7779.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index a2b5430d32575f99..6afa909865b52b71 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -173,6 +173,7 @@
reg = <0xffc70000 0x1000>;
interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -183,6 +184,7 @@
reg = <0xffc71000 0x1000>;
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -193,6 +195,7 @@
reg = <0xffc72000 0x1000>;
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -203,6 +206,7 @@
reg = <0xffc73000 0x1000>;
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -212,6 +216,7 @@
interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF0>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -221,6 +226,7 @@
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF1>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -230,6 +236,7 @@
interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF2>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -239,6 +246,7 @@
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF3>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -248,6 +256,7 @@
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF4>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -257,6 +266,7 @@
interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF5>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -278,6 +288,7 @@
<0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -292,6 +303,7 @@
<0 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -306,6 +318,7 @@
<0 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -317,6 +330,7 @@
reg = <0xfc600000 0x2000>;
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_SATA>;
+ power-domains = <&cpg_clocks>;
};
sdhi0: sd@ffe4c000 {
@@ -324,6 +338,7 @@
reg = <0xffe4c000 0x100>;
interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -332,6 +347,7 @@
reg = <0xffe4d000 0x100>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -340,6 +356,7 @@
reg = <0xffe4e000 0x100>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -348,6 +365,7 @@
reg = <0xffe4f000 0x100>;
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -358,6 +376,7 @@
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -368,6 +387,7 @@
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -378,6 +398,7 @@
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -386,6 +407,7 @@
reg = <0 0xfff80000 0 0x40000>;
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_DU>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
ports {
@@ -427,6 +449,7 @@
#clock-cells = <1>;
clock-output-names = "plla", "z", "zs", "s",
"s1", "p", "b", "out";
+ #power-domain-cells = <0>;
};
/* Fixed factor clocks */
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 08/16] ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: linux-clk, linux-pm, linux-sh, linux-arm-kernel, devicetree,
linux-kernel, Geert Uytterhoeven
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
arch/arm/boot/dts/r8a7779.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index a2b5430d32575f99..6afa909865b52b71 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -173,6 +173,7 @@
reg = <0xffc70000 0x1000>;
interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -183,6 +184,7 @@
reg = <0xffc71000 0x1000>;
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -193,6 +195,7 @@
reg = <0xffc72000 0x1000>;
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -203,6 +206,7 @@
reg = <0xffc73000 0x1000>;
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -212,6 +216,7 @@
interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF0>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -221,6 +226,7 @@
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF1>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -230,6 +236,7 @@
interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF2>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -239,6 +246,7 @@
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF3>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -248,6 +256,7 @@
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF4>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -257,6 +266,7 @@
interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF5>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -278,6 +288,7 @@
<0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -292,6 +303,7 @@
<0 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -306,6 +318,7 @@
<0 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -317,6 +330,7 @@
reg = <0xfc600000 0x2000>;
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_SATA>;
+ power-domains = <&cpg_clocks>;
};
sdhi0: sd@ffe4c000 {
@@ -324,6 +338,7 @@
reg = <0xffe4c000 0x100>;
interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -332,6 +347,7 @@
reg = <0xffe4d000 0x100>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -340,6 +356,7 @@
reg = <0xffe4e000 0x100>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -348,6 +365,7 @@
reg = <0xffe4f000 0x100>;
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -358,6 +376,7 @@
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -368,6 +387,7 @@
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -378,6 +398,7 @@
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -386,6 +407,7 @@
reg = <0 0xfff80000 0 0x40000>;
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_DU>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
ports {
@@ -427,6 +449,7 @@
#clock-cells = <1>;
clock-output-names = "plla", "z", "zs", "s",
"s1", "p", "b", "out";
+ #power-domain-cells = <0>;
};
/* Fixed factor clocks */
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 08/16] ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
arch/arm/boot/dts/r8a7779.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index a2b5430d32575f99..6afa909865b52b71 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -173,6 +173,7 @@
reg = <0xffc70000 0x1000>;
interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -183,6 +184,7 @@
reg = <0xffc71000 0x1000>;
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -193,6 +195,7 @@
reg = <0xffc72000 0x1000>;
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -203,6 +206,7 @@
reg = <0xffc73000 0x1000>;
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -212,6 +216,7 @@
interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF0>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -221,6 +226,7 @@
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF1>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -230,6 +236,7 @@
interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF2>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -239,6 +246,7 @@
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF3>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -248,6 +256,7 @@
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF4>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -257,6 +266,7 @@
interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF5>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -278,6 +288,7 @@
<0 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -292,6 +303,7 @@
<0 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -306,6 +318,7 @@
<0 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#renesas,channels = <3>;
@@ -317,6 +330,7 @@
reg = <0xfc600000 0x2000>;
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_SATA>;
+ power-domains = <&cpg_clocks>;
};
sdhi0: sd at ffe4c000 {
@@ -324,6 +338,7 @@
reg = <0xffe4c000 0x100>;
interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -332,6 +347,7 @@
reg = <0xffe4d000 0x100>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -340,6 +356,7 @@
reg = <0xffe4e000 0x100>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -348,6 +365,7 @@
reg = <0xffe4f000 0x100>;
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -358,6 +376,7 @@
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -368,6 +387,7 @@
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -378,6 +398,7 @@
#address-cells = <1>;
#size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -386,6 +407,7 @@
reg = <0 0xfff80000 0 0x40000>;
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_DU>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
ports {
@@ -427,6 +449,7 @@
#clock-cells = <1>;
clock-output-names = "plla", "z", "zs", "s",
"s1", "p", "b", "out";
+ #power-domain-cells = <0>;
};
/* Fixed factor clocks */
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 09/16] ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
2015-08-04 12:28 ` Geert Uytterhoeven
(?)
@ 2015-08-04 12:28 ` Geert Uytterhoeven
-1 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node. Notable
exceptions are the "display" and "sound" nodes, which represent multiple
SoC devices, each having their own MSTP clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add "power-domains" properties to recently introduced jpu device
node,
- Consistently add "power-domains" properties after clock and dma
properties,
v3:
- Add "power-domains" property to recently introduced Ethernet AVB
device node,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- Add Reviewed-by,
- Add "power-domains" properties to recently introduced USB-DMAC
device nodes,
- Drop adding "power-domains" properties to the GIC device node, as
adding the INTC_SYS clock is postponed.
---
arch/arm/boot/dts/r8a7790.dtsi | 86 +++++++++++++++++++++++++++++++++++++-----
1 file changed, 77 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 5b2952d5c700fabe..a0b2a79cbfbdf0b4 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -134,6 +134,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
+ power-domains = <&cpg_clocks>;
};
gpio1: gpio@e6051000 {
@@ -146,6 +147,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
+ power-domains = <&cpg_clocks>;
};
gpio2: gpio@e6052000 {
@@ -158,6 +160,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
+ power-domains = <&cpg_clocks>;
};
gpio3: gpio@e6053000 {
@@ -170,6 +173,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
+ power-domains = <&cpg_clocks>;
};
gpio4: gpio@e6054000 {
@@ -182,6 +186,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
+ power-domains = <&cpg_clocks>;
};
gpio5: gpio@e6055000 {
@@ -194,6 +199,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
+ power-domains = <&cpg_clocks>;
};
thermal@e61f0000 {
@@ -201,6 +207,7 @@
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
+ power-domains = <&cpg_clocks>;
};
timer {
@@ -218,6 +225,7 @@
<0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0x60>;
@@ -237,6 +245,7 @@
<0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0xff>;
@@ -253,6 +262,7 @@
<0 2 IRQ_TYPE_LEVEL_HIGH>,
<0 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
+ power-domains = <&cpg_clocks>;
};
dmac0: dma-controller@e6700000 {
@@ -281,6 +291,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -311,6 +322,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -339,6 +351,7 @@
"ch12";
clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <13>;
};
@@ -367,6 +380,7 @@
"ch12";
clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <13>;
};
@@ -378,6 +392,7 @@
0 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <2>;
};
@@ -389,6 +404,7 @@
0 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <2>;
};
@@ -400,6 +416,7 @@
reg = <0 0xe6508000 0 0x40>;
interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -410,6 +427,7 @@
reg = <0 0xe6518000 0 0x40>;
interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -420,6 +438,7 @@
reg = <0 0xe6530000 0 0x40>;
interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -430,6 +449,7 @@
reg = <0 0xe6540000 0 0x40>;
interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -442,6 +462,7 @@
clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
dmas = <&dmac0 0x61>, <&dmac0 0x62>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -454,6 +475,7 @@
clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
dmas = <&dmac0 0x65>, <&dmac0 0x66>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -466,6 +488,7 @@
clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -478,6 +501,7 @@
clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
dmas = <&dmac0 0x77>, <&dmac0 0x78>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -488,6 +512,7 @@
clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
reg-io-width = <4>;
status = "disabled";
max-frequency = <97500000>;
@@ -500,6 +525,7 @@
clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
reg-io-width = <4>;
status = "disabled";
max-frequency = <97500000>;
@@ -517,6 +543,7 @@
clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -527,6 +554,7 @@
clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -537,6 +565,7 @@
clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -547,6 +576,7 @@
clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -558,6 +588,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x21>, <&dmac0 0x22>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -569,6 +600,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x25>, <&dmac0 0x26>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -580,6 +612,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x27>, <&dmac0 0x28>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -591,6 +624,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -602,6 +636,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -613,6 +648,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -624,6 +660,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -635,6 +672,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -646,6 +684,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -657,6 +696,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -665,6 +705,7 @@
reg = <0 0xee700000 0 0x400>;
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
+ power-domains = <&cpg_clocks>;
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
@@ -676,6 +717,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -686,6 +728,7 @@
reg = <0 0xee300000 0 0x2000>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -694,6 +737,7 @@
reg = <0 0xee500000 0 0x2000>;
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -702,12 +746,13 @@
reg = <0 0xe6590000 0 0x100>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
- renesas,buswait = <4>;
- phys = <&usb0 1>;
- phy-names = "usb";
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
<&usb_dmac1 0>, <&usb_dmac1 1>;
dma-names = "ch0", "ch1", "ch2", "ch3";
+ power-domains = <&cpg_clocks>;
+ renesas,buswait = <4>;
+ phys = <&usb0 1>;
+ phy-names = "usb";
status = "disabled";
};
@@ -718,6 +763,7 @@
#size-cells = <0>;
clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
clock-names = "usbhs";
+ power-domains = <&cpg_clocks>;
status = "disabled";
usb0: usb-channel@0 {
@@ -732,33 +778,37 @@
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a7790";
- clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
vin1: video@e6ef1000 {
compatible = "renesas,vin-r8a7790";
- clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
vin2: video@e6ef2000 {
compatible = "renesas,vin-r8a7790";
- clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
reg = <0 0xe6ef2000 0 0x1000>;
interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
vin3: video@e6ef3000 {
compatible = "renesas,vin-r8a7790";
- clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
reg = <0 0xe6ef3000 0 0x1000>;
interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -767,6 +817,7 @@
reg = <0 0xfe920000 0 0x8000>;
interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
+ power-domains = <&cpg_clocks>;
renesas,has-sru;
renesas,#rpf = <5>;
@@ -779,6 +830,7 @@
reg = <0 0xfe928000 0 0x8000>;
interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
+ power-domains = <&cpg_clocks>;
renesas,has-lut;
renesas,has-sru;
@@ -792,6 +844,7 @@
reg = <0 0xfe930000 0 0x8000>;
interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
+ power-domains = <&cpg_clocks>;
renesas,has-lif;
renesas,has-lut;
@@ -805,6 +858,7 @@
reg = <0 0xfe938000 0 0x8000>;
interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
+ power-domains = <&cpg_clocks>;
renesas,has-lif;
renesas,has-lut;
@@ -859,6 +913,7 @@
clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
<&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -869,6 +924,7 @@
clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
<&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -877,6 +933,7 @@
reg = <0 0xfe980000 0 0x10300>;
interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_JPU>;
+ power-domains = <&cpg_clocks>;
};
clocks {
@@ -953,6 +1010,7 @@
clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "sd1",
"z", "rcan", "adsp";
+ #power-domain-cells = <0>;
};
/* Variable factor clocks */
@@ -1343,6 +1401,7 @@
clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
dmas = <&dmac0 0x17>, <&dmac0 0x18>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1356,6 +1415,7 @@
clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
dmas = <&dmac0 0x51>, <&dmac0 0x52>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1368,6 +1428,7 @@
clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
dmas = <&dmac0 0x55>, <&dmac0 0x56>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1380,6 +1441,7 @@
clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
dmas = <&dmac0 0x41>, <&dmac0 0x42>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1392,6 +1454,7 @@
clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
dmas = <&dmac0 0x45>, <&dmac0 0x46>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1402,6 +1465,7 @@
reg = <0 0xee000000 0 0xc00>;
interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
+ power-domains = <&cpg_clocks>;
phys = <&usb2 1>;
phy-names = "usb";
status = "disabled";
@@ -1410,10 +1474,11 @@
pci0: pci@ee090000 {
compatible = "renesas,pci-r8a7790";
device_type = "pci";
- clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
reg = <0 0xee090000 0 0xc00>,
<0 0xee080000 0 0x1100>;
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
bus-range = <0 0>;
@@ -1444,10 +1509,11 @@
pci1: pci@ee0b0000 {
compatible = "renesas,pci-r8a7790";
device_type = "pci";
- clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
reg = <0 0xee0b0000 0 0xc00>,
<0 0xee0a0000 0 0x1100>;
interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
bus-range = <1 1>;
@@ -1465,6 +1531,7 @@
compatible = "renesas,pci-r8a7790";
device_type = "pci";
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
+ power-domains = <&cpg_clocks>;
reg = <0 0xee0d0000 0 0xc00>,
<0 0xee0c0000 0 0x1100>;
interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
@@ -1517,6 +1584,7 @@
interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
clock-names = "pcie", "pcie_bus";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 09/16] ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: linux-clk, linux-pm, linux-sh, linux-arm-kernel, devicetree,
linux-kernel, Geert Uytterhoeven
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node. Notable
exceptions are the "display" and "sound" nodes, which represent multiple
SoC devices, each having their own MSTP clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add "power-domains" properties to recently introduced jpu device
node,
- Consistently add "power-domains" properties after clock and dma
properties,
v3:
- Add "power-domains" property to recently introduced Ethernet AVB
device node,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- Add Reviewed-by,
- Add "power-domains" properties to recently introduced USB-DMAC
device nodes,
- Drop adding "power-domains" properties to the GIC device node, as
adding the INTC_SYS clock is postponed.
---
arch/arm/boot/dts/r8a7790.dtsi | 86 +++++++++++++++++++++++++++++++++++++-----
1 file changed, 77 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 5b2952d5c700fabe..a0b2a79cbfbdf0b4 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -134,6 +134,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
+ power-domains = <&cpg_clocks>;
};
gpio1: gpio@e6051000 {
@@ -146,6 +147,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
+ power-domains = <&cpg_clocks>;
};
gpio2: gpio@e6052000 {
@@ -158,6 +160,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
+ power-domains = <&cpg_clocks>;
};
gpio3: gpio@e6053000 {
@@ -170,6 +173,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
+ power-domains = <&cpg_clocks>;
};
gpio4: gpio@e6054000 {
@@ -182,6 +186,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
+ power-domains = <&cpg_clocks>;
};
gpio5: gpio@e6055000 {
@@ -194,6 +199,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
+ power-domains = <&cpg_clocks>;
};
thermal@e61f0000 {
@@ -201,6 +207,7 @@
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
+ power-domains = <&cpg_clocks>;
};
timer {
@@ -218,6 +225,7 @@
<0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0x60>;
@@ -237,6 +245,7 @@
<0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0xff>;
@@ -253,6 +262,7 @@
<0 2 IRQ_TYPE_LEVEL_HIGH>,
<0 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
+ power-domains = <&cpg_clocks>;
};
dmac0: dma-controller@e6700000 {
@@ -281,6 +291,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -311,6 +322,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -339,6 +351,7 @@
"ch12";
clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <13>;
};
@@ -367,6 +380,7 @@
"ch12";
clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <13>;
};
@@ -378,6 +392,7 @@
0 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <2>;
};
@@ -389,6 +404,7 @@
0 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <2>;
};
@@ -400,6 +416,7 @@
reg = <0 0xe6508000 0 0x40>;
interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -410,6 +427,7 @@
reg = <0 0xe6518000 0 0x40>;
interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -420,6 +438,7 @@
reg = <0 0xe6530000 0 0x40>;
interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -430,6 +449,7 @@
reg = <0 0xe6540000 0 0x40>;
interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -442,6 +462,7 @@
clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
dmas = <&dmac0 0x61>, <&dmac0 0x62>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -454,6 +475,7 @@
clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
dmas = <&dmac0 0x65>, <&dmac0 0x66>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -466,6 +488,7 @@
clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -478,6 +501,7 @@
clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
dmas = <&dmac0 0x77>, <&dmac0 0x78>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -488,6 +512,7 @@
clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
reg-io-width = <4>;
status = "disabled";
max-frequency = <97500000>;
@@ -500,6 +525,7 @@
clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
reg-io-width = <4>;
status = "disabled";
max-frequency = <97500000>;
@@ -517,6 +543,7 @@
clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -527,6 +554,7 @@
clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -537,6 +565,7 @@
clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -547,6 +576,7 @@
clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -558,6 +588,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x21>, <&dmac0 0x22>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -569,6 +600,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x25>, <&dmac0 0x26>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -580,6 +612,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x27>, <&dmac0 0x28>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -591,6 +624,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -602,6 +636,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -613,6 +648,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -624,6 +660,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -635,6 +672,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -646,6 +684,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -657,6 +696,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -665,6 +705,7 @@
reg = <0 0xee700000 0 0x400>;
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
+ power-domains = <&cpg_clocks>;
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
@@ -676,6 +717,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -686,6 +728,7 @@
reg = <0 0xee300000 0 0x2000>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -694,6 +737,7 @@
reg = <0 0xee500000 0 0x2000>;
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -702,12 +746,13 @@
reg = <0 0xe6590000 0 0x100>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
- renesas,buswait = <4>;
- phys = <&usb0 1>;
- phy-names = "usb";
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
<&usb_dmac1 0>, <&usb_dmac1 1>;
dma-names = "ch0", "ch1", "ch2", "ch3";
+ power-domains = <&cpg_clocks>;
+ renesas,buswait = <4>;
+ phys = <&usb0 1>;
+ phy-names = "usb";
status = "disabled";
};
@@ -718,6 +763,7 @@
#size-cells = <0>;
clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
clock-names = "usbhs";
+ power-domains = <&cpg_clocks>;
status = "disabled";
usb0: usb-channel@0 {
@@ -732,33 +778,37 @@
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a7790";
- clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
vin1: video@e6ef1000 {
compatible = "renesas,vin-r8a7790";
- clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
vin2: video@e6ef2000 {
compatible = "renesas,vin-r8a7790";
- clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
reg = <0 0xe6ef2000 0 0x1000>;
interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
vin3: video@e6ef3000 {
compatible = "renesas,vin-r8a7790";
- clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
reg = <0 0xe6ef3000 0 0x1000>;
interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -767,6 +817,7 @@
reg = <0 0xfe920000 0 0x8000>;
interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
+ power-domains = <&cpg_clocks>;
renesas,has-sru;
renesas,#rpf = <5>;
@@ -779,6 +830,7 @@
reg = <0 0xfe928000 0 0x8000>;
interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
+ power-domains = <&cpg_clocks>;
renesas,has-lut;
renesas,has-sru;
@@ -792,6 +844,7 @@
reg = <0 0xfe930000 0 0x8000>;
interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
+ power-domains = <&cpg_clocks>;
renesas,has-lif;
renesas,has-lut;
@@ -805,6 +858,7 @@
reg = <0 0xfe938000 0 0x8000>;
interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
+ power-domains = <&cpg_clocks>;
renesas,has-lif;
renesas,has-lut;
@@ -859,6 +913,7 @@
clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
<&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -869,6 +924,7 @@
clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
<&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -877,6 +933,7 @@
reg = <0 0xfe980000 0 0x10300>;
interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_JPU>;
+ power-domains = <&cpg_clocks>;
};
clocks {
@@ -953,6 +1010,7 @@
clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "sd1",
"z", "rcan", "adsp";
+ #power-domain-cells = <0>;
};
/* Variable factor clocks */
@@ -1343,6 +1401,7 @@
clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
dmas = <&dmac0 0x17>, <&dmac0 0x18>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1356,6 +1415,7 @@
clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
dmas = <&dmac0 0x51>, <&dmac0 0x52>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1368,6 +1428,7 @@
clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
dmas = <&dmac0 0x55>, <&dmac0 0x56>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1380,6 +1441,7 @@
clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
dmas = <&dmac0 0x41>, <&dmac0 0x42>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1392,6 +1454,7 @@
clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
dmas = <&dmac0 0x45>, <&dmac0 0x46>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1402,6 +1465,7 @@
reg = <0 0xee000000 0 0xc00>;
interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
+ power-domains = <&cpg_clocks>;
phys = <&usb2 1>;
phy-names = "usb";
status = "disabled";
@@ -1410,10 +1474,11 @@
pci0: pci@ee090000 {
compatible = "renesas,pci-r8a7790";
device_type = "pci";
- clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
reg = <0 0xee090000 0 0xc00>,
<0 0xee080000 0 0x1100>;
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
bus-range = <0 0>;
@@ -1444,10 +1509,11 @@
pci1: pci@ee0b0000 {
compatible = "renesas,pci-r8a7790";
device_type = "pci";
- clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
reg = <0 0xee0b0000 0 0xc00>,
<0 0xee0a0000 0 0x1100>;
interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
bus-range = <1 1>;
@@ -1465,6 +1531,7 @@
compatible = "renesas,pci-r8a7790";
device_type = "pci";
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
+ power-domains = <&cpg_clocks>;
reg = <0 0xee0d0000 0 0xc00>,
<0 0xee0c0000 0 0x1100>;
interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
@@ -1517,6 +1584,7 @@
interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
clock-names = "pcie", "pcie_bus";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 09/16] ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node. Notable
exceptions are the "display" and "sound" nodes, which represent multiple
SoC devices, each having their own MSTP clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add "power-domains" properties to recently introduced jpu device
node,
- Consistently add "power-domains" properties after clock and dma
properties,
v3:
- Add "power-domains" property to recently introduced Ethernet AVB
device node,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- Add Reviewed-by,
- Add "power-domains" properties to recently introduced USB-DMAC
device nodes,
- Drop adding "power-domains" properties to the GIC device node, as
adding the INTC_SYS clock is postponed.
---
arch/arm/boot/dts/r8a7790.dtsi | 86 +++++++++++++++++++++++++++++++++++++-----
1 file changed, 77 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 5b2952d5c700fabe..a0b2a79cbfbdf0b4 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -134,6 +134,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
+ power-domains = <&cpg_clocks>;
};
gpio1: gpio at e6051000 {
@@ -146,6 +147,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
+ power-domains = <&cpg_clocks>;
};
gpio2: gpio at e6052000 {
@@ -158,6 +160,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
+ power-domains = <&cpg_clocks>;
};
gpio3: gpio at e6053000 {
@@ -170,6 +173,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
+ power-domains = <&cpg_clocks>;
};
gpio4: gpio at e6054000 {
@@ -182,6 +186,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
+ power-domains = <&cpg_clocks>;
};
gpio5: gpio at e6055000 {
@@ -194,6 +199,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
+ power-domains = <&cpg_clocks>;
};
thermal at e61f0000 {
@@ -201,6 +207,7 @@
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
+ power-domains = <&cpg_clocks>;
};
timer {
@@ -218,6 +225,7 @@
<0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0x60>;
@@ -237,6 +245,7 @@
<0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0xff>;
@@ -253,6 +262,7 @@
<0 2 IRQ_TYPE_LEVEL_HIGH>,
<0 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
+ power-domains = <&cpg_clocks>;
};
dmac0: dma-controller at e6700000 {
@@ -281,6 +291,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -311,6 +322,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -339,6 +351,7 @@
"ch12";
clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <13>;
};
@@ -367,6 +380,7 @@
"ch12";
clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <13>;
};
@@ -378,6 +392,7 @@
0 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <2>;
};
@@ -389,6 +404,7 @@
0 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <2>;
};
@@ -400,6 +416,7 @@
reg = <0 0xe6508000 0 0x40>;
interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -410,6 +427,7 @@
reg = <0 0xe6518000 0 0x40>;
interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -420,6 +438,7 @@
reg = <0 0xe6530000 0 0x40>;
interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -430,6 +449,7 @@
reg = <0 0xe6540000 0 0x40>;
interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -442,6 +462,7 @@
clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
dmas = <&dmac0 0x61>, <&dmac0 0x62>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -454,6 +475,7 @@
clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
dmas = <&dmac0 0x65>, <&dmac0 0x66>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -466,6 +488,7 @@
clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -478,6 +501,7 @@
clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
dmas = <&dmac0 0x77>, <&dmac0 0x78>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -488,6 +512,7 @@
clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
reg-io-width = <4>;
status = "disabled";
max-frequency = <97500000>;
@@ -500,6 +525,7 @@
clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
reg-io-width = <4>;
status = "disabled";
max-frequency = <97500000>;
@@ -517,6 +543,7 @@
clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -527,6 +554,7 @@
clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -537,6 +565,7 @@
clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -547,6 +576,7 @@
clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -558,6 +588,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x21>, <&dmac0 0x22>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -569,6 +600,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x25>, <&dmac0 0x26>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -580,6 +612,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x27>, <&dmac0 0x28>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -591,6 +624,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -602,6 +636,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -613,6 +648,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -624,6 +660,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -635,6 +672,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -646,6 +684,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -657,6 +696,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -665,6 +705,7 @@
reg = <0 0xee700000 0 0x400>;
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
+ power-domains = <&cpg_clocks>;
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
@@ -676,6 +717,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -686,6 +728,7 @@
reg = <0 0xee300000 0 0x2000>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -694,6 +737,7 @@
reg = <0 0xee500000 0 0x2000>;
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -702,12 +746,13 @@
reg = <0 0xe6590000 0 0x100>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
- renesas,buswait = <4>;
- phys = <&usb0 1>;
- phy-names = "usb";
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
<&usb_dmac1 0>, <&usb_dmac1 1>;
dma-names = "ch0", "ch1", "ch2", "ch3";
+ power-domains = <&cpg_clocks>;
+ renesas,buswait = <4>;
+ phys = <&usb0 1>;
+ phy-names = "usb";
status = "disabled";
};
@@ -718,6 +763,7 @@
#size-cells = <0>;
clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
clock-names = "usbhs";
+ power-domains = <&cpg_clocks>;
status = "disabled";
usb0: usb-channel at 0 {
@@ -732,33 +778,37 @@
vin0: video at e6ef0000 {
compatible = "renesas,vin-r8a7790";
- clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
vin1: video at e6ef1000 {
compatible = "renesas,vin-r8a7790";
- clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
vin2: video at e6ef2000 {
compatible = "renesas,vin-r8a7790";
- clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
reg = <0 0xe6ef2000 0 0x1000>;
interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
vin3: video at e6ef3000 {
compatible = "renesas,vin-r8a7790";
- clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
reg = <0 0xe6ef3000 0 0x1000>;
interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -767,6 +817,7 @@
reg = <0 0xfe920000 0 0x8000>;
interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
+ power-domains = <&cpg_clocks>;
renesas,has-sru;
renesas,#rpf = <5>;
@@ -779,6 +830,7 @@
reg = <0 0xfe928000 0 0x8000>;
interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
+ power-domains = <&cpg_clocks>;
renesas,has-lut;
renesas,has-sru;
@@ -792,6 +844,7 @@
reg = <0 0xfe930000 0 0x8000>;
interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
+ power-domains = <&cpg_clocks>;
renesas,has-lif;
renesas,has-lut;
@@ -805,6 +858,7 @@
reg = <0 0xfe938000 0 0x8000>;
interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
+ power-domains = <&cpg_clocks>;
renesas,has-lif;
renesas,has-lut;
@@ -859,6 +913,7 @@
clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
<&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -869,6 +924,7 @@
clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
<&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -877,6 +933,7 @@
reg = <0 0xfe980000 0 0x10300>;
interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_JPU>;
+ power-domains = <&cpg_clocks>;
};
clocks {
@@ -953,6 +1010,7 @@
clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "sd1",
"z", "rcan", "adsp";
+ #power-domain-cells = <0>;
};
/* Variable factor clocks */
@@ -1343,6 +1401,7 @@
clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
dmas = <&dmac0 0x17>, <&dmac0 0x18>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1356,6 +1415,7 @@
clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
dmas = <&dmac0 0x51>, <&dmac0 0x52>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1368,6 +1428,7 @@
clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
dmas = <&dmac0 0x55>, <&dmac0 0x56>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1380,6 +1441,7 @@
clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
dmas = <&dmac0 0x41>, <&dmac0 0x42>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1392,6 +1454,7 @@
clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
dmas = <&dmac0 0x45>, <&dmac0 0x46>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1402,6 +1465,7 @@
reg = <0 0xee000000 0 0xc00>;
interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
+ power-domains = <&cpg_clocks>;
phys = <&usb2 1>;
phy-names = "usb";
status = "disabled";
@@ -1410,10 +1474,11 @@
pci0: pci at ee090000 {
compatible = "renesas,pci-r8a7790";
device_type = "pci";
- clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
reg = <0 0xee090000 0 0xc00>,
<0 0xee080000 0 0x1100>;
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
bus-range = <0 0>;
@@ -1444,10 +1509,11 @@
pci1: pci at ee0b0000 {
compatible = "renesas,pci-r8a7790";
device_type = "pci";
- clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
reg = <0 0xee0b0000 0 0xc00>,
<0 0xee0a0000 0 0x1100>;
interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
bus-range = <1 1>;
@@ -1465,6 +1531,7 @@
compatible = "renesas,pci-r8a7790";
device_type = "pci";
clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
+ power-domains = <&cpg_clocks>;
reg = <0 0xee0d0000 0 0xc00>,
<0 0xee0c0000 0 0x1100>;
interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
@@ -1517,6 +1584,7 @@
interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
clock-names = "pcie", "pcie_bus";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 10/16] ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
2015-08-04 12:28 ` Geert Uytterhoeven
(?)
@ 2015-08-04 12:28 ` Geert Uytterhoeven
-1 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node. Notable
exceptions are the "display" and "sound" nodes, which represent multiple
SoC devices, each having their own MSTP clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add "power-domains" properties to recently introduced jpu device
node,
- Consistently add "power-domains" properties after clock and dma
properties,
v3:
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- Add Reviewed-by,
- Add "power-domains" properties to recently introduced USB-DMAC
device nodes,
- Drop adding "power-domains" properties to the GIC device node, as
adding the INTC_SYS clock is postponed.
---
arch/arm/boot/dts/r8a7791.dtsi | 88 ++++++++++++++++++++++++++++++++++++++----
1 file changed, 80 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 1cb6c2d079331d4f..831525dd39a60ad7 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -91,6 +91,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
+ power-domains = <&cpg_clocks>;
};
gpio1: gpio@e6051000 {
@@ -103,6 +104,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
+ power-domains = <&cpg_clocks>;
};
gpio2: gpio@e6052000 {
@@ -115,6 +117,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
+ power-domains = <&cpg_clocks>;
};
gpio3: gpio@e6053000 {
@@ -127,6 +130,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
+ power-domains = <&cpg_clocks>;
};
gpio4: gpio@e6054000 {
@@ -139,6 +143,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
+ power-domains = <&cpg_clocks>;
};
gpio5: gpio@e6055000 {
@@ -151,6 +156,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
+ power-domains = <&cpg_clocks>;
};
gpio6: gpio@e6055400 {
@@ -163,6 +169,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
+ power-domains = <&cpg_clocks>;
};
gpio7: gpio@e6055800 {
@@ -175,6 +182,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
+ power-domains = <&cpg_clocks>;
};
thermal@e61f0000 {
@@ -182,6 +190,7 @@
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
+ power-domains = <&cpg_clocks>;
};
timer {
@@ -199,6 +208,7 @@
<0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0x60>;
@@ -218,6 +228,7 @@
<0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0xff>;
@@ -240,6 +251,7 @@
<0 16 IRQ_TYPE_LEVEL_HIGH>,
<0 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
+ power-domains = <&cpg_clocks>;
};
dmac0: dma-controller@e6700000 {
@@ -268,6 +280,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -298,6 +311,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -326,6 +340,7 @@
"ch12";
clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <13>;
};
@@ -354,6 +369,7 @@
"ch12";
clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <13>;
};
@@ -365,6 +381,7 @@
0 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <2>;
};
@@ -376,6 +393,7 @@
0 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <2>;
};
@@ -388,6 +406,7 @@
reg = <0 0xe6508000 0 0x40>;
interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -398,6 +417,7 @@
reg = <0 0xe6518000 0 0x40>;
interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -408,6 +428,7 @@
reg = <0 0xe6530000 0 0x40>;
interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -418,6 +439,7 @@
reg = <0 0xe6540000 0 0x40>;
interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -428,6 +450,7 @@
reg = <0 0xe6520000 0 0x40>;
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -439,6 +462,7 @@
reg = <0 0xe6528000 0 0x40>;
interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -452,6 +476,7 @@
clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
dmas = <&dmac0 0x77>, <&dmac0 0x78>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -464,6 +489,7 @@
clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
dmas = <&dmac0 0x61>, <&dmac0 0x62>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -476,6 +502,7 @@
clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
dmas = <&dmac0 0x65>, <&dmac0 0x66>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -492,6 +519,7 @@
clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
reg-io-width = <4>;
status = "disabled";
max-frequency = <97500000>;
@@ -504,6 +532,7 @@
clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -514,6 +543,7 @@
clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -524,6 +554,7 @@
clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -535,6 +566,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x21>, <&dmac0 0x22>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -546,6 +578,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x25>, <&dmac0 0x26>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -557,6 +590,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x27>, <&dmac0 0x28>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -568,6 +602,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -579,6 +614,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -590,6 +626,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x23>, <&dmac0 0x24>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -601,6 +638,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -612,6 +650,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -623,6 +662,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -634,6 +674,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -645,6 +686,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -656,6 +698,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -667,6 +710,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -678,6 +722,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -689,6 +734,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -700,6 +746,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -711,6 +758,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -722,6 +770,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -730,6 +779,7 @@
reg = <0 0xee700000 0 0x400>;
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
+ power-domains = <&cpg_clocks>;
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
@@ -741,6 +791,7 @@
reg = <0 0xee300000 0 0x2000>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -749,6 +800,7 @@
reg = <0 0xee500000 0 0x2000>;
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -757,12 +809,13 @@
reg = <0 0xe6590000 0 0x100>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
- renesas,buswait = <4>;
- phys = <&usb0 1>;
- phy-names = "usb";
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
<&usb_dmac1 0>, <&usb_dmac1 1>;
dma-names = "ch0", "ch1", "ch2", "ch3";
+ power-domains = <&cpg_clocks>;
+ renesas,buswait = <4>;
+ phys = <&usb0 1>;
+ phy-names = "usb";
status = "disabled";
};
@@ -773,6 +826,7 @@
#size-cells = <0>;
clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
clock-names = "usbhs";
+ power-domains = <&cpg_clocks>;
status = "disabled";
usb0: usb-channel@0 {
@@ -787,25 +841,28 @@
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a7791";
- clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
vin1: video@e6ef1000 {
compatible = "renesas,vin-r8a7791";
- clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
vin2: video@e6ef2000 {
compatible = "renesas,vin-r8a7791";
- clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
reg = <0 0xe6ef2000 0 0x1000>;
interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -814,6 +871,7 @@
reg = <0 0xfe928000 0 0x8000>;
interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
+ power-domains = <&cpg_clocks>;
renesas,has-lut;
renesas,has-sru;
@@ -827,6 +885,7 @@
reg = <0 0xfe930000 0 0x8000>;
interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
+ power-domains = <&cpg_clocks>;
renesas,has-lif;
renesas,has-lut;
@@ -840,6 +899,7 @@
reg = <0 0xfe938000 0 0x8000>;
interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
+ power-domains = <&cpg_clocks>;
renesas,has-lif;
renesas,has-lut;
@@ -885,6 +945,7 @@
clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
<&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -895,6 +956,7 @@
clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
<&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -903,6 +965,7 @@
reg = <0 0xfe980000 0 0x10300>;
interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_JPU>;
+ power-domains = <&cpg_clocks>;
};
clocks {
@@ -979,6 +1042,7 @@
clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "z",
"rcan", "adsp";
+ #power-domain-cells = <0>;
};
/* Variable factor clocks */
@@ -1361,6 +1425,7 @@
clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
dmas = <&dmac0 0x17>, <&dmac0 0x18>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1374,6 +1439,7 @@
clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
dmas = <&dmac0 0x51>, <&dmac0 0x52>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1386,6 +1452,7 @@
clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
dmas = <&dmac0 0x55>, <&dmac0 0x56>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1398,6 +1465,7 @@
clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
dmas = <&dmac0 0x41>, <&dmac0 0x42>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1408,6 +1476,7 @@
reg = <0 0xee000000 0 0xc00>;
interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
+ power-domains = <&cpg_clocks>;
phys = <&usb2 1>;
phy-names = "usb";
status = "disabled";
@@ -1416,10 +1485,11 @@
pci0: pci@ee090000 {
compatible = "renesas,pci-r8a7791";
device_type = "pci";
- clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
reg = <0 0xee090000 0 0xc00>,
<0 0xee080000 0 0x1100>;
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
bus-range = <0 0>;
@@ -1450,10 +1520,11 @@
pci1: pci@ee0d0000 {
compatible = "renesas,pci-r8a7791";
device_type = "pci";
- clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
reg = <0 0xee0d0000 0 0xc00>,
<0 0xee0c0000 0 0x1100>;
interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
bus-range = <1 1>;
@@ -1503,6 +1574,7 @@
interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
clock-names = "pcie", "pcie_bus";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 10/16] ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: linux-clk, linux-pm, linux-sh, linux-arm-kernel, devicetree,
linux-kernel, Geert Uytterhoeven
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node. Notable
exceptions are the "display" and "sound" nodes, which represent multiple
SoC devices, each having their own MSTP clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add "power-domains" properties to recently introduced jpu device
node,
- Consistently add "power-domains" properties after clock and dma
properties,
v3:
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- Add Reviewed-by,
- Add "power-domains" properties to recently introduced USB-DMAC
device nodes,
- Drop adding "power-domains" properties to the GIC device node, as
adding the INTC_SYS clock is postponed.
---
arch/arm/boot/dts/r8a7791.dtsi | 88 ++++++++++++++++++++++++++++++++++++++----
1 file changed, 80 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 1cb6c2d079331d4f..831525dd39a60ad7 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -91,6 +91,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
+ power-domains = <&cpg_clocks>;
};
gpio1: gpio@e6051000 {
@@ -103,6 +104,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
+ power-domains = <&cpg_clocks>;
};
gpio2: gpio@e6052000 {
@@ -115,6 +117,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
+ power-domains = <&cpg_clocks>;
};
gpio3: gpio@e6053000 {
@@ -127,6 +130,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
+ power-domains = <&cpg_clocks>;
};
gpio4: gpio@e6054000 {
@@ -139,6 +143,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
+ power-domains = <&cpg_clocks>;
};
gpio5: gpio@e6055000 {
@@ -151,6 +156,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
+ power-domains = <&cpg_clocks>;
};
gpio6: gpio@e6055400 {
@@ -163,6 +169,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
+ power-domains = <&cpg_clocks>;
};
gpio7: gpio@e6055800 {
@@ -175,6 +182,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
+ power-domains = <&cpg_clocks>;
};
thermal@e61f0000 {
@@ -182,6 +190,7 @@
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
+ power-domains = <&cpg_clocks>;
};
timer {
@@ -199,6 +208,7 @@
<0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0x60>;
@@ -218,6 +228,7 @@
<0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0xff>;
@@ -240,6 +251,7 @@
<0 16 IRQ_TYPE_LEVEL_HIGH>,
<0 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
+ power-domains = <&cpg_clocks>;
};
dmac0: dma-controller@e6700000 {
@@ -268,6 +280,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -298,6 +311,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -326,6 +340,7 @@
"ch12";
clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <13>;
};
@@ -354,6 +369,7 @@
"ch12";
clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <13>;
};
@@ -365,6 +381,7 @@
0 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <2>;
};
@@ -376,6 +393,7 @@
0 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <2>;
};
@@ -388,6 +406,7 @@
reg = <0 0xe6508000 0 0x40>;
interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -398,6 +417,7 @@
reg = <0 0xe6518000 0 0x40>;
interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -408,6 +428,7 @@
reg = <0 0xe6530000 0 0x40>;
interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -418,6 +439,7 @@
reg = <0 0xe6540000 0 0x40>;
interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -428,6 +450,7 @@
reg = <0 0xe6520000 0 0x40>;
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -439,6 +462,7 @@
reg = <0 0xe6528000 0 0x40>;
interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -452,6 +476,7 @@
clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
dmas = <&dmac0 0x77>, <&dmac0 0x78>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -464,6 +489,7 @@
clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
dmas = <&dmac0 0x61>, <&dmac0 0x62>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -476,6 +502,7 @@
clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
dmas = <&dmac0 0x65>, <&dmac0 0x66>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -492,6 +519,7 @@
clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
reg-io-width = <4>;
status = "disabled";
max-frequency = <97500000>;
@@ -504,6 +532,7 @@
clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -514,6 +543,7 @@
clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -524,6 +554,7 @@
clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -535,6 +566,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x21>, <&dmac0 0x22>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -546,6 +578,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x25>, <&dmac0 0x26>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -557,6 +590,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x27>, <&dmac0 0x28>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -568,6 +602,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -579,6 +614,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -590,6 +626,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x23>, <&dmac0 0x24>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -601,6 +638,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -612,6 +650,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -623,6 +662,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -634,6 +674,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -645,6 +686,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -656,6 +698,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -667,6 +710,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -678,6 +722,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -689,6 +734,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -700,6 +746,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -711,6 +758,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -722,6 +770,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -730,6 +779,7 @@
reg = <0 0xee700000 0 0x400>;
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
+ power-domains = <&cpg_clocks>;
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
@@ -741,6 +791,7 @@
reg = <0 0xee300000 0 0x2000>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -749,6 +800,7 @@
reg = <0 0xee500000 0 0x2000>;
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -757,12 +809,13 @@
reg = <0 0xe6590000 0 0x100>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
- renesas,buswait = <4>;
- phys = <&usb0 1>;
- phy-names = "usb";
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
<&usb_dmac1 0>, <&usb_dmac1 1>;
dma-names = "ch0", "ch1", "ch2", "ch3";
+ power-domains = <&cpg_clocks>;
+ renesas,buswait = <4>;
+ phys = <&usb0 1>;
+ phy-names = "usb";
status = "disabled";
};
@@ -773,6 +826,7 @@
#size-cells = <0>;
clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
clock-names = "usbhs";
+ power-domains = <&cpg_clocks>;
status = "disabled";
usb0: usb-channel@0 {
@@ -787,25 +841,28 @@
vin0: video@e6ef0000 {
compatible = "renesas,vin-r8a7791";
- clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
vin1: video@e6ef1000 {
compatible = "renesas,vin-r8a7791";
- clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
vin2: video@e6ef2000 {
compatible = "renesas,vin-r8a7791";
- clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
reg = <0 0xe6ef2000 0 0x1000>;
interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -814,6 +871,7 @@
reg = <0 0xfe928000 0 0x8000>;
interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
+ power-domains = <&cpg_clocks>;
renesas,has-lut;
renesas,has-sru;
@@ -827,6 +885,7 @@
reg = <0 0xfe930000 0 0x8000>;
interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
+ power-domains = <&cpg_clocks>;
renesas,has-lif;
renesas,has-lut;
@@ -840,6 +899,7 @@
reg = <0 0xfe938000 0 0x8000>;
interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
+ power-domains = <&cpg_clocks>;
renesas,has-lif;
renesas,has-lut;
@@ -885,6 +945,7 @@
clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
<&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -895,6 +956,7 @@
clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
<&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -903,6 +965,7 @@
reg = <0 0xfe980000 0 0x10300>;
interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_JPU>;
+ power-domains = <&cpg_clocks>;
};
clocks {
@@ -979,6 +1042,7 @@
clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "z",
"rcan", "adsp";
+ #power-domain-cells = <0>;
};
/* Variable factor clocks */
@@ -1361,6 +1425,7 @@
clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
dmas = <&dmac0 0x17>, <&dmac0 0x18>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1374,6 +1439,7 @@
clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
dmas = <&dmac0 0x51>, <&dmac0 0x52>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1386,6 +1452,7 @@
clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
dmas = <&dmac0 0x55>, <&dmac0 0x56>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1398,6 +1465,7 @@
clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
dmas = <&dmac0 0x41>, <&dmac0 0x42>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1408,6 +1476,7 @@
reg = <0 0xee000000 0 0xc00>;
interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
+ power-domains = <&cpg_clocks>;
phys = <&usb2 1>;
phy-names = "usb";
status = "disabled";
@@ -1416,10 +1485,11 @@
pci0: pci@ee090000 {
compatible = "renesas,pci-r8a7791";
device_type = "pci";
- clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
reg = <0 0xee090000 0 0xc00>,
<0 0xee080000 0 0x1100>;
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
bus-range = <0 0>;
@@ -1450,10 +1520,11 @@
pci1: pci@ee0d0000 {
compatible = "renesas,pci-r8a7791";
device_type = "pci";
- clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
reg = <0 0xee0d0000 0 0xc00>,
<0 0xee0c0000 0 0x1100>;
interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
bus-range = <1 1>;
@@ -1503,6 +1574,7 @@
interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
clock-names = "pcie", "pcie_bus";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 10/16] ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node. Notable
exceptions are the "display" and "sound" nodes, which represent multiple
SoC devices, each having their own MSTP clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add "power-domains" properties to recently introduced jpu device
node,
- Consistently add "power-domains" properties after clock and dma
properties,
v3:
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- Add Reviewed-by,
- Add "power-domains" properties to recently introduced USB-DMAC
device nodes,
- Drop adding "power-domains" properties to the GIC device node, as
adding the INTC_SYS clock is postponed.
---
arch/arm/boot/dts/r8a7791.dtsi | 88 ++++++++++++++++++++++++++++++++++++++----
1 file changed, 80 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 1cb6c2d079331d4f..831525dd39a60ad7 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -91,6 +91,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
+ power-domains = <&cpg_clocks>;
};
gpio1: gpio at e6051000 {
@@ -103,6 +104,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
+ power-domains = <&cpg_clocks>;
};
gpio2: gpio at e6052000 {
@@ -115,6 +117,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
+ power-domains = <&cpg_clocks>;
};
gpio3: gpio at e6053000 {
@@ -127,6 +130,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
+ power-domains = <&cpg_clocks>;
};
gpio4: gpio at e6054000 {
@@ -139,6 +143,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
+ power-domains = <&cpg_clocks>;
};
gpio5: gpio at e6055000 {
@@ -151,6 +156,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
+ power-domains = <&cpg_clocks>;
};
gpio6: gpio at e6055400 {
@@ -163,6 +169,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
+ power-domains = <&cpg_clocks>;
};
gpio7: gpio at e6055800 {
@@ -175,6 +182,7 @@
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
+ power-domains = <&cpg_clocks>;
};
thermal at e61f0000 {
@@ -182,6 +190,7 @@
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
+ power-domains = <&cpg_clocks>;
};
timer {
@@ -199,6 +208,7 @@
<0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0x60>;
@@ -218,6 +228,7 @@
<0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0xff>;
@@ -240,6 +251,7 @@
<0 16 IRQ_TYPE_LEVEL_HIGH>,
<0 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7791_CLK_IRQC>;
+ power-domains = <&cpg_clocks>;
};
dmac0: dma-controller at e6700000 {
@@ -268,6 +280,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -298,6 +311,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -326,6 +340,7 @@
"ch12";
clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <13>;
};
@@ -354,6 +369,7 @@
"ch12";
clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <13>;
};
@@ -365,6 +381,7 @@
0 109 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>;
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <2>;
};
@@ -376,6 +393,7 @@
0 110 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>;
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <2>;
};
@@ -388,6 +406,7 @@
reg = <0 0xe6508000 0 0x40>;
interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -398,6 +417,7 @@
reg = <0 0xe6518000 0 0x40>;
interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -408,6 +428,7 @@
reg = <0 0xe6530000 0 0x40>;
interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -418,6 +439,7 @@
reg = <0 0xe6540000 0 0x40>;
interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -428,6 +450,7 @@
reg = <0 0xe6520000 0 0x40>;
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -439,6 +462,7 @@
reg = <0 0xe6528000 0 0x40>;
interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -452,6 +476,7 @@
clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
dmas = <&dmac0 0x77>, <&dmac0 0x78>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -464,6 +489,7 @@
clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
dmas = <&dmac0 0x61>, <&dmac0 0x62>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -476,6 +502,7 @@
clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
dmas = <&dmac0 0x65>, <&dmac0 0x66>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -492,6 +519,7 @@
clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
reg-io-width = <4>;
status = "disabled";
max-frequency = <97500000>;
@@ -504,6 +532,7 @@
clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -514,6 +543,7 @@
clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -524,6 +554,7 @@
clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -535,6 +566,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x21>, <&dmac0 0x22>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -546,6 +578,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x25>, <&dmac0 0x26>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -557,6 +590,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x27>, <&dmac0 0x28>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -568,6 +602,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -579,6 +614,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -590,6 +626,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x23>, <&dmac0 0x24>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -601,6 +638,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -612,6 +650,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -623,6 +662,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -634,6 +674,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -645,6 +686,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -656,6 +698,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -667,6 +710,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -678,6 +722,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -689,6 +734,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -700,6 +746,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -711,6 +758,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -722,6 +770,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -730,6 +779,7 @@
reg = <0 0xee700000 0 0x400>;
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
+ power-domains = <&cpg_clocks>;
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
@@ -741,6 +791,7 @@
reg = <0 0xee300000 0 0x2000>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -749,6 +800,7 @@
reg = <0 0xee500000 0 0x2000>;
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -757,12 +809,13 @@
reg = <0 0xe6590000 0 0x100>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
- renesas,buswait = <4>;
- phys = <&usb0 1>;
- phy-names = "usb";
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
<&usb_dmac1 0>, <&usb_dmac1 1>;
dma-names = "ch0", "ch1", "ch2", "ch3";
+ power-domains = <&cpg_clocks>;
+ renesas,buswait = <4>;
+ phys = <&usb0 1>;
+ phy-names = "usb";
status = "disabled";
};
@@ -773,6 +826,7 @@
#size-cells = <0>;
clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
clock-names = "usbhs";
+ power-domains = <&cpg_clocks>;
status = "disabled";
usb0: usb-channel at 0 {
@@ -787,25 +841,28 @@
vin0: video at e6ef0000 {
compatible = "renesas,vin-r8a7791";
- clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
vin1: video at e6ef1000 {
compatible = "renesas,vin-r8a7791";
- clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
vin2: video at e6ef2000 {
compatible = "renesas,vin-r8a7791";
- clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
reg = <0 0xe6ef2000 0 0x1000>;
interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -814,6 +871,7 @@
reg = <0 0xfe928000 0 0x8000>;
interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
+ power-domains = <&cpg_clocks>;
renesas,has-lut;
renesas,has-sru;
@@ -827,6 +885,7 @@
reg = <0 0xfe930000 0 0x8000>;
interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
+ power-domains = <&cpg_clocks>;
renesas,has-lif;
renesas,has-lut;
@@ -840,6 +899,7 @@
reg = <0 0xfe938000 0 0x8000>;
interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
+ power-domains = <&cpg_clocks>;
renesas,has-lif;
renesas,has-lut;
@@ -885,6 +945,7 @@
clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
<&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -895,6 +956,7 @@
clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
<&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -903,6 +965,7 @@
reg = <0 0xfe980000 0 0x10300>;
interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_JPU>;
+ power-domains = <&cpg_clocks>;
};
clocks {
@@ -979,6 +1042,7 @@
clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "z",
"rcan", "adsp";
+ #power-domain-cells = <0>;
};
/* Variable factor clocks */
@@ -1361,6 +1425,7 @@
clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
dmas = <&dmac0 0x17>, <&dmac0 0x18>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1374,6 +1439,7 @@
clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
dmas = <&dmac0 0x51>, <&dmac0 0x52>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1386,6 +1452,7 @@
clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
dmas = <&dmac0 0x55>, <&dmac0 0x56>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1398,6 +1465,7 @@
clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
dmas = <&dmac0 0x41>, <&dmac0 0x42>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1408,6 +1476,7 @@
reg = <0 0xee000000 0 0xc00>;
interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
+ power-domains = <&cpg_clocks>;
phys = <&usb2 1>;
phy-names = "usb";
status = "disabled";
@@ -1416,10 +1485,11 @@
pci0: pci at ee090000 {
compatible = "renesas,pci-r8a7791";
device_type = "pci";
- clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
reg = <0 0xee090000 0 0xc00>,
<0 0xee080000 0 0x1100>;
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
bus-range = <0 0>;
@@ -1450,10 +1520,11 @@
pci1: pci at ee0d0000 {
compatible = "renesas,pci-r8a7791";
device_type = "pci";
- clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
reg = <0 0xee0d0000 0 0xc00>,
<0 0xee0c0000 0 0x1100>;
interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
bus-range = <1 1>;
@@ -1503,6 +1574,7 @@
interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
clock-names = "pcie", "pcie_bus";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 11/16] ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
2015-08-04 12:28 ` Geert Uytterhoeven
(?)
@ 2015-08-04 12:28 ` Geert Uytterhoeven
-1 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- New.
---
arch/arm/boot/dts/r8a7793.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 3355c487d108360f..c4654047e684ff09 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -68,6 +68,7 @@
<0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0x60>;
@@ -87,6 +88,7 @@
<0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0xff>;
@@ -109,6 +111,7 @@
<0 16 IRQ_TYPE_LEVEL_HIGH>,
<0 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
+ power-domains = <&cpg_clocks>;
};
scif0: serial@e6e60000 {
@@ -117,6 +120,7 @@
interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7793_CLK_SCIF0>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -126,6 +130,7 @@
interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7793_CLK_SCIF1>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -134,6 +139,7 @@
reg = <0 0xee700000 0 0x400>;
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
+ power-domains = <&cpg_clocks>;
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
@@ -164,6 +170,7 @@
clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "z",
"rcan", "adsp";
+ #power-domain-cells = <0>;
};
/* Variable factor clocks */
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 11/16] ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: linux-clk, linux-pm, linux-sh, linux-arm-kernel, devicetree,
linux-kernel, Geert Uytterhoeven
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- New.
---
arch/arm/boot/dts/r8a7793.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 3355c487d108360f..c4654047e684ff09 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -68,6 +68,7 @@
<0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0x60>;
@@ -87,6 +88,7 @@
<0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0xff>;
@@ -109,6 +111,7 @@
<0 16 IRQ_TYPE_LEVEL_HIGH>,
<0 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
+ power-domains = <&cpg_clocks>;
};
scif0: serial@e6e60000 {
@@ -117,6 +120,7 @@
interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7793_CLK_SCIF0>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -126,6 +130,7 @@
interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7793_CLK_SCIF1>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -134,6 +139,7 @@
reg = <0 0xee700000 0 0x400>;
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
+ power-domains = <&cpg_clocks>;
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
@@ -164,6 +170,7 @@
clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "z",
"rcan", "adsp";
+ #power-domain-cells = <0>;
};
/* Variable factor clocks */
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 11/16] ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- New.
---
arch/arm/boot/dts/r8a7793.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 3355c487d108360f..c4654047e684ff09 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -68,6 +68,7 @@
<0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0x60>;
@@ -87,6 +88,7 @@
<0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0xff>;
@@ -109,6 +111,7 @@
<0 16 IRQ_TYPE_LEVEL_HIGH>,
<0 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
+ power-domains = <&cpg_clocks>;
};
scif0: serial at e6e60000 {
@@ -117,6 +120,7 @@
interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7793_CLK_SCIF0>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -126,6 +130,7 @@
interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7793_CLK_SCIF1>;
clock-names = "sci_ick";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -134,6 +139,7 @@
reg = <0 0xee700000 0 0x400>;
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
+ power-domains = <&cpg_clocks>;
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
@@ -164,6 +170,7 @@
clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "z",
"rcan", "adsp";
+ #power-domain-cells = <0>;
};
/* Variable factor clocks */
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 12/16] ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
2015-08-04 12:28 ` Geert Uytterhoeven
(?)
@ 2015-08-04 12:28 ` Geert Uytterhoeven
-1 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add "power-domains" properties to recently introduced mmcif0 device
node,
- Consistently add "power-domains" properties after clock and dma
properties,
v3:
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- Add Reviewed-by,
- Add "power-domains" properties to recently introduced USB-DMAC
device nodes,
- Drop adding "power-domains" properties to the GIC device node, as
adding the INTC_SYS clock is postponed.
---
arch/arm/boot/dts/r8a7794.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 43acf185ecc43f40..97c8e9ace5ebee1e 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -57,6 +57,7 @@
<0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0x60>;
@@ -76,6 +77,7 @@
<0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0xff>;
@@ -106,6 +108,7 @@
<0 16 IRQ_TYPE_LEVEL_HIGH>,
<0 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
+ power-domains = <&cpg_clocks>;
};
pfc: pin-controller@e6060000 {
@@ -140,6 +143,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -170,6 +174,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -182,6 +187,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x21>, <&dmac0 0x22>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -193,6 +199,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x25>, <&dmac0 0x26>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -204,6 +211,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x27>, <&dmac0 0x28>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -215,6 +223,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -226,6 +235,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -237,6 +247,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x23>, <&dmac0 0x24>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -248,6 +259,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -259,6 +271,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -270,6 +283,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -281,6 +295,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -292,6 +307,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -303,6 +319,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -314,6 +331,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -325,6 +343,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -336,6 +355,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -347,6 +367,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -358,6 +379,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -369,6 +391,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -377,6 +400,7 @@
reg = <0 0xee700000 0 0x400>;
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
+ power-domains = <&cpg_clocks>;
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
@@ -390,6 +414,7 @@
clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
reg-io-width = <4>;
status = "disabled";
};
@@ -399,6 +424,7 @@
reg = <0 0xee100000 0 0x200>;
interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -407,6 +433,7 @@
reg = <0 0xee140000 0 0x100>;
interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -415,6 +442,7 @@
reg = <0 0xee160000 0 0x100>;
interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -441,6 +469,7 @@
#clock-cells = <1>;
clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "z";
+ #power-domain-cells = <0>;
};
/* Variable factor clocks */
sd2_clk: sd2_clk@e6150078 {
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 12/16] ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: linux-clk, linux-pm, linux-sh, linux-arm-kernel, devicetree,
linux-kernel, Geert Uytterhoeven
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add "power-domains" properties to recently introduced mmcif0 device
node,
- Consistently add "power-domains" properties after clock and dma
properties,
v3:
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- Add Reviewed-by,
- Add "power-domains" properties to recently introduced USB-DMAC
device nodes,
- Drop adding "power-domains" properties to the GIC device node, as
adding the INTC_SYS clock is postponed.
---
arch/arm/boot/dts/r8a7794.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 43acf185ecc43f40..97c8e9ace5ebee1e 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -57,6 +57,7 @@
<0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0x60>;
@@ -76,6 +77,7 @@
<0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0xff>;
@@ -106,6 +108,7 @@
<0 16 IRQ_TYPE_LEVEL_HIGH>,
<0 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
+ power-domains = <&cpg_clocks>;
};
pfc: pin-controller@e6060000 {
@@ -140,6 +143,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -170,6 +174,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -182,6 +187,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x21>, <&dmac0 0x22>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -193,6 +199,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x25>, <&dmac0 0x26>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -204,6 +211,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x27>, <&dmac0 0x28>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -215,6 +223,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -226,6 +235,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -237,6 +247,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x23>, <&dmac0 0x24>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -248,6 +259,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -259,6 +271,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -270,6 +283,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -281,6 +295,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -292,6 +307,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -303,6 +319,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -314,6 +331,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -325,6 +343,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -336,6 +355,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -347,6 +367,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -358,6 +379,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -369,6 +391,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -377,6 +400,7 @@
reg = <0 0xee700000 0 0x400>;
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
+ power-domains = <&cpg_clocks>;
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
@@ -390,6 +414,7 @@
clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
reg-io-width = <4>;
status = "disabled";
};
@@ -399,6 +424,7 @@
reg = <0 0xee100000 0 0x200>;
interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -407,6 +433,7 @@
reg = <0 0xee140000 0 0x100>;
interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -415,6 +442,7 @@
reg = <0 0xee160000 0 0x100>;
interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -441,6 +469,7 @@
#clock-cells = <1>;
clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "z";
+ #power-domain-cells = <0>;
};
/* Variable factor clocks */
sd2_clk: sd2_clk@e6150078 {
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 12/16] ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.
Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock. This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add "power-domains" properties to recently introduced mmcif0 device
node,
- Consistently add "power-domains" properties after clock and dma
properties,
v3:
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- Add Reviewed-by,
- Add "power-domains" properties to recently introduced USB-DMAC
device nodes,
- Drop adding "power-domains" properties to the GIC device node, as
adding the INTC_SYS clock is postponed.
---
arch/arm/boot/dts/r8a7794.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 43acf185ecc43f40..97c8e9ace5ebee1e 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -57,6 +57,7 @@
<0 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7794_CLK_CMT0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0x60>;
@@ -76,6 +77,7 @@
<0 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7794_CLK_CMT1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
renesas,channels-mask = <0xff>;
@@ -106,6 +108,7 @@
<0 16 IRQ_TYPE_LEVEL_HIGH>,
<0 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7794_CLK_IRQC>;
+ power-domains = <&cpg_clocks>;
};
pfc: pin-controller at e6060000 {
@@ -140,6 +143,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -170,6 +174,7 @@
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
clock-names = "fck";
+ power-domains = <&cpg_clocks>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -182,6 +187,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x21>, <&dmac0 0x22>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -193,6 +199,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x25>, <&dmac0 0x26>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -204,6 +211,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x27>, <&dmac0 0x28>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -215,6 +223,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -226,6 +235,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -237,6 +247,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x23>, <&dmac0 0x24>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -248,6 +259,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -259,6 +271,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -270,6 +283,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -281,6 +295,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -292,6 +307,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -303,6 +319,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -314,6 +331,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -325,6 +343,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -336,6 +355,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -347,6 +367,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -358,6 +379,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -369,6 +391,7 @@
clock-names = "sci_ick";
dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -377,6 +400,7 @@
reg = <0 0xee700000 0 0x400>;
interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
+ power-domains = <&cpg_clocks>;
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;
@@ -390,6 +414,7 @@
clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
dma-names = "tx", "rx";
+ power-domains = <&cpg_clocks>;
reg-io-width = <4>;
status = "disabled";
};
@@ -399,6 +424,7 @@
reg = <0 0xee100000 0 0x200>;
interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -407,6 +433,7 @@
reg = <0 0xee140000 0 0x100>;
interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -415,6 +442,7 @@
reg = <0 0xee160000 0 0x100>;
interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
+ power-domains = <&cpg_clocks>;
status = "disabled";
};
@@ -441,6 +469,7 @@
#clock-cells = <1>;
clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "z";
+ #power-domain-cells = <0>;
};
/* Variable factor clocks */
sd2_clk: sd2_clk at e6150078 {
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 13/16] drivers: sh: Disable legacy default PM Domain on emev2
2015-08-04 12:28 ` Geert Uytterhoeven
(?)
(?)
@ 2015-08-04 12:28 ` Geert Uytterhoeven
-1 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
EMMA Mobile EV2 doesn't have MSTP clocks. All its device drivers manage
clocks explicitly, without relying on Runtime PM, so it doesn't need the
legacy default PM Domain.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- New, extracted from "[PATCH v2 12/14] drivers: sh: Stop using
pm_runtime.c for multi-platform shmobile with genpd".
---
drivers/sh/pm_runtime.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/sh/pm_runtime.c b/drivers/sh/pm_runtime.c
index d3d1891cda3cf9a8..ad9188138ed56ffb 100644
--- a/drivers/sh/pm_runtime.c
+++ b/drivers/sh/pm_runtime.c
@@ -35,8 +35,7 @@ static struct pm_clk_notifier_block platform_bus_notifier = {
static int __init sh_pm_runtime_init(void)
{
if (IS_ENABLED(CONFIG_ARCH_SHMOBILE_MULTI)) {
- if (!of_machine_is_compatible("renesas,emev2") &&
- !of_machine_is_compatible("renesas,r7s72100") &&
+ if (!of_machine_is_compatible("renesas,r7s72100") &&
#ifndef CONFIG_PM_GENERIC_DOMAINS_OF
!of_machine_is_compatible("renesas,r8a73a4") &&
!of_machine_is_compatible("renesas,r8a7740") &&
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 13/16] drivers: sh: Disable legacy default PM Domain on emev2
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: linux-clk, linux-pm, linux-sh, linux-arm-kernel, devicetree,
linux-kernel, Geert Uytterhoeven
EMMA Mobile EV2 doesn't have MSTP clocks. All its device drivers manage
clocks explicitly, without relying on Runtime PM, so it doesn't need the
legacy default PM Domain.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- New, extracted from "[PATCH v2 12/14] drivers: sh: Stop using
pm_runtime.c for multi-platform shmobile with genpd".
---
drivers/sh/pm_runtime.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/sh/pm_runtime.c b/drivers/sh/pm_runtime.c
index d3d1891cda3cf9a8..ad9188138ed56ffb 100644
--- a/drivers/sh/pm_runtime.c
+++ b/drivers/sh/pm_runtime.c
@@ -35,8 +35,7 @@ static struct pm_clk_notifier_block platform_bus_notifier = {
static int __init sh_pm_runtime_init(void)
{
if (IS_ENABLED(CONFIG_ARCH_SHMOBILE_MULTI)) {
- if (!of_machine_is_compatible("renesas,emev2") &&
- !of_machine_is_compatible("renesas,r7s72100") &&
+ if (!of_machine_is_compatible("renesas,r7s72100") &&
#ifndef CONFIG_PM_GENERIC_DOMAINS_OF
!of_machine_is_compatible("renesas,r8a73a4") &&
!of_machine_is_compatible("renesas,r8a7740") &&
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 13/16] drivers: sh: Disable legacy default PM Domain on emev2
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: devicetree, Geert Uytterhoeven, linux-sh, linux-pm, linux-kernel,
linux-clk, linux-arm-kernel
EMMA Mobile EV2 doesn't have MSTP clocks. All its device drivers manage
clocks explicitly, without relying on Runtime PM, so it doesn't need the
legacy default PM Domain.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- New, extracted from "[PATCH v2 12/14] drivers: sh: Stop using
pm_runtime.c for multi-platform shmobile with genpd".
---
drivers/sh/pm_runtime.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/sh/pm_runtime.c b/drivers/sh/pm_runtime.c
index d3d1891cda3cf9a8..ad9188138ed56ffb 100644
--- a/drivers/sh/pm_runtime.c
+++ b/drivers/sh/pm_runtime.c
@@ -35,8 +35,7 @@ static struct pm_clk_notifier_block platform_bus_notifier = {
static int __init sh_pm_runtime_init(void)
{
if (IS_ENABLED(CONFIG_ARCH_SHMOBILE_MULTI)) {
- if (!of_machine_is_compatible("renesas,emev2") &&
- !of_machine_is_compatible("renesas,r7s72100") &&
+ if (!of_machine_is_compatible("renesas,r7s72100") &&
#ifndef CONFIG_PM_GENERIC_DOMAINS_OF
!of_machine_is_compatible("renesas,r8a73a4") &&
!of_machine_is_compatible("renesas,r8a7740") &&
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 13/16] drivers: sh: Disable legacy default PM Domain on emev2
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
EMMA Mobile EV2 doesn't have MSTP clocks. All its device drivers manage
clocks explicitly, without relying on Runtime PM, so it doesn't need the
legacy default PM Domain.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- New, extracted from "[PATCH v2 12/14] drivers: sh: Stop using
pm_runtime.c for multi-platform shmobile with genpd".
---
drivers/sh/pm_runtime.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/sh/pm_runtime.c b/drivers/sh/pm_runtime.c
index d3d1891cda3cf9a8..ad9188138ed56ffb 100644
--- a/drivers/sh/pm_runtime.c
+++ b/drivers/sh/pm_runtime.c
@@ -35,8 +35,7 @@ static struct pm_clk_notifier_block platform_bus_notifier = {
static int __init sh_pm_runtime_init(void)
{
if (IS_ENABLED(CONFIG_ARCH_SHMOBILE_MULTI)) {
- if (!of_machine_is_compatible("renesas,emev2") &&
- !of_machine_is_compatible("renesas,r7s72100") &&
+ if (!of_machine_is_compatible("renesas,r7s72100") &&
#ifndef CONFIG_PM_GENERIC_DOMAINS_OF
!of_machine_is_compatible("renesas,r8a73a4") &&
!of_machine_is_compatible("renesas,r8a7740") &&
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 14/16] drivers: sh: Disable PM runtime for multi-platform ARM with genpd
2015-08-04 12:28 ` Geert Uytterhoeven
(?)
(?)
@ 2015-08-04 12:28 ` Geert Uytterhoeven
-1 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
If the default PM Domain using PM_CLK is used for PM runtime, the real
Clock Domain cannot be registered from DT later.
Hence do not enable it when running a multi-platform kernel with genpd
support on R-Car or RZ. The CPG/MSTP Clock Domain driver will take care
of PM runtime management of the module clocks.
Now most multi-platform ARM shmobile platforms (SH-Mobile, R-Mobile,
R-Car, RZ) use DT-based PM Domains to take care of PM runtime management
of the module clocks, simplify the platform logic by replacing the
explicit SoC checks by a single check for the presence of MSTP clocks in
DT.
Backwards-compatiblity with old DTs (mainly for R-Car Gen2) is provided
by checking for the presence of a "#power-domain-cells" property in DT.
The default PM Domain is still needed for:
- backwards-compatibility with old DTs that lack PM Domain properties,
- the CONFIG_PM=n case,
- legacy (non-DT) ARM/shmobile platforms without genpd support
(r8a7778, r8a7779),
- legacy SuperH.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- No changes,
v3:
- The runtime check must stay for the ARM multiplatform CONFIG_PM=n
case, to prevent the code from running on non-shmobile machines,
- Provide backwards-compatibility with old DTs,
- Extract EMMA Mobile EV2 removal into a separate patch,
- Replace explicit platform checks by a check for the presence of MSTP
clocks,
- Drop references to legacy r8a7740/sh73a0, which are gone,
- Rephrase description,
v2:
- Add Reviewed-by,
- Just stop compiling pm_runtime.c instead of using a runtime check,
as no multi-platform ARM platforms need this anymore.
---
drivers/sh/pm_runtime.c | 18 +++++-------------
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/drivers/sh/pm_runtime.c b/drivers/sh/pm_runtime.c
index ad9188138ed56ffb..25abd4eb7d102113 100644
--- a/drivers/sh/pm_runtime.c
+++ b/drivers/sh/pm_runtime.c
@@ -35,19 +35,11 @@ static struct pm_clk_notifier_block platform_bus_notifier = {
static int __init sh_pm_runtime_init(void)
{
if (IS_ENABLED(CONFIG_ARCH_SHMOBILE_MULTI)) {
- if (!of_machine_is_compatible("renesas,r7s72100") &&
-#ifndef CONFIG_PM_GENERIC_DOMAINS_OF
- !of_machine_is_compatible("renesas,r8a73a4") &&
- !of_machine_is_compatible("renesas,r8a7740") &&
- !of_machine_is_compatible("renesas,sh73a0") &&
-#endif
- !of_machine_is_compatible("renesas,r8a7778") &&
- !of_machine_is_compatible("renesas,r8a7779") &&
- !of_machine_is_compatible("renesas,r8a7790") &&
- !of_machine_is_compatible("renesas,r8a7791") &&
- !of_machine_is_compatible("renesas,r8a7792") &&
- !of_machine_is_compatible("renesas,r8a7793") &&
- !of_machine_is_compatible("renesas,r8a7794"))
+ if (!of_find_compatible_node(NULL, NULL,
+ "renesas,cpg-mstp-clocks"))
+ return 0;
+ if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS_OF) &&
+ of_find_node_with_property(NULL, "#power-domain-cells"))
return 0;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 14/16] drivers: sh: Disable PM runtime for multi-platform ARM with genpd
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: linux-clk, linux-pm, linux-sh, linux-arm-kernel, devicetree,
linux-kernel, Geert Uytterhoeven
If the default PM Domain using PM_CLK is used for PM runtime, the real
Clock Domain cannot be registered from DT later.
Hence do not enable it when running a multi-platform kernel with genpd
support on R-Car or RZ. The CPG/MSTP Clock Domain driver will take care
of PM runtime management of the module clocks.
Now most multi-platform ARM shmobile platforms (SH-Mobile, R-Mobile,
R-Car, RZ) use DT-based PM Domains to take care of PM runtime management
of the module clocks, simplify the platform logic by replacing the
explicit SoC checks by a single check for the presence of MSTP clocks in
DT.
Backwards-compatiblity with old DTs (mainly for R-Car Gen2) is provided
by checking for the presence of a "#power-domain-cells" property in DT.
The default PM Domain is still needed for:
- backwards-compatibility with old DTs that lack PM Domain properties,
- the CONFIG_PM=n case,
- legacy (non-DT) ARM/shmobile platforms without genpd support
(r8a7778, r8a7779),
- legacy SuperH.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- No changes,
v3:
- The runtime check must stay for the ARM multiplatform CONFIG_PM=n
case, to prevent the code from running on non-shmobile machines,
- Provide backwards-compatibility with old DTs,
- Extract EMMA Mobile EV2 removal into a separate patch,
- Replace explicit platform checks by a check for the presence of MSTP
clocks,
- Drop references to legacy r8a7740/sh73a0, which are gone,
- Rephrase description,
v2:
- Add Reviewed-by,
- Just stop compiling pm_runtime.c instead of using a runtime check,
as no multi-platform ARM platforms need this anymore.
---
drivers/sh/pm_runtime.c | 18 +++++-------------
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/drivers/sh/pm_runtime.c b/drivers/sh/pm_runtime.c
index ad9188138ed56ffb..25abd4eb7d102113 100644
--- a/drivers/sh/pm_runtime.c
+++ b/drivers/sh/pm_runtime.c
@@ -35,19 +35,11 @@ static struct pm_clk_notifier_block platform_bus_notifier = {
static int __init sh_pm_runtime_init(void)
{
if (IS_ENABLED(CONFIG_ARCH_SHMOBILE_MULTI)) {
- if (!of_machine_is_compatible("renesas,r7s72100") &&
-#ifndef CONFIG_PM_GENERIC_DOMAINS_OF
- !of_machine_is_compatible("renesas,r8a73a4") &&
- !of_machine_is_compatible("renesas,r8a7740") &&
- !of_machine_is_compatible("renesas,sh73a0") &&
-#endif
- !of_machine_is_compatible("renesas,r8a7778") &&
- !of_machine_is_compatible("renesas,r8a7779") &&
- !of_machine_is_compatible("renesas,r8a7790") &&
- !of_machine_is_compatible("renesas,r8a7791") &&
- !of_machine_is_compatible("renesas,r8a7792") &&
- !of_machine_is_compatible("renesas,r8a7793") &&
- !of_machine_is_compatible("renesas,r8a7794"))
+ if (!of_find_compatible_node(NULL, NULL,
+ "renesas,cpg-mstp-clocks"))
+ return 0;
+ if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS_OF) &&
+ of_find_node_with_property(NULL, "#power-domain-cells"))
return 0;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 14/16] drivers: sh: Disable PM runtime for multi-platform ARM with genpd
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA, linux-sh-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Geert Uytterhoeven
If the default PM Domain using PM_CLK is used for PM runtime, the real
Clock Domain cannot be registered from DT later.
Hence do not enable it when running a multi-platform kernel with genpd
support on R-Car or RZ. The CPG/MSTP Clock Domain driver will take care
of PM runtime management of the module clocks.
Now most multi-platform ARM shmobile platforms (SH-Mobile, R-Mobile,
R-Car, RZ) use DT-based PM Domains to take care of PM runtime management
of the module clocks, simplify the platform logic by replacing the
explicit SoC checks by a single check for the presence of MSTP clocks in
DT.
Backwards-compatiblity with old DTs (mainly for R-Car Gen2) is provided
by checking for the presence of a "#power-domain-cells" property in DT.
The default PM Domain is still needed for:
- backwards-compatibility with old DTs that lack PM Domain properties,
- the CONFIG_PM=n case,
- legacy (non-DT) ARM/shmobile platforms without genpd support
(r8a7778, r8a7779),
- legacy SuperH.
Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
Reviewed-by: Ulf Hansson <ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
v4:
- No changes,
v3:
- The runtime check must stay for the ARM multiplatform CONFIG_PM=n
case, to prevent the code from running on non-shmobile machines,
- Provide backwards-compatibility with old DTs,
- Extract EMMA Mobile EV2 removal into a separate patch,
- Replace explicit platform checks by a check for the presence of MSTP
clocks,
- Drop references to legacy r8a7740/sh73a0, which are gone,
- Rephrase description,
v2:
- Add Reviewed-by,
- Just stop compiling pm_runtime.c instead of using a runtime check,
as no multi-platform ARM platforms need this anymore.
---
drivers/sh/pm_runtime.c | 18 +++++-------------
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/drivers/sh/pm_runtime.c b/drivers/sh/pm_runtime.c
index ad9188138ed56ffb..25abd4eb7d102113 100644
--- a/drivers/sh/pm_runtime.c
+++ b/drivers/sh/pm_runtime.c
@@ -35,19 +35,11 @@ static struct pm_clk_notifier_block platform_bus_notifier = {
static int __init sh_pm_runtime_init(void)
{
if (IS_ENABLED(CONFIG_ARCH_SHMOBILE_MULTI)) {
- if (!of_machine_is_compatible("renesas,r7s72100") &&
-#ifndef CONFIG_PM_GENERIC_DOMAINS_OF
- !of_machine_is_compatible("renesas,r8a73a4") &&
- !of_machine_is_compatible("renesas,r8a7740") &&
- !of_machine_is_compatible("renesas,sh73a0") &&
-#endif
- !of_machine_is_compatible("renesas,r8a7778") &&
- !of_machine_is_compatible("renesas,r8a7779") &&
- !of_machine_is_compatible("renesas,r8a7790") &&
- !of_machine_is_compatible("renesas,r8a7791") &&
- !of_machine_is_compatible("renesas,r8a7792") &&
- !of_machine_is_compatible("renesas,r8a7793") &&
- !of_machine_is_compatible("renesas,r8a7794"))
+ if (!of_find_compatible_node(NULL, NULL,
+ "renesas,cpg-mstp-clocks"))
+ return 0;
+ if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS_OF) &&
+ of_find_node_with_property(NULL, "#power-domain-cells"))
return 0;
}
--
1.9.1
--
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More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 14/16] drivers: sh: Disable PM runtime for multi-platform ARM with genpd
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
If the default PM Domain using PM_CLK is used for PM runtime, the real
Clock Domain cannot be registered from DT later.
Hence do not enable it when running a multi-platform kernel with genpd
support on R-Car or RZ. The CPG/MSTP Clock Domain driver will take care
of PM runtime management of the module clocks.
Now most multi-platform ARM shmobile platforms (SH-Mobile, R-Mobile,
R-Car, RZ) use DT-based PM Domains to take care of PM runtime management
of the module clocks, simplify the platform logic by replacing the
explicit SoC checks by a single check for the presence of MSTP clocks in
DT.
Backwards-compatiblity with old DTs (mainly for R-Car Gen2) is provided
by checking for the presence of a "#power-domain-cells" property in DT.
The default PM Domain is still needed for:
- backwards-compatibility with old DTs that lack PM Domain properties,
- the CONFIG_PM=n case,
- legacy (non-DT) ARM/shmobile platforms without genpd support
(r8a7778, r8a7779),
- legacy SuperH.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- No changes,
v3:
- The runtime check must stay for the ARM multiplatform CONFIG_PM=n
case, to prevent the code from running on non-shmobile machines,
- Provide backwards-compatibility with old DTs,
- Extract EMMA Mobile EV2 removal into a separate patch,
- Replace explicit platform checks by a check for the presence of MSTP
clocks,
- Drop references to legacy r8a7740/sh73a0, which are gone,
- Rephrase description,
v2:
- Add Reviewed-by,
- Just stop compiling pm_runtime.c instead of using a runtime check,
as no multi-platform ARM platforms need this anymore.
---
drivers/sh/pm_runtime.c | 18 +++++-------------
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/drivers/sh/pm_runtime.c b/drivers/sh/pm_runtime.c
index ad9188138ed56ffb..25abd4eb7d102113 100644
--- a/drivers/sh/pm_runtime.c
+++ b/drivers/sh/pm_runtime.c
@@ -35,19 +35,11 @@ static struct pm_clk_notifier_block platform_bus_notifier = {
static int __init sh_pm_runtime_init(void)
{
if (IS_ENABLED(CONFIG_ARCH_SHMOBILE_MULTI)) {
- if (!of_machine_is_compatible("renesas,r7s72100") &&
-#ifndef CONFIG_PM_GENERIC_DOMAINS_OF
- !of_machine_is_compatible("renesas,r8a73a4") &&
- !of_machine_is_compatible("renesas,r8a7740") &&
- !of_machine_is_compatible("renesas,sh73a0") &&
-#endif
- !of_machine_is_compatible("renesas,r8a7778") &&
- !of_machine_is_compatible("renesas,r8a7779") &&
- !of_machine_is_compatible("renesas,r8a7790") &&
- !of_machine_is_compatible("renesas,r8a7791") &&
- !of_machine_is_compatible("renesas,r8a7792") &&
- !of_machine_is_compatible("renesas,r8a7793") &&
- !of_machine_is_compatible("renesas,r8a7794"))
+ if (!of_find_compatible_node(NULL, NULL,
+ "renesas,cpg-mstp-clocks"))
+ return 0;
+ if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS_OF) &&
+ of_find_node_with_property(NULL, "#power-domain-cells"))
return 0;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management
2015-08-04 12:28 ` Geert Uytterhoeven
(?)
@ 2015-08-04 12:28 ` Geert Uytterhoeven
-1 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
manage a device.
Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
the Bus State Controller (BSC) is not power-managed by an MSTP clock,
but by a plain CPG clock (zb_clk). Add a special case to handle this,
so the clock is properly managed, and devices connected to the BSC work
as expected.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
drivers/clk/shmobile/clk-mstp.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
index b1df7b2f1e970adb..a117c3f0f257b5e1 100644
--- a/drivers/clk/shmobile/clk-mstp.c
+++ b/drivers/clk/shmobile/clk-mstp.c
@@ -259,6 +259,10 @@ int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
"renesas,cpg-mstp-clocks"))
goto found;
+ /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock*/
+ if (!strcmp(clkspec.np->name, "zb_clk"))
+ goto found;
+
of_node_put(clkspec.np);
i++;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: linux-clk, linux-pm, linux-sh, linux-arm-kernel, devicetree,
linux-kernel, Geert Uytterhoeven
Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
manage a device.
Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
the Bus State Controller (BSC) is not power-managed by an MSTP clock,
but by a plain CPG clock (zb_clk). Add a special case to handle this,
so the clock is properly managed, and devices connected to the BSC work
as expected.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
drivers/clk/shmobile/clk-mstp.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
index b1df7b2f1e970adb..a117c3f0f257b5e1 100644
--- a/drivers/clk/shmobile/clk-mstp.c
+++ b/drivers/clk/shmobile/clk-mstp.c
@@ -259,6 +259,10 @@ int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
"renesas,cpg-mstp-clocks"))
goto found;
+ /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock*/
+ if (!strcmp(clkspec.np->name, "zb_clk"))
+ goto found;
+
of_node_put(clkspec.np);
i++;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
manage a device.
Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
the Bus State Controller (BSC) is not power-managed by an MSTP clock,
but by a plain CPG clock (zb_clk). Add a special case to handle this,
so the clock is properly managed, and devices connected to the BSC work
as expected.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
drivers/clk/shmobile/clk-mstp.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
index b1df7b2f1e970adb..a117c3f0f257b5e1 100644
--- a/drivers/clk/shmobile/clk-mstp.c
+++ b/drivers/clk/shmobile/clk-mstp.c
@@ -259,6 +259,10 @@ int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
"renesas,cpg-mstp-clocks"))
goto found;
+ /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock*/
+ if (!strcmp(clkspec.np->name, "zb_clk"))
+ goto found;
+
of_node_put(clkspec.np);
i++;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 16/16] ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
2015-08-04 12:28 ` Geert Uytterhoeven
(?)
(?)
@ 2015-08-04 12:28 ` Geert Uytterhoeven
-1 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
The R-Mobile PM Domain driver manages both power domains and a clock
domain.
The clock domain part is very similar to the CPG/MSTP Clock Domain,
which is used on shmobile SoCs without device power domains, except for
the way how clocks suitable for power management are selected:
- The former uses the first clock tied to the device through the NULL
con_id, which is a relic from the legacy pm_clk_notifier-based
method in drivers/sh/pm_runtime.c,
- The latter looks for suitable clocks in DT, which is more
future-proof.
All platforms using this driver are now supported in DT-based ARM
multi-platform builds only, hence switch to using the CPG/MSTP Clock
Domain helpers.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Drop -legacy support, hence this patch depends on r8a7740/sh73a0
legacy removal,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
arch/arm/mach-shmobile/pm-rmobile.c | 35 +++--------------------------------
1 file changed, 3 insertions(+), 32 deletions(-)
diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
index a5b96b990aea8dfc..89068c8ec50f2c76 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.c
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -12,6 +12,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
+#include <linux/clk/shmobile.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/of.h>
@@ -124,36 +125,6 @@ static bool rmobile_pd_active_wakeup(struct device *dev)
return true;
}
-static int rmobile_pd_attach_dev(struct generic_pm_domain *domain,
- struct device *dev)
-{
- int error;
-
- error = pm_clk_create(dev);
- if (error) {
- dev_err(dev, "pm_clk_create failed %d\n", error);
- return error;
- }
-
- error = pm_clk_add(dev, NULL);
- if (error) {
- dev_err(dev, "pm_clk_add failed %d\n", error);
- goto fail;
- }
-
- return 0;
-
-fail:
- pm_clk_destroy(dev);
- return error;
-}
-
-static void rmobile_pd_detach_dev(struct generic_pm_domain *domain,
- struct device *dev)
-{
- pm_clk_destroy(dev);
-}
-
static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
{
struct generic_pm_domain *genpd = &rmobile_pd->genpd;
@@ -164,8 +135,8 @@ static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
genpd->dev_ops.active_wakeup = rmobile_pd_active_wakeup;
genpd->power_off = rmobile_pd_power_down;
genpd->power_on = rmobile_pd_power_up;
- genpd->attach_dev = rmobile_pd_attach_dev;
- genpd->detach_dev = rmobile_pd_detach_dev;
+ genpd->attach_dev = cpg_mstp_attach_dev;
+ genpd->detach_dev = cpg_mstp_detach_dev;
__rmobile_pd_power_up(rmobile_pd, false);
}
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 16/16] ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: linux-clk, linux-pm, linux-sh, linux-arm-kernel, devicetree,
linux-kernel, Geert Uytterhoeven
The R-Mobile PM Domain driver manages both power domains and a clock
domain.
The clock domain part is very similar to the CPG/MSTP Clock Domain,
which is used on shmobile SoCs without device power domains, except for
the way how clocks suitable for power management are selected:
- The former uses the first clock tied to the device through the NULL
con_id, which is a relic from the legacy pm_clk_notifier-based
method in drivers/sh/pm_runtime.c,
- The latter looks for suitable clocks in DT, which is more
future-proof.
All platforms using this driver are now supported in DT-based ARM
multi-platform builds only, hence switch to using the CPG/MSTP Clock
Domain helpers.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Drop -legacy support, hence this patch depends on r8a7740/sh73a0
legacy removal,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
arch/arm/mach-shmobile/pm-rmobile.c | 35 +++--------------------------------
1 file changed, 3 insertions(+), 32 deletions(-)
diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
index a5b96b990aea8dfc..89068c8ec50f2c76 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.c
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -12,6 +12,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
+#include <linux/clk/shmobile.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/of.h>
@@ -124,36 +125,6 @@ static bool rmobile_pd_active_wakeup(struct device *dev)
return true;
}
-static int rmobile_pd_attach_dev(struct generic_pm_domain *domain,
- struct device *dev)
-{
- int error;
-
- error = pm_clk_create(dev);
- if (error) {
- dev_err(dev, "pm_clk_create failed %d\n", error);
- return error;
- }
-
- error = pm_clk_add(dev, NULL);
- if (error) {
- dev_err(dev, "pm_clk_add failed %d\n", error);
- goto fail;
- }
-
- return 0;
-
-fail:
- pm_clk_destroy(dev);
- return error;
-}
-
-static void rmobile_pd_detach_dev(struct generic_pm_domain *domain,
- struct device *dev)
-{
- pm_clk_destroy(dev);
-}
-
static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
{
struct generic_pm_domain *genpd = &rmobile_pd->genpd;
@@ -164,8 +135,8 @@ static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
genpd->dev_ops.active_wakeup = rmobile_pd_active_wakeup;
genpd->power_off = rmobile_pd_power_down;
genpd->power_on = rmobile_pd_power_up;
- genpd->attach_dev = rmobile_pd_attach_dev;
- genpd->detach_dev = rmobile_pd_detach_dev;
+ genpd->attach_dev = cpg_mstp_attach_dev;
+ genpd->detach_dev = cpg_mstp_detach_dev;
__rmobile_pd_power_up(rmobile_pd, false);
}
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 16/16] ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson
Cc: devicetree, Geert Uytterhoeven, linux-sh, linux-pm, linux-kernel,
linux-clk, linux-arm-kernel
The R-Mobile PM Domain driver manages both power domains and a clock
domain.
The clock domain part is very similar to the CPG/MSTP Clock Domain,
which is used on shmobile SoCs without device power domains, except for
the way how clocks suitable for power management are selected:
- The former uses the first clock tied to the device through the NULL
con_id, which is a relic from the legacy pm_clk_notifier-based
method in drivers/sh/pm_runtime.c,
- The latter looks for suitable clocks in DT, which is more
future-proof.
All platforms using this driver are now supported in DT-based ARM
multi-platform builds only, hence switch to using the CPG/MSTP Clock
Domain helpers.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Drop -legacy support, hence this patch depends on r8a7740/sh73a0
legacy removal,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
arch/arm/mach-shmobile/pm-rmobile.c | 35 +++--------------------------------
1 file changed, 3 insertions(+), 32 deletions(-)
diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
index a5b96b990aea8dfc..89068c8ec50f2c76 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.c
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -12,6 +12,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
+#include <linux/clk/shmobile.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/of.h>
@@ -124,36 +125,6 @@ static bool rmobile_pd_active_wakeup(struct device *dev)
return true;
}
-static int rmobile_pd_attach_dev(struct generic_pm_domain *domain,
- struct device *dev)
-{
- int error;
-
- error = pm_clk_create(dev);
- if (error) {
- dev_err(dev, "pm_clk_create failed %d\n", error);
- return error;
- }
-
- error = pm_clk_add(dev, NULL);
- if (error) {
- dev_err(dev, "pm_clk_add failed %d\n", error);
- goto fail;
- }
-
- return 0;
-
-fail:
- pm_clk_destroy(dev);
- return error;
-}
-
-static void rmobile_pd_detach_dev(struct generic_pm_domain *domain,
- struct device *dev)
-{
- pm_clk_destroy(dev);
-}
-
static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
{
struct generic_pm_domain *genpd = &rmobile_pd->genpd;
@@ -164,8 +135,8 @@ static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
genpd->dev_ops.active_wakeup = rmobile_pd_active_wakeup;
genpd->power_off = rmobile_pd_power_down;
genpd->power_on = rmobile_pd_power_up;
- genpd->attach_dev = rmobile_pd_attach_dev;
- genpd->detach_dev = rmobile_pd_detach_dev;
+ genpd->attach_dev = cpg_mstp_attach_dev;
+ genpd->detach_dev = cpg_mstp_detach_dev;
__rmobile_pd_power_up(rmobile_pd, false);
}
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* [PATCH v4 16/16] ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
@ 2015-08-04 12:28 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 12:28 UTC (permalink / raw)
To: linux-arm-kernel
The R-Mobile PM Domain driver manages both power domains and a clock
domain.
The clock domain part is very similar to the CPG/MSTP Clock Domain,
which is used on shmobile SoCs without device power domains, except for
the way how clocks suitable for power management are selected:
- The former uses the first clock tied to the device through the NULL
con_id, which is a relic from the legacy pm_clk_notifier-based
method in drivers/sh/pm_runtime.c,
- The latter looks for suitable clocks in DT, which is more
future-proof.
All platforms using this driver are now supported in DT-based ARM
multi-platform builds only, hence switch to using the CPG/MSTP Clock
Domain helpers.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Drop -legacy support, hence this patch depends on r8a7740/sh73a0
legacy removal,
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
arch/arm/mach-shmobile/pm-rmobile.c | 35 +++--------------------------------
1 file changed, 3 insertions(+), 32 deletions(-)
diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
index a5b96b990aea8dfc..89068c8ec50f2c76 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.c
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -12,6 +12,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
+#include <linux/clk/shmobile.h>
#include <linux/console.h>
#include <linux/delay.h>
#include <linux/of.h>
@@ -124,36 +125,6 @@ static bool rmobile_pd_active_wakeup(struct device *dev)
return true;
}
-static int rmobile_pd_attach_dev(struct generic_pm_domain *domain,
- struct device *dev)
-{
- int error;
-
- error = pm_clk_create(dev);
- if (error) {
- dev_err(dev, "pm_clk_create failed %d\n", error);
- return error;
- }
-
- error = pm_clk_add(dev, NULL);
- if (error) {
- dev_err(dev, "pm_clk_add failed %d\n", error);
- goto fail;
- }
-
- return 0;
-
-fail:
- pm_clk_destroy(dev);
- return error;
-}
-
-static void rmobile_pd_detach_dev(struct generic_pm_domain *domain,
- struct device *dev)
-{
- pm_clk_destroy(dev);
-}
-
static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
{
struct generic_pm_domain *genpd = &rmobile_pd->genpd;
@@ -164,8 +135,8 @@ static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
genpd->dev_ops.active_wakeup = rmobile_pd_active_wakeup;
genpd->power_off = rmobile_pd_power_down;
genpd->power_on = rmobile_pd_power_up;
- genpd->attach_dev = rmobile_pd_attach_dev;
- genpd->detach_dev = rmobile_pd_detach_dev;
+ genpd->attach_dev = cpg_mstp_attach_dev;
+ genpd->detach_dev = cpg_mstp_detach_dev;
__rmobile_pd_power_up(rmobile_pd, false);
}
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* Re: [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management
2015-08-04 12:28 ` Geert Uytterhoeven
(?)
(?)
@ 2015-08-04 13:20 ` Sergei Shtylyov
-1 siblings, 0 replies; 88+ messages in thread
From: Sergei Shtylyov @ 2015-08-04 13:20 UTC (permalink / raw)
To: linux-arm-kernel
Hello.
On 08/04/2015 03:28 PM, Geert Uytterhoeven wrote:
> Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
> manage a device.
> Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
> the Bus State Controller (BSC) is not power-managed by an MSTP clock,
> but by a plain CPG clock (zb_clk). Add a special case to handle this,
> so the clock is properly managed, and devices connected to the BSC work
> as expected.
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
[...]
> diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
> index b1df7b2f1e970adb..a117c3f0f257b5e1 100644
> --- a/drivers/clk/shmobile/clk-mstp.c
> +++ b/drivers/clk/shmobile/clk-mstp.c
> @@ -259,6 +259,10 @@ int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
> "renesas,cpg-mstp-clocks"))
> goto found;
>
> + /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock*/
Please add a space before */.
> + if (!strcmp(clkspec.np->name, "zb_clk"))
> + goto found;
> +
> of_node_put(clkspec.np);
> i++;
> }
MBR, Sergei
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management
@ 2015-08-04 13:20 ` Sergei Shtylyov
0 siblings, 0 replies; 88+ messages in thread
From: Sergei Shtylyov @ 2015-08-04 13:20 UTC (permalink / raw)
To: Geert Uytterhoeven, Simon Horman, Magnus Damm, Michael Turquette,
Stephen Boyd, Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman,
Ulf Hansson
Cc: linux-clk, linux-pm, linux-sh, linux-arm-kernel, devicetree,
linux-kernel
Hello.
On 08/04/2015 03:28 PM, Geert Uytterhoeven wrote:
> Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
> manage a device.
> Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
> the Bus State Controller (BSC) is not power-managed by an MSTP clock,
> but by a plain CPG clock (zb_clk). Add a special case to handle this,
> so the clock is properly managed, and devices connected to the BSC work
> as expected.
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
[...]
> diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
> index b1df7b2f1e970adb..a117c3f0f257b5e1 100644
> --- a/drivers/clk/shmobile/clk-mstp.c
> +++ b/drivers/clk/shmobile/clk-mstp.c
> @@ -259,6 +259,10 @@ int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
> "renesas,cpg-mstp-clocks"))
> goto found;
>
> + /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock*/
Please add a space before */.
> + if (!strcmp(clkspec.np->name, "zb_clk"))
> + goto found;
> +
> of_node_put(clkspec.np);
> i++;
> }
MBR, Sergei
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management
@ 2015-08-04 13:20 ` Sergei Shtylyov
0 siblings, 0 replies; 88+ messages in thread
From: Sergei Shtylyov @ 2015-08-04 13:20 UTC (permalink / raw)
To: Geert Uytterhoeven, Simon Horman, Magnus Damm, Michael Turquette,
Stephen Boyd, Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman,
Ulf Hansson
Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA, linux-sh-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Hello.
On 08/04/2015 03:28 PM, Geert Uytterhoeven wrote:
> Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
> manage a device.
> Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
> the Bus State Controller (BSC) is not power-managed by an MSTP clock,
> but by a plain CPG clock (zb_clk). Add a special case to handle this,
> so the clock is properly managed, and devices connected to the BSC work
> as expected.
> Signed-off-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
> Reviewed-by: Ulf Hansson <ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
[...]
> diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
> index b1df7b2f1e970adb..a117c3f0f257b5e1 100644
> --- a/drivers/clk/shmobile/clk-mstp.c
> +++ b/drivers/clk/shmobile/clk-mstp.c
> @@ -259,6 +259,10 @@ int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
> "renesas,cpg-mstp-clocks"))
> goto found;
>
> + /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock*/
Please add a space before */.
> + if (!strcmp(clkspec.np->name, "zb_clk"))
> + goto found;
> +
> of_node_put(clkspec.np);
> i++;
> }
MBR, Sergei
--
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^ permalink raw reply [flat|nested] 88+ messages in thread
* [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management
@ 2015-08-04 13:20 ` Sergei Shtylyov
0 siblings, 0 replies; 88+ messages in thread
From: Sergei Shtylyov @ 2015-08-04 13:20 UTC (permalink / raw)
To: linux-arm-kernel
Hello.
On 08/04/2015 03:28 PM, Geert Uytterhoeven wrote:
> Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
> manage a device.
> Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
> the Bus State Controller (BSC) is not power-managed by an MSTP clock,
> but by a plain CPG clock (zb_clk). Add a special case to handle this,
> so the clock is properly managed, and devices connected to the BSC work
> as expected.
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
[...]
> diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
> index b1df7b2f1e970adb..a117c3f0f257b5e1 100644
> --- a/drivers/clk/shmobile/clk-mstp.c
> +++ b/drivers/clk/shmobile/clk-mstp.c
> @@ -259,6 +259,10 @@ int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
> "renesas,cpg-mstp-clocks"))
> goto found;
>
> + /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock*/
Please add a space before */.
> + if (!strcmp(clkspec.np->name, "zb_clk"))
> + goto found;
> +
> of_node_put(clkspec.np);
> i++;
> }
MBR, Sergei
^ permalink raw reply [flat|nested] 88+ messages in thread
* [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management
2015-08-04 12:28 ` Geert Uytterhoeven
` (2 preceding siblings ...)
(?)
@ 2015-08-04 13:25 ` Geert Uytterhoeven
-1 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-04 13:25 UTC (permalink / raw)
To: linux-sh
Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
manage a device.
Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
the Bus State Controller (BSC) is not power-managed by an MSTP clock,
but by a plain CPG clock (zb_clk). Add a special case to handle this,
so the clock is properly managed, and devices connected to the BSC work
as expected.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
---
v4:
- Add Reviewed-by,
v3:
- Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
v2:
- New.
---
drivers/clk/shmobile/clk-mstp.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
index b1df7b2f1e970adb..a117c3f0f257b5e1 100644
--- a/drivers/clk/shmobile/clk-mstp.c
+++ b/drivers/clk/shmobile/clk-mstp.c
@@ -259,6 +259,10 @@ int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
"renesas,cpg-mstp-clocks"))
goto found;
+ /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock */
+ if (!strcmp(clkspec.np->name, "zb_clk"))
+ goto found;
+
of_node_put(clkspec.np);
i++;
}
--
1.9.1
^ permalink raw reply related [flat|nested] 88+ messages in thread
* Re: [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain
2015-08-04 12:28 ` Geert Uytterhoeven
(?)
@ 2015-08-04 13:48 ` Simon Horman
-1 siblings, 0 replies; 88+ messages in thread
From: Simon Horman @ 2015-08-04 13:48 UTC (permalink / raw)
To: linux-arm-kernel
Thanks Geert,
I have tentatively queued this up in its own branch,
cpg-mstp-clock-domain-for-v4.3.
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain
@ 2015-08-04 13:48 ` Simon Horman
0 siblings, 0 replies; 88+ messages in thread
From: Simon Horman @ 2015-08-04 13:48 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Magnus Damm, Michael Turquette, Stephen Boyd, Laurent Pinchart,
Rafael J. Wysocki, Kevin Hilman, Ulf Hansson, linux-clk,
linux-pm, linux-sh, linux-arm-kernel, devicetree, linux-kernel
Thanks Geert,
I have tentatively queued this up in its own branch,
cpg-mstp-clock-domain-for-v4.3.
^ permalink raw reply [flat|nested] 88+ messages in thread
* [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain
@ 2015-08-04 13:48 ` Simon Horman
0 siblings, 0 replies; 88+ messages in thread
From: Simon Horman @ 2015-08-04 13:48 UTC (permalink / raw)
To: linux-arm-kernel
Thanks Geert,
I have tentatively queued this up in its own branch,
cpg-mstp-clock-domain-for-v4.3.
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain
2015-08-04 13:48 ` Simon Horman
(?)
@ 2015-08-05 0:55 ` Simon Horman
-1 siblings, 0 replies; 88+ messages in thread
From: Simon Horman @ 2015-08-05 0:55 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Aug 04, 2015 at 10:48:28PM +0900, Simon Horman wrote:
> Thanks Geert,
>
> I have tentatively queued this up in its own branch,
> cpg-mstp-clock-domain-for-v4.3.
Where possible I prefer not to apply non-DTS/DTSI patches on top of
DTS/DTSI patches, I believe this is in keeping with how the ARM SoC
maintainers like things handled. With this in mind I have shuffled things
around a little, the result is:
1. The following are (still) queued up for v4.3 in their own
cpg-mstp-clock-domain-for-v4.3 branch:
clk: shmobile: Add CPG/MSTP Clock Domain support
clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
clk: shmobile: rz: Add CPG/MSTP Clock Domain support
ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
2. The following are now queued up for v4.3 in a separate
sh-drivers-for-v4.3 branch. That branch is on top of the
cpg-mstp-clock-domain-for-v4.3 branch and I intend to send it directly
to Linus if/when a v4.3-rc has been released with the patches
listed in 1. present.
drivers: sh: Disable legacy default PM Domain on emev2
drivers: sh: Disable PM runtime for multi-platform ARM with genpd
3. I have deferred the remaining two patches, listed below, for v4.4.
they currently reside in cpg-mstp-clock-domain-for-v4.4. That
branch is based on the sh-drivers-for-v4.3 branch.
clk: shmobile: mstp: Consider "zb_clk" suitable for power management
ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
This means that the last two patches will disappear from next until
after v4.3-rc1 is released but they, along with all the other patches,
will be present in the renesas devel branch.
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain
@ 2015-08-05 0:55 ` Simon Horman
0 siblings, 0 replies; 88+ messages in thread
From: Simon Horman @ 2015-08-05 0:55 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Magnus Damm, Michael Turquette, Stephen Boyd, Laurent Pinchart,
Rafael J. Wysocki, Kevin Hilman, Ulf Hansson, linux-clk,
linux-pm, linux-sh, linux-arm-kernel, devicetree, linux-kernel
On Tue, Aug 04, 2015 at 10:48:28PM +0900, Simon Horman wrote:
> Thanks Geert,
>
> I have tentatively queued this up in its own branch,
> cpg-mstp-clock-domain-for-v4.3.
Where possible I prefer not to apply non-DTS/DTSI patches on top of
DTS/DTSI patches, I believe this is in keeping with how the ARM SoC
maintainers like things handled. With this in mind I have shuffled things
around a little, the result is:
1. The following are (still) queued up for v4.3 in their own
cpg-mstp-clock-domain-for-v4.3 branch:
clk: shmobile: Add CPG/MSTP Clock Domain support
clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
clk: shmobile: rz: Add CPG/MSTP Clock Domain support
ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
2. The following are now queued up for v4.3 in a separate
sh-drivers-for-v4.3 branch. That branch is on top of the
cpg-mstp-clock-domain-for-v4.3 branch and I intend to send it directly
to Linus if/when a v4.3-rc has been released with the patches
listed in 1. present.
drivers: sh: Disable legacy default PM Domain on emev2
drivers: sh: Disable PM runtime for multi-platform ARM with genpd
3. I have deferred the remaining two patches, listed below, for v4.4.
they currently reside in cpg-mstp-clock-domain-for-v4.4. That
branch is based on the sh-drivers-for-v4.3 branch.
clk: shmobile: mstp: Consider "zb_clk" suitable for power management
ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
This means that the last two patches will disappear from next until
after v4.3-rc1 is released but they, along with all the other patches,
will be present in the renesas devel branch.
^ permalink raw reply [flat|nested] 88+ messages in thread
* [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain
@ 2015-08-05 0:55 ` Simon Horman
0 siblings, 0 replies; 88+ messages in thread
From: Simon Horman @ 2015-08-05 0:55 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Aug 04, 2015 at 10:48:28PM +0900, Simon Horman wrote:
> Thanks Geert,
>
> I have tentatively queued this up in its own branch,
> cpg-mstp-clock-domain-for-v4.3.
Where possible I prefer not to apply non-DTS/DTSI patches on top of
DTS/DTSI patches, I believe this is in keeping with how the ARM SoC
maintainers like things handled. With this in mind I have shuffled things
around a little, the result is:
1. The following are (still) queued up for v4.3 in their own
cpg-mstp-clock-domain-for-v4.3 branch:
clk: shmobile: Add CPG/MSTP Clock Domain support
clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
clk: shmobile: rz: Add CPG/MSTP Clock Domain support
ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
2. The following are now queued up for v4.3 in a separate
sh-drivers-for-v4.3 branch. That branch is on top of the
cpg-mstp-clock-domain-for-v4.3 branch and I intend to send it directly
to Linus if/when a v4.3-rc has been released with the patches
listed in 1. present.
drivers: sh: Disable legacy default PM Domain on emev2
drivers: sh: Disable PM runtime for multi-platform ARM with genpd
3. I have deferred the remaining two patches, listed below, for v4.4.
they currently reside in cpg-mstp-clock-domain-for-v4.4. That
branch is based on the sh-drivers-for-v4.3 branch.
clk: shmobile: mstp: Consider "zb_clk" suitable for power management
ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
This means that the last two patches will disappear from next until
after v4.3-rc1 is released but they, along with all the other patches,
will be present in the renesas devel branch.
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain
2015-08-05 0:55 ` Simon Horman
(?)
(?)
@ 2015-08-05 6:58 ` Geert Uytterhoeven
-1 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-05 6:58 UTC (permalink / raw)
To: linux-arm-kernel
Hi Simon,
On Wed, Aug 5, 2015 at 2:55 AM, Simon Horman <horms@verge.net.au> wrote:
> On Tue, Aug 04, 2015 at 10:48:28PM +0900, Simon Horman wrote:
>> I have tentatively queued this up in its own branch,
>> cpg-mstp-clock-domain-for-v4.3.
>
> Where possible I prefer not to apply non-DTS/DTSI patches on top of
> DTS/DTSI patches, I believe this is in keeping with how the ARM SoC
> maintainers like things handled. With this in mind I have shuffled things
> around a little, the result is:
>
> 1. The following are (still) queued up for v4.3 in their own
> cpg-mstp-clock-domain-for-v4.3 branch:
>
> clk: shmobile: Add CPG/MSTP Clock Domain support
> clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
> clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
> clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
> clk: shmobile: rz: Add CPG/MSTP Clock Domain support
> ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
OK.
> 2. The following are now queued up for v4.3 in a separate
> sh-drivers-for-v4.3 branch. That branch is on top of the
> cpg-mstp-clock-domain-for-v4.3 branch and I intend to send it directly
> to Linus if/when a v4.3-rc has been released with the patches
> listed in 1. present.
>
> drivers: sh: Disable legacy default PM Domain on emev2
> drivers: sh: Disable PM runtime for multi-platform ARM with genpd
OK
> 3. I have deferred the remaining two patches, listed below, for v4.4.
> they currently reside in cpg-mstp-clock-domain-for-v4.4. That
> branch is based on the sh-drivers-for-v4.3 branch.
>
> clk: shmobile: mstp: Consider "zb_clk" suitable for power management
> ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
>
> This means that the last two patches will disappear from next until
> after v4.3-rc1 is released but they, along with all the other patches,
> will be present in the renesas devel branch.
OK.
Note that as the last two depend on patch 1 only, you could e.g. queue
them up in group 1, between the clk and dtsi patches.
But it's up to you to reconsider.
I'm happy as-is, as the last two patches are just a code duplication clean up.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain
@ 2015-08-05 6:58 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-05 6:58 UTC (permalink / raw)
To: Simon Horman
Cc: Geert Uytterhoeven, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson,
linux-clk, Linux PM list, Linux-sh list, linux-arm-kernel,
devicetree, linux-kernel
Hi Simon,
On Wed, Aug 5, 2015 at 2:55 AM, Simon Horman <horms@verge.net.au> wrote:
> On Tue, Aug 04, 2015 at 10:48:28PM +0900, Simon Horman wrote:
>> I have tentatively queued this up in its own branch,
>> cpg-mstp-clock-domain-for-v4.3.
>
> Where possible I prefer not to apply non-DTS/DTSI patches on top of
> DTS/DTSI patches, I believe this is in keeping with how the ARM SoC
> maintainers like things handled. With this in mind I have shuffled things
> around a little, the result is:
>
> 1. The following are (still) queued up for v4.3 in their own
> cpg-mstp-clock-domain-for-v4.3 branch:
>
> clk: shmobile: Add CPG/MSTP Clock Domain support
> clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
> clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
> clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
> clk: shmobile: rz: Add CPG/MSTP Clock Domain support
> ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
OK.
> 2. The following are now queued up for v4.3 in a separate
> sh-drivers-for-v4.3 branch. That branch is on top of the
> cpg-mstp-clock-domain-for-v4.3 branch and I intend to send it directly
> to Linus if/when a v4.3-rc has been released with the patches
> listed in 1. present.
>
> drivers: sh: Disable legacy default PM Domain on emev2
> drivers: sh: Disable PM runtime for multi-platform ARM with genpd
OK
> 3. I have deferred the remaining two patches, listed below, for v4.4.
> they currently reside in cpg-mstp-clock-domain-for-v4.4. That
> branch is based on the sh-drivers-for-v4.3 branch.
>
> clk: shmobile: mstp: Consider "zb_clk" suitable for power management
> ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
>
> This means that the last two patches will disappear from next until
> after v4.3-rc1 is released but they, along with all the other patches,
> will be present in the renesas devel branch.
OK.
Note that as the last two depend on patch 1 only, you could e.g. queue
them up in group 1, between the clk and dtsi patches.
But it's up to you to reconsider.
I'm happy as-is, as the last two patches are just a code duplication clean up.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain
@ 2015-08-05 6:58 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-05 6:58 UTC (permalink / raw)
To: Simon Horman
Cc: Geert Uytterhoeven, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson,
linux-clk, Linux PM list, Linux-sh list, linux-arm-kernel,
devicetree, linux-kernel
Hi Simon,
On Wed, Aug 5, 2015 at 2:55 AM, Simon Horman <horms@verge.net.au> wrote:
> On Tue, Aug 04, 2015 at 10:48:28PM +0900, Simon Horman wrote:
>> I have tentatively queued this up in its own branch,
>> cpg-mstp-clock-domain-for-v4.3.
>
> Where possible I prefer not to apply non-DTS/DTSI patches on top of
> DTS/DTSI patches, I believe this is in keeping with how the ARM SoC
> maintainers like things handled. With this in mind I have shuffled things
> around a little, the result is:
>
> 1. The following are (still) queued up for v4.3 in their own
> cpg-mstp-clock-domain-for-v4.3 branch:
>
> clk: shmobile: Add CPG/MSTP Clock Domain support
> clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
> clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
> clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
> clk: shmobile: rz: Add CPG/MSTP Clock Domain support
> ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
OK.
> 2. The following are now queued up for v4.3 in a separate
> sh-drivers-for-v4.3 branch. That branch is on top of the
> cpg-mstp-clock-domain-for-v4.3 branch and I intend to send it directly
> to Linus if/when a v4.3-rc has been released with the patches
> listed in 1. present.
>
> drivers: sh: Disable legacy default PM Domain on emev2
> drivers: sh: Disable PM runtime for multi-platform ARM with genpd
OK
> 3. I have deferred the remaining two patches, listed below, for v4.4.
> they currently reside in cpg-mstp-clock-domain-for-v4.4. That
> branch is based on the sh-drivers-for-v4.3 branch.
>
> clk: shmobile: mstp: Consider "zb_clk" suitable for power management
> ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
>
> This means that the last two patches will disappear from next until
> after v4.3-rc1 is released but they, along with all the other patches,
> will be present in the renesas devel branch.
OK.
Note that as the last two depend on patch 1 only, you could e.g. queue
them up in group 1, between the clk and dtsi patches.
But it's up to you to reconsider.
I'm happy as-is, as the last two patches are just a code duplication clean up.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain
@ 2015-08-05 6:58 ` Geert Uytterhoeven
0 siblings, 0 replies; 88+ messages in thread
From: Geert Uytterhoeven @ 2015-08-05 6:58 UTC (permalink / raw)
To: linux-arm-kernel
Hi Simon,
On Wed, Aug 5, 2015 at 2:55 AM, Simon Horman <horms@verge.net.au> wrote:
> On Tue, Aug 04, 2015 at 10:48:28PM +0900, Simon Horman wrote:
>> I have tentatively queued this up in its own branch,
>> cpg-mstp-clock-domain-for-v4.3.
>
> Where possible I prefer not to apply non-DTS/DTSI patches on top of
> DTS/DTSI patches, I believe this is in keeping with how the ARM SoC
> maintainers like things handled. With this in mind I have shuffled things
> around a little, the result is:
>
> 1. The following are (still) queued up for v4.3 in their own
> cpg-mstp-clock-domain-for-v4.3 branch:
>
> clk: shmobile: Add CPG/MSTP Clock Domain support
> clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
> clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
> clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
> clk: shmobile: rz: Add CPG/MSTP Clock Domain support
> ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
> ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
OK.
> 2. The following are now queued up for v4.3 in a separate
> sh-drivers-for-v4.3 branch. That branch is on top of the
> cpg-mstp-clock-domain-for-v4.3 branch and I intend to send it directly
> to Linus if/when a v4.3-rc has been released with the patches
> listed in 1. present.
>
> drivers: sh: Disable legacy default PM Domain on emev2
> drivers: sh: Disable PM runtime for multi-platform ARM with genpd
OK
> 3. I have deferred the remaining two patches, listed below, for v4.4.
> they currently reside in cpg-mstp-clock-domain-for-v4.4. That
> branch is based on the sh-drivers-for-v4.3 branch.
>
> clk: shmobile: mstp: Consider "zb_clk" suitable for power management
> ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
>
> This means that the last two patches will disappear from next until
> after v4.3-rc1 is released but they, along with all the other patches,
> will be present in the renesas devel branch.
OK.
Note that as the last two depend on patch 1 only, you could e.g. queue
them up in group 1, between the clk and dtsi patches.
But it's up to you to reconsider.
I'm happy as-is, as the last two patches are just a code duplication clean up.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain
2015-08-05 6:58 ` Geert Uytterhoeven
` (2 preceding siblings ...)
(?)
@ 2015-08-06 0:50 ` Simon Horman
-1 siblings, 0 replies; 88+ messages in thread
From: Simon Horman @ 2015-08-06 0:50 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Aug 05, 2015 at 08:58:29AM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Wed, Aug 5, 2015 at 2:55 AM, Simon Horman <horms@verge.net.au> wrote:
> > On Tue, Aug 04, 2015 at 10:48:28PM +0900, Simon Horman wrote:
> >> I have tentatively queued this up in its own branch,
> >> cpg-mstp-clock-domain-for-v4.3.
> >
> > Where possible I prefer not to apply non-DTS/DTSI patches on top of
> > DTS/DTSI patches, I believe this is in keeping with how the ARM SoC
> > maintainers like things handled. With this in mind I have shuffled things
> > around a little, the result is:
> >
> > 1. The following are (still) queued up for v4.3 in their own
> > cpg-mstp-clock-domain-for-v4.3 branch:
> >
> > clk: shmobile: Add CPG/MSTP Clock Domain support
> > clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
> > clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
> > clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
> > clk: shmobile: rz: Add CPG/MSTP Clock Domain support
> > ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
>
> OK.
>
> > 2. The following are now queued up for v4.3 in a separate
> > sh-drivers-for-v4.3 branch. That branch is on top of the
> > cpg-mstp-clock-domain-for-v4.3 branch and I intend to send it directly
> > to Linus if/when a v4.3-rc has been released with the patches
> > listed in 1. present.
> >
> > drivers: sh: Disable legacy default PM Domain on emev2
> > drivers: sh: Disable PM runtime for multi-platform ARM with genpd
>
> OK
>
> > 3. I have deferred the remaining two patches, listed below, for v4.4.
> > they currently reside in cpg-mstp-clock-domain-for-v4.4. That
> > branch is based on the sh-drivers-for-v4.3 branch.
> >
> > clk: shmobile: mstp: Consider "zb_clk" suitable for power management
> > ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
> >
> > This means that the last two patches will disappear from next until
> > after v4.3-rc1 is released but they, along with all the other patches,
> > will be present in the renesas devel branch.
>
> OK.
>
> Note that as the last two depend on patch 1 only, you could e.g. queue
> them up in group 1, between the clk and dtsi patches.
> But it's up to you to reconsider.
> I'm happy as-is, as the last two patches are just a code duplication clean up.
Thanks, and sorry for not realising that.
For now I will keep things as-is because I would like to stabilise my
branches.
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain
@ 2015-08-06 0:50 ` Simon Horman
0 siblings, 0 replies; 88+ messages in thread
From: Simon Horman @ 2015-08-06 0:50 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Geert Uytterhoeven, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson,
linux-clk, Linux PM list, Linux-sh list, linux-arm-kernel,
devicetree, linux-kernel
On Wed, Aug 05, 2015 at 08:58:29AM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Wed, Aug 5, 2015 at 2:55 AM, Simon Horman <horms@verge.net.au> wrote:
> > On Tue, Aug 04, 2015 at 10:48:28PM +0900, Simon Horman wrote:
> >> I have tentatively queued this up in its own branch,
> >> cpg-mstp-clock-domain-for-v4.3.
> >
> > Where possible I prefer not to apply non-DTS/DTSI patches on top of
> > DTS/DTSI patches, I believe this is in keeping with how the ARM SoC
> > maintainers like things handled. With this in mind I have shuffled things
> > around a little, the result is:
> >
> > 1. The following are (still) queued up for v4.3 in their own
> > cpg-mstp-clock-domain-for-v4.3 branch:
> >
> > clk: shmobile: Add CPG/MSTP Clock Domain support
> > clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
> > clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
> > clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
> > clk: shmobile: rz: Add CPG/MSTP Clock Domain support
> > ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
>
> OK.
>
> > 2. The following are now queued up for v4.3 in a separate
> > sh-drivers-for-v4.3 branch. That branch is on top of the
> > cpg-mstp-clock-domain-for-v4.3 branch and I intend to send it directly
> > to Linus if/when a v4.3-rc has been released with the patches
> > listed in 1. present.
> >
> > drivers: sh: Disable legacy default PM Domain on emev2
> > drivers: sh: Disable PM runtime for multi-platform ARM with genpd
>
> OK
>
> > 3. I have deferred the remaining two patches, listed below, for v4.4.
> > they currently reside in cpg-mstp-clock-domain-for-v4.4. That
> > branch is based on the sh-drivers-for-v4.3 branch.
> >
> > clk: shmobile: mstp: Consider "zb_clk" suitable for power management
> > ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
> >
> > This means that the last two patches will disappear from next until
> > after v4.3-rc1 is released but they, along with all the other patches,
> > will be present in the renesas devel branch.
>
> OK.
>
> Note that as the last two depend on patch 1 only, you could e.g. queue
> them up in group 1, between the clk and dtsi patches.
> But it's up to you to reconsider.
> I'm happy as-is, as the last two patches are just a code duplication clean up.
Thanks, and sorry for not realising that.
For now I will keep things as-is because I would like to stabilise my
branches.
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain
@ 2015-08-06 0:50 ` Simon Horman
0 siblings, 0 replies; 88+ messages in thread
From: Simon Horman @ 2015-08-06 0:50 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Geert Uytterhoeven, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson,
linux-clk-u79uwXL29TY76Z2rM5mHXA, Linux PM list, Linux-sh list,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On Wed, Aug 05, 2015 at 08:58:29AM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Wed, Aug 5, 2015 at 2:55 AM, Simon Horman <horms-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org> wrote:
> > On Tue, Aug 04, 2015 at 10:48:28PM +0900, Simon Horman wrote:
> >> I have tentatively queued this up in its own branch,
> >> cpg-mstp-clock-domain-for-v4.3.
> >
> > Where possible I prefer not to apply non-DTS/DTSI patches on top of
> > DTS/DTSI patches, I believe this is in keeping with how the ARM SoC
> > maintainers like things handled. With this in mind I have shuffled things
> > around a little, the result is:
> >
> > 1. The following are (still) queued up for v4.3 in their own
> > cpg-mstp-clock-domain-for-v4.3 branch:
> >
> > clk: shmobile: Add CPG/MSTP Clock Domain support
> > clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
> > clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
> > clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
> > clk: shmobile: rz: Add CPG/MSTP Clock Domain support
> > ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
>
> OK.
>
> > 2. The following are now queued up for v4.3 in a separate
> > sh-drivers-for-v4.3 branch. That branch is on top of the
> > cpg-mstp-clock-domain-for-v4.3 branch and I intend to send it directly
> > to Linus if/when a v4.3-rc has been released with the patches
> > listed in 1. present.
> >
> > drivers: sh: Disable legacy default PM Domain on emev2
> > drivers: sh: Disable PM runtime for multi-platform ARM with genpd
>
> OK
>
> > 3. I have deferred the remaining two patches, listed below, for v4.4.
> > they currently reside in cpg-mstp-clock-domain-for-v4.4. That
> > branch is based on the sh-drivers-for-v4.3 branch.
> >
> > clk: shmobile: mstp: Consider "zb_clk" suitable for power management
> > ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
> >
> > This means that the last two patches will disappear from next until
> > after v4.3-rc1 is released but they, along with all the other patches,
> > will be present in the renesas devel branch.
>
> OK.
>
> Note that as the last two depend on patch 1 only, you could e.g. queue
> them up in group 1, between the clk and dtsi patches.
> But it's up to you to reconsider.
> I'm happy as-is, as the last two patches are just a code duplication clean up.
Thanks, and sorry for not realising that.
For now I will keep things as-is because I would like to stabilise my
branches.
--
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^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain
@ 2015-08-06 0:50 ` Simon Horman
0 siblings, 0 replies; 88+ messages in thread
From: Simon Horman @ 2015-08-06 0:50 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Geert Uytterhoeven, Magnus Damm, Michael Turquette, Stephen Boyd,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson,
linux-clk, Linux PM list, Linux-sh list, linux-arm-kernel,
devicetree, linux-kernel
On Wed, Aug 05, 2015 at 08:58:29AM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Wed, Aug 5, 2015 at 2:55 AM, Simon Horman <horms@verge.net.au> wrote:
> > On Tue, Aug 04, 2015 at 10:48:28PM +0900, Simon Horman wrote:
> >> I have tentatively queued this up in its own branch,
> >> cpg-mstp-clock-domain-for-v4.3.
> >
> > Where possible I prefer not to apply non-DTS/DTSI patches on top of
> > DTS/DTSI patches, I believe this is in keeping with how the ARM SoC
> > maintainers like things handled. With this in mind I have shuffled things
> > around a little, the result is:
> >
> > 1. The following are (still) queued up for v4.3 in their own
> > cpg-mstp-clock-domain-for-v4.3 branch:
> >
> > clk: shmobile: Add CPG/MSTP Clock Domain support
> > clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
> > clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
> > clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
> > clk: shmobile: rz: Add CPG/MSTP Clock Domain support
> > ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
>
> OK.
>
> > 2. The following are now queued up for v4.3 in a separate
> > sh-drivers-for-v4.3 branch. That branch is on top of the
> > cpg-mstp-clock-domain-for-v4.3 branch and I intend to send it directly
> > to Linus if/when a v4.3-rc has been released with the patches
> > listed in 1. present.
> >
> > drivers: sh: Disable legacy default PM Domain on emev2
> > drivers: sh: Disable PM runtime for multi-platform ARM with genpd
>
> OK
>
> > 3. I have deferred the remaining two patches, listed below, for v4.4.
> > they currently reside in cpg-mstp-clock-domain-for-v4.4. That
> > branch is based on the sh-drivers-for-v4.3 branch.
> >
> > clk: shmobile: mstp: Consider "zb_clk" suitable for power management
> > ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
> >
> > This means that the last two patches will disappear from next until
> > after v4.3-rc1 is released but they, along with all the other patches,
> > will be present in the renesas devel branch.
>
> OK.
>
> Note that as the last two depend on patch 1 only, you could e.g. queue
> them up in group 1, between the clk and dtsi patches.
> But it's up to you to reconsider.
> I'm happy as-is, as the last two patches are just a code duplication clean up.
Thanks, and sorry for not realising that.
For now I will keep things as-is because I would like to stabilise my
branches.
^ permalink raw reply [flat|nested] 88+ messages in thread
* [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain
@ 2015-08-06 0:50 ` Simon Horman
0 siblings, 0 replies; 88+ messages in thread
From: Simon Horman @ 2015-08-06 0:50 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Aug 05, 2015 at 08:58:29AM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Wed, Aug 5, 2015 at 2:55 AM, Simon Horman <horms@verge.net.au> wrote:
> > On Tue, Aug 04, 2015 at 10:48:28PM +0900, Simon Horman wrote:
> >> I have tentatively queued this up in its own branch,
> >> cpg-mstp-clock-domain-for-v4.3.
> >
> > Where possible I prefer not to apply non-DTS/DTSI patches on top of
> > DTS/DTSI patches, I believe this is in keeping with how the ARM SoC
> > maintainers like things handled. With this in mind I have shuffled things
> > around a little, the result is:
> >
> > 1. The following are (still) queued up for v4.3 in their own
> > cpg-mstp-clock-domain-for-v4.3 branch:
> >
> > clk: shmobile: Add CPG/MSTP Clock Domain support
> > clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
> > clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
> > clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
> > clk: shmobile: rz: Add CPG/MSTP Clock Domain support
> > ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
> > ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
>
> OK.
>
> > 2. The following are now queued up for v4.3 in a separate
> > sh-drivers-for-v4.3 branch. That branch is on top of the
> > cpg-mstp-clock-domain-for-v4.3 branch and I intend to send it directly
> > to Linus if/when a v4.3-rc has been released with the patches
> > listed in 1. present.
> >
> > drivers: sh: Disable legacy default PM Domain on emev2
> > drivers: sh: Disable PM runtime for multi-platform ARM with genpd
>
> OK
>
> > 3. I have deferred the remaining two patches, listed below, for v4.4.
> > they currently reside in cpg-mstp-clock-domain-for-v4.4. That
> > branch is based on the sh-drivers-for-v4.3 branch.
> >
> > clk: shmobile: mstp: Consider "zb_clk" suitable for power management
> > ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers
> >
> > This means that the last two patches will disappear from next until
> > after v4.3-rc1 is released but they, along with all the other patches,
> > will be present in the renesas devel branch.
>
> OK.
>
> Note that as the last two depend on patch 1 only, you could e.g. queue
> them up in group 1, between the clk and dtsi patches.
> But it's up to you to reconsider.
> I'm happy as-is, as the last two patches are just a code duplication clean up.
Thanks, and sorry for not realising that.
For now I will keep things as-is because I would like to stabilise my
branches.
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management
2015-08-04 12:28 ` Geert Uytterhoeven
(?)
@ 2015-09-17 8:45 ` Simon Horman
-1 siblings, 0 replies; 88+ messages in thread
From: Simon Horman @ 2015-09-17 8:45 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mike, Hi Stephen,
On Tue, Aug 04, 2015 at 02:28:16PM +0200, Geert Uytterhoeven wrote:
> Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
> manage a device.
>
> Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
> the Bus State Controller (BSC) is not power-managed by an MSTP clock,
> but by a plain CPG clock (zb_clk). Add a special case to handle this,
> so the clock is properly managed, and devices connected to the BSC work
> as expected.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
for one reason or another I seem to have this patch queued up in
my renesas tree for v4.4, without any Acks.
I think it would be best if one of you took the patch instead.
Though I'm also happy to take it with Acks.
Let me know how you would like to proceed.
> ---
> v4:
> - Add Reviewed-by,
>
> v3:
> - Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
>
> v2:
> - New.
> ---
> drivers/clk/shmobile/clk-mstp.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
> index b1df7b2f1e970adb..a117c3f0f257b5e1 100644
> --- a/drivers/clk/shmobile/clk-mstp.c
> +++ b/drivers/clk/shmobile/clk-mstp.c
> @@ -259,6 +259,10 @@ int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
> "renesas,cpg-mstp-clocks"))
> goto found;
>
> + /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock*/
> + if (!strcmp(clkspec.np->name, "zb_clk"))
> + goto found;
> +
> of_node_put(clkspec.np);
> i++;
> }
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management
@ 2015-09-17 8:45 ` Simon Horman
0 siblings, 0 replies; 88+ messages in thread
From: Simon Horman @ 2015-09-17 8:45 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Geert Uytterhoeven, Magnus Damm, Laurent Pinchart,
Rafael J. Wysocki, Kevin Hilman, Ulf Hansson, linux-clk,
linux-pm, linux-sh, linux-arm-kernel, devicetree, linux-kernel
Hi Mike, Hi Stephen,
On Tue, Aug 04, 2015 at 02:28:16PM +0200, Geert Uytterhoeven wrote:
> Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
> manage a device.
>
> Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
> the Bus State Controller (BSC) is not power-managed by an MSTP clock,
> but by a plain CPG clock (zb_clk). Add a special case to handle this,
> so the clock is properly managed, and devices connected to the BSC work
> as expected.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
for one reason or another I seem to have this patch queued up in
my renesas tree for v4.4, without any Acks.
I think it would be best if one of you took the patch instead.
Though I'm also happy to take it with Acks.
Let me know how you would like to proceed.
> ---
> v4:
> - Add Reviewed-by,
>
> v3:
> - Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
>
> v2:
> - New.
> ---
> drivers/clk/shmobile/clk-mstp.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
> index b1df7b2f1e970adb..a117c3f0f257b5e1 100644
> --- a/drivers/clk/shmobile/clk-mstp.c
> +++ b/drivers/clk/shmobile/clk-mstp.c
> @@ -259,6 +259,10 @@ int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
> "renesas,cpg-mstp-clocks"))
> goto found;
>
> + /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock*/
> + if (!strcmp(clkspec.np->name, "zb_clk"))
> + goto found;
> +
> of_node_put(clkspec.np);
> i++;
> }
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 88+ messages in thread
* [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management
@ 2015-09-17 8:45 ` Simon Horman
0 siblings, 0 replies; 88+ messages in thread
From: Simon Horman @ 2015-09-17 8:45 UTC (permalink / raw)
To: linux-arm-kernel
Hi Mike, Hi Stephen,
On Tue, Aug 04, 2015 at 02:28:16PM +0200, Geert Uytterhoeven wrote:
> Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
> manage a device.
>
> Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
> the Bus State Controller (BSC) is not power-managed by an MSTP clock,
> but by a plain CPG clock (zb_clk). Add a special case to handle this,
> so the clock is properly managed, and devices connected to the BSC work
> as expected.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
for one reason or another I seem to have this patch queued up in
my renesas tree for v4.4, without any Acks.
I think it would be best if one of you took the patch instead.
Though I'm also happy to take it with Acks.
Let me know how you would like to proceed.
> ---
> v4:
> - Add Reviewed-by,
>
> v3:
> - Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
>
> v2:
> - New.
> ---
> drivers/clk/shmobile/clk-mstp.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
> index b1df7b2f1e970adb..a117c3f0f257b5e1 100644
> --- a/drivers/clk/shmobile/clk-mstp.c
> +++ b/drivers/clk/shmobile/clk-mstp.c
> @@ -259,6 +259,10 @@ int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
> "renesas,cpg-mstp-clocks"))
> goto found;
>
> + /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock*/
> + if (!strcmp(clkspec.np->name, "zb_clk"))
> + goto found;
> +
> of_node_put(clkspec.np);
> i++;
> }
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management
2015-09-17 8:45 ` Simon Horman
(?)
@ 2015-09-17 8:53 ` Simon Horman
-1 siblings, 0 replies; 88+ messages in thread
From: Simon Horman @ 2015-09-17 8:53 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Sep 17, 2015 at 05:45:18PM +0900, Simon Horman wrote:
> Hi Mike, Hi Stephen,
>
> On Tue, Aug 04, 2015 at 02:28:16PM +0200, Geert Uytterhoeven wrote:
> > Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
> > manage a device.
> >
> > Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
> > the Bus State Controller (BSC) is not power-managed by an MSTP clock,
> > but by a plain CPG clock (zb_clk). Add a special case to handle this,
> > so the clock is properly managed, and devices connected to the BSC work
> > as expected.
> >
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
>
> for one reason or another I seem to have this patch queued up in
> my renesas tree for v4.4, without any Acks.
>
> I think it would be best if one of you took the patch instead.
> Though I'm also happy to take it with Acks.
>
> Let me know how you would like to proceed.
Sorry to revise the above, I should have checked more closely
before I sent my previous email. I now see that I have an SoC patch
that depends on this one. So if possible I'd like to take this one
through my tree with an Ack or two.
Thanks in advance!
> > ---
> > v4:
> > - Add Reviewed-by,
> >
> > v3:
> > - Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
> >
> > v2:
> > - New.
> > ---
> > drivers/clk/shmobile/clk-mstp.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
> > index b1df7b2f1e970adb..a117c3f0f257b5e1 100644
> > --- a/drivers/clk/shmobile/clk-mstp.c
> > +++ b/drivers/clk/shmobile/clk-mstp.c
> > @@ -259,6 +259,10 @@ int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
> > "renesas,cpg-mstp-clocks"))
> > goto found;
> >
> > + /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock*/
> > + if (!strcmp(clkspec.np->name, "zb_clk"))
> > + goto found;
> > +
> > of_node_put(clkspec.np);
> > i++;
> > }
> > --
> > 1.9.1
> >
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management
@ 2015-09-17 8:53 ` Simon Horman
0 siblings, 0 replies; 88+ messages in thread
From: Simon Horman @ 2015-09-17 8:53 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Geert Uytterhoeven, Magnus Damm, Laurent Pinchart,
Rafael J. Wysocki, Kevin Hilman, Ulf Hansson, linux-clk,
linux-pm, linux-sh, linux-arm-kernel, devicetree, linux-kernel
On Thu, Sep 17, 2015 at 05:45:18PM +0900, Simon Horman wrote:
> Hi Mike, Hi Stephen,
>
> On Tue, Aug 04, 2015 at 02:28:16PM +0200, Geert Uytterhoeven wrote:
> > Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
> > manage a device.
> >
> > Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
> > the Bus State Controller (BSC) is not power-managed by an MSTP clock,
> > but by a plain CPG clock (zb_clk). Add a special case to handle this,
> > so the clock is properly managed, and devices connected to the BSC work
> > as expected.
> >
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
>
> for one reason or another I seem to have this patch queued up in
> my renesas tree for v4.4, without any Acks.
>
> I think it would be best if one of you took the patch instead.
> Though I'm also happy to take it with Acks.
>
> Let me know how you would like to proceed.
Sorry to revise the above, I should have checked more closely
before I sent my previous email. I now see that I have an SoC patch
that depends on this one. So if possible I'd like to take this one
through my tree with an Ack or two.
Thanks in advance!
> > ---
> > v4:
> > - Add Reviewed-by,
> >
> > v3:
> > - Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
> >
> > v2:
> > - New.
> > ---
> > drivers/clk/shmobile/clk-mstp.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
> > index b1df7b2f1e970adb..a117c3f0f257b5e1 100644
> > --- a/drivers/clk/shmobile/clk-mstp.c
> > +++ b/drivers/clk/shmobile/clk-mstp.c
> > @@ -259,6 +259,10 @@ int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
> > "renesas,cpg-mstp-clocks"))
> > goto found;
> >
> > + /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock*/
> > + if (!strcmp(clkspec.np->name, "zb_clk"))
> > + goto found;
> > +
> > of_node_put(clkspec.np);
> > i++;
> > }
> > --
> > 1.9.1
> >
^ permalink raw reply [flat|nested] 88+ messages in thread
* [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management
@ 2015-09-17 8:53 ` Simon Horman
0 siblings, 0 replies; 88+ messages in thread
From: Simon Horman @ 2015-09-17 8:53 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Sep 17, 2015 at 05:45:18PM +0900, Simon Horman wrote:
> Hi Mike, Hi Stephen,
>
> On Tue, Aug 04, 2015 at 02:28:16PM +0200, Geert Uytterhoeven wrote:
> > Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
> > manage a device.
> >
> > Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
> > the Bus State Controller (BSC) is not power-managed by an MSTP clock,
> > but by a plain CPG clock (zb_clk). Add a special case to handle this,
> > so the clock is properly managed, and devices connected to the BSC work
> > as expected.
> >
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
>
> for one reason or another I seem to have this patch queued up in
> my renesas tree for v4.4, without any Acks.
>
> I think it would be best if one of you took the patch instead.
> Though I'm also happy to take it with Acks.
>
> Let me know how you would like to proceed.
Sorry to revise the above, I should have checked more closely
before I sent my previous email. I now see that I have an SoC patch
that depends on this one. So if possible I'd like to take this one
through my tree with an Ack or two.
Thanks in advance!
> > ---
> > v4:
> > - Add Reviewed-by,
> >
> > v3:
> > - Use "CPG/MSTP Clock Domain" instead of "CPG Clock Domain",
> >
> > v2:
> > - New.
> > ---
> > drivers/clk/shmobile/clk-mstp.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/clk/shmobile/clk-mstp.c b/drivers/clk/shmobile/clk-mstp.c
> > index b1df7b2f1e970adb..a117c3f0f257b5e1 100644
> > --- a/drivers/clk/shmobile/clk-mstp.c
> > +++ b/drivers/clk/shmobile/clk-mstp.c
> > @@ -259,6 +259,10 @@ int cpg_mstp_attach_dev(struct generic_pm_domain *domain, struct device *dev)
> > "renesas,cpg-mstp-clocks"))
> > goto found;
> >
> > + /* BSC on r8a73a4/sh73a0 uses zb_clk instead of an mstp clock*/
> > + if (!strcmp(clkspec.np->name, "zb_clk"))
> > + goto found;
> > +
> > of_node_put(clkspec.np);
> > i++;
> > }
> > --
> > 1.9.1
> >
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management
2015-09-17 8:53 ` Simon Horman
(?)
@ 2015-09-17 22:24 ` Stephen Boyd
-1 siblings, 0 replies; 88+ messages in thread
From: Stephen Boyd @ 2015-09-17 22:24 UTC (permalink / raw)
To: linux-arm-kernel
On 09/17, Simon Horman wrote:
> On Thu, Sep 17, 2015 at 05:45:18PM +0900, Simon Horman wrote:
> > Hi Mike, Hi Stephen,
> >
> > On Tue, Aug 04, 2015 at 02:28:16PM +0200, Geert Uytterhoeven wrote:
> > > Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
> > > manage a device.
> > >
> > > Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
> > > the Bus State Controller (BSC) is not power-managed by an MSTP clock,
> > > but by a plain CPG clock (zb_clk). Add a special case to handle this,
> > > so the clock is properly managed, and devices connected to the BSC work
> > > as expected.
> > >
> > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
> >
> > for one reason or another I seem to have this patch queued up in
> > my renesas tree for v4.4, without any Acks.
> >
> > I think it would be best if one of you took the patch instead.
> > Though I'm also happy to take it with Acks.
> >
> > Let me know how you would like to proceed.
>
> Sorry to revise the above, I should have checked more closely
> before I sent my previous email. I now see that I have an SoC patch
> that depends on this one. So if possible I'd like to take this one
> through my tree with an Ack or two.
>
Sure.
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management
@ 2015-09-17 22:24 ` Stephen Boyd
0 siblings, 0 replies; 88+ messages in thread
From: Stephen Boyd @ 2015-09-17 22:24 UTC (permalink / raw)
To: Simon Horman
Cc: Michael Turquette, Geert Uytterhoeven, Magnus Damm,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson,
linux-clk, linux-pm, linux-sh, linux-arm-kernel, devicetree,
linux-kernel
On 09/17, Simon Horman wrote:
> On Thu, Sep 17, 2015 at 05:45:18PM +0900, Simon Horman wrote:
> > Hi Mike, Hi Stephen,
> >
> > On Tue, Aug 04, 2015 at 02:28:16PM +0200, Geert Uytterhoeven wrote:
> > > Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
> > > manage a device.
> > >
> > > Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
> > > the Bus State Controller (BSC) is not power-managed by an MSTP clock,
> > > but by a plain CPG clock (zb_clk). Add a special case to handle this,
> > > so the clock is properly managed, and devices connected to the BSC work
> > > as expected.
> > >
> > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
> >
> > for one reason or another I seem to have this patch queued up in
> > my renesas tree for v4.4, without any Acks.
> >
> > I think it would be best if one of you took the patch instead.
> > Though I'm also happy to take it with Acks.
> >
> > Let me know how you would like to proceed.
>
> Sorry to revise the above, I should have checked more closely
> before I sent my previous email. I now see that I have an SoC patch
> that depends on this one. So if possible I'd like to take this one
> through my tree with an Ack or two.
>
Sure.
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 88+ messages in thread
* [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management
@ 2015-09-17 22:24 ` Stephen Boyd
0 siblings, 0 replies; 88+ messages in thread
From: Stephen Boyd @ 2015-09-17 22:24 UTC (permalink / raw)
To: linux-arm-kernel
On 09/17, Simon Horman wrote:
> On Thu, Sep 17, 2015 at 05:45:18PM +0900, Simon Horman wrote:
> > Hi Mike, Hi Stephen,
> >
> > On Tue, Aug 04, 2015 at 02:28:16PM +0200, Geert Uytterhoeven wrote:
> > > Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
> > > manage a device.
> > >
> > > Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
> > > the Bus State Controller (BSC) is not power-managed by an MSTP clock,
> > > but by a plain CPG clock (zb_clk). Add a special case to handle this,
> > > so the clock is properly managed, and devices connected to the BSC work
> > > as expected.
> > >
> > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
> >
> > for one reason or another I seem to have this patch queued up in
> > my renesas tree for v4.4, without any Acks.
> >
> > I think it would be best if one of you took the patch instead.
> > Though I'm also happy to take it with Acks.
> >
> > Let me know how you would like to proceed.
>
> Sorry to revise the above, I should have checked more closely
> before I sent my previous email. I now see that I have an SoC patch
> that depends on this one. So if possible I'd like to take this one
> through my tree with an Ack or two.
>
Sure.
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management
2015-09-17 22:24 ` Stephen Boyd
(?)
@ 2015-09-18 0:12 ` Simon Horman
-1 siblings, 0 replies; 88+ messages in thread
From: Simon Horman @ 2015-09-18 0:12 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Sep 17, 2015 at 03:24:54PM -0700, Stephen Boyd wrote:
> On 09/17, Simon Horman wrote:
> > On Thu, Sep 17, 2015 at 05:45:18PM +0900, Simon Horman wrote:
> > > Hi Mike, Hi Stephen,
> > >
> > > On Tue, Aug 04, 2015 at 02:28:16PM +0200, Geert Uytterhoeven wrote:
> > > > Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
> > > > manage a device.
> > > >
> > > > Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
> > > > the Bus State Controller (BSC) is not power-managed by an MSTP clock,
> > > > but by a plain CPG clock (zb_clk). Add a special case to handle this,
> > > > so the clock is properly managed, and devices connected to the BSC work
> > > > as expected.
> > > >
> > > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > > Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
> > >
> > > for one reason or another I seem to have this patch queued up in
> > > my renesas tree for v4.4, without any Acks.
> > >
> > > I think it would be best if one of you took the patch instead.
> > > Though I'm also happy to take it with Acks.
> > >
> > > Let me know how you would like to proceed.
> >
> > Sorry to revise the above, I should have checked more closely
> > before I sent my previous email. I now see that I have an SoC patch
> > that depends on this one. So if possible I'd like to take this one
> > through my tree with an Ack or two.
> >
>
> Sure.
>
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Thanks, much appreciated.
^ permalink raw reply [flat|nested] 88+ messages in thread
* Re: [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management
@ 2015-09-18 0:12 ` Simon Horman
0 siblings, 0 replies; 88+ messages in thread
From: Simon Horman @ 2015-09-18 0:12 UTC (permalink / raw)
To: Stephen Boyd
Cc: Michael Turquette, Geert Uytterhoeven, Magnus Damm,
Laurent Pinchart, Rafael J. Wysocki, Kevin Hilman, Ulf Hansson,
linux-clk, linux-pm, linux-sh, linux-arm-kernel, devicetree,
linux-kernel
On Thu, Sep 17, 2015 at 03:24:54PM -0700, Stephen Boyd wrote:
> On 09/17, Simon Horman wrote:
> > On Thu, Sep 17, 2015 at 05:45:18PM +0900, Simon Horman wrote:
> > > Hi Mike, Hi Stephen,
> > >
> > > On Tue, Aug 04, 2015 at 02:28:16PM +0200, Geert Uytterhoeven wrote:
> > > > Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
> > > > manage a device.
> > > >
> > > > Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
> > > > the Bus State Controller (BSC) is not power-managed by an MSTP clock,
> > > > but by a plain CPG clock (zb_clk). Add a special case to handle this,
> > > > so the clock is properly managed, and devices connected to the BSC work
> > > > as expected.
> > > >
> > > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > > Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
> > >
> > > for one reason or another I seem to have this patch queued up in
> > > my renesas tree for v4.4, without any Acks.
> > >
> > > I think it would be best if one of you took the patch instead.
> > > Though I'm also happy to take it with Acks.
> > >
> > > Let me know how you would like to proceed.
> >
> > Sorry to revise the above, I should have checked more closely
> > before I sent my previous email. I now see that I have an SoC patch
> > that depends on this one. So if possible I'd like to take this one
> > through my tree with an Ack or two.
> >
>
> Sure.
>
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Thanks, much appreciated.
^ permalink raw reply [flat|nested] 88+ messages in thread
* [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management
@ 2015-09-18 0:12 ` Simon Horman
0 siblings, 0 replies; 88+ messages in thread
From: Simon Horman @ 2015-09-18 0:12 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Sep 17, 2015 at 03:24:54PM -0700, Stephen Boyd wrote:
> On 09/17, Simon Horman wrote:
> > On Thu, Sep 17, 2015 at 05:45:18PM +0900, Simon Horman wrote:
> > > Hi Mike, Hi Stephen,
> > >
> > > On Tue, Aug 04, 2015 at 02:28:16PM +0200, Geert Uytterhoeven wrote:
> > > > Currently the CPG/MSTP Clock Domain code looks for MSTP clocks to power
> > > > manage a device.
> > > >
> > > > Unfortunately, on R-Mobile APE6 (r8a73a4) and SH-Mobile AG5 (sh73a0),
> > > > the Bus State Controller (BSC) is not power-managed by an MSTP clock,
> > > > but by a plain CPG clock (zb_clk). Add a special case to handle this,
> > > > so the clock is properly managed, and devices connected to the BSC work
> > > > as expected.
> > > >
> > > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > > Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
> > >
> > > for one reason or another I seem to have this patch queued up in
> > > my renesas tree for v4.4, without any Acks.
> > >
> > > I think it would be best if one of you took the patch instead.
> > > Though I'm also happy to take it with Acks.
> > >
> > > Let me know how you would like to proceed.
> >
> > Sorry to revise the above, I should have checked more closely
> > before I sent my previous email. I now see that I have an SoC patch
> > that depends on this one. So if possible I'd like to take this one
> > through my tree with an Ack or two.
> >
>
> Sure.
>
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Thanks, much appreciated.
^ permalink raw reply [flat|nested] 88+ messages in thread
end of thread, other threads:[~2015-09-18 0:12 UTC | newest]
Thread overview: 88+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-08-04 12:28 [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` [PATCH v4 01/16] clk: shmobile: Add CPG/MSTP Clock Domain support Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` [PATCH v4 02/16] clk: shmobile: r8a7778: " Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` [PATCH v4 03/16] clk: shmobile: r8a7779: " Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` [PATCH v4 04/16] clk: shmobile: rcar-gen2: " Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` [PATCH v4 05/16] clk: shmobile: rz: " Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` [PATCH v4 06/16] ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` [PATCH v4 07/16] ARM: shmobile: r8a7778 " Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` [PATCH v4 08/16] ARM: shmobile: r8a7779 " Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` [PATCH v4 09/16] ARM: shmobile: r8a7790 " Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` [PATCH v4 10/16] ARM: shmobile: r8a7791 " Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` [PATCH v4 11/16] ARM: shmobile: r8a7793 " Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` [PATCH v4 12/16] ARM: shmobile: r8a7794 " Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` [PATCH v4 13/16] drivers: sh: Disable legacy default PM Domain on emev2 Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` [PATCH v4 14/16] drivers: sh: Disable PM runtime for multi-platform ARM with genpd Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` [PATCH v4 15/16] clk: shmobile: mstp: Consider "zb_clk" suitable for power management Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 13:20 ` Sergei Shtylyov
2015-08-04 13:20 ` Sergei Shtylyov
2015-08-04 13:20 ` Sergei Shtylyov
2015-08-04 13:20 ` Sergei Shtylyov
2015-08-04 13:25 ` Geert Uytterhoeven
2015-09-17 8:45 ` Simon Horman
2015-09-17 8:45 ` Simon Horman
2015-09-17 8:45 ` Simon Horman
2015-09-17 8:53 ` Simon Horman
2015-09-17 8:53 ` Simon Horman
2015-09-17 8:53 ` Simon Horman
2015-09-17 22:24 ` Stephen Boyd
2015-09-17 22:24 ` Stephen Boyd
2015-09-17 22:24 ` Stephen Boyd
2015-09-18 0:12 ` Simon Horman
2015-09-18 0:12 ` Simon Horman
2015-09-18 0:12 ` Simon Horman
2015-08-04 12:28 ` [PATCH v4 16/16] ARM: shmobile: R-Mobile: Use CPG/MSTP Clock Domain attach/detach helpers Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 12:28 ` Geert Uytterhoeven
2015-08-04 13:48 ` [PATCH v4 00/16] ARM: shmobile: Add CPG/MSTP Clock Domain Simon Horman
2015-08-04 13:48 ` Simon Horman
2015-08-04 13:48 ` Simon Horman
2015-08-05 0:55 ` Simon Horman
2015-08-05 0:55 ` Simon Horman
2015-08-05 0:55 ` Simon Horman
2015-08-05 6:58 ` Geert Uytterhoeven
2015-08-05 6:58 ` Geert Uytterhoeven
2015-08-05 6:58 ` Geert Uytterhoeven
2015-08-05 6:58 ` Geert Uytterhoeven
2015-08-06 0:50 ` Simon Horman
2015-08-06 0:50 ` Simon Horman
2015-08-06 0:50 ` Simon Horman
2015-08-06 0:50 ` Simon Horman
2015-08-06 0:50 ` Simon Horman
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