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* [U-Boot] [PATCH V2 3/3] imx: mx6ul_14x14_evk add ENET support
  2015-08-12  9:40 ` [U-Boot] [PATCH V2 3/3] imx: mx6ul_14x14_evk add ENET support Peng Fan
@ 2015-08-12  8:34   ` Peng Fan
  2015-08-23 15:45     ` Stefano Babic
  0 siblings, 1 reply; 16+ messages in thread
From: Peng Fan @ 2015-08-12  8:34 UTC (permalink / raw)
  To: u-boot

Wrong patch version. Please ignore.

Sorry.
Peng.

On Wed, Aug 12, 2015 at 05:40:47PM +0800, Peng Fan wrote:
>Add enet support for mx6ul_14x14_evk board:
>1. add pinmux settings
>2. implement board_eth_init
>3. implement board_phy_config
>
>Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
>Cc: Stefano Babic <sbabic@denx.de>
>Cc: Fabio Estevam <fabio.estevam@freescale.com>
>---
>
>Changes v2:
> Addressed Fabio's comments, using "fec_id == 0", but not "0 == fec_id".
>
> board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 116 ++++++++++++++++++++++
> configs/mx6ul_14x14_evk_defconfig                 |   3 +
> include/configs/mx6ul_14x14_evk.h                 |  21 ++++
> 3 files changed, 140 insertions(+)
>
>diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
>index 8f712cb..af07487 100644
>--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
>+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
>@@ -19,8 +19,10 @@
> #include <common.h>
> #include <fsl_esdhc.h>
> #include <i2c.h>
>+#include <miiphy.h>
> #include <linux/sizes.h>
> #include <mmc.h>
>+#include <netdev.h>
> #include <usb.h>
> #include <usb/ehci-fsl.h>
> 
>@@ -43,6 +45,18 @@ DECLARE_GLOBAL_DATA_PTR;
> 	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
> 	PAD_CTL_ODE)
> 
>+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
>+	PAD_CTL_SPEED_HIGH   |                                  \
>+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
>+
>+#define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
>+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
>+
>+#define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
>+
>+#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
>+	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
>+
> #define IOX_SDI IMX_GPIO_NR(5, 10)
> #define IOX_STCP IMX_GPIO_NR(5, 7)
> #define IOX_SHCP IMX_GPIO_NR(5, 11)
>@@ -457,6 +471,104 @@ int board_ehci_hcd_init(int port)
> }
> #endif
> 
>+#ifdef CONFIG_FEC_MXC
>+/*
>+ * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
>+ * be used for ENET1 or ENET2, cannot be used for both.
>+ */
>+static iomux_v3_cfg_t const fec1_pads[] = {
>+	MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
>+	MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
>+	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+};
>+
>+static iomux_v3_cfg_t const fec2_pads[] = {
>+	MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
>+	MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+
>+	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+	MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
>+	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+
>+	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
>+};
>+
>+static void setup_iomux_fec(int fec_id)
>+{
>+	if (fec_id == 0)
>+		imx_iomux_v3_setup_multiple_pads(fec1_pads,
>+						 ARRAY_SIZE(fec1_pads));
>+	else
>+		imx_iomux_v3_setup_multiple_pads(fec2_pads,
>+						 ARRAY_SIZE(fec2_pads));
>+}
>+
>+int board_eth_init(bd_t *bis)
>+{
>+	int ret;
>+
>+	setup_iomux_fec(CONFIG_FEC_ENET_DEV);
>+
>+	ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
>+		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
>+	if (ret)
>+		printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__);
>+
>+	return 0;
>+}
>+
>+static int setup_fec(int fec_id)
>+{
>+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
>+	int ret;
>+
>+	if (fec_id == 0) {
>+		/*
>+		 * Use 50M anatop loopback REF_CLK1 for ENET1,
>+		 * clear gpr1[13], set gpr1[17].
>+		 */
>+		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
>+				IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
>+	} else {
>+		/*
>+		 * Use 50M anatop loopback REF_CLK2 for ENET2,
>+		 * clear gpr1[14], set gpr1[18].
>+		 */
>+		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
>+				IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
>+	}
>+
>+	ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
>+	if (ret)
>+		return ret;
>+
>+	enable_enet_clk(1);
>+
>+	return 0;
>+}
>+
>+int board_phy_config(struct phy_device *phydev)
>+{
>+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
>+
>+	if (phydev->drv->config)
>+		phydev->drv->config(phydev);
>+
>+	return 0;
>+}
>+#endif
>+
> int board_early_init_f(void)
> {
> 	setup_iomux_uart();
>@@ -477,6 +589,10 @@ int board_init(void)
> 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
> #endif
> 
>+#ifdef	CONFIG_FEC_MXC
>+	setup_fec(CONFIG_FEC_ENET_DEV);
>+#endif
>+
> #ifdef CONFIG_USB_EHCI_MX6
> 	setup_usb();
> #endif
>diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
>index b6eefaf..85952e4 100644
>--- a/configs/mx6ul_14x14_evk_defconfig
>+++ b/configs/mx6ul_14x14_evk_defconfig
>@@ -2,3 +2,6 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6UL"
> CONFIG_ARM=y
> CONFIG_TARGET_MX6UL_14X14_EVK=y
> CONFIG_SPL=y
>+CONFIG_CMD_NET=y
>+CONFIG_CMD_PING=y
>+CONFIG_CMD_DHCP=y
>diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
>index 757aa6a..f643e4d 100644
>--- a/include/configs/mx6ul_14x14_evk.h
>+++ b/include/configs/mx6ul_14x14_evk.h
>@@ -221,6 +221,27 @@
> #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
> #endif
> 
>+#ifdef CONFIG_CMD_NET
>+#define CONFIG_FEC_MXC
>+#define CONFIG_MII
>+#define CONFIG_FEC_ENET_DEV		1
>+
>+#if (CONFIG_FEC_ENET_DEV == 0)
>+#define IMX_FEC_BASE			ENET_BASE_ADDR
>+#define CONFIG_FEC_MXC_PHYADDR          0x2
>+#define CONFIG_FEC_XCV_TYPE             RMII
>+#elif (CONFIG_FEC_ENET_DEV == 1)
>+#define IMX_FEC_BASE			ENET2_BASE_ADDR
>+#define CONFIG_FEC_MXC_PHYADDR		0x1
>+#define CONFIG_FEC_XCV_TYPE		RMII
>+#endif
>+#define CONFIG_ETHPRIME			"FEC"
>+
>+#define CONFIG_PHYLIB
>+#define CONFIG_PHY_MICREL
>+#define CONFIG_FEC_DMA_MINALIGN		64
>+#endif
>+
> #define CONFIG_IMX6_THERMAL
> 
> #endif
>-- 
>1.8.4
>
>

-- 

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 1/3] imx: clock support enet2 anatop clock support
@ 2015-08-12  9:40 Peng Fan
  2015-08-12  9:40 ` [U-Boot] [PATCH V2 2/3] net: fec: do not access reserved register for i.MX6UL Peng Fan
                   ` (2 more replies)
  0 siblings, 3 replies; 16+ messages in thread
From: Peng Fan @ 2015-08-12  9:40 UTC (permalink / raw)
  To: u-boot

To i.MX6SX/UL, two ethernet interfaces are supported.
Add ENET2 clock support:
1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed.
   To value 1, only i.MX6SX/UL can pass the check.
2. Modify board code who use this api to follow new api prototype.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos@imgtec.com>
Cc: Stefano Babic <sbabic@denx.de>
---

Changes v2:
 Addressed Fabio's comments. Using "fec_id == 0", but not "0 == fec_id".

 arch/arm/cpu/armv7/mx6/clock.c                | 23 ++++++++++++++++++-----
 arch/arm/include/asm/arch-mx6/clock.h         |  2 +-
 arch/arm/include/asm/arch-mx6/crm_regs.h      |  6 ++++++
 board/aristainetos/aristainetos-v1.c          |  2 +-
 board/barco/platinum/platinum_picon.c         |  2 +-
 board/freescale/mx6qsabreauto/mx6qsabreauto.c |  2 +-
 board/freescale/mx6slevk/mx6slevk.c           |  2 +-
 board/freescale/mx6sxsabresd/mx6sxsabresd.c   |  2 +-
 board/solidrun/mx6cuboxi/mx6cuboxi.c          |  2 +-
 9 files changed, 31 insertions(+), 12 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 9cf4eec..ba6cc75 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -524,7 +524,7 @@ void enable_qspi_clk(int qspi_num)
 #endif
 
 #ifdef CONFIG_FEC_MXC
-int enable_fec_anatop_clock(enum enet_freq freq)
+int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
 {
 	u32 reg = 0;
 	s32 timeout = 100000;
@@ -535,9 +535,19 @@ int enable_fec_anatop_clock(enum enet_freq freq)
 	if (freq < ENET_25MHZ || freq > ENET_125MHZ)
 		return -EINVAL;
 
-	reg = readl(&anatop->pll_enet);
-	reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
-	reg |= freq;
+	if (fec_id == 0) {
+		reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
+		reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
+	} else if (fec_id == 1) {
+		/* Only i.MX6SX/UL support ENET2 */
+		if (!(is_cpu_type(MXC_CPU_MX6SX) ||
+		      is_cpu_type(MXC_CPU_MX6UL)))
+			return -EINVAL;
+		reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
+		reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
+	} else {
+		return -EINVAL;
+	}
 
 	if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
 	    (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
@@ -552,7 +562,10 @@ int enable_fec_anatop_clock(enum enet_freq freq)
 	}
 
 	/* Enable FEC clock */
-	reg |= BM_ANADIG_PLL_ENET_ENABLE;
+	if (fec_id == 0)
+		reg |= BM_ANADIG_PLL_ENET_ENABLE;
+	else
+		reg |= BM_ANADIG_PLL_ENET2_ENABLE;
 	reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 	writel(reg, &anatop->pll_enet);
 
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 7b3bbb8..2b220d6 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -64,7 +64,7 @@ int enable_pcie_clock(void);
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 int enable_spi_clk(unsigned char enable, unsigned spi_num);
 void enable_ipu_clock(void);
-int enable_fec_anatop_clock(enum enet_freq freq);
+int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
 void enable_enet_clk(unsigned char enable);
 void enable_qspi_clk(int qspi_num);
 void enable_thermal_clk(void);
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index fe75da4..10306cd 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -1052,6 +1052,12 @@ struct mxc_ccm_reg {
 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v)  \
 	(((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
 
+/* ENET2 for i.MX6SX/UL */
+#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000
+#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C
+#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v)  \
+	(((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT)
+
 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
 #define BP_ANADIG_PFD_480_PFD3_FRAC      24
diff --git a/board/aristainetos/aristainetos-v1.c b/board/aristainetos/aristainetos-v1.c
index d6a7614..b8fed2e 100644
--- a/board/aristainetos/aristainetos-v1.c
+++ b/board/aristainetos/aristainetos-v1.c
@@ -185,7 +185,7 @@ int board_eth_init(bd_t *bis)
 	/* clear gpr1[14], gpr1[18:17] to select anatop clock */
 	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
 
-	ret = enable_fec_anatop_clock(ENET_50MHZ);
+	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 	if (ret)
 		return ret;
 
diff --git a/board/barco/platinum/platinum_picon.c b/board/barco/platinum/platinum_picon.c
index b2eab76..0384a26 100644
--- a/board/barco/platinum/platinum_picon.c
+++ b/board/barco/platinum/platinum_picon.c
@@ -148,7 +148,7 @@ int platinum_setup_enet(void)
 	/* set GPIO_16 as ENET_REF_CLK_OUT */
 	setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 
-	return enable_fec_anatop_clock(ENET_50MHZ);
+	return enable_fec_anatop_clock(0, ENET_50MHZ);
 }
 
 int platinum_setup_i2c(void)
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 98602f8..7c0e90a 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -361,7 +361,7 @@ static void setup_fec(void)
 		 * select ENET MAC0 TX clock from PLL
 		 */
 		imx_iomux_set_gpr_register(5, 9, 1, 1);
-		enable_fec_anatop_clock(ENET_125MHZ);
+		enable_fec_anatop_clock(0, ENET_125MHZ);
 	}
 
 	setup_iomux_enet();
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 7c18c90..98e3ef0 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -279,7 +279,7 @@ static int setup_fec(void)
 	/* clear gpr1[14], gpr1[18:17] to select anatop clock */
 	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
 
-	return enable_fec_anatop_clock(ENET_50MHZ);
+	return enable_fec_anatop_clock(0, ENET_50MHZ);
 }
 #endif
 
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index d58a79a..ffc0046 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -170,7 +170,7 @@ static int setup_fec(void)
 	reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
 	writel(reg, &anatop->pll_enet);
 
-	return enable_fec_anatop_clock(ENET_125MHZ);
+	return enable_fec_anatop_clock(0, ENET_125MHZ);
 }
 
 int board_eth_init(bd_t *bis)
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 9b1ecf0..8247e43 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -164,7 +164,7 @@ int board_eth_init(bd_t *bis)
 	struct mii_dev *bus;
 	struct phy_device *phydev;
 
-	int ret = enable_fec_anatop_clock(ENET_25MHZ);
+	int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
 	if (ret)
 		return ret;
 
-- 
1.8.4

^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 2/3] net: fec: do not access reserved register for i.MX6UL
  2015-08-12  9:40 [U-Boot] [PATCH V2 1/3] imx: clock support enet2 anatop clock support Peng Fan
@ 2015-08-12  9:40 ` Peng Fan
  2015-08-12 19:15   ` Joe Hershberger
  2015-08-23 15:43   ` Stefano Babic
  2015-08-12  9:40 ` [U-Boot] [PATCH V2 3/3] imx: mx6ul_14x14_evk add ENET support Peng Fan
  2015-08-23 15:43 ` [U-Boot] [PATCH V2 1/3] imx: clock support enet2 anatop clock support Stefano Babic
  2 siblings, 2 replies; 16+ messages in thread
From: Peng Fan @ 2015-08-12  9:40 UTC (permalink / raw)
  To: u-boot

The MIB RAM and FIFO receive start register does not exist on
i.MX6UL. Accessing these register will cause enet not work well.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Stefano Babic <sbabic@denx.de>
---

Changes v2:
 Using runtime check, but not hardcoding "#ifdef".
 This patch depends on the runtime checking patch:
 https://patchwork.ozlabs.org/patch/505621/.

 drivers/net/fec_mxc.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index c5dcbbb..bff5fd1 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -17,6 +17,7 @@
 
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/imx-common/sys_proto.h>
 #include <asm/io.h>
 #include <asm/errno.h>
 #include <linux/compiler.h>
@@ -551,12 +552,15 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
 	writel(0x00000000, &fec->eth->gaddr2);
 
 
-	/* clear MIB RAM */
-	for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
-		writel(0, i);
+	/* Do not access reserved register for i.MX6UL */
+	if (!is_cpu_type(MXC_CPU_MX6UL)) {
+		/* clear MIB RAM */
+		for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
+			writel(0, i);
 
-	/* FIFO receive start register */
-	writel(0x520, &fec->eth->r_fstart);
+		/* FIFO receive start register */
+		writel(0x520, &fec->eth->r_fstart);
+	}
 
 	/* size and address of each buffer */
 	writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
-- 
1.8.4

^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 3/3] imx: mx6ul_14x14_evk add ENET support
  2015-08-12  9:40 [U-Boot] [PATCH V2 1/3] imx: clock support enet2 anatop clock support Peng Fan
  2015-08-12  9:40 ` [U-Boot] [PATCH V2 2/3] net: fec: do not access reserved register for i.MX6UL Peng Fan
@ 2015-08-12  9:40 ` Peng Fan
  2015-08-12  8:34   ` Peng Fan
  2015-08-23 15:43 ` [U-Boot] [PATCH V2 1/3] imx: clock support enet2 anatop clock support Stefano Babic
  2 siblings, 1 reply; 16+ messages in thread
From: Peng Fan @ 2015-08-12  9:40 UTC (permalink / raw)
  To: u-boot

Add enet support for mx6ul_14x14_evk board:
1. add pinmux settings
2. implement board_eth_init
3. implement board_phy_config

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
---

Changes v2:
 Addressed Fabio's comments, using "fec_id == 0", but not "0 == fec_id".

 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 116 ++++++++++++++++++++++
 configs/mx6ul_14x14_evk_defconfig                 |   3 +
 include/configs/mx6ul_14x14_evk.h                 |  21 ++++
 3 files changed, 140 insertions(+)

diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 8f712cb..af07487 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -19,8 +19,10 @@
 #include <common.h>
 #include <fsl_esdhc.h>
 #include <i2c.h>
+#include <miiphy.h>
 #include <linux/sizes.h>
 #include <mmc.h>
+#include <netdev.h>
 #include <usb.h>
 #include <usb/ehci-fsl.h>
 
@@ -43,6 +45,18 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
 	PAD_CTL_ODE)
 
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_SPEED_HIGH   |                                  \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
+
+#define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
+
+#define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
+	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
+
 #define IOX_SDI IMX_GPIO_NR(5, 10)
 #define IOX_STCP IMX_GPIO_NR(5, 7)
 #define IOX_SHCP IMX_GPIO_NR(5, 11)
@@ -457,6 +471,104 @@ int board_ehci_hcd_init(int port)
 }
 #endif
 
+#ifdef CONFIG_FEC_MXC
+/*
+ * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
+ * be used for ENET1 or ENET2, cannot be used for both.
+ */
+static iomux_v3_cfg_t const fec1_pads[] = {
+	MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
+	MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec2_pads[] = {
+	MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
+	MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_fec(int fec_id)
+{
+	if (fec_id == 0)
+		imx_iomux_v3_setup_multiple_pads(fec1_pads,
+						 ARRAY_SIZE(fec1_pads));
+	else
+		imx_iomux_v3_setup_multiple_pads(fec2_pads,
+						 ARRAY_SIZE(fec2_pads));
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int ret;
+
+	setup_iomux_fec(CONFIG_FEC_ENET_DEV);
+
+	ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
+		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+	if (ret)
+		printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__);
+
+	return 0;
+}
+
+static int setup_fec(int fec_id)
+{
+	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+
+	if (fec_id == 0) {
+		/*
+		 * Use 50M anatop loopback REF_CLK1 for ENET1,
+		 * clear gpr1[13], set gpr1[17].
+		 */
+		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
+				IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+	} else {
+		/*
+		 * Use 50M anatop loopback REF_CLK2 for ENET2,
+		 * clear gpr1[14], set gpr1[18].
+		 */
+		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
+				IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+	}
+
+	ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
+	if (ret)
+		return ret;
+
+	enable_enet_clk(1);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -477,6 +589,10 @@ int board_init(void)
 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 #endif
 
+#ifdef	CONFIG_FEC_MXC
+	setup_fec(CONFIG_FEC_ENET_DEV);
+#endif
+
 #ifdef CONFIG_USB_EHCI_MX6
 	setup_usb();
 #endif
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index b6eefaf..85952e4 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -2,3 +2,6 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6UL"
 CONFIG_ARM=y
 CONFIG_TARGET_MX6UL_14X14_EVK=y
 CONFIG_SPL=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
index 757aa6a..f643e4d 100644
--- a/include/configs/mx6ul_14x14_evk.h
+++ b/include/configs/mx6ul_14x14_evk.h
@@ -221,6 +221,27 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 #endif
 
+#ifdef CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define CONFIG_FEC_ENET_DEV		1
+
+#if (CONFIG_FEC_ENET_DEV == 0)
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR          0x2
+#define CONFIG_FEC_XCV_TYPE             RMII
+#elif (CONFIG_FEC_ENET_DEV == 1)
+#define IMX_FEC_BASE			ENET2_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR		0x1
+#define CONFIG_FEC_XCV_TYPE		RMII
+#endif
+#define CONFIG_ETHPRIME			"FEC"
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_FEC_DMA_MINALIGN		64
+#endif
+
 #define CONFIG_IMX6_THERMAL
 
 #endif
-- 
1.8.4

^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 2/3] net: fec: do not access reserved register for i.MX6UL
  2015-08-12  9:40 ` [U-Boot] [PATCH V2 2/3] net: fec: do not access reserved register for i.MX6UL Peng Fan
@ 2015-08-12 19:15   ` Joe Hershberger
  2015-08-23 15:43   ` Stefano Babic
  1 sibling, 0 replies; 16+ messages in thread
From: Joe Hershberger @ 2015-08-12 19:15 UTC (permalink / raw)
  To: u-boot

Hi Peng,

On Wed, Aug 12, 2015 at 4:40 AM, Peng Fan <Peng.Fan@freescale.com> wrote:
> The MIB RAM and FIFO receive start register does not exist on
> i.MX6UL. Accessing these register will cause enet not work well.
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> Signed-off-by: Fugang Duan <B38611@freescale.com>
> Cc: Joe Hershberger <joe.hershberger@ni.com>
> Cc: Stefano Babic <sbabic@denx.de>

Looks reasonable to me.

Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 1/3] imx: clock support enet2 anatop clock support
  2015-08-12  9:40 [U-Boot] [PATCH V2 1/3] imx: clock support enet2 anatop clock support Peng Fan
  2015-08-12  9:40 ` [U-Boot] [PATCH V2 2/3] net: fec: do not access reserved register for i.MX6UL Peng Fan
  2015-08-12  9:40 ` [U-Boot] [PATCH V2 3/3] imx: mx6ul_14x14_evk add ENET support Peng Fan
@ 2015-08-23 15:43 ` Stefano Babic
  2 siblings, 0 replies; 16+ messages in thread
From: Stefano Babic @ 2015-08-23 15:43 UTC (permalink / raw)
  To: u-boot

On 12/08/2015 11:40, Peng Fan wrote:
> To i.MX6SX/UL, two ethernet interfaces are supported.
> Add ENET2 clock support:
> 1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed.
>    To value 1, only i.MX6SX/UL can pass the check.
> 2. Modify board code who use this api to follow new api prototype.
> 
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> Cc: Heiko Schocher <hs@denx.de>
> Cc: Fabio Estevam <fabio.estevam@freescale.com>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos@imgtec.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> 
> Changes v2:
>  Addressed Fabio's comments. Using "fec_id == 0", but not "0 == fec_id".
> 
>  arch/arm/cpu/armv7/mx6/clock.c                | 23 ++++++++++++++++++-----
>  arch/arm/include/asm/arch-mx6/clock.h         |  2 +-
>  arch/arm/include/asm/arch-mx6/crm_regs.h      |  6 ++++++
>  board/aristainetos/aristainetos-v1.c          |  2 +-
>  board/barco/platinum/platinum_picon.c         |  2 +-
>  board/freescale/mx6qsabreauto/mx6qsabreauto.c |  2 +-
>  board/freescale/mx6slevk/mx6slevk.c           |  2 +-
>  board/freescale/mx6sxsabresd/mx6sxsabresd.c   |  2 +-
>  board/solidrun/mx6cuboxi/mx6cuboxi.c          |  2 +-
>  9 files changed, 31 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
> index 9cf4eec..ba6cc75 100644
> --- a/arch/arm/cpu/armv7/mx6/clock.c
> +++ b/arch/arm/cpu/armv7/mx6/clock.c
> @@ -524,7 +524,7 @@ void enable_qspi_clk(int qspi_num)
>  #endif
>  
>  #ifdef CONFIG_FEC_MXC
> -int enable_fec_anatop_clock(enum enet_freq freq)
> +int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
>  {
>  	u32 reg = 0;
>  	s32 timeout = 100000;
> @@ -535,9 +535,19 @@ int enable_fec_anatop_clock(enum enet_freq freq)
>  	if (freq < ENET_25MHZ || freq > ENET_125MHZ)
>  		return -EINVAL;
>  
> -	reg = readl(&anatop->pll_enet);
> -	reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
> -	reg |= freq;
> +	if (fec_id == 0) {
> +		reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
> +		reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
> +	} else if (fec_id == 1) {
> +		/* Only i.MX6SX/UL support ENET2 */
> +		if (!(is_cpu_type(MXC_CPU_MX6SX) ||
> +		      is_cpu_type(MXC_CPU_MX6UL)))
> +			return -EINVAL;
> +		reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
> +		reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
> +	} else {
> +		return -EINVAL;
> +	}
>  
>  	if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
>  	    (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
> @@ -552,7 +562,10 @@ int enable_fec_anatop_clock(enum enet_freq freq)
>  	}
>  
>  	/* Enable FEC clock */
> -	reg |= BM_ANADIG_PLL_ENET_ENABLE;
> +	if (fec_id == 0)
> +		reg |= BM_ANADIG_PLL_ENET_ENABLE;
> +	else
> +		reg |= BM_ANADIG_PLL_ENET2_ENABLE;
>  	reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
>  	writel(reg, &anatop->pll_enet);
>  
> diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
> index 7b3bbb8..2b220d6 100644
> --- a/arch/arm/include/asm/arch-mx6/clock.h
> +++ b/arch/arm/include/asm/arch-mx6/clock.h
> @@ -64,7 +64,7 @@ int enable_pcie_clock(void);
>  int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
>  int enable_spi_clk(unsigned char enable, unsigned spi_num);
>  void enable_ipu_clock(void);
> -int enable_fec_anatop_clock(enum enet_freq freq);
> +int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
>  void enable_enet_clk(unsigned char enable);
>  void enable_qspi_clk(int qspi_num);
>  void enable_thermal_clk(void);
> diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
> index fe75da4..10306cd 100644
> --- a/arch/arm/include/asm/arch-mx6/crm_regs.h
> +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
> @@ -1052,6 +1052,12 @@ struct mxc_ccm_reg {
>  #define BF_ANADIG_PLL_ENET_DIV_SELECT(v)  \
>  	(((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
>  
> +/* ENET2 for i.MX6SX/UL */
> +#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000
> +#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C
> +#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v)  \
> +	(((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT)
> +
>  #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
>  #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
>  #define BP_ANADIG_PFD_480_PFD3_FRAC      24
> diff --git a/board/aristainetos/aristainetos-v1.c b/board/aristainetos/aristainetos-v1.c
> index d6a7614..b8fed2e 100644
> --- a/board/aristainetos/aristainetos-v1.c
> +++ b/board/aristainetos/aristainetos-v1.c
> @@ -185,7 +185,7 @@ int board_eth_init(bd_t *bis)
>  	/* clear gpr1[14], gpr1[18:17] to select anatop clock */
>  	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
>  
> -	ret = enable_fec_anatop_clock(ENET_50MHZ);
> +	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
>  	if (ret)
>  		return ret;
>  
> diff --git a/board/barco/platinum/platinum_picon.c b/board/barco/platinum/platinum_picon.c
> index b2eab76..0384a26 100644
> --- a/board/barco/platinum/platinum_picon.c
> +++ b/board/barco/platinum/platinum_picon.c
> @@ -148,7 +148,7 @@ int platinum_setup_enet(void)
>  	/* set GPIO_16 as ENET_REF_CLK_OUT */
>  	setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
>  
> -	return enable_fec_anatop_clock(ENET_50MHZ);
> +	return enable_fec_anatop_clock(0, ENET_50MHZ);
>  }
>  
>  int platinum_setup_i2c(void)
> diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
> index 98602f8..7c0e90a 100644
> --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
> +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
> @@ -361,7 +361,7 @@ static void setup_fec(void)
>  		 * select ENET MAC0 TX clock from PLL
>  		 */
>  		imx_iomux_set_gpr_register(5, 9, 1, 1);
> -		enable_fec_anatop_clock(ENET_125MHZ);
> +		enable_fec_anatop_clock(0, ENET_125MHZ);
>  	}
>  
>  	setup_iomux_enet();
> diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
> index 7c18c90..98e3ef0 100644
> --- a/board/freescale/mx6slevk/mx6slevk.c
> +++ b/board/freescale/mx6slevk/mx6slevk.c
> @@ -279,7 +279,7 @@ static int setup_fec(void)
>  	/* clear gpr1[14], gpr1[18:17] to select anatop clock */
>  	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
>  
> -	return enable_fec_anatop_clock(ENET_50MHZ);
> +	return enable_fec_anatop_clock(0, ENET_50MHZ);
>  }
>  #endif
>  
> diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
> index d58a79a..ffc0046 100644
> --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
> +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
> @@ -170,7 +170,7 @@ static int setup_fec(void)
>  	reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
>  	writel(reg, &anatop->pll_enet);
>  
> -	return enable_fec_anatop_clock(ENET_125MHZ);
> +	return enable_fec_anatop_clock(0, ENET_125MHZ);
>  }
>  
>  int board_eth_init(bd_t *bis)
> diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
> index 9b1ecf0..8247e43 100644
> --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
> +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
> @@ -164,7 +164,7 @@ int board_eth_init(bd_t *bis)
>  	struct mii_dev *bus;
>  	struct phy_device *phydev;
>  
> -	int ret = enable_fec_anatop_clock(ENET_25MHZ);
> +	int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
>  	if (ret)
>  		return ret;
>  
> 

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 2/3] net: fec: do not access reserved register for i.MX6UL
  2015-08-12  9:40 ` [U-Boot] [PATCH V2 2/3] net: fec: do not access reserved register for i.MX6UL Peng Fan
  2015-08-12 19:15   ` Joe Hershberger
@ 2015-08-23 15:43   ` Stefano Babic
  2015-08-31 17:14     ` Stefano Babic
  1 sibling, 1 reply; 16+ messages in thread
From: Stefano Babic @ 2015-08-23 15:43 UTC (permalink / raw)
  To: u-boot

On 12/08/2015 11:40, Peng Fan wrote:
> The MIB RAM and FIFO receive start register does not exist on
> i.MX6UL. Accessing these register will cause enet not work well.
> 
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> Signed-off-by: Fugang Duan <B38611@freescale.com>
> Cc: Joe Hershberger <joe.hershberger@ni.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> 
> Changes v2:
>  Using runtime check, but not hardcoding "#ifdef".
>  This patch depends on the runtime checking patch:
>  https://patchwork.ozlabs.org/patch/505621/.
> 
>  drivers/net/fec_mxc.c | 14 +++++++++-----
>  1 file changed, 9 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> index c5dcbbb..bff5fd1 100644
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
> @@ -17,6 +17,7 @@
>  
>  #include <asm/arch/clock.h>
>  #include <asm/arch/imx-regs.h>
> +#include <asm/imx-common/sys_proto.h>
>  #include <asm/io.h>
>  #include <asm/errno.h>
>  #include <linux/compiler.h>
> @@ -551,12 +552,15 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
>  	writel(0x00000000, &fec->eth->gaddr2);
>  
>  
> -	/* clear MIB RAM */
> -	for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
> -		writel(0, i);
> +	/* Do not access reserved register for i.MX6UL */
> +	if (!is_cpu_type(MXC_CPU_MX6UL)) {
> +		/* clear MIB RAM */
> +		for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
> +			writel(0, i);
>  
> -	/* FIFO receive start register */
> -	writel(0x520, &fec->eth->r_fstart);
> +		/* FIFO receive start register */
> +		writel(0x520, &fec->eth->r_fstart);
> +	}
>  
>  	/* size and address of each buffer */
>  	writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
> 

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 3/3] imx: mx6ul_14x14_evk add ENET support
  2015-08-12  8:34   ` Peng Fan
@ 2015-08-23 15:45     ` Stefano Babic
  2015-08-24  0:07       ` Peng Fan
  0 siblings, 1 reply; 16+ messages in thread
From: Stefano Babic @ 2015-08-23 15:45 UTC (permalink / raw)
  To: u-boot

On 12/08/2015 10:34, Peng Fan wrote:
> Wrong patch version. Please ignore.
> 

It is, discarded.

Best regards,
Stefano Babic

> Sorry.
> Peng.
> 
> On Wed, Aug 12, 2015 at 05:40:47PM +0800, Peng Fan wrote:
>> Add enet support for mx6ul_14x14_evk board:
>> 1. add pinmux settings
>> 2. implement board_eth_init
>> 3. implement board_phy_config
>>
>> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
>> Cc: Stefano Babic <sbabic@denx.de>
>> Cc: Fabio Estevam <fabio.estevam@freescale.com>
>> ---
>>
>> Changes v2:
>> Addressed Fabio's comments, using "fec_id == 0", but not "0 == fec_id".
>>
>> board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 116 ++++++++++++++++++++++
>> configs/mx6ul_14x14_evk_defconfig                 |   3 +
>> include/configs/mx6ul_14x14_evk.h                 |  21 ++++
>> 3 files changed, 140 insertions(+)
>>
>> diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
>> index 8f712cb..af07487 100644
>> --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
>> +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
>> @@ -19,8 +19,10 @@
>> #include <common.h>
>> #include <fsl_esdhc.h>
>> #include <i2c.h>
>> +#include <miiphy.h>
>> #include <linux/sizes.h>
>> #include <mmc.h>
>> +#include <netdev.h>
>> #include <usb.h>
>> #include <usb/ehci-fsl.h>
>>
>> @@ -43,6 +45,18 @@ DECLARE_GLOBAL_DATA_PTR;
>> 	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
>> 	PAD_CTL_ODE)
>>
>> +#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
>> +	PAD_CTL_SPEED_HIGH   |                                  \
>> +	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
>> +
>> +#define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
>> +	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
>> +
>> +#define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
>> +
>> +#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
>> +	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
>> +
>> #define IOX_SDI IMX_GPIO_NR(5, 10)
>> #define IOX_STCP IMX_GPIO_NR(5, 7)
>> #define IOX_SHCP IMX_GPIO_NR(5, 11)
>> @@ -457,6 +471,104 @@ int board_ehci_hcd_init(int port)
>> }
>> #endif
>>
>> +#ifdef CONFIG_FEC_MXC
>> +/*
>> + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
>> + * be used for ENET1 or ENET2, cannot be used for both.
>> + */
>> +static iomux_v3_cfg_t const fec1_pads[] = {
>> +	MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
>> +	MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
>> +	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +};
>> +
>> +static iomux_v3_cfg_t const fec2_pads[] = {
>> +	MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
>> +	MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +
>> +	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +	MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
>> +	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +
>> +	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +};
>> +
>> +static void setup_iomux_fec(int fec_id)
>> +{
>> +	if (fec_id == 0)
>> +		imx_iomux_v3_setup_multiple_pads(fec1_pads,
>> +						 ARRAY_SIZE(fec1_pads));
>> +	else
>> +		imx_iomux_v3_setup_multiple_pads(fec2_pads,
>> +						 ARRAY_SIZE(fec2_pads));
>> +}
>> +
>> +int board_eth_init(bd_t *bis)
>> +{
>> +	int ret;
>> +
>> +	setup_iomux_fec(CONFIG_FEC_ENET_DEV);
>> +
>> +	ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
>> +		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
>> +	if (ret)
>> +		printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__);
>> +
>> +	return 0;
>> +}
>> +
>> +static int setup_fec(int fec_id)
>> +{
>> +	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
>> +	int ret;
>> +
>> +	if (fec_id == 0) {
>> +		/*
>> +		 * Use 50M anatop loopback REF_CLK1 for ENET1,
>> +		 * clear gpr1[13], set gpr1[17].
>> +		 */
>> +		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
>> +				IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
>> +	} else {
>> +		/*
>> +		 * Use 50M anatop loopback REF_CLK2 for ENET2,
>> +		 * clear gpr1[14], set gpr1[18].
>> +		 */
>> +		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
>> +				IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
>> +	}
>> +
>> +	ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
>> +	if (ret)
>> +		return ret;
>> +
>> +	enable_enet_clk(1);
>> +
>> +	return 0;
>> +}
>> +
>> +int board_phy_config(struct phy_device *phydev)
>> +{
>> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
>> +
>> +	if (phydev->drv->config)
>> +		phydev->drv->config(phydev);
>> +
>> +	return 0;
>> +}
>> +#endif
>> +
>> int board_early_init_f(void)
>> {
>> 	setup_iomux_uart();
>> @@ -477,6 +589,10 @@ int board_init(void)
>> 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
>> #endif
>>
>> +#ifdef	CONFIG_FEC_MXC
>> +	setup_fec(CONFIG_FEC_ENET_DEV);
>> +#endif
>> +
>> #ifdef CONFIG_USB_EHCI_MX6
>> 	setup_usb();
>> #endif
>> diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
>> index b6eefaf..85952e4 100644
>> --- a/configs/mx6ul_14x14_evk_defconfig
>> +++ b/configs/mx6ul_14x14_evk_defconfig
>> @@ -2,3 +2,6 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6UL"
>> CONFIG_ARM=y
>> CONFIG_TARGET_MX6UL_14X14_EVK=y
>> CONFIG_SPL=y
>> +CONFIG_CMD_NET=y
>> +CONFIG_CMD_PING=y
>> +CONFIG_CMD_DHCP=y
>> diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
>> index 757aa6a..f643e4d 100644
>> --- a/include/configs/mx6ul_14x14_evk.h
>> +++ b/include/configs/mx6ul_14x14_evk.h
>> @@ -221,6 +221,27 @@
>> #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
>> #endif
>>
>> +#ifdef CONFIG_CMD_NET
>> +#define CONFIG_FEC_MXC
>> +#define CONFIG_MII
>> +#define CONFIG_FEC_ENET_DEV		1
>> +
>> +#if (CONFIG_FEC_ENET_DEV == 0)
>> +#define IMX_FEC_BASE			ENET_BASE_ADDR
>> +#define CONFIG_FEC_MXC_PHYADDR          0x2
>> +#define CONFIG_FEC_XCV_TYPE             RMII
>> +#elif (CONFIG_FEC_ENET_DEV == 1)
>> +#define IMX_FEC_BASE			ENET2_BASE_ADDR
>> +#define CONFIG_FEC_MXC_PHYADDR		0x1
>> +#define CONFIG_FEC_XCV_TYPE		RMII
>> +#endif
>> +#define CONFIG_ETHPRIME			"FEC"
>> +
>> +#define CONFIG_PHYLIB
>> +#define CONFIG_PHY_MICREL
>> +#define CONFIG_FEC_DMA_MINALIGN		64
>> +#endif
>> +
>> #define CONFIG_IMX6_THERMAL
>>
>> #endif
>> -- 
>> 1.8.4
>>
>>
> 


-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 3/3] imx: mx6ul_14x14_evk add ENET support
  2015-08-23 15:45     ` Stefano Babic
@ 2015-08-24  0:07       ` Peng Fan
  2015-08-24  7:31         ` Stefano Babic
  0 siblings, 1 reply; 16+ messages in thread
From: Peng Fan @ 2015-08-24  0:07 UTC (permalink / raw)
  To: u-boot

Hi Stefano,

On Sun, Aug 23, 2015 at 05:45:45PM +0200, Stefano Babic wrote:
>On 12/08/2015 10:34, Peng Fan wrote:
>> Wrong patch version. Please ignore.
>> 
>
>It is, discarded.

Can you please pick this one instead?
http://lists.denx.de/pipermail/u-boot/2015-August/223124.html
This one is the correct patch version.
I can not find this patch in patchwork.

Regards,
Peng.

>
>Best regards,
>Stefano Babic
>
>> Sorry.
>> Peng.
>> 
>> On Wed, Aug 12, 2015 at 05:40:47PM +0800, Peng Fan wrote:
>>> Add enet support for mx6ul_14x14_evk board:
>>> 1. add pinmux settings
>>> 2. implement board_eth_init
>>> 3. implement board_phy_config
>>>
>>> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
>>> Cc: Stefano Babic <sbabic@denx.de>
>>> Cc: Fabio Estevam <fabio.estevam@freescale.com>
>>> ---
>>>
>>> Changes v2:
>>> Addressed Fabio's comments, using "fec_id == 0", but not "0 == fec_id".
>>>
>>> board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 116 ++++++++++++++++++++++
>>> configs/mx6ul_14x14_evk_defconfig                 |   3 +
>>> include/configs/mx6ul_14x14_evk.h                 |  21 ++++
>>> 3 files changed, 140 insertions(+)
>>>
>>> diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
>>> index 8f712cb..af07487 100644
>>> --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
>>> +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
>>> @@ -19,8 +19,10 @@
>>> #include <common.h>
>>> #include <fsl_esdhc.h>
>>> #include <i2c.h>
>>> +#include <miiphy.h>
>>> #include <linux/sizes.h>
>>> #include <mmc.h>
>>> +#include <netdev.h>
>>> #include <usb.h>
>>> #include <usb/ehci-fsl.h>
>>>
>>> @@ -43,6 +45,18 @@ DECLARE_GLOBAL_DATA_PTR;
>>> 	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
>>> 	PAD_CTL_ODE)
>>>
>>> +#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
>>> +	PAD_CTL_SPEED_HIGH   |                                  \
>>> +	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
>>> +
>>> +#define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
>>> +	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
>>> +
>>> +#define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
>>> +
>>> +#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
>>> +	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
>>> +
>>> #define IOX_SDI IMX_GPIO_NR(5, 10)
>>> #define IOX_STCP IMX_GPIO_NR(5, 7)
>>> #define IOX_SHCP IMX_GPIO_NR(5, 11)
>>> @@ -457,6 +471,104 @@ int board_ehci_hcd_init(int port)
>>> }
>>> #endif
>>>
>>> +#ifdef CONFIG_FEC_MXC
>>> +/*
>>> + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
>>> + * be used for ENET1 or ENET2, cannot be used for both.
>>> + */
>>> +static iomux_v3_cfg_t const fec1_pads[] = {
>>> +	MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
>>> +	MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> +	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> +	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> +	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> +	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
>>> +	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> +	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> +	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> +	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> +};
>>> +
>>> +static iomux_v3_cfg_t const fec2_pads[] = {
>>> +	MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
>>> +	MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> +
>>> +	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> +	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> +	MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
>>> +	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> +
>>> +	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> +	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> +	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> +	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>> +};
>>> +
>>> +static void setup_iomux_fec(int fec_id)
>>> +{
>>> +	if (fec_id == 0)
>>> +		imx_iomux_v3_setup_multiple_pads(fec1_pads,
>>> +						 ARRAY_SIZE(fec1_pads));
>>> +	else
>>> +		imx_iomux_v3_setup_multiple_pads(fec2_pads,
>>> +						 ARRAY_SIZE(fec2_pads));
>>> +}
>>> +
>>> +int board_eth_init(bd_t *bis)
>>> +{
>>> +	int ret;
>>> +
>>> +	setup_iomux_fec(CONFIG_FEC_ENET_DEV);
>>> +
>>> +	ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
>>> +		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
>>> +	if (ret)
>>> +		printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static int setup_fec(int fec_id)
>>> +{
>>> +	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
>>> +	int ret;
>>> +
>>> +	if (fec_id == 0) {
>>> +		/*
>>> +		 * Use 50M anatop loopback REF_CLK1 for ENET1,
>>> +		 * clear gpr1[13], set gpr1[17].
>>> +		 */
>>> +		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
>>> +				IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
>>> +	} else {
>>> +		/*
>>> +		 * Use 50M anatop loopback REF_CLK2 for ENET2,
>>> +		 * clear gpr1[14], set gpr1[18].
>>> +		 */
>>> +		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
>>> +				IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
>>> +	}
>>> +
>>> +	ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
>>> +	if (ret)
>>> +		return ret;
>>> +
>>> +	enable_enet_clk(1);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +int board_phy_config(struct phy_device *phydev)
>>> +{
>>> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
>>> +
>>> +	if (phydev->drv->config)
>>> +		phydev->drv->config(phydev);
>>> +
>>> +	return 0;
>>> +}
>>> +#endif
>>> +
>>> int board_early_init_f(void)
>>> {
>>> 	setup_iomux_uart();
>>> @@ -477,6 +589,10 @@ int board_init(void)
>>> 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
>>> #endif
>>>
>>> +#ifdef	CONFIG_FEC_MXC
>>> +	setup_fec(CONFIG_FEC_ENET_DEV);
>>> +#endif
>>> +
>>> #ifdef CONFIG_USB_EHCI_MX6
>>> 	setup_usb();
>>> #endif
>>> diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
>>> index b6eefaf..85952e4 100644
>>> --- a/configs/mx6ul_14x14_evk_defconfig
>>> +++ b/configs/mx6ul_14x14_evk_defconfig
>>> @@ -2,3 +2,6 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6UL"
>>> CONFIG_ARM=y
>>> CONFIG_TARGET_MX6UL_14X14_EVK=y
>>> CONFIG_SPL=y
>>> +CONFIG_CMD_NET=y
>>> +CONFIG_CMD_PING=y
>>> +CONFIG_CMD_DHCP=y
>>> diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
>>> index 757aa6a..f643e4d 100644
>>> --- a/include/configs/mx6ul_14x14_evk.h
>>> +++ b/include/configs/mx6ul_14x14_evk.h
>>> @@ -221,6 +221,27 @@
>>> #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
>>> #endif
>>>
>>> +#ifdef CONFIG_CMD_NET
>>> +#define CONFIG_FEC_MXC
>>> +#define CONFIG_MII
>>> +#define CONFIG_FEC_ENET_DEV		1
>>> +
>>> +#if (CONFIG_FEC_ENET_DEV == 0)
>>> +#define IMX_FEC_BASE			ENET_BASE_ADDR
>>> +#define CONFIG_FEC_MXC_PHYADDR          0x2
>>> +#define CONFIG_FEC_XCV_TYPE             RMII
>>> +#elif (CONFIG_FEC_ENET_DEV == 1)
>>> +#define IMX_FEC_BASE			ENET2_BASE_ADDR
>>> +#define CONFIG_FEC_MXC_PHYADDR		0x1
>>> +#define CONFIG_FEC_XCV_TYPE		RMII
>>> +#endif
>>> +#define CONFIG_ETHPRIME			"FEC"
>>> +
>>> +#define CONFIG_PHYLIB
>>> +#define CONFIG_PHY_MICREL
>>> +#define CONFIG_FEC_DMA_MINALIGN		64
>>> +#endif
>>> +
>>> #define CONFIG_IMX6_THERMAL
>>>
>>> #endif
>>> -- 
>>> 1.8.4
>>>
>>>
>> 
>
>
>-- 
>=====================================================================
>DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
>HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
>=====================================================================

-- 

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 3/3] imx: mx6ul_14x14_evk add ENET support
  2015-08-24  7:31         ` Stefano Babic
@ 2015-08-24  6:35           ` Peng Fan
  0 siblings, 0 replies; 16+ messages in thread
From: Peng Fan @ 2015-08-24  6:35 UTC (permalink / raw)
  To: u-boot

On Mon, Aug 24, 2015 at 09:31:32AM +0200, Stefano Babic wrote:
>Hi Peng,
>
>On 24/08/2015 02:07, Peng Fan wrote:
>> Hi Stefano,
>> 
>> On Sun, Aug 23, 2015 at 05:45:45PM +0200, Stefano Babic wrote:
>>> On 12/08/2015 10:34, Peng Fan wrote:
>>>> Wrong patch version. Please ignore.
>>>>
>>>
>>> It is, discarded.
>> 
>> Can you please pick this one instead?
>> http://lists.denx.de/pipermail/u-boot/2015-August/223124.html
>> This one is the correct patch version.
>> I can not find this patch in patchwork.
>> 
>
>Right - I was not able to find it, too. I found only the one to be
>discarded.
>
>I applied the correct one, it is already on the server.

Thanks.

Peng.

>
>Regards,
>Stefano Babic
>
>> Regards,
>> Peng.
>> 
>>>
>>> Best regards,
>>> Stefano Babic
>>>
>>>> Sorry.
>>>> Peng.
>>>>

-- 

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 3/3] imx: mx6ul_14x14_evk add ENET support
  2015-08-24  0:07       ` Peng Fan
@ 2015-08-24  7:31         ` Stefano Babic
  2015-08-24  6:35           ` Peng Fan
  0 siblings, 1 reply; 16+ messages in thread
From: Stefano Babic @ 2015-08-24  7:31 UTC (permalink / raw)
  To: u-boot

Hi Peng,

On 24/08/2015 02:07, Peng Fan wrote:
> Hi Stefano,
> 
> On Sun, Aug 23, 2015 at 05:45:45PM +0200, Stefano Babic wrote:
>> On 12/08/2015 10:34, Peng Fan wrote:
>>> Wrong patch version. Please ignore.
>>>
>>
>> It is, discarded.
> 
> Can you please pick this one instead?
> http://lists.denx.de/pipermail/u-boot/2015-August/223124.html
> This one is the correct patch version.
> I can not find this patch in patchwork.
> 

Right - I was not able to find it, too. I found only the one to be
discarded.

I applied the correct one, it is already on the server.

Regards,
Stefano Babic

> Regards,
> Peng.
> 
>>
>> Best regards,
>> Stefano Babic
>>
>>> Sorry.
>>> Peng.
>>>
>>> On Wed, Aug 12, 2015 at 05:40:47PM +0800, Peng Fan wrote:
>>>> Add enet support for mx6ul_14x14_evk board:
>>>> 1. add pinmux settings
>>>> 2. implement board_eth_init
>>>> 3. implement board_phy_config
>>>>
>>>> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
>>>> Cc: Stefano Babic <sbabic@denx.de>
>>>> Cc: Fabio Estevam <fabio.estevam@freescale.com>
>>>> ---
>>>>
>>>> Changes v2:
>>>> Addressed Fabio's comments, using "fec_id == 0", but not "0 == fec_id".
>>>>
>>>> board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 116 ++++++++++++++++++++++
>>>> configs/mx6ul_14x14_evk_defconfig                 |   3 +
>>>> include/configs/mx6ul_14x14_evk.h                 |  21 ++++
>>>> 3 files changed, 140 insertions(+)
>>>>
>>>> diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
>>>> index 8f712cb..af07487 100644
>>>> --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
>>>> +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
>>>> @@ -19,8 +19,10 @@
>>>> #include <common.h>
>>>> #include <fsl_esdhc.h>
>>>> #include <i2c.h>
>>>> +#include <miiphy.h>
>>>> #include <linux/sizes.h>
>>>> #include <mmc.h>
>>>> +#include <netdev.h>
>>>> #include <usb.h>
>>>> #include <usb/ehci-fsl.h>
>>>>
>>>> @@ -43,6 +45,18 @@ DECLARE_GLOBAL_DATA_PTR;
>>>> 	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
>>>> 	PAD_CTL_ODE)
>>>>
>>>> +#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
>>>> +	PAD_CTL_SPEED_HIGH   |                                  \
>>>> +	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
>>>> +
>>>> +#define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
>>>> +	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
>>>> +
>>>> +#define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
>>>> +
>>>> +#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
>>>> +	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
>>>> +
>>>> #define IOX_SDI IMX_GPIO_NR(5, 10)
>>>> #define IOX_STCP IMX_GPIO_NR(5, 7)
>>>> #define IOX_SHCP IMX_GPIO_NR(5, 11)
>>>> @@ -457,6 +471,104 @@ int board_ehci_hcd_init(int port)
>>>> }
>>>> #endif
>>>>
>>>> +#ifdef CONFIG_FEC_MXC
>>>> +/*
>>>> + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
>>>> + * be used for ENET1 or ENET2, cannot be used for both.
>>>> + */
>>>> +static iomux_v3_cfg_t const fec1_pads[] = {
>>>> +	MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
>>>> +	MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>>> +	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>>> +	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>>> +	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>>> +	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
>>>> +	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>>> +	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>>> +	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>>> +	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>>> +};
>>>> +
>>>> +static iomux_v3_cfg_t const fec2_pads[] = {
>>>> +	MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
>>>> +	MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>>> +
>>>> +	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>>> +	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>>> +	MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
>>>> +	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>>> +
>>>> +	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>>> +	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>>> +	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>>> +	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
>>>> +};
>>>> +
>>>> +static void setup_iomux_fec(int fec_id)
>>>> +{
>>>> +	if (fec_id == 0)
>>>> +		imx_iomux_v3_setup_multiple_pads(fec1_pads,
>>>> +						 ARRAY_SIZE(fec1_pads));
>>>> +	else
>>>> +		imx_iomux_v3_setup_multiple_pads(fec2_pads,
>>>> +						 ARRAY_SIZE(fec2_pads));
>>>> +}
>>>> +
>>>> +int board_eth_init(bd_t *bis)
>>>> +{
>>>> +	int ret;
>>>> +
>>>> +	setup_iomux_fec(CONFIG_FEC_ENET_DEV);
>>>> +
>>>> +	ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
>>>> +		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
>>>> +	if (ret)
>>>> +		printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__);
>>>> +
>>>> +	return 0;
>>>> +}
>>>> +
>>>> +static int setup_fec(int fec_id)
>>>> +{
>>>> +	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
>>>> +	int ret;
>>>> +
>>>> +	if (fec_id == 0) {
>>>> +		/*
>>>> +		 * Use 50M anatop loopback REF_CLK1 for ENET1,
>>>> +		 * clear gpr1[13], set gpr1[17].
>>>> +		 */
>>>> +		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
>>>> +				IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
>>>> +	} else {
>>>> +		/*
>>>> +		 * Use 50M anatop loopback REF_CLK2 for ENET2,
>>>> +		 * clear gpr1[14], set gpr1[18].
>>>> +		 */
>>>> +		clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
>>>> +				IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
>>>> +	}
>>>> +
>>>> +	ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
>>>> +	if (ret)
>>>> +		return ret;
>>>> +
>>>> +	enable_enet_clk(1);
>>>> +
>>>> +	return 0;
>>>> +}
>>>> +
>>>> +int board_phy_config(struct phy_device *phydev)
>>>> +{
>>>> +	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
>>>> +
>>>> +	if (phydev->drv->config)
>>>> +		phydev->drv->config(phydev);
>>>> +
>>>> +	return 0;
>>>> +}
>>>> +#endif
>>>> +
>>>> int board_early_init_f(void)
>>>> {
>>>> 	setup_iomux_uart();
>>>> @@ -477,6 +589,10 @@ int board_init(void)
>>>> 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
>>>> #endif
>>>>
>>>> +#ifdef	CONFIG_FEC_MXC
>>>> +	setup_fec(CONFIG_FEC_ENET_DEV);
>>>> +#endif
>>>> +
>>>> #ifdef CONFIG_USB_EHCI_MX6
>>>> 	setup_usb();
>>>> #endif
>>>> diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
>>>> index b6eefaf..85952e4 100644
>>>> --- a/configs/mx6ul_14x14_evk_defconfig
>>>> +++ b/configs/mx6ul_14x14_evk_defconfig
>>>> @@ -2,3 +2,6 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6UL"
>>>> CONFIG_ARM=y
>>>> CONFIG_TARGET_MX6UL_14X14_EVK=y
>>>> CONFIG_SPL=y
>>>> +CONFIG_CMD_NET=y
>>>> +CONFIG_CMD_PING=y
>>>> +CONFIG_CMD_DHCP=y
>>>> diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h
>>>> index 757aa6a..f643e4d 100644
>>>> --- a/include/configs/mx6ul_14x14_evk.h
>>>> +++ b/include/configs/mx6ul_14x14_evk.h
>>>> @@ -221,6 +221,27 @@
>>>> #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
>>>> #endif
>>>>
>>>> +#ifdef CONFIG_CMD_NET
>>>> +#define CONFIG_FEC_MXC
>>>> +#define CONFIG_MII
>>>> +#define CONFIG_FEC_ENET_DEV		1
>>>> +
>>>> +#if (CONFIG_FEC_ENET_DEV == 0)
>>>> +#define IMX_FEC_BASE			ENET_BASE_ADDR
>>>> +#define CONFIG_FEC_MXC_PHYADDR          0x2
>>>> +#define CONFIG_FEC_XCV_TYPE             RMII
>>>> +#elif (CONFIG_FEC_ENET_DEV == 1)
>>>> +#define IMX_FEC_BASE			ENET2_BASE_ADDR
>>>> +#define CONFIG_FEC_MXC_PHYADDR		0x1
>>>> +#define CONFIG_FEC_XCV_TYPE		RMII
>>>> +#endif
>>>> +#define CONFIG_ETHPRIME			"FEC"
>>>> +
>>>> +#define CONFIG_PHYLIB
>>>> +#define CONFIG_PHY_MICREL
>>>> +#define CONFIG_FEC_DMA_MINALIGN		64
>>>> +#endif
>>>> +
>>>> #define CONFIG_IMX6_THERMAL
>>>>
>>>> #endif
>>>> -- 
>>>> 1.8.4
>>>>
>>>>
>>>
>>
>>
>> -- 
>> =====================================================================
>> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
>> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>> Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
>> =====================================================================
> 


-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 2/3] net: fec: do not access reserved register for i.MX6UL
  2015-08-23 15:43   ` Stefano Babic
@ 2015-08-31 17:14     ` Stefano Babic
  2015-09-01  0:32       ` Peng Fan
  0 siblings, 1 reply; 16+ messages in thread
From: Stefano Babic @ 2015-08-31 17:14 UTC (permalink / raw)
  To: u-boot

Hi Peng,

On 23/08/2015 17:43, Stefano Babic wrote:
> On 12/08/2015 11:40, Peng Fan wrote:
>> The MIB RAM and FIFO receive start register does not exist on
>> i.MX6UL. Accessing these register will cause enet not work well.
>>
>> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
>> Signed-off-by: Fugang Duan <B38611@freescale.com>
>> Cc: Joe Hershberger <joe.hershberger@ni.com>
>> Cc: Stefano Babic <sbabic@denx.de>
>> ---
>>
>> Changes v2:
>>  Using runtime check, but not hardcoding "#ifdef".
>>  This patch depends on the runtime checking patch:
>>  https://patchwork.ozlabs.org/patch/505621/.
>>
>>  drivers/net/fec_mxc.c | 14 +++++++++-----
>>  1 file changed, 9 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
>> index c5dcbbb..bff5fd1 100644
>> --- a/drivers/net/fec_mxc.c
>> +++ b/drivers/net/fec_mxc.c
>> @@ -17,6 +17,7 @@
>>  
>>  #include <asm/arch/clock.h>
>>  #include <asm/arch/imx-regs.h>
>> +#include <asm/imx-common/sys_proto.h>
>>  #include <asm/io.h>
>>  #include <asm/errno.h>
>>  #include <linux/compiler.h>
>> @@ -551,12 +552,15 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
>>  	writel(0x00000000, &fec->eth->gaddr2);
>>  
>>  
>> -	/* clear MIB RAM */
>> -	for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
>> -		writel(0, i);
>> +	/* Do not access reserved register for i.MX6UL */
>> +	if (!is_cpu_type(MXC_CPU_MX6UL)) {
>> +		/* clear MIB RAM */
>> +		for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
>> +			writel(0, i);
>>  
>> -	/* FIFO receive start register */
>> -	writel(0x520, &fec->eth->r_fstart);
>> +		/* FIFO receive start register */
>> +		writel(0x520, &fec->eth->r_fstart);
>> +	}
>>  
>>  	/* size and address of each buffer */
>>  	writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
>>
> 

Patch is already applied - however, I have found that this break build
for vf610 boards (they have not a get_cpu_rev()). You can check with the
current u-boot-imx.

Can you take a look, please ?

Thanks,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 2/3] net: fec: do not access reserved register for i.MX6UL
  2015-08-31 17:14     ` Stefano Babic
@ 2015-09-01  0:32       ` Peng Fan
  2015-09-01  7:15         ` Stefano Babic
  0 siblings, 1 reply; 16+ messages in thread
From: Peng Fan @ 2015-09-01  0:32 UTC (permalink / raw)
  To: u-boot

Hi Stefano,

On Mon, Aug 31, 2015 at 07:14:06PM +0200, Stefano Babic wrote:
>Hi Peng,
>
>On 23/08/2015 17:43, Stefano Babic wrote:
>> On 12/08/2015 11:40, Peng Fan wrote:
>>> The MIB RAM and FIFO receive start register does not exist on
>>> i.MX6UL. Accessing these register will cause enet not work well.
>>>
>>> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
>>> Signed-off-by: Fugang Duan <B38611@freescale.com>
>>> Cc: Joe Hershberger <joe.hershberger@ni.com>
>>> Cc: Stefano Babic <sbabic@denx.de>
>>> ---
>>>
>>> Changes v2:
>>>  Using runtime check, but not hardcoding "#ifdef".
>>>  This patch depends on the runtime checking patch:
>>>  https://patchwork.ozlabs.org/patch/505621/.
>>>
>>>  drivers/net/fec_mxc.c | 14 +++++++++-----
>>>  1 file changed, 9 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
>>> index c5dcbbb..bff5fd1 100644
>>> --- a/drivers/net/fec_mxc.c
>>> +++ b/drivers/net/fec_mxc.c
>>> @@ -17,6 +17,7 @@
>>>  
>>>  #include <asm/arch/clock.h>
>>>  #include <asm/arch/imx-regs.h>
>>> +#include <asm/imx-common/sys_proto.h>
>>>  #include <asm/io.h>
>>>  #include <asm/errno.h>
>>>  #include <linux/compiler.h>
>>> @@ -551,12 +552,15 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
>>>  	writel(0x00000000, &fec->eth->gaddr2);
>>>  
>>>  
>>> -	/* clear MIB RAM */
>>> -	for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
>>> -		writel(0, i);
>>> +	/* Do not access reserved register for i.MX6UL */
>>> +	if (!is_cpu_type(MXC_CPU_MX6UL)) {
>>> +		/* clear MIB RAM */
>>> +		for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
>>> +			writel(0, i);
>>>  
>>> -	/* FIFO receive start register */
>>> -	writel(0x520, &fec->eth->r_fstart);
>>> +		/* FIFO receive start register */
>>> +		writel(0x520, &fec->eth->r_fstart);
>>> +	}
>>>  
>>>  	/* size and address of each buffer */
>>>  	writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
>>>
>> 
>
>Patch is already applied - however, I have found that this break build
>for vf610 boards (they have not a get_cpu_rev()). You can check with the
>current u-boot-imx.
>

Sorry, I checked all i.MXes, but missed vf610.

>Can you take a look, please ?

I worked a simple patch: https://patchwork.ozlabs.org/patch/512669/
Add an empty function to avoid build errors. Current we do not have
drivers to check vf610 cpu types, later if we need saying
"is_cpu_type(VF610)", we can add more stuff to the function get_cpu_rev
for vf610.

Regards,
Peng.
>
>Thanks,
>Stefano Babic
>
>
>-- 
>=====================================================================
>DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
>HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
>=====================================================================

-- 

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 2/3] net: fec: do not access reserved register for i.MX6UL
  2015-09-01  0:32       ` Peng Fan
@ 2015-09-01  7:15         ` Stefano Babic
  0 siblings, 0 replies; 16+ messages in thread
From: Stefano Babic @ 2015-09-01  7:15 UTC (permalink / raw)
  To: u-boot

Hi Peng,

On 01/09/2015 02:32, Peng Fan wrote:

>> Patch is already applied - however, I have found that this break build
>> for vf610 boards (they have not a get_cpu_rev()). You can check with the
>> current u-boot-imx.
>>
> 
> Sorry, I checked all i.MXes, but missed vf610.

No problem - we fix it !

> 
>> Can you take a look, please ?
> 
> I worked a simple patch: https://patchwork.ozlabs.org/patch/512669/
> Add an empty function to avoid build errors. Current we do not have
> drivers to check vf610 cpu types, later if we need saying
> "is_cpu_type(VF610)", we can add more stuff to the function get_cpu_rev
> for vf610.
> 

I hoped to have a right get_cpu_rev() for VF610, too. Then I checked in
the VF610 manual, but I found revision only for specific controllers -
EHCI, etc. I have not found anything equivalent, but maybe it is better
hidden.

Of course, we can do with an empty function if we have not something
better. Maybe do you can check in Freescale if there is a way to get the
cpu revision instead of a dummy ?

Thanks,
Stefano Babic


-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 1/3] imx: clock support enet2 anatop clock support
  2015-08-12  9:46 Peng Fan
@ 2015-08-12 10:18 ` Stefan Roese
  0 siblings, 0 replies; 16+ messages in thread
From: Stefan Roese @ 2015-08-12 10:18 UTC (permalink / raw)
  To: u-boot

On 12.08.2015 11:46, Peng Fan wrote:
> To i.MX6SX/UL, two ethernet interfaces are supported.
> Add ENET2 clock support:
> 1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed.
>     To value 1, only i.MX6SX/UL can pass the check.
> 2. Modify board code who use this api to follow new api prototype.
>
> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
> Cc: Heiko Schocher <hs@denx.de>
> Cc: Fabio Estevam <fabio.estevam@freescale.com>
> Cc: Stefan Roese <sr@denx.de>
> Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos@imgtec.com>
> Cc: Stefano Babic <sbabic@denx.de>

Reviewed-by: Stefan Roese <sr@denx.de>

Thanks,
Stefan

^ permalink raw reply	[flat|nested] 16+ messages in thread
* [U-Boot] [PATCH V2 1/3] imx: clock support enet2 anatop clock support
@ 2015-08-12  9:46 Peng Fan
  2015-08-12 10:18 ` Stefan Roese
  0 siblings, 1 reply; 16+ messages in thread
From: Peng Fan @ 2015-08-12  9:46 UTC (permalink / raw)
  To: u-boot

To i.MX6SX/UL, two ethernet interfaces are supported.
Add ENET2 clock support:
1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed.
   To value 1, only i.MX6SX/UL can pass the check.
2. Modify board code who use this api to follow new api prototype.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos@imgtec.com>
Cc: Stefano Babic <sbabic@denx.de>
---

Changes v2:
 Addressed Fabio's comments. Using "fec_id == 0", but not "0 == fec_id".

 arch/arm/cpu/armv7/mx6/clock.c                | 23 ++++++++++++++++++-----
 arch/arm/include/asm/arch-mx6/clock.h         |  2 +-
 arch/arm/include/asm/arch-mx6/crm_regs.h      |  6 ++++++
 board/aristainetos/aristainetos-v1.c          |  2 +-
 board/barco/platinum/platinum_picon.c         |  2 +-
 board/freescale/mx6qsabreauto/mx6qsabreauto.c |  2 +-
 board/freescale/mx6slevk/mx6slevk.c           |  2 +-
 board/freescale/mx6sxsabresd/mx6sxsabresd.c   |  2 +-
 board/solidrun/mx6cuboxi/mx6cuboxi.c          |  2 +-
 9 files changed, 31 insertions(+), 12 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 9cf4eec..ba6cc75 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -524,7 +524,7 @@ void enable_qspi_clk(int qspi_num)
 #endif
 
 #ifdef CONFIG_FEC_MXC
-int enable_fec_anatop_clock(enum enet_freq freq)
+int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
 {
 	u32 reg = 0;
 	s32 timeout = 100000;
@@ -535,9 +535,19 @@ int enable_fec_anatop_clock(enum enet_freq freq)
 	if (freq < ENET_25MHZ || freq > ENET_125MHZ)
 		return -EINVAL;
 
-	reg = readl(&anatop->pll_enet);
-	reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
-	reg |= freq;
+	if (fec_id == 0) {
+		reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
+		reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
+	} else if (fec_id == 1) {
+		/* Only i.MX6SX/UL support ENET2 */
+		if (!(is_cpu_type(MXC_CPU_MX6SX) ||
+		      is_cpu_type(MXC_CPU_MX6UL)))
+			return -EINVAL;
+		reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
+		reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
+	} else {
+		return -EINVAL;
+	}
 
 	if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
 	    (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
@@ -552,7 +562,10 @@ int enable_fec_anatop_clock(enum enet_freq freq)
 	}
 
 	/* Enable FEC clock */
-	reg |= BM_ANADIG_PLL_ENET_ENABLE;
+	if (fec_id == 0)
+		reg |= BM_ANADIG_PLL_ENET_ENABLE;
+	else
+		reg |= BM_ANADIG_PLL_ENET2_ENABLE;
 	reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 	writel(reg, &anatop->pll_enet);
 
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 7b3bbb8..2b220d6 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -64,7 +64,7 @@ int enable_pcie_clock(void);
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 int enable_spi_clk(unsigned char enable, unsigned spi_num);
 void enable_ipu_clock(void);
-int enable_fec_anatop_clock(enum enet_freq freq);
+int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
 void enable_enet_clk(unsigned char enable);
 void enable_qspi_clk(int qspi_num);
 void enable_thermal_clk(void);
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index fe75da4..10306cd 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -1052,6 +1052,12 @@ struct mxc_ccm_reg {
 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v)  \
 	(((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
 
+/* ENET2 for i.MX6SX/UL */
+#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000
+#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C
+#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v)  \
+	(((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT)
+
 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
 #define BP_ANADIG_PFD_480_PFD3_FRAC      24
diff --git a/board/aristainetos/aristainetos-v1.c b/board/aristainetos/aristainetos-v1.c
index d6a7614..b8fed2e 100644
--- a/board/aristainetos/aristainetos-v1.c
+++ b/board/aristainetos/aristainetos-v1.c
@@ -185,7 +185,7 @@ int board_eth_init(bd_t *bis)
 	/* clear gpr1[14], gpr1[18:17] to select anatop clock */
 	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
 
-	ret = enable_fec_anatop_clock(ENET_50MHZ);
+	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
 	if (ret)
 		return ret;
 
diff --git a/board/barco/platinum/platinum_picon.c b/board/barco/platinum/platinum_picon.c
index b2eab76..0384a26 100644
--- a/board/barco/platinum/platinum_picon.c
+++ b/board/barco/platinum/platinum_picon.c
@@ -148,7 +148,7 @@ int platinum_setup_enet(void)
 	/* set GPIO_16 as ENET_REF_CLK_OUT */
 	setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
 
-	return enable_fec_anatop_clock(ENET_50MHZ);
+	return enable_fec_anatop_clock(0, ENET_50MHZ);
 }
 
 int platinum_setup_i2c(void)
diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 98602f8..7c0e90a 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -361,7 +361,7 @@ static void setup_fec(void)
 		 * select ENET MAC0 TX clock from PLL
 		 */
 		imx_iomux_set_gpr_register(5, 9, 1, 1);
-		enable_fec_anatop_clock(ENET_125MHZ);
+		enable_fec_anatop_clock(0, ENET_125MHZ);
 	}
 
 	setup_iomux_enet();
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index 7c18c90..98e3ef0 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -279,7 +279,7 @@ static int setup_fec(void)
 	/* clear gpr1[14], gpr1[18:17] to select anatop clock */
 	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
 
-	return enable_fec_anatop_clock(ENET_50MHZ);
+	return enable_fec_anatop_clock(0, ENET_50MHZ);
 }
 #endif
 
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index d58a79a..ffc0046 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -170,7 +170,7 @@ static int setup_fec(void)
 	reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
 	writel(reg, &anatop->pll_enet);
 
-	return enable_fec_anatop_clock(ENET_125MHZ);
+	return enable_fec_anatop_clock(0, ENET_125MHZ);
 }
 
 int board_eth_init(bd_t *bis)
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index 9b1ecf0..8247e43 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -164,7 +164,7 @@ int board_eth_init(bd_t *bis)
 	struct mii_dev *bus;
 	struct phy_device *phydev;
 
-	int ret = enable_fec_anatop_clock(ENET_25MHZ);
+	int ret = enable_fec_anatop_clock(0, ENET_25MHZ);
 	if (ret)
 		return ret;
 
-- 
1.8.4

^ permalink raw reply related	[flat|nested] 16+ messages in thread
end of thread, other threads:[~2015-09-01  7:15 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-08-12  9:40 [U-Boot] [PATCH V2 1/3] imx: clock support enet2 anatop clock support Peng Fan
2015-08-12  9:40 ` [U-Boot] [PATCH V2 2/3] net: fec: do not access reserved register for i.MX6UL Peng Fan
2015-08-12 19:15   ` Joe Hershberger
2015-08-23 15:43   ` Stefano Babic
2015-08-31 17:14     ` Stefano Babic
2015-09-01  0:32       ` Peng Fan
2015-09-01  7:15         ` Stefano Babic
2015-08-12  9:40 ` [U-Boot] [PATCH V2 3/3] imx: mx6ul_14x14_evk add ENET support Peng Fan
2015-08-12  8:34   ` Peng Fan
2015-08-23 15:45     ` Stefano Babic
2015-08-24  0:07       ` Peng Fan
2015-08-24  7:31         ` Stefano Babic
2015-08-24  6:35           ` Peng Fan
2015-08-23 15:43 ` [U-Boot] [PATCH V2 1/3] imx: clock support enet2 anatop clock support Stefano Babic
2015-08-12  9:46 Peng Fan
2015-08-12 10:18 ` Stefan Roese

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