* [PATCH v2 0/5] Add fec1 and fec2 support for i.MX7d sdb board
@ 2015-08-24 3:29 Fugang Duan
2015-08-24 3:29 ` [PATCH v2 1/5] ARM: imx7d: add imx7d iomux-gpr field define Fugang Duan
` (5 more replies)
0 siblings, 6 replies; 13+ messages in thread
From: Fugang Duan @ 2015-08-24 3:29 UTC (permalink / raw)
To: linux-arm-kernel
The patch series is to add fec support for i.MX7d sdb board. Since i.MX7d fec ip is
the same as i.MX6SX, so there have no change for driver itself.
Patch#1: add bcm54220 PHY ID entry into brcmphy.h file.
Patch#2: add new iomux-gpr file to define iomux-gpr register and field for i.MX7d.
Patch#3: i.MX7d sdb board install bcm54220 phy, i.MX7d arm2 board install AR8031 phy.
For the two phys, there needs extra phy setting, so package the setting to fixup.
Patch#4~6: Add fec dts node and pinmux setting in dts file.
Change:
V2:
* Remove patch#1 in V1 patch series. Move the sigle BCM54220 PHY ID define to machine file.
* The current BCM54220 switch phy still use generic phy driver since broadcom phy driver don't
support the switch phy, there need effort to add the switch phy support. Once broadcom phy driver
will support the bcm54220 switch phy, we can add the special config to imx_v6_v7_defconfig.
Fugang Duan (5):
ARM: imx7d: add imx7d iomux-gpr field define
ARM: imx: add enet init for i.MX7D platform
ARM: dts: imx: pinfunc: add GPIO1 pin define for i.MX7d
ARM: dts: imx7d: add fec1 and fec2 support for i.MX7d soc
ARM: dts: imx7d-sdb: add fec1 and fec2 support
arch/arm/boot/dts/imx7d-pinfunc.h | 115 +++++++++++++++++++++++++++++
arch/arm/boot/dts/imx7d-sdb.dts | 76 ++++++++++++++++++-
arch/arm/boot/dts/imx7d.dtsi | 36 +++++++++
arch/arm/mach-imx/mach-imx7d.c | 76 ++++++++++++++++++-
include/linux/mfd/syscon/imx7-iomuxc-gpr.h | 49 ++++++++++++
5 files changed, 349 insertions(+), 3 deletions(-)
create mode 100644 include/linux/mfd/syscon/imx7-iomuxc-gpr.h
--
1.9.1
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 1/5] ARM: imx7d: add imx7d iomux-gpr field define
2015-08-24 3:29 [PATCH v2 0/5] Add fec1 and fec2 support for i.MX7d sdb board Fugang Duan
@ 2015-08-24 3:29 ` Fugang Duan
2015-09-06 12:33 ` Shawn Guo
2015-08-24 3:29 ` [PATCH v2 2/5] ARM: imx: add enet init for i.MX7D platform Fugang Duan
` (4 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Fugang Duan @ 2015-08-24 3:29 UTC (permalink / raw)
To: linux-arm-kernel
Add imx7d iomux-gpr field define.
Signed-off-by: Fugang Duan <B38611@freescale.com>
---
include/linux/mfd/syscon/imx7-iomuxc-gpr.h | 49 ++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/include/linux/mfd/syscon/imx7-iomuxc-gpr.h b/include/linux/mfd/syscon/imx7-iomuxc-gpr.h
new file mode 100644
index 0000000..5cc0553
--- /dev/null
+++ b/include/linux/mfd/syscon/imx7-iomuxc-gpr.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_IMX7_IOMUXC_GPR_H
+#define __LINUX_IMX7_IOMUXC_GPR_H
+
+#include <linux/bitops.h>
+
+#define IOMUXC_GPR0 0x00
+#define IOMUXC_GPR1 0x04
+#define IOMUXC_GPR2 0x08
+#define IOMUXC_GPR3 0x0c
+#define IOMUXC_GPR4 0x10
+#define IOMUXC_GPR5 0x14
+#define IOMUXC_GPR6 0x18
+#define IOMUXC_GPR7 0x1c
+#define IOMUXC_GPR8 0x20
+#define IOMUXC_GPR9 0x24
+#define IOMUXC_GPR10 0x28
+#define IOMUXC_GPR11 0x2c
+#define IOMUXC_GPR12 0x30
+#define IOMUXC_GPR13 0x34
+#define IOMUXC_GPR14 0x38
+#define IOMUXC_GPR15 0x3c
+#define IOMUXC_GPR16 0x40
+#define IOMUXC_GPR17 0x44
+#define IOMUXC_GPR18 0x48
+#define IOMUXC_GPR19 0x4c
+#define IOMUXC_GPR20 0x50
+#define IOMUXC_GPR21 0x54
+#define IOMUXC_GPR22 0x58
+
+/* For imx7d iomux gpr register field define */
+#define IMX7D_GPR1_IRQ_MASK (0x1 << 12)
+#define IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK (0x1 << 13)
+#define IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK (0x1 << 14)
+#define IMX7D_GPR1_ENET_TX_CLK_SEL_MASK (0x3 << 13)
+#define IMX7D_GPR1_ENET1_CLK_DIR_MASK (0x1 << 17)
+#define IMX7D_GPR1_ENET2_CLK_DIR_MASK (0x1 << 18)
+#define IMX7D_GPR1_ENET_CLK_DIR_MASK (0x3 << 17)
+
+#define IMX7D_GPR5_CSI_MUX_CONTROL_MIPI (0x1 << 4)
+
+#endif /* __LINUX_IMX7_IOMUXC_GPR_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 2/5] ARM: imx: add enet init for i.MX7D platform
2015-08-24 3:29 [PATCH v2 0/5] Add fec1 and fec2 support for i.MX7d sdb board Fugang Duan
2015-08-24 3:29 ` [PATCH v2 1/5] ARM: imx7d: add imx7d iomux-gpr field define Fugang Duan
@ 2015-08-24 3:29 ` Fugang Duan
2015-09-06 12:37 ` Shawn Guo
2015-08-24 3:29 ` [PATCH v2 3/5] ARM: dts: imx: pinfunc: add GPIO1 pin define for i.MX7d Fugang Duan
` (3 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Fugang Duan @ 2015-08-24 3:29 UTC (permalink / raw)
To: linux-arm-kernel
Add enet phy fixup, clock source init for i.MX7D platform.
Signed-off-by: Fugang Duan <B38611@freescale.com>
---
arch/arm/mach-imx/mach-imx7d.c | 76 ++++++++++++++++++++++++++++++++++++++++--
1 file changed, 74 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c
index 4d4a190..07e9a7e 100644
--- a/arch/arm/mach-imx/mach-imx7d.c
+++ b/arch/arm/mach-imx/mach-imx7d.c
@@ -5,13 +5,84 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-#include <linux/irqchip.h>
-#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
+#include <linux/irqchip.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
+#include <linux/of_platform.h>
+#include <linux/phy.h>
+#include <linux/regmap.h>
#include "common.h"
+static int ar8031_phy_fixup(struct phy_device *dev)
+{
+ u16 val;
+
+ /* Set RGMII IO voltage to 1.8V */
+ phy_write(dev, 0x1d, 0x1f);
+ phy_write(dev, 0x1e, 0x8);
+
+ /* disable phy AR8031 SmartEEE function. */
+ phy_write(dev, 0xd, 0x3);
+ phy_write(dev, 0xe, 0x805d);
+ phy_write(dev, 0xd, 0x4003);
+ val = phy_read(dev, 0xe);
+ val &= ~(0x1 << 8);
+ phy_write(dev, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(dev, 0x1d, 0x5);
+ val = phy_read(dev, 0x1e);
+ val |= 0x0100;
+ phy_write(dev, 0x1e, val);
+
+ return 0;
+}
+
+static int bcm54220_phy_fixup(struct phy_device *dev)
+{
+ /* enable RXC skew select RGMII copper mode */
+ phy_write(dev, 0x1e, 0x21);
+ phy_write(dev, 0x1f, 0x7ea8);
+ phy_write(dev, 0x1e, 0x2f);
+ phy_write(dev, 0x1f, 0x71b7);
+
+ return 0;
+}
+
+#define PHY_ID_AR8031 0x004dd074
+#define PHY_ID_BCM54220 0x600d8589
+static void __init imx7d_enet_phy_init(void)
+{
+ if (IS_BUILTIN(CONFIG_PHYLIB)) {
+ phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
+ ar8031_phy_fixup);
+ phy_register_fixup_for_uid(PHY_ID_BCM54220, 0xffffffff,
+ bcm54220_phy_fixup);
+ }
+}
+
+static void __init imx7d_enet_clk_sel(void)
+{
+ struct regmap *gpr;
+
+ gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr");
+ if (!IS_ERR(gpr)) {
+ regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0);
+ regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0);
+ } else {
+ pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n");
+ }
+}
+
+static inline void imx7d_enet_init(void)
+{
+ imx7d_enet_phy_init();
+ imx7d_enet_clk_sel();
+}
+
static void __init imx7d_init_machine(void)
{
struct device *parent;
@@ -22,6 +93,7 @@ static void __init imx7d_init_machine(void)
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
imx_anatop_init();
+ imx7d_enet_init();
}
static void __init imx7d_init_irq(void)
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 3/5] ARM: dts: imx: pinfunc: add GPIO1 pin define for i.MX7d
2015-08-24 3:29 [PATCH v2 0/5] Add fec1 and fec2 support for i.MX7d sdb board Fugang Duan
2015-08-24 3:29 ` [PATCH v2 1/5] ARM: imx7d: add imx7d iomux-gpr field define Fugang Duan
2015-08-24 3:29 ` [PATCH v2 2/5] ARM: imx: add enet init for i.MX7D platform Fugang Duan
@ 2015-08-24 3:29 ` Fugang Duan
2015-09-06 13:08 ` Shawn Guo
2015-08-24 3:29 ` [PATCH v2 4/5] ARM: dts: imx7d: add fec1 and fec2 support for i.MX7d soc Fugang Duan
` (2 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Fugang Duan @ 2015-08-24 3:29 UTC (permalink / raw)
To: linux-arm-kernel
Add GPIO1 pin define for i.MX7d.
Signed-off-by: Fugang Duan <B38611@freescale.com>
---
arch/arm/boot/dts/imx7d-pinfunc.h | 115 ++++++++++++++++++++++++++++++++++++++
1 file changed, 115 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h
index a8d8149..8b3cf2bc 100644
--- a/arch/arm/boot/dts/imx7d-pinfunc.h
+++ b/arch/arm/boot/dts/imx7d-pinfunc.h
@@ -15,6 +15,121 @@
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
+#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
+#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3
+#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0
+#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3
+#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3
+#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0
+#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3
+#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1
+#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1
+#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x4
+#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2
+#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1
+#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5
+#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2
+#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1
+#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1
+#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0x4
+#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2
+#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0
+#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1
+#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1
+#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA 0x001C 0x004C 0x0714 0x3 0x5
+#define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2
+#define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0
+#define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1
+#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO08__UART3_DCE_RX 0x0014 0x026C 0x0704 0x3 0x0
+#define MX7D_PAD_GPIO1_IO08__UART3_DTE_TX 0x0014 0x026C 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO08__I2C3_SCL 0x0014 0x026C 0x05E4 0x4 0x0
+#define MX7D_PAD_GPIO1_IO08__KPP_COL5 0x0014 0x026C 0x0608 0x6 0x0
+#define MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x0014 0x026C 0x0000 0x7 0x0
+#define MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x0018 0x0270 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO09__SD1_LCTL 0x0018 0x0270 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 0x0018 0x0270 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO09__UART3_DCE_TX 0x0018 0x0270 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO09__UART3_DTE_RX 0x0018 0x0270 0x0704 0x3 0x1
+#define MX7D_PAD_GPIO1_IO09__I2C3_SDA 0x0018 0x0270 0x05E8 0x4 0x0
+#define MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY 0x0018 0x0270 0x04F4 0x5 0x0
+#define MX7D_PAD_GPIO1_IO09__KPP_ROW5 0x0018 0x0270 0x0628 0x6 0x0
+#define MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x0018 0x0270 0x0000 0x7 0x0
+#define MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x001C 0x0274 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO10__SD2_LCTL 0x001C 0x0274 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x001C 0x0274 0x0568 0x2 0x0
+#define MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS 0x001C 0x0274 0x0700 0x3 0x0
+#define MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS 0x001C 0x0274 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO10__I2C4_SCL 0x001C 0x0274 0x05EC 0x4 0x0
+#define MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA 0x001C 0x0274 0x05A4 0x5 0x0
+#define MX7D_PAD_GPIO1_IO10__KPP_COL6 0x001C 0x0274 0x060C 0x6 0x0
+#define MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x001C 0x0274 0x0000 0x7 0x0
+#define MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x0020 0x0278 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO11__SD3_LCTL 0x0020 0x0278 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x0020 0x0278 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS 0x0020 0x0278 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS 0x0020 0x0278 0x0700 0x3 0x1
+#define MX7D_PAD_GPIO1_IO11__I2C4_SDA 0x0020 0x0278 0x05F0 0x4 0x0
+#define MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB 0x0020 0x0278 0x05A8 0x5 0x0
+#define MX7D_PAD_GPIO1_IO11__KPP_ROW6 0x0020 0x0278 0x062C 0x6 0x0
+#define MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x0020 0x0278 0x0000 0x7 0x0
+#define MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0024 0x027C 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x0024 0x027C 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x0024 0x027C 0x0564 0x2 0x0
+#define MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0024 0x027C 0x04DC 0x3 0x0
+#define MX7D_PAD_GPIO1_IO12__CM4_NMI 0x0024 0x027C 0x0000 0x4 0x0
+#define MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 0x0024 0x027C 0x04E4 0x5 0x0
+#define MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 0x0024 0x027C 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO12__USB_OTG1_ID 0x0024 0x027C 0x0734 0x7 0x0
+#define MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x0028 0x0280 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO13__SD3_VSELECT 0x0028 0x0280 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 0x0028 0x0280 0x0570 0x2 0x0
+#define MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0028 0x0280 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY 0x0028 0x0280 0x04F4 0x4 0x1
+#define MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 0x0028 0x0280 0x04E8 0x5 0x0
+#define MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL 0x0028 0x0280 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO13__USB_OTG2_ID 0x0028 0x0280 0x0730 0x7 0x0
+#define MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x002C 0x0284 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO14__SD3_CD_B 0x002C 0x0284 0x0738 0x1 0x0
+#define MX7D_PAD_GPIO1_IO14__ENET2_MDIO 0x002C 0x0284 0x0574 0x2 0x0
+#define MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x002C 0x0284 0x04E0 0x3 0x0
+#define MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B 0x002C 0x0284 0x0000 0x4 0x0
+#define MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 0x002C 0x0284 0x04EC 0x5 0x0
+#define MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 0x002C 0x0284 0x06D8 0x6 0x0
+#define MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x0030 0x0288 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO15__SD3_WP 0x0030 0x0288 0x073C 0x1 0x0
+#define MX7D_PAD_GPIO1_IO15__ENET2_MDC 0x0030 0x0288 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0030 0x0288 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B 0x0030 0x0288 0x0000 0x4 0x0
+#define MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 0x0030 0x0288 0x04F0 0x5 0x0
+#define MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 0x0030 0x0288 0x06DC 0x6 0x0
#define MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x0034 0x02A4 0x0000 0x0 0x0
#define MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD 0x0034 0x02A4 0x0000 0x1 0x0
#define MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x0034 0x02A4 0x0000 0x2 0x0
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 4/5] ARM: dts: imx7d: add fec1 and fec2 support for i.MX7d soc
2015-08-24 3:29 [PATCH v2 0/5] Add fec1 and fec2 support for i.MX7d sdb board Fugang Duan
` (2 preceding siblings ...)
2015-08-24 3:29 ` [PATCH v2 3/5] ARM: dts: imx: pinfunc: add GPIO1 pin define for i.MX7d Fugang Duan
@ 2015-08-24 3:29 ` Fugang Duan
2015-08-24 3:29 ` [PATCH v2 5/5] ARM: dts: imx7d-sdb: add fec1 and fec2 support Fugang Duan
2015-09-06 13:11 ` [PATCH v2 0/5] Add fec1 and fec2 support for i.MX7d sdb board Shawn Guo
5 siblings, 0 replies; 13+ messages in thread
From: Fugang Duan @ 2015-08-24 3:29 UTC (permalink / raw)
To: linux-arm-kernel
Add fec1 and fec2 nodes for i.MX7d soc.
Signed-off-by: Fugang Duan <B38611@freescale.com>
---
arch/arm/boot/dts/imx7d.dtsi | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index b738ce0..7631492 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -729,6 +729,42 @@
bus-width = <4>;
status = "disabled";
};
+
+ fec1: ethernet at 30be0000 {
+ compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
+ reg = <0x30be0000 0x10000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+ <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+ <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
+ <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
+ <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
+ clock-names = "ipg", "ahb", "ptp",
+ "enet_clk_ref", "enet_out";
+ fsl,num-tx-queues=<3>;
+ fsl,num-rx-queues=<3>;
+ status = "disabled";
+ };
+
+ fec2: ethernet at 30bf0000 {
+ compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
+ reg = <0x30bf0000 0x10000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+ <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+ <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
+ <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
+ <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
+ clock-names = "ipg", "ahb", "ptp",
+ "enet_clk_ref", "enet_out";
+ fsl,num-tx-queues=<3>;
+ fsl,num-rx-queues=<3>;
+ status = "disabled";
+ };
};
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 5/5] ARM: dts: imx7d-sdb: add fec1 and fec2 support
2015-08-24 3:29 [PATCH v2 0/5] Add fec1 and fec2 support for i.MX7d sdb board Fugang Duan
` (3 preceding siblings ...)
2015-08-24 3:29 ` [PATCH v2 4/5] ARM: dts: imx7d: add fec1 and fec2 support for i.MX7d soc Fugang Duan
@ 2015-08-24 3:29 ` Fugang Duan
2015-09-06 13:11 ` [PATCH v2 0/5] Add fec1 and fec2 support for i.MX7d sdb board Shawn Guo
5 siblings, 0 replies; 13+ messages in thread
From: Fugang Duan @ 2015-08-24 3:29 UTC (permalink / raw)
To: linux-arm-kernel
Enable fec1 and fec2 for i.MX7d-sdb board.
Signed-off-by: Fugang Duan <B38611@freescale.com>
---
arch/arm/boot/dts/imx7d-sdb.dts | 76 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 75 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 4d1a4b9..7d3e980 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -101,6 +101,45 @@
arm-supply = <&sw1a_reg>;
};
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+ <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+ assigned-clock-rates = <0>, <100000000>;
+ phy-mode = "rgmii";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy at 0 {
+ reg = <0>;
+ };
+
+ ethphy1: ethernet-phy at 1 {
+ reg = <1>;
+ };
+ };
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2>;
+ assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
+ <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+ assigned-clock-rates = <0>, <100000000>;
+ phy-mode = "rgmii";
+ phy-handle = <ðphy1>;
+ fsl,magic-packet;
+ status = "okay";
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
@@ -246,6 +285,42 @@
pinctrl-0 = <&pinctrl_hog>;
imx7d-sdb {
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
+ MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
+ MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
+ MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
+ MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
+ MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
+ MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
+ MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
+ MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
+ MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
+ MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
+ MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
+ MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
+ MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1
+ MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1
+ MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1
+ MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1
+ MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1
+ MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1
+ MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1
+ MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1
+ MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1
+ MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1
+ MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1
+ MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1
+ >;
+ };
+
pinctrl_hog: hoggrp {
fsl,pins = <
MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14
@@ -281,7 +356,6 @@
>;
};
-
pinctrl_uart1: uart1grp {
fsl,pins = <
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
--
1.9.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 1/5] ARM: imx7d: add imx7d iomux-gpr field define
2015-08-24 3:29 ` [PATCH v2 1/5] ARM: imx7d: add imx7d iomux-gpr field define Fugang Duan
@ 2015-09-06 12:33 ` Shawn Guo
2015-09-07 2:20 ` Duan Andy
0 siblings, 1 reply; 13+ messages in thread
From: Shawn Guo @ 2015-09-06 12:33 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Aug 24, 2015 at 11:29:48AM +0800, Fugang Duan wrote:
> Add imx7d iomux-gpr field define.
>
> Signed-off-by: Fugang Duan <B38611@freescale.com>
> ---
> include/linux/mfd/syscon/imx7-iomuxc-gpr.h | 49 ++++++++++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
>
> diff --git a/include/linux/mfd/syscon/imx7-iomuxc-gpr.h b/include/linux/mfd/syscon/imx7-iomuxc-gpr.h
> new file mode 100644
> index 0000000..5cc0553
> --- /dev/null
> +++ b/include/linux/mfd/syscon/imx7-iomuxc-gpr.h
> @@ -0,0 +1,49 @@
> +/*
> + * Copyright (C) 2015 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __LINUX_IMX7_IOMUXC_GPR_H
> +#define __LINUX_IMX7_IOMUXC_GPR_H
> +
> +#include <linux/bitops.h>
> +
> +#define IOMUXC_GPR0 0x00
> +#define IOMUXC_GPR1 0x04
> +#define IOMUXC_GPR2 0x08
> +#define IOMUXC_GPR3 0x0c
> +#define IOMUXC_GPR4 0x10
> +#define IOMUXC_GPR5 0x14
> +#define IOMUXC_GPR6 0x18
> +#define IOMUXC_GPR7 0x1c
> +#define IOMUXC_GPR8 0x20
> +#define IOMUXC_GPR9 0x24
> +#define IOMUXC_GPR10 0x28
> +#define IOMUXC_GPR11 0x2c
> +#define IOMUXC_GPR12 0x30
> +#define IOMUXC_GPR13 0x34
> +#define IOMUXC_GPR14 0x38
> +#define IOMUXC_GPR15 0x3c
> +#define IOMUXC_GPR16 0x40
> +#define IOMUXC_GPR17 0x44
> +#define IOMUXC_GPR18 0x48
> +#define IOMUXC_GPR19 0x4c
> +#define IOMUXC_GPR20 0x50
> +#define IOMUXC_GPR21 0x54
> +#define IOMUXC_GPR22 0x58
> +
> +/* For imx7d iomux gpr register field define */
> +#define IMX7D_GPR1_IRQ_MASK (0x1 << 12)
You might want to use BIT() macro here or drop <linux/bitops.h>
inclusion above.
Shawn
> +#define IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK (0x1 << 13)
> +#define IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK (0x1 << 14)
> +#define IMX7D_GPR1_ENET_TX_CLK_SEL_MASK (0x3 << 13)
> +#define IMX7D_GPR1_ENET1_CLK_DIR_MASK (0x1 << 17)
> +#define IMX7D_GPR1_ENET2_CLK_DIR_MASK (0x1 << 18)
> +#define IMX7D_GPR1_ENET_CLK_DIR_MASK (0x3 << 17)
> +
> +#define IMX7D_GPR5_CSI_MUX_CONTROL_MIPI (0x1 << 4)
> +
> +#endif /* __LINUX_IMX7_IOMUXC_GPR_H */
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 2/5] ARM: imx: add enet init for i.MX7D platform
2015-08-24 3:29 ` [PATCH v2 2/5] ARM: imx: add enet init for i.MX7D platform Fugang Duan
@ 2015-09-06 12:37 ` Shawn Guo
2015-09-07 2:21 ` Duan Andy
0 siblings, 1 reply; 13+ messages in thread
From: Shawn Guo @ 2015-09-06 12:37 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Aug 24, 2015 at 11:29:49AM +0800, Fugang Duan wrote:
> Add enet phy fixup, clock source init for i.MX7D platform.
>
> Signed-off-by: Fugang Duan <B38611@freescale.com>
> ---
> arch/arm/mach-imx/mach-imx7d.c | 76 ++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 74 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c
> index 4d4a190..07e9a7e 100644
> --- a/arch/arm/mach-imx/mach-imx7d.c
> +++ b/arch/arm/mach-imx/mach-imx7d.c
> @@ -5,13 +5,84 @@
> * it under the terms of the GNU General Public License version 2 as
> * published by the Free Software Foundation.
> */
> -#include <linux/irqchip.h>
> -#include <linux/of_platform.h>
> #include <asm/mach/arch.h>
> #include <asm/mach/map.h>
> +#include <linux/irqchip.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> +#include <linux/of_platform.h>
> +#include <linux/phy.h>
> +#include <linux/regmap.h>
>
> #include "common.h"
Please arrange the headers like below:
#include <linux/irqchip.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
#include <linux/of_platform.h>
#include <linux/phy.h>
#include <linux/regmap.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "common.h"
>
> +static int ar8031_phy_fixup(struct phy_device *dev)
> +{
> + u16 val;
> +
> + /* Set RGMII IO voltage to 1.8V */
> + phy_write(dev, 0x1d, 0x1f);
> + phy_write(dev, 0x1e, 0x8);
> +
> + /* disable phy AR8031 SmartEEE function. */
> + phy_write(dev, 0xd, 0x3);
> + phy_write(dev, 0xe, 0x805d);
> + phy_write(dev, 0xd, 0x4003);
> + val = phy_read(dev, 0xe);
> + val &= ~(0x1 << 8);
> + phy_write(dev, 0xe, val);
> +
> + /* introduce tx clock delay */
> + phy_write(dev, 0x1d, 0x5);
> + val = phy_read(dev, 0x1e);
> + val |= 0x0100;
> + phy_write(dev, 0x1e, val);
> +
> + return 0;
> +}
> +
> +static int bcm54220_phy_fixup(struct phy_device *dev)
> +{
> + /* enable RXC skew select RGMII copper mode */
> + phy_write(dev, 0x1e, 0x21);
> + phy_write(dev, 0x1f, 0x7ea8);
> + phy_write(dev, 0x1e, 0x2f);
> + phy_write(dev, 0x1f, 0x71b7);
> +
> + return 0;
> +}
> +
> +#define PHY_ID_AR8031 0x004dd074
> +#define PHY_ID_BCM54220 0x600d8589
Have a blank line here.
Shawn
> +static void __init imx7d_enet_phy_init(void)
> +{
> + if (IS_BUILTIN(CONFIG_PHYLIB)) {
> + phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
> + ar8031_phy_fixup);
> + phy_register_fixup_for_uid(PHY_ID_BCM54220, 0xffffffff,
> + bcm54220_phy_fixup);
> + }
> +}
> +
> +static void __init imx7d_enet_clk_sel(void)
> +{
> + struct regmap *gpr;
> +
> + gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr");
> + if (!IS_ERR(gpr)) {
> + regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0);
> + regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0);
> + } else {
> + pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n");
> + }
> +}
> +
> +static inline void imx7d_enet_init(void)
> +{
> + imx7d_enet_phy_init();
> + imx7d_enet_clk_sel();
> +}
> +
> static void __init imx7d_init_machine(void)
> {
> struct device *parent;
> @@ -22,6 +93,7 @@ static void __init imx7d_init_machine(void)
>
> of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> imx_anatop_init();
> + imx7d_enet_init();
> }
>
> static void __init imx7d_init_irq(void)
> --
> 1.9.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 3/5] ARM: dts: imx: pinfunc: add GPIO1 pin define for i.MX7d
2015-08-24 3:29 ` [PATCH v2 3/5] ARM: dts: imx: pinfunc: add GPIO1 pin define for i.MX7d Fugang Duan
@ 2015-09-06 13:08 ` Shawn Guo
2015-09-07 2:23 ` Duan Andy
0 siblings, 1 reply; 13+ messages in thread
From: Shawn Guo @ 2015-09-06 13:08 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Aug 24, 2015 at 11:29:50AM +0800, Fugang Duan wrote:
> Add GPIO1 pin define for i.MX7d.
>
> Signed-off-by: Fugang Duan <B38611@freescale.com>
> ---
> arch/arm/boot/dts/imx7d-pinfunc.h | 115 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 115 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h
> index a8d8149..8b3cf2bc 100644
> --- a/arch/arm/boot/dts/imx7d-pinfunc.h
> +++ b/arch/arm/boot/dts/imx7d-pinfunc.h
> @@ -15,6 +15,121 @@
> * <mux_reg conf_reg input_reg mux_mode input_val>
> */
>
> +#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0
> +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0
> +#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0
> +#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3
> +#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3
> +#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3
> +#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3
> +#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1
> +#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1
> +#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x4
> +#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2
> +#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1
> +#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5
> +#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2
> +#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1
> +#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1
> +#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0x4
> +#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2
> +#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1
> +#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1
> +#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA 0x001C 0x004C 0x0714 0x3 0x5
> +#define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2
> +#define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1
All above lines use tab + spaces for indentation, which is different
from the indentation already used in this file.
Shawn
> +#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0
> +#define MX7D_PAD_GPIO1_IO08__UART3_DCE_RX 0x0014 0x026C 0x0704 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO08__UART3_DTE_TX 0x0014 0x026C 0x0000 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO08__I2C3_SCL 0x0014 0x026C 0x05E4 0x4 0x0
> +#define MX7D_PAD_GPIO1_IO08__KPP_COL5 0x0014 0x026C 0x0608 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x0014 0x026C 0x0000 0x7 0x0
> +#define MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x0018 0x0270 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO09__SD1_LCTL 0x0018 0x0270 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 0x0018 0x0270 0x0000 0x2 0x0
> +#define MX7D_PAD_GPIO1_IO09__UART3_DCE_TX 0x0018 0x0270 0x0000 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO09__UART3_DTE_RX 0x0018 0x0270 0x0704 0x3 0x1
> +#define MX7D_PAD_GPIO1_IO09__I2C3_SDA 0x0018 0x0270 0x05E8 0x4 0x0
> +#define MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY 0x0018 0x0270 0x04F4 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO09__KPP_ROW5 0x0018 0x0270 0x0628 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x0018 0x0270 0x0000 0x7 0x0
> +#define MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x001C 0x0274 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO10__SD2_LCTL 0x001C 0x0274 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x001C 0x0274 0x0568 0x2 0x0
> +#define MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS 0x001C 0x0274 0x0700 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS 0x001C 0x0274 0x0000 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO10__I2C4_SCL 0x001C 0x0274 0x05EC 0x4 0x0
> +#define MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA 0x001C 0x0274 0x05A4 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO10__KPP_COL6 0x001C 0x0274 0x060C 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x001C 0x0274 0x0000 0x7 0x0
> +#define MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x0020 0x0278 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO11__SD3_LCTL 0x0020 0x0278 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x0020 0x0278 0x0000 0x2 0x0
> +#define MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS 0x0020 0x0278 0x0000 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS 0x0020 0x0278 0x0700 0x3 0x1
> +#define MX7D_PAD_GPIO1_IO11__I2C4_SDA 0x0020 0x0278 0x05F0 0x4 0x0
> +#define MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB 0x0020 0x0278 0x05A8 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO11__KPP_ROW6 0x0020 0x0278 0x062C 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x0020 0x0278 0x0000 0x7 0x0
> +#define MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0024 0x027C 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x0024 0x027C 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x0024 0x027C 0x0564 0x2 0x0
> +#define MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0024 0x027C 0x04DC 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO12__CM4_NMI 0x0024 0x027C 0x0000 0x4 0x0
> +#define MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 0x0024 0x027C 0x04E4 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 0x0024 0x027C 0x0000 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO12__USB_OTG1_ID 0x0024 0x027C 0x0734 0x7 0x0
> +#define MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x0028 0x0280 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO13__SD3_VSELECT 0x0028 0x0280 0x0000 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 0x0028 0x0280 0x0570 0x2 0x0
> +#define MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0028 0x0280 0x0000 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY 0x0028 0x0280 0x04F4 0x4 0x1
> +#define MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 0x0028 0x0280 0x04E8 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL 0x0028 0x0280 0x0000 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO13__USB_OTG2_ID 0x0028 0x0280 0x0730 0x7 0x0
> +#define MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x002C 0x0284 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO14__SD3_CD_B 0x002C 0x0284 0x0738 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO14__ENET2_MDIO 0x002C 0x0284 0x0574 0x2 0x0
> +#define MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x002C 0x0284 0x04E0 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B 0x002C 0x0284 0x0000 0x4 0x0
> +#define MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 0x002C 0x0284 0x04EC 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 0x002C 0x0284 0x06D8 0x6 0x0
> +#define MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x0030 0x0288 0x0000 0x0 0x0
> +#define MX7D_PAD_GPIO1_IO15__SD3_WP 0x0030 0x0288 0x073C 0x1 0x0
> +#define MX7D_PAD_GPIO1_IO15__ENET2_MDC 0x0030 0x0288 0x0000 0x2 0x0
> +#define MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0030 0x0288 0x0000 0x3 0x0
> +#define MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B 0x0030 0x0288 0x0000 0x4 0x0
> +#define MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 0x0030 0x0288 0x04F0 0x5 0x0
> +#define MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 0x0030 0x0288 0x06DC 0x6 0x0
> #define MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x0034 0x02A4 0x0000 0x0 0x0
> #define MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD 0x0034 0x02A4 0x0000 0x1 0x0
> #define MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x0034 0x02A4 0x0000 0x2 0x0
> --
> 1.9.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 0/5] Add fec1 and fec2 support for i.MX7d sdb board
2015-08-24 3:29 [PATCH v2 0/5] Add fec1 and fec2 support for i.MX7d sdb board Fugang Duan
` (4 preceding siblings ...)
2015-08-24 3:29 ` [PATCH v2 5/5] ARM: dts: imx7d-sdb: add fec1 and fec2 support Fugang Duan
@ 2015-09-06 13:11 ` Shawn Guo
5 siblings, 0 replies; 13+ messages in thread
From: Shawn Guo @ 2015-09-06 13:11 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Aug 24, 2015 at 11:29:47AM +0800, Fugang Duan wrote:
> The patch series is to add fec support for i.MX7d sdb board. Since i.MX7d fec ip is
> the same as i.MX6SX, so there have no change for driver itself.
>
> Patch#1: add bcm54220 PHY ID entry into brcmphy.h file.
> Patch#2: add new iomux-gpr file to define iomux-gpr register and field for i.MX7d.
> Patch#3: i.MX7d sdb board install bcm54220 phy, i.MX7d arm2 board install AR8031 phy.
> For the two phys, there needs extra phy setting, so package the setting to fixup.
> Patch#4~6: Add fec dts node and pinmux setting in dts file.
>
> Change:
> V2:
> * Remove patch#1 in V1 patch series. Move the sigle BCM54220 PHY ID define to machine file.
> * The current BCM54220 switch phy still use generic phy driver since broadcom phy driver don't
> support the switch phy, there need effort to add the switch phy support. Once broadcom phy driver
> will support the bcm54220 switch phy, we can add the special config to imx_v6_v7_defconfig.
>
>
> Fugang Duan (5):
> ARM: imx7d: add imx7d iomux-gpr field define
> ARM: imx: add enet init for i.MX7D platform
> ARM: dts: imx: pinfunc: add GPIO1 pin define for i.MX7d
> ARM: dts: imx7d: add fec1 and fec2 support for i.MX7d soc
> ARM: dts: imx7d-sdb: add fec1 and fec2 support
When you submit i.MX platform patches, please remember to copy
kernel at pengutronix.de, which is listed in MAINTAINERS.
Shawn
>
> arch/arm/boot/dts/imx7d-pinfunc.h | 115 +++++++++++++++++++++++++++++
> arch/arm/boot/dts/imx7d-sdb.dts | 76 ++++++++++++++++++-
> arch/arm/boot/dts/imx7d.dtsi | 36 +++++++++
> arch/arm/mach-imx/mach-imx7d.c | 76 ++++++++++++++++++-
> include/linux/mfd/syscon/imx7-iomuxc-gpr.h | 49 ++++++++++++
> 5 files changed, 349 insertions(+), 3 deletions(-)
> create mode 100644 include/linux/mfd/syscon/imx7-iomuxc-gpr.h
>
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 1/5] ARM: imx7d: add imx7d iomux-gpr field define
2015-09-06 12:33 ` Shawn Guo
@ 2015-09-07 2:20 ` Duan Andy
0 siblings, 0 replies; 13+ messages in thread
From: Duan Andy @ 2015-09-07 2:20 UTC (permalink / raw)
To: linux-arm-kernel
From: Shawn Guo <shawnguo@kernel.org> Sent: Sunday, September 06, 2015 8:34 PM
> To: Duan Fugang-B38611
> Cc: linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH v2 1/5] ARM: imx7d: add imx7d iomux-gpr field define
>
> On Mon, Aug 24, 2015 at 11:29:48AM +0800, Fugang Duan wrote:
> > Add imx7d iomux-gpr field define.
> >
> > Signed-off-by: Fugang Duan <B38611@freescale.com>
> > ---
> > include/linux/mfd/syscon/imx7-iomuxc-gpr.h | 49
> > ++++++++++++++++++++++++++++++
> > 1 file changed, 49 insertions(+)
> >
> > diff --git a/include/linux/mfd/syscon/imx7-iomuxc-gpr.h
> > b/include/linux/mfd/syscon/imx7-iomuxc-gpr.h
> > new file mode 100644
> > index 0000000..5cc0553
> > --- /dev/null
> > +++ b/include/linux/mfd/syscon/imx7-iomuxc-gpr.h
> > @@ -0,0 +1,49 @@
> > +/*
> > + * Copyright (C) 2015 Freescale Semiconductor, Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > +modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + */
> > +
> > +#ifndef __LINUX_IMX7_IOMUXC_GPR_H
> > +#define __LINUX_IMX7_IOMUXC_GPR_H
> > +
> > +#include <linux/bitops.h>
> > +
> > +#define IOMUXC_GPR0 0x00
> > +#define IOMUXC_GPR1 0x04
> > +#define IOMUXC_GPR2 0x08
> > +#define IOMUXC_GPR3 0x0c
> > +#define IOMUXC_GPR4 0x10
> > +#define IOMUXC_GPR5 0x14
> > +#define IOMUXC_GPR6 0x18
> > +#define IOMUXC_GPR7 0x1c
> > +#define IOMUXC_GPR8 0x20
> > +#define IOMUXC_GPR9 0x24
> > +#define IOMUXC_GPR10 0x28
> > +#define IOMUXC_GPR11 0x2c
> > +#define IOMUXC_GPR12 0x30
> > +#define IOMUXC_GPR13 0x34
> > +#define IOMUXC_GPR14 0x38
> > +#define IOMUXC_GPR15 0x3c
> > +#define IOMUXC_GPR16 0x40
> > +#define IOMUXC_GPR17 0x44
> > +#define IOMUXC_GPR18 0x48
> > +#define IOMUXC_GPR19 0x4c
> > +#define IOMUXC_GPR20 0x50
> > +#define IOMUXC_GPR21 0x54
> > +#define IOMUXC_GPR22 0x58
> > +
> > +/* For imx7d iomux gpr register field define */
> > +#define IMX7D_GPR1_IRQ_MASK (0x1 << 12)
>
> You might want to use BIT() macro here or drop <linux/bitops.h> inclusion
> above.
>
> Shawn
>
Thanks, I will change it in next version.
> > +#define IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK (0x1 << 13)
> > +#define IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK (0x1 << 14)
> > +#define IMX7D_GPR1_ENET_TX_CLK_SEL_MASK (0x3 << 13)
> > +#define IMX7D_GPR1_ENET1_CLK_DIR_MASK (0x1 << 17)
> > +#define IMX7D_GPR1_ENET2_CLK_DIR_MASK (0x1 << 18)
> > +#define IMX7D_GPR1_ENET_CLK_DIR_MASK (0x3 << 17)
> > +
> > +#define IMX7D_GPR5_CSI_MUX_CONTROL_MIPI (0x1 << 4)
> > +
> > +#endif /* __LINUX_IMX7_IOMUXC_GPR_H */
> > --
> > 1.9.1
> >
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 2/5] ARM: imx: add enet init for i.MX7D platform
2015-09-06 12:37 ` Shawn Guo
@ 2015-09-07 2:21 ` Duan Andy
0 siblings, 0 replies; 13+ messages in thread
From: Duan Andy @ 2015-09-07 2:21 UTC (permalink / raw)
To: linux-arm-kernel
From: Shawn Guo <shawnguo@kernel.org> Sent: Sunday, September 06, 2015 8:38 PM
> To: Duan Fugang-B38611
> Cc: linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH v2 2/5] ARM: imx: add enet init for i.MX7D platform
>
> On Mon, Aug 24, 2015 at 11:29:49AM +0800, Fugang Duan wrote:
> > Add enet phy fixup, clock source init for i.MX7D platform.
> >
> > Signed-off-by: Fugang Duan <B38611@freescale.com>
> > ---
Thanks for your comments, will change it in next version.
> > arch/arm/mach-imx/mach-imx7d.c | 76
> > ++++++++++++++++++++++++++++++++++++++++--
> > 1 file changed, 74 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/mach-imx/mach-imx7d.c
> > b/arch/arm/mach-imx/mach-imx7d.c index 4d4a190..07e9a7e 100644
> > --- a/arch/arm/mach-imx/mach-imx7d.c
> > +++ b/arch/arm/mach-imx/mach-imx7d.c
> > @@ -5,13 +5,84 @@
> > * it under the terms of the GNU General Public License version 2 as
> > * published by the Free Software Foundation.
> > */
> > -#include <linux/irqchip.h>
> > -#include <linux/of_platform.h>
> > #include <asm/mach/arch.h>
> > #include <asm/mach/map.h>
> > +#include <linux/irqchip.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/phy.h>
> > +#include <linux/regmap.h>
> >
> > #include "common.h"
>
> Please arrange the headers like below:
>
> #include <linux/irqchip.h>
> #include <linux/mfd/syscon.h>
> #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> #include <linux/of_platform.h>
> #include <linux/phy.h>
> #include <linux/regmap.h>
>
> #include <asm/mach/arch.h>
> #include <asm/mach/map.h>
>
> #include "common.h"
>
> >
> > +static int ar8031_phy_fixup(struct phy_device *dev) {
> > + u16 val;
> > +
> > + /* Set RGMII IO voltage to 1.8V */
> > + phy_write(dev, 0x1d, 0x1f);
> > + phy_write(dev, 0x1e, 0x8);
> > +
> > + /* disable phy AR8031 SmartEEE function. */
> > + phy_write(dev, 0xd, 0x3);
> > + phy_write(dev, 0xe, 0x805d);
> > + phy_write(dev, 0xd, 0x4003);
> > + val = phy_read(dev, 0xe);
> > + val &= ~(0x1 << 8);
> > + phy_write(dev, 0xe, val);
> > +
> > + /* introduce tx clock delay */
> > + phy_write(dev, 0x1d, 0x5);
> > + val = phy_read(dev, 0x1e);
> > + val |= 0x0100;
> > + phy_write(dev, 0x1e, val);
> > +
> > + return 0;
> > +}
> > +
> > +static int bcm54220_phy_fixup(struct phy_device *dev) {
> > + /* enable RXC skew select RGMII copper mode */
> > + phy_write(dev, 0x1e, 0x21);
> > + phy_write(dev, 0x1f, 0x7ea8);
> > + phy_write(dev, 0x1e, 0x2f);
> > + phy_write(dev, 0x1f, 0x71b7);
> > +
> > + return 0;
> > +}
> > +
> > +#define PHY_ID_AR8031 0x004dd074
> > +#define PHY_ID_BCM54220 0x600d8589
>
> Have a blank line here.
>
> Shawn
>
> > +static void __init imx7d_enet_phy_init(void) {
> > + if (IS_BUILTIN(CONFIG_PHYLIB)) {
> > + phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
> > + ar8031_phy_fixup);
> > + phy_register_fixup_for_uid(PHY_ID_BCM54220, 0xffffffff,
> > + bcm54220_phy_fixup);
> > + }
> > +}
> > +
> > +static void __init imx7d_enet_clk_sel(void) {
> > + struct regmap *gpr;
> > +
> > + gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr");
> > + if (!IS_ERR(gpr)) {
> > + regmap_update_bits(gpr, IOMUXC_GPR1,
> IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0);
> > + regmap_update_bits(gpr, IOMUXC_GPR1,
> IMX7D_GPR1_ENET_CLK_DIR_MASK, 0);
> > + } else {
> > + pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n");
> > + }
> > +}
> > +
> > +static inline void imx7d_enet_init(void) {
> > + imx7d_enet_phy_init();
> > + imx7d_enet_clk_sel();
> > +}
> > +
> > static void __init imx7d_init_machine(void) {
> > struct device *parent;
> > @@ -22,6 +93,7 @@ static void __init imx7d_init_machine(void)
> >
> > of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> > imx_anatop_init();
> > + imx7d_enet_init();
> > }
> >
> > static void __init imx7d_init_irq(void)
> > --
> > 1.9.1
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 3/5] ARM: dts: imx: pinfunc: add GPIO1 pin define for i.MX7d
2015-09-06 13:08 ` Shawn Guo
@ 2015-09-07 2:23 ` Duan Andy
0 siblings, 0 replies; 13+ messages in thread
From: Duan Andy @ 2015-09-07 2:23 UTC (permalink / raw)
To: linux-arm-kernel
From: Shawn Guo <shawnguo@kernel.org> Sent: Sunday, September 06, 2015 9:09 PM
> To: Duan Fugang-B38611
> Cc: linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH v2 3/5] ARM: dts: imx: pinfunc: add GPIO1 pin define
> for i.MX7d
>
> On Mon, Aug 24, 2015 at 11:29:50AM +0800, Fugang Duan wrote:
> > Add GPIO1 pin define for i.MX7d.
> >
> > Signed-off-by: Fugang Duan <B38611@freescale.com>
> > ---
Will drop the patch in next version. Pls apply Adrian pinfunc patch firstly.
> > arch/arm/boot/dts/imx7d-pinfunc.h | 115
> > ++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 115 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h
> > b/arch/arm/boot/dts/imx7d-pinfunc.h
> > index a8d8149..8b3cf2bc 100644
> > --- a/arch/arm/boot/dts/imx7d-pinfunc.h
> > +++ b/arch/arm/boot/dts/imx7d-pinfunc.h
> > @@ -15,6 +15,121 @@
> > * <mux_reg conf_reg input_reg mux_mode input_val>
> > */
> >
> > +#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x0000
> 0x0030 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x0000
> 0x0030 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000
> 0x0030 0x0000 0x2 0x0
> > +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x0000
> 0x0030 0x0000 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000
> 0x0030 0x0000 0x4 0x0
> > +#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004
> 0x0034 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004
> 0x0034 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3
> 0x0004 0x0034 0x0000 0x2 0x0
> > +#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004
> 0x0034 0x0000 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004
> 0x0034 0x0000 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008
> 0x0038 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008
> 0x0038 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1
> 0x0008 0x0038 0x0564 0x2 0x3
> > +#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008
> 0x0038 0x0000 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008
> 0x0038 0x0000 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008
> 0x0038 0x0000 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008
> 0x0038 0x0734 0x7 0x3
> > +#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C
> 0x003C 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C
> 0x003C 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2
> 0x000C 0x003C 0x0570 0x2 0x3
> > +#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C
> 0x003C 0x0000 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C
> 0x003C 0x0000 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C
> 0x003C 0x0000 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C
> 0x003C 0x0730 0x7 0x3
> > +#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010
> 0x0040 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010
> 0x0040 0x072C 0x1 0x1
> > +#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010
> 0x0040 0x0594 0x2 0x1
> > +#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010
> 0x0040 0x0710 0x3 0x4
> > +#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010
> 0x0040 0x05D4 0x4 0x2
> > +#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010
> 0x0040 0x0000 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014
> 0x0044 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014
> 0x0044 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014
> 0x0044 0x0598 0x2 0x1
> > +#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014
> 0x0044 0x0710 0x3 0x5
> > +#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014
> 0x0044 0x05D8 0x4 0x2
> > +#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014
> 0x0044 0x0000 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018
> 0x0048 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018
> 0x0048 0x0728 0x1 0x1
> > +#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018
> 0x0048 0x059C 0x2 0x1
> > +#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018
> 0x0048 0x0714 0x3 0x4
> > +#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018
> 0x0048 0x05DC 0x4 0x2
> > +#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018
> 0x0048 0x0000 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018
> 0x0048 0x0624 0x6 0x1
> > +#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C
> 0x004C 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C
> 0x004C 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C
> 0x004C 0x05A0 0x2 0x1
> > +#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA 0x001C
> 0x004C 0x0714 0x3 0x5
> > +#define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C
> 0x004C 0x05E0 0x4 0x2
> > +#define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C
> 0x004C 0x0000 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C
> 0x004C 0x0604 0x6 0x1
>
> All above lines use tab + spaces for indentation, which is different from
> the indentation already used in this file.
>
> Shawn
>
> > +#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8
> 0x0014 0x026C 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT
> 0x0014 0x026C 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B
> 0x0014 0x026C 0x0000 0x2 0x0
> > +#define MX7D_PAD_GPIO1_IO08__UART3_DCE_RX
> 0x0014 0x026C 0x0704 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO08__UART3_DTE_TX
> 0x0014 0x026C 0x0000 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO08__I2C3_SCL
> 0x0014 0x026C 0x05E4 0x4 0x0
> > +#define MX7D_PAD_GPIO1_IO08__KPP_COL5
> 0x0014 0x026C 0x0608 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO08__PWM1_OUT
> 0x0014 0x026C 0x0000 0x7 0x0
> > +#define MX7D_PAD_GPIO1_IO09__GPIO1_IO9
> 0x0018 0x0270 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO09__SD1_LCTL
> 0x0018 0x0270 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3
> 0x0018 0x0270 0x0000 0x2 0x0
> > +#define MX7D_PAD_GPIO1_IO09__UART3_DCE_TX
> 0x0018 0x0270 0x0000 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO09__UART3_DTE_RX
> 0x0018 0x0270 0x0704 0x3 0x1
> > +#define MX7D_PAD_GPIO1_IO09__I2C3_SDA
> 0x0018 0x0270 0x05E8 0x4 0x0
> > +#define MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY
> 0x0018 0x0270 0x04F4 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO09__KPP_ROW5
> 0x0018 0x0270 0x0628 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO09__PWM2_OUT
> 0x0018 0x0270 0x0000 0x7 0x0
> > +#define MX7D_PAD_GPIO1_IO10__GPIO1_IO10
> 0x001C 0x0274 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO10__SD2_LCTL
> 0x001C 0x0274 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO10__ENET1_MDIO
> 0x001C 0x0274 0x0568 0x2 0x0
> > +#define MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS
> 0x001C 0x0274 0x0700 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS
> 0x001C 0x0274 0x0000 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO10__I2C4_SCL
> 0x001C 0x0274 0x05EC 0x4 0x0
> > +#define MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA
> 0x001C 0x0274 0x05A4 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO10__KPP_COL6
> 0x001C 0x0274 0x060C 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO10__PWM3_OUT
> 0x001C 0x0274 0x0000 0x7 0x0
> > +#define MX7D_PAD_GPIO1_IO11__GPIO1_IO11
> 0x0020 0x0278 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO11__SD3_LCTL
> 0x0020 0x0278 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO11__ENET1_MDC
> 0x0020 0x0278 0x0000 0x2 0x0
> > +#define MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS
> 0x0020 0x0278 0x0000 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS
> 0x0020 0x0278 0x0700 0x3 0x1
> > +#define MX7D_PAD_GPIO1_IO11__I2C4_SDA
> 0x0020 0x0278 0x05F0 0x4 0x0
> > +#define MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB
> 0x0020 0x0278 0x05A8 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO11__KPP_ROW6
> 0x0020 0x0278 0x062C 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO11__PWM4_OUT
> 0x0020 0x0278 0x0000 0x7 0x0
> > +#define MX7D_PAD_GPIO1_IO12__GPIO1_IO12
> 0x0024 0x027C 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO12__SD2_VSELECT
> 0x0024 0x027C 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1
> 0x0024 0x027C 0x0564 0x2 0x0
> > +#define MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX
> 0x0024 0x027C 0x04DC 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO12__CM4_NMI
> 0x0024 0x027C 0x0000 0x4 0x0
> > +#define MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1
> 0x0024 0x027C 0x04E4 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO12__SNVS_VIO_5
> 0x0024 0x027C 0x0000 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO12__USB_OTG1_ID
> 0x0024 0x027C 0x0734 0x7 0x0
> > +#define MX7D_PAD_GPIO1_IO13__GPIO1_IO13
> 0x0028 0x0280 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO13__SD3_VSELECT
> 0x0028 0x0280 0x0000 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2
> 0x0028 0x0280 0x0570 0x2 0x0
> > +#define MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX
> 0x0028 0x0280 0x0000 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY
> 0x0028 0x0280 0x04F4 0x4 0x1
> > +#define MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2
> 0x0028 0x0280 0x04E8 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL
> 0x0028 0x0280 0x0000 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO13__USB_OTG2_ID
> 0x0028 0x0280 0x0730 0x7 0x0
> > +#define MX7D_PAD_GPIO1_IO14__GPIO1_IO14
> 0x002C 0x0284 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO14__SD3_CD_B
> 0x002C 0x0284 0x0738 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO14__ENET2_MDIO
> 0x002C 0x0284 0x0574 0x2 0x0
> > +#define MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX
> 0x002C 0x0284 0x04E0 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B
> 0x002C 0x0284 0x0000 0x4 0x0
> > +#define MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3
> 0x002C 0x0284 0x04EC 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0
> 0x002C 0x0284 0x06D8 0x6 0x0
> > +#define MX7D_PAD_GPIO1_IO15__GPIO1_IO15
> 0x0030 0x0288 0x0000 0x0 0x0
> > +#define MX7D_PAD_GPIO1_IO15__SD3_WP
> 0x0030 0x0288 0x073C 0x1 0x0
> > +#define MX7D_PAD_GPIO1_IO15__ENET2_MDC
> 0x0030 0x0288 0x0000 0x2 0x0
> > +#define MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX
> 0x0030 0x0288 0x0000 0x3 0x0
> > +#define MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B
> 0x0030 0x0288 0x0000 0x4 0x0
> > +#define MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4
> 0x0030 0x0288 0x04F0 0x5 0x0
> > +#define MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1
> 0x0030 0x0288 0x06DC 0x6 0x0
> > #define MX7D_PAD_EPDC_DATA00__EPDC_DATA0
> 0x0034 0x02A4 0x0000 0x0 0x0
> > #define MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD
> 0x0034 0x02A4 0x0000 0x1 0x0
> > #define MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0
> 0x0034 0x02A4 0x0000 0x2 0x0
> > --
> > 1.9.1
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2015-09-07 2:23 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-08-24 3:29 [PATCH v2 0/5] Add fec1 and fec2 support for i.MX7d sdb board Fugang Duan
2015-08-24 3:29 ` [PATCH v2 1/5] ARM: imx7d: add imx7d iomux-gpr field define Fugang Duan
2015-09-06 12:33 ` Shawn Guo
2015-09-07 2:20 ` Duan Andy
2015-08-24 3:29 ` [PATCH v2 2/5] ARM: imx: add enet init for i.MX7D platform Fugang Duan
2015-09-06 12:37 ` Shawn Guo
2015-09-07 2:21 ` Duan Andy
2015-08-24 3:29 ` [PATCH v2 3/5] ARM: dts: imx: pinfunc: add GPIO1 pin define for i.MX7d Fugang Duan
2015-09-06 13:08 ` Shawn Guo
2015-09-07 2:23 ` Duan Andy
2015-08-24 3:29 ` [PATCH v2 4/5] ARM: dts: imx7d: add fec1 and fec2 support for i.MX7d soc Fugang Duan
2015-08-24 3:29 ` [PATCH v2 5/5] ARM: dts: imx7d-sdb: add fec1 and fec2 support Fugang Duan
2015-09-06 13:11 ` [PATCH v2 0/5] Add fec1 and fec2 support for i.MX7d sdb board Shawn Guo
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