From: Alexander Kuleshov <kuleshovmail@gmail.com> To: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will.deacon@arm.com> Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alexander Kuleshov <kuleshovmail@gmail.com> Subject: [PATCH 1/3] arm64/cpufeature.h: Add macros for a cpu features testing Date: Fri, 4 Sep 2015 00:11:51 +0600 [thread overview] Message-ID: <1441303911-9421-1-git-send-email-kuleshovmail@gmail.com> (raw) This patch provides a couple of macros for the testing of processor features (crypto and FP/SIMD) like support of SHA1, AES instructions, support for FPU and etc. There is already a couple of places in the arch/arm64/kernel where these processor features are tested and these macros are facilitate this. Signed-off-by: Alexander Kuleshov <kuleshovmail@gmail.com> --- arch/arm64/include/asm/cpufeature.h | 44 +++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index c104421..2919455 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -28,7 +28,50 @@ #define ARM64_NCAPS 4 +/* + * ID_AA64ISAR0_EL1 AES, bits [7:4] + */ +#define ID_AA64ISAR0_EL1_AES_MASK 4 +#define ID_AA64ISAR0_EL1_AES(feature) \ + (((feature >> ID_AA64ISAR0_EL1_AES_MASK) & 0xf) & 1UL) +#define ID_AA64ISAR0_EL1_PMULL(feature) \ + (((feature >> ID_AA64ISAR0_EL1_AES_MASK) & 0xf) & 2UL) + +/* + * ID_AA64ISAR0_EL1 SHA1, bits [11:8] + */ +#define ID_AA64ISAR0_EL1_SHA1_MASK 8 +#define ID_AA64ISAR0_EL1_SHA1(feature) \ + (((feature >> ID_AA64ISAR0_EL1_SHA1_MASK) & 0xf) & 1UL) + +/* + * ID_AA64ISAR0_EL1 SHA2, bits [15:12] + */ +#define ID_AA64ISAR0_EL1_SHA2_MASK 12 +#define ID_AA64ISAR0_EL1_SHA2(feature) \ + (((feature >> ID_AA64ISAR0_EL1_SHA2_MASK) & 0xf) & 1UL) + +/* + * ID_AA64ISAR0_EL1 CRC32, bits [19:16] + */ +#define ID_AA64ISAR0_EL1_CRC32_MASK 16 +#define ID_AA64ISAR0_EL1_CRC32(feature) \ + (((feature >> ID_AA64ISAR0_EL1_CRC32_MASK) & 0xf) & 1UL) + +/* + * ID_AA64PFR0_EL1 FP, bits [19:16] + */ +#define ID_AA64PFR0_EL1_FP_MASK 16 +#define ID_AA64PFR0_EL1_FP(ptr) \ + (ptr & (0xf << ID_AA64PFR0_EL1_FP_MASK)) + +/* + * ID_AA64PFR0_EL1 AdvSIMD, bits [23:20] + */ +#define ID_AA64PFR0_EL1_ADV_SIMD_MASK 20 +#define ID_AA64PFR0_EL1_ADV_SIMD(ptr) \ + (ptr & (0xf << ID_AA64PFR0_EL1_ADV_SIMD_MASK)) + #ifndef __ASSEMBLY__ struct arm64_cpu_capabilities { -- 2.5.0
WARNING: multiple messages have this Message-ID (diff)
From: kuleshovmail@gmail.com (Alexander Kuleshov) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/3] arm64/cpufeature.h: Add macros for a cpu features testing Date: Fri, 4 Sep 2015 00:11:51 +0600 [thread overview] Message-ID: <1441303911-9421-1-git-send-email-kuleshovmail@gmail.com> (raw) This patch provides a couple of macros for the testing of processor features (crypto and FP/SIMD) like support of SHA1, AES instructions, support for FPU and etc. There is already a couple of places in the arch/arm64/kernel where these processor features are tested and these macros are facilitate this. Signed-off-by: Alexander Kuleshov <kuleshovmail@gmail.com> --- arch/arm64/include/asm/cpufeature.h | 44 +++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index c104421..2919455 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -28,7 +28,50 @@ #define ARM64_NCAPS 4 +/* + * ID_AA64ISAR0_EL1 AES, bits [7:4] + */ +#define ID_AA64ISAR0_EL1_AES_MASK 4 +#define ID_AA64ISAR0_EL1_AES(feature) \ + (((feature >> ID_AA64ISAR0_EL1_AES_MASK) & 0xf) & 1UL) +#define ID_AA64ISAR0_EL1_PMULL(feature) \ + (((feature >> ID_AA64ISAR0_EL1_AES_MASK) & 0xf) & 2UL) + +/* + * ID_AA64ISAR0_EL1 SHA1, bits [11:8] + */ +#define ID_AA64ISAR0_EL1_SHA1_MASK 8 +#define ID_AA64ISAR0_EL1_SHA1(feature) \ + (((feature >> ID_AA64ISAR0_EL1_SHA1_MASK) & 0xf) & 1UL) + +/* + * ID_AA64ISAR0_EL1 SHA2, bits [15:12] + */ +#define ID_AA64ISAR0_EL1_SHA2_MASK 12 +#define ID_AA64ISAR0_EL1_SHA2(feature) \ + (((feature >> ID_AA64ISAR0_EL1_SHA2_MASK) & 0xf) & 1UL) + +/* + * ID_AA64ISAR0_EL1 CRC32, bits [19:16] + */ +#define ID_AA64ISAR0_EL1_CRC32_MASK 16 +#define ID_AA64ISAR0_EL1_CRC32(feature) \ + (((feature >> ID_AA64ISAR0_EL1_CRC32_MASK) & 0xf) & 1UL) + +/* + * ID_AA64PFR0_EL1 FP, bits [19:16] + */ +#define ID_AA64PFR0_EL1_FP_MASK 16 +#define ID_AA64PFR0_EL1_FP(ptr) \ + (ptr & (0xf << ID_AA64PFR0_EL1_FP_MASK)) + +/* + * ID_AA64PFR0_EL1 AdvSIMD, bits [23:20] + */ +#define ID_AA64PFR0_EL1_ADV_SIMD_MASK 20 +#define ID_AA64PFR0_EL1_ADV_SIMD(ptr) \ + (ptr & (0xf << ID_AA64PFR0_EL1_ADV_SIMD_MASK)) + #ifndef __ASSEMBLY__ struct arm64_cpu_capabilities { -- 2.5.0
next reply other threads:[~2015-09-03 18:13 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-09-03 18:11 Alexander Kuleshov [this message] 2015-09-03 18:11 ` [PATCH 1/3] arm64/cpufeature.h: Add macros for a cpu features testing Alexander Kuleshov 2015-09-03 18:12 ` [PATCH 2/3] arm64/setup: Use ID_AA64ISAR0_EL1_.* macros Alexander Kuleshov 2015-09-03 18:12 ` Alexander Kuleshov 2015-09-04 11:26 ` Catalin Marinas 2015-09-04 11:26 ` Catalin Marinas 2016-11-07 16:30 ` Suzuki K Poulose 2016-11-07 16:30 ` Suzuki K Poulose 2015-09-03 18:12 ` [PATCH 3/3] arm64/fpsimd: Use ID_AA64PFR0_EL1_.* macros Alexander Kuleshov 2015-09-03 18:12 ` Alexander Kuleshov 2016-11-07 16:31 ` Suzuki K Poulose 2016-11-07 16:31 ` Suzuki K Poulose 2015-09-04 11:25 ` [PATCH 1/3] arm64/cpufeature.h: Add macros for a cpu features testing Catalin Marinas 2015-09-04 11:25 ` Catalin Marinas 2015-09-04 12:00 ` Suzuki K. Poulose 2015-09-04 12:00 ` Suzuki K. Poulose 2015-09-04 12:19 ` Alexander Kuleshov 2015-09-04 12:19 ` Alexander Kuleshov 2015-09-16 14:48 ` Suzuki K. Poulose 2015-09-16 14:48 ` Suzuki K. Poulose
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1441303911-9421-1-git-send-email-kuleshovmail@gmail.com \ --to=kuleshovmail@gmail.com \ --cc=catalin.marinas@arm.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=will.deacon@arm.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.