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From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
To: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au
Cc: linuxppc-dev@lists.ozlabs.org,
	"Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
Subject: [PATCH 05/31] powerpc/mm: Move hash specific pte width and other defines to book3s
Date: Mon, 21 Sep 2015 12:10:32 +0530	[thread overview]
Message-ID: <1442817658-2588-6-git-send-email-aneesh.kumar@linux.vnet.ibm.com> (raw)
In-Reply-To: <1442817658-2588-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com>

This further make a copy of pte defines to book3s/64/hash*.h. This
remove the dependency on ppc64-4k.h and ppc64-64k.h

Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
 arch/powerpc/include/asm/book3s/64/hash-4k.h  | 86 ++++++++++++++++++++++++++-
 arch/powerpc/include/asm/book3s/64/hash-64k.h | 46 +++++++++++++-
 arch/powerpc/include/asm/book3s/64/pgtable.h  |  6 +-
 3 files changed, 129 insertions(+), 9 deletions(-)

diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h
index c134e809aac3..f2c51cd61f69 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-4k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h
@@ -1,4 +1,51 @@
-/* To be include by pgtable-hash64.h only */
+#ifndef _ASM_POWERPC_BOOK3S_64_HASH_4K_H
+#define _ASM_POWERPC_BOOK3S_64_HASH_4K_H
+/*
+ * Entries per page directory level.  The PTE level must use a 64b record
+ * for each page table entry.  The PMD and PGD level use a 32b record for
+ * each entry by assuming that each entry is page aligned.
+ */
+#define PTE_INDEX_SIZE  9
+#define PMD_INDEX_SIZE  7
+#define PUD_INDEX_SIZE  9
+#define PGD_INDEX_SIZE  9
+
+#ifndef __ASSEMBLY__
+#define PTE_TABLE_SIZE	(sizeof(pte_t) << PTE_INDEX_SIZE)
+#define PMD_TABLE_SIZE	(sizeof(pmd_t) << PMD_INDEX_SIZE)
+#define PUD_TABLE_SIZE	(sizeof(pud_t) << PUD_INDEX_SIZE)
+#define PGD_TABLE_SIZE	(sizeof(pgd_t) << PGD_INDEX_SIZE)
+#endif	/* __ASSEMBLY__ */
+
+#define PTRS_PER_PTE	(1 << PTE_INDEX_SIZE)
+#define PTRS_PER_PMD	(1 << PMD_INDEX_SIZE)
+#define PTRS_PER_PUD	(1 << PUD_INDEX_SIZE)
+#define PTRS_PER_PGD	(1 << PGD_INDEX_SIZE)
+
+/* PMD_SHIFT determines what a second-level page table entry can map */
+#define PMD_SHIFT	(PAGE_SHIFT + PTE_INDEX_SIZE)
+#define PMD_SIZE	(1UL << PMD_SHIFT)
+#define PMD_MASK	(~(PMD_SIZE-1))
+
+/* With 4k base page size, hugepage PTEs go at the PMD level */
+#define MIN_HUGEPTE_SHIFT	PMD_SHIFT
+
+/* PUD_SHIFT determines what a third-level page table entry can map */
+#define PUD_SHIFT	(PMD_SHIFT + PMD_INDEX_SIZE)
+#define PUD_SIZE	(1UL << PUD_SHIFT)
+#define PUD_MASK	(~(PUD_SIZE-1))
+
+/* PGDIR_SHIFT determines what a fourth-level page table entry can map */
+#define PGDIR_SHIFT	(PUD_SHIFT + PUD_INDEX_SIZE)
+#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
+#define PGDIR_MASK	(~(PGDIR_SIZE-1))
+
+/* Bits to mask out from a PMD to get to the PTE page */
+#define PMD_MASKED_BITS		0
+/* Bits to mask out from a PUD to get to the PMD page */
+#define PUD_MASKED_BITS		0
+/* Bits to mask out from a PGD to get to the PUD page */
+#define PGD_MASKED_BITS		0
 
 /* PTE bits */
 #define _PAGE_HASHPTE	0x0400 /* software: pte has an associated HPTE */
@@ -15,3 +62,40 @@
 /* shift to put page number into pte */
 #define PTE_RPN_SHIFT	(17)
 
+#ifndef __ASSEMBLY__
+/*
+ * 4-level page tables related bits
+ */
+
+#define pgd_none(pgd)		(!pgd_val(pgd))
+#define pgd_bad(pgd)		(pgd_val(pgd) == 0)
+#define pgd_present(pgd)	(pgd_val(pgd) != 0)
+#define pgd_clear(pgdp)		(pgd_val(*(pgdp)) = 0)
+#define pgd_page_vaddr(pgd)	(pgd_val(pgd) & ~PGD_MASKED_BITS)
+
+static inline pte_t pgd_pte(pgd_t pgd)
+{
+	return __pte(pgd_val(pgd));
+}
+
+static inline pgd_t pte_pgd(pte_t pte)
+{
+	return __pgd(pte_val(pte));
+}
+extern struct page *pgd_page(pgd_t pgd);
+
+#define pud_offset(pgdp, addr)	\
+  (((pud_t *) pgd_page_vaddr(*(pgdp))) + \
+    (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)))
+
+#define pud_ERROR(e) \
+	pr_err("%s:%d: bad pud %08lx.\n", __FILE__, __LINE__, pud_val(e))
+
+/*
+ * On all 4K setups, remap_4k_pfn() equates to remap_pfn_range() */
+#define remap_4k_pfn(vma, addr, pfn, prot)	\
+	remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_BOOK3S_64_HASH_4K_H */
diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h
index 4f4ec2ab45c9..ee073822145d 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h
@@ -1,4 +1,35 @@
-/* To be include by pgtable-hash64.h only */
+#ifndef _ASM_POWERPC_BOOK3S_64_HASH_64K_H
+#define _ASM_POWERPC_BOOK3S_64_HASH_64K_H
+
+#include <asm-generic/pgtable-nopud.h>
+
+#define PTE_INDEX_SIZE  8
+#define PMD_INDEX_SIZE  10
+#define PUD_INDEX_SIZE	0
+#define PGD_INDEX_SIZE  12
+
+#define PTRS_PER_PTE	(1 << PTE_INDEX_SIZE)
+#define PTRS_PER_PMD	(1 << PMD_INDEX_SIZE)
+#define PTRS_PER_PGD	(1 << PGD_INDEX_SIZE)
+
+/* With 4k base page size, hugepage PTEs go at the PMD level */
+#define MIN_HUGEPTE_SHIFT	PAGE_SHIFT
+
+/* PMD_SHIFT determines what a second-level page table entry can map */
+#define PMD_SHIFT	(PAGE_SHIFT + PTE_INDEX_SIZE)
+#define PMD_SIZE	(1UL << PMD_SHIFT)
+#define PMD_MASK	(~(PMD_SIZE-1))
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#define PGDIR_SHIFT	(PMD_SHIFT + PMD_INDEX_SIZE)
+#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
+#define PGDIR_MASK	(~(PGDIR_SIZE-1))
+
+/* Bits to mask out from a PMD to get to the PTE page */
+/* PMDs point to PTE table fragments which are 4K aligned.  */
+#define PMD_MASKED_BITS		0xfff
+/* Bits to mask out from a PGD/PUD to get to the PMD page */
+#define PUD_MASKED_BITS		0x1ff
 
 /* Additional PTE bits (don't change without checking asm in hash_low.S) */
 #define _PAGE_SPECIAL	0x00000400 /* software: special page */
@@ -74,8 +105,8 @@ static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index)
 #define __rpte_to_pte(r)	((r).pte)
 #define __rpte_sub_valid(rpte, index) \
 	(pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
-
-/* Trick: we set __end to va + 64k, which happens works for
+/*
+ * Trick: we set __end to va + 64k, which happens works for
  * a 16M page as well as we want only one iteration
  */
 #define pte_iterate_hashed_subpages(rpte, psize, vpn, index, shift)	\
@@ -99,4 +130,13 @@ static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index)
 		remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE,	\
 			__pgprot(pgprot_val((prot)) | _PAGE_4K_PFN)))
 
+#define PTE_TABLE_SIZE	(sizeof(real_pte_t) << PTE_INDEX_SIZE)
+#define PMD_TABLE_SIZE	(sizeof(pmd_t) << PMD_INDEX_SIZE)
+#define PGD_TABLE_SIZE	(sizeof(pgd_t) << PGD_INDEX_SIZE)
+
+#define pgd_pte(pgd)	(pud_pte(((pud_t){ pgd })))
+#define pte_pgd(pte)	((pgd_t)pte_pud(pte))
+
 #endif	/* __ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_BOOK3S_64_HASH_64K_H */
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h
index 449c61a5d9b0..42d6f51dd81b 100644
--- a/arch/powerpc/include/asm/book3s/64/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/64/pgtable.h
@@ -5,11 +5,7 @@
  * the ppc64 hashed page table.
  */
 
-#ifdef CONFIG_PPC_64K_PAGES
-#include <asm/pgtable-ppc64-64k.h>
-#else
-#include <asm/pgtable-ppc64-4k.h>
-#endif
+#include <asm/book3s/64/hash.h>
 #include <asm/barrier.h>
 
 #define FIRST_USER_ADDRESS	0UL
-- 
2.5.0

  parent reply	other threads:[~2015-09-21  6:42 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-21  6:40 [PATCH 00/31] powerpc/mm: Update page table format for book3s 64 Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 01/31] powerpc/mm: move pte headers to book3s directory Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 02/31] powerpc/mm: move pte headers to book3s directory (part 2) Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 03/31] powerpc/mm: make a separate copy for book3s Aneesh Kumar K.V
2015-09-21 21:58   ` Scott Wood
2015-09-22  6:42     ` Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 04/31] powerpc/mm: make a separate copy for book3s (part 2) Aneesh Kumar K.V
2015-09-21  6:40 ` Aneesh Kumar K.V [this message]
2015-09-21  6:40 ` [PATCH 06/31] powerpc/mm: Delete booke bits from book3s Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 07/31] powerpc/mm: Don't have generic headers introduce functions touching pte bits Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 08/31] powerpc/mm: Drop pte-common.h from BOOK3S 64 Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 09/31] powerpc/mm: Don't use pte_val as lvalue Aneesh Kumar K.V
2015-09-22  2:22   ` Scott Wood
2015-09-22  6:44     ` Aneesh Kumar K.V
2015-09-22  6:46       ` Scott Wood
2015-09-21  6:40 ` [PATCH 10/31] powerpc/mm: Don't use pmd_val, pud_val and pgd_val " Aneesh Kumar K.V
2015-09-22  2:23   ` Scott Wood
2015-09-22  6:45     ` Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 11/31] powerpc/mm: Move hash64 PTE bits from book3s/64/pgtable.h to hash.h Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 12/31] powerpc/mm: Move PTE bits from generic functions to hash64 functions Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 13/31] powerpc/booke: Move booke headers (part 1) Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 14/31] powerpc/booke: Move booke headers (part 2) Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 15/31] powerpc/booke: Move booke headers (part 3) Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 16/31] powerpc/booke: Move booke headers (part 4) Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 17/31] powerpc/booke: Move booke headers (part 5) Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 18/31] powerpc/mm: Increase the pte frag size Aneesh Kumar K.V
2015-09-21  8:14   ` Benjamin Herrenschmidt
2015-09-21  8:45     ` Aneesh Kumar K.V
2015-09-21 11:06       ` Benjamin Herrenschmidt
2015-09-21 11:53         ` Aneesh Kumar K.V
2015-09-23 21:37           ` Benjamin Herrenschmidt
2015-09-28  4:55             ` Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 19/31] powerpc/mm: Convert 4k hash insert to C Aneesh Kumar K.V
2015-09-21  8:16   ` Benjamin Herrenschmidt
2015-09-21  8:57     ` Aneesh Kumar K.V
2015-09-29  8:13     ` Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 20/31] powerpc/mm: update __real_pte to take address as argument Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 21/31] powerpc/mm: make pte page hash index slot 8 bits Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 22/31] powerpc/mm: Don't track subpage valid bit in pte_t Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 23/31] powerpc/mm: Increase the width of #define Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 24/31] powerpc/mm: Convert __hash_page_64K to C Aneesh Kumar K.V
2015-09-23 13:56   ` Anshuman Khandual
2015-09-28  4:58     ` Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 25/31] powerpc/mm: Convert 4k insert from asm " Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 26/31] powerpc/mm: Remove the dependency on pte bit position in asm code Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 27/31] powerpc/mm: Add helper for converting pte bit to hpte bits Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 28/31] powerpc/mm: Move WIMG update to helper Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 29/31] powerpc/mm: Move hugetlb related headers Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 30/31] powerpc/mm: Move THP headers around Aneesh Kumar K.V
2015-09-21  6:40 ` [PATCH 31/31] powerpc/mm: Add a _PAGE_PTE bit Aneesh Kumar K.V
2015-09-21 21:48 ` [PATCH 00/31] powerpc/mm: Update page table format for book3s 64 Scott Wood
2015-09-22  6:48   ` Aneesh Kumar K.V
2015-09-22  6:57     ` Scott Wood
2015-09-28  4:56       ` Aneesh Kumar K.V
2015-09-28 16:41         ` Scott Wood
2015-09-30  1:44           ` Michael Ellerman
2015-09-29  0:12         ` Benjamin Herrenschmidt

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