* [PATCH 01/15] drm/i915: Drop redundant watermark programming
2015-09-24 22:53 [PATCH 00/15] Atomic watermark updates (v5) Matt Roper
@ 2015-09-24 22:53 ` Matt Roper
2015-09-24 22:53 ` [PATCH 02/15] drm/i915: Eliminate usage of plane_wm_parameters from ILK-style WM code (v2) Matt Roper
` (14 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Matt Roper @ 2015-09-24 22:53 UTC (permalink / raw)
To: intel-gfx
In commit
commit e4ca061275ec6a48b66c6edebe08644e666994c0
Author: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Date: Wed Jul 8 15:31:52 2015 +0200
drm/i915: Don't forget to mark crtc as inactive after disable
we added extra watermark updates to all of the .crtc_disable()
entrypoints to avoid problems problems with system resume on SKL. Those
disable entrypoints are currently called in just two places in the
driver: intel_atomic_commit (i.e., during a modeset) and
intel_crtc_disable_noatomic (which is called during hardware readout).
It seems that this extra watermark recalculation should only be
important in the latter case (which happens during a resume operation);
the former case should always have appropriate watermark programming
happening at other points in the modeset sequence.
Let's move the watermark update out of the .crtc_disable() entrypoints
and place it directly in intel_crtc_disable_noatomic() so that it only
happens on S3 resume and not during a regular modeset (since the
existing watermark handling should properly update watermarks during
normal atomic commits).
Cc: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1847257..dea1f23 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5067,9 +5067,6 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
ironlake_fdi_pll_disable(intel_crtc);
}
-
- intel_crtc->active = false;
- intel_update_watermarks(crtc);
}
static void haswell_crtc_disable(struct drm_crtc *crtc)
@@ -5113,9 +5110,6 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
for_each_encoder_on_crtc(dev, crtc, encoder)
if (encoder->post_disable)
encoder->post_disable(encoder);
-
- intel_crtc->active = false;
- intel_update_watermarks(crtc);
}
static void i9xx_pfit_enable(struct intel_crtc *crtc)
@@ -6214,9 +6208,6 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
if (!IS_GEN2(dev))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
-
- intel_crtc->active = false;
- intel_update_watermarks(crtc);
}
static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
@@ -6236,6 +6227,8 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
dev_priv->display.crtc_disable(crtc);
+ intel_crtc->active = false;
+ intel_update_watermarks(crtc);
intel_disable_shared_dpll(intel_crtc);
domains = intel_crtc->enabled_power_domains;
--
2.1.4
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 02/15] drm/i915: Eliminate usage of plane_wm_parameters from ILK-style WM code (v2)
2015-09-24 22:53 [PATCH 00/15] Atomic watermark updates (v5) Matt Roper
2015-09-24 22:53 ` [PATCH 01/15] drm/i915: Drop redundant watermark programming Matt Roper
@ 2015-09-24 22:53 ` Matt Roper
2016-01-05 12:49 ` Flicker caused by "drm/i915: Eliminate usage of plane_wm_parameters from ILK-style WM code (v2)" Jan Niehusmann
2015-09-24 22:53 ` [PATCH 03/15] drm/i915: Eliminate usage of pipe_wm_parameters from ILK-style WM (v2) Matt Roper
` (13 subsequent siblings)
15 siblings, 1 reply; 29+ messages in thread
From: Matt Roper @ 2015-09-24 22:53 UTC (permalink / raw)
To: intel-gfx
Just pull the info out of the plane state structure rather than staging
it in an additional structure.
v2: Add 'visible' condition to sprites_scaled so that we don't limit the
WM level when the sprite isn't enabled. (Ville)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by(v1): Ander Conselvan de Oliveira <conselvan2@gmail.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 133 +++++++++++++++++++++-------------------
1 file changed, 70 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ab5ac5e..bfea446 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1799,9 +1799,6 @@ struct ilk_pipe_wm_parameters {
bool active;
uint32_t pipe_htotal;
uint32_t pixel_rate;
- struct intel_plane_wm_parameters pri;
- struct intel_plane_wm_parameters spr;
- struct intel_plane_wm_parameters cur;
};
struct ilk_wm_maximums {
@@ -1823,25 +1820,25 @@ struct intel_wm_config {
* mem_value must be in 0.1us units.
*/
static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
+ const struct intel_plane_state *pstate,
uint32_t mem_value,
bool is_lp)
{
+ int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
uint32_t method1, method2;
- if (!params->active || !params->pri.enabled)
+ if (!params->active || !pstate->visible)
return 0;
- method1 = ilk_wm_method1(params->pixel_rate,
- params->pri.bytes_per_pixel,
- mem_value);
+ method1 = ilk_wm_method1(params->pixel_rate, bpp, mem_value);
if (!is_lp)
return method1;
method2 = ilk_wm_method2(params->pixel_rate,
params->pipe_htotal,
- params->pri.horiz_pixels,
- params->pri.bytes_per_pixel,
+ drm_rect_width(&pstate->dst),
+ bpp,
mem_value);
return min(method1, method2);
@@ -1852,20 +1849,20 @@ static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
* mem_value must be in 0.1us units.
*/
static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
+ const struct intel_plane_state *pstate,
uint32_t mem_value)
{
+ int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
uint32_t method1, method2;
- if (!params->active || !params->spr.enabled)
+ if (!params->active || !pstate->visible)
return 0;
- method1 = ilk_wm_method1(params->pixel_rate,
- params->spr.bytes_per_pixel,
- mem_value);
+ method1 = ilk_wm_method1(params->pixel_rate, bpp, mem_value);
method2 = ilk_wm_method2(params->pixel_rate,
params->pipe_htotal,
- params->spr.horiz_pixels,
- params->spr.bytes_per_pixel,
+ drm_rect_width(&pstate->dst),
+ bpp,
mem_value);
return min(method1, method2);
}
@@ -1875,28 +1872,32 @@ static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
* mem_value must be in 0.1us units.
*/
static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
+ const struct intel_plane_state *pstate,
uint32_t mem_value)
{
- if (!params->active || !params->cur.enabled)
+ int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
+
+ if (!params->active || !pstate->visible)
return 0;
return ilk_wm_method2(params->pixel_rate,
params->pipe_htotal,
- params->cur.horiz_pixels,
- params->cur.bytes_per_pixel,
+ drm_rect_width(&pstate->dst),
+ bpp,
mem_value);
}
/* Only for WM_LP. */
static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
+ const struct intel_plane_state *pstate,
uint32_t pri_val)
{
- if (!params->active || !params->pri.enabled)
+ int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
+
+ if (!params->active || !pstate->visible)
return 0;
- return ilk_wm_fbc(pri_val,
- params->pri.horiz_pixels,
- params->pri.bytes_per_pixel);
+ return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
}
static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
@@ -2061,10 +2062,12 @@ static bool ilk_validate_wm_level(int level,
}
static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
+ const struct intel_crtc *intel_crtc,
int level,
const struct ilk_pipe_wm_parameters *p,
struct intel_wm_level *result)
{
+ struct intel_plane *intel_plane;
uint16_t pri_latency = dev_priv->wm.pri_latency[level];
uint16_t spr_latency = dev_priv->wm.spr_latency[level];
uint16_t cur_latency = dev_priv->wm.cur_latency[level];
@@ -2076,10 +2079,29 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
cur_latency *= 5;
}
- result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
- result->spr_val = ilk_compute_spr_wm(p, spr_latency);
- result->cur_val = ilk_compute_cur_wm(p, cur_latency);
- result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
+ for_each_intel_plane_on_crtc(dev_priv->dev, intel_crtc, intel_plane) {
+ struct intel_plane_state *pstate =
+ to_intel_plane_state(intel_plane->base.state);
+
+ switch (intel_plane->base.type) {
+ case DRM_PLANE_TYPE_PRIMARY:
+ result->pri_val = ilk_compute_pri_wm(p, pstate,
+ pri_latency,
+ level);
+ result->fbc_val = ilk_compute_fbc_wm(p, pstate,
+ result->pri_val);
+ break;
+ case DRM_PLANE_TYPE_OVERLAY:
+ result->spr_val = ilk_compute_spr_wm(p, pstate,
+ spr_latency);
+ break;
+ case DRM_PLANE_TYPE_CURSOR:
+ result->cur_val = ilk_compute_cur_wm(p, pstate,
+ cur_latency);
+ break;
+ }
+ }
+
result->enable = true;
}
@@ -2341,10 +2363,7 @@ static void skl_setup_wm_latency(struct drm_device *dev)
static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
struct ilk_pipe_wm_parameters *p)
{
- struct drm_device *dev = crtc->dev;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
- struct drm_plane *plane;
if (!intel_crtc->active)
return;
@@ -2352,32 +2371,6 @@ static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
p->active = true;
p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
-
- if (crtc->primary->state->fb)
- p->pri.bytes_per_pixel =
- crtc->primary->state->fb->bits_per_pixel / 8;
- else
- p->pri.bytes_per_pixel = 4;
-
- p->cur.bytes_per_pixel = 4;
- /*
- * TODO: for now, assume primary and cursor planes are always enabled.
- * Setting them to false makes the screen flicker.
- */
- p->pri.enabled = true;
- p->cur.enabled = true;
-
- p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
- p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
-
- drm_for_each_legacy_plane(plane, dev) {
- struct intel_plane *intel_plane = to_intel_plane(plane);
-
- if (intel_plane->pipe == pipe) {
- p->spr = intel_plane->wm;
- break;
- }
- }
}
static void ilk_compute_wm_config(struct drm_device *dev,
@@ -2405,28 +2398,42 @@ static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
{
struct drm_device *dev = crtc->dev;
const struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_plane *intel_plane;
+ struct intel_plane_state *sprstate = NULL;
int level, max_level = ilk_wm_max_level(dev);
/* LP0 watermark maximums depend on this pipe alone */
struct intel_wm_config config = {
.num_pipes_active = 1,
- .sprites_enabled = params->spr.enabled,
- .sprites_scaled = params->spr.scaled,
};
struct ilk_wm_maximums max;
+ for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
+ if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) {
+ sprstate = to_intel_plane_state(intel_plane->base.state);
+ break;
+ }
+ }
+
+ config.sprites_enabled = sprstate->visible;
+ config.sprites_scaled = sprstate->visible &&
+ (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
+ drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
+
+
pipe_wm->pipe_enabled = params->active;
- pipe_wm->sprites_enabled = params->spr.enabled;
- pipe_wm->sprites_scaled = params->spr.scaled;
+ pipe_wm->sprites_enabled = sprstate->visible;
+ pipe_wm->sprites_scaled = config.sprites_scaled;
/* ILK/SNB: LP2+ watermarks only w/o sprites */
- if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
+ if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
max_level = 1;
/* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
- if (params->spr.scaled)
+ if (config.sprites_scaled)
max_level = 0;
- ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
+ ilk_compute_wm_level(dev_priv, intel_crtc, 0, params, &pipe_wm->wm[0]);
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
@@ -2443,7 +2450,7 @@ static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
for (level = 1; level <= max_level; level++) {
struct intel_wm_level wm = {};
- ilk_compute_wm_level(dev_priv, level, params, &wm);
+ ilk_compute_wm_level(dev_priv, intel_crtc, level, params, &wm);
/*
* Disable any watermark level that exceeds the
--
2.1.4
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^ permalink raw reply related [flat|nested] 29+ messages in thread* Flicker caused by "drm/i915: Eliminate usage of plane_wm_parameters from ILK-style WM code (v2)"
2015-09-24 22:53 ` [PATCH 02/15] drm/i915: Eliminate usage of plane_wm_parameters from ILK-style WM code (v2) Matt Roper
@ 2016-01-05 12:49 ` Jan Niehusmann
2016-01-05 21:58 ` Matt Roper
0 siblings, 1 reply; 29+ messages in thread
From: Jan Niehusmann @ 2016-01-05 12:49 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
Hi,
On Thu, Sep 24, 2015 at 03:53:07PM -0700, Matt Roper wrote:
> Just pull the info out of the plane state structure rather than staging
> it in an additional structure.
>
> v2: Add 'visible' condition to sprites_scaled so that we don't limit the
> WM level when the sprite isn't enabled. (Ville)
It looks like this patch - specifically the visible condition in
ilk_compute_cur_wm - causes screen flicker when moving the cursor from
one screen to another one in a multi-screen setup.
My hardware is a Thinkpad x201s
(http://www.thinkwiki.org/wiki/Category:X201s)
00:02.0 VGA compatible controller [0300]: Intel Corporation Core Processor Integrated Graphics Controller [8086:0046] (rev 02),
CPU is an i7-620LM.
The screen flickering is the one the coursor is leaving. In most cases,
parts of the screen just blank for a very short moment. In some rare
cases, the screen even stays blanked until I move the cursor back to
that screen. No stability issues were observed, this seems to be a
purely cosmetic issue.
I bisected the issue to 43d59eda1f69631c267e06ab6b94ed3c14f1f6d1. As I
knew the flickering was cursor-related, I tried the following minimal
patch, which actually fixed the symptom, when applied to 4.4-rc8:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f091ad1..1ef0c54 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1791,7 +1791,7 @@ static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
{
int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
- if (!cstate->base.active || !pstate->visible)
+ if (!cstate->base.active)
return 0;
return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
I have no idea at all if this is actually fixing anything or if it's
just hiding the real bug. All I can say is that the flickering doesn't
occur any longer.
Jan
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^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: Flicker caused by "drm/i915: Eliminate usage of plane_wm_parameters from ILK-style WM code (v2)"
2016-01-05 12:49 ` Flicker caused by "drm/i915: Eliminate usage of plane_wm_parameters from ILK-style WM code (v2)" Jan Niehusmann
@ 2016-01-05 21:58 ` Matt Roper
2016-01-06 0:46 ` Jan Niehusmann
0 siblings, 1 reply; 29+ messages in thread
From: Matt Roper @ 2016-01-05 21:58 UTC (permalink / raw)
To: Jan Niehusmann; +Cc: intel-gfx
On Tue, Jan 05, 2016 at 01:49:33PM +0100, Jan Niehusmann wrote:
> Hi,
>
> On Thu, Sep 24, 2015 at 03:53:07PM -0700, Matt Roper wrote:
> > Just pull the info out of the plane state structure rather than staging
> > it in an additional structure.
> >
> > v2: Add 'visible' condition to sprites_scaled so that we don't limit the
> > WM level when the sprite isn't enabled. (Ville)
>
> It looks like this patch - specifically the visible condition in
> ilk_compute_cur_wm - causes screen flicker when moving the cursor from
> one screen to another one in a multi-screen setup.
>
> My hardware is a Thinkpad x201s
> (http://www.thinkwiki.org/wiki/Category:X201s)
> 00:02.0 VGA compatible controller [0300]: Intel Corporation Core Processor Integrated Graphics Controller [8086:0046] (rev 02),
> CPU is an i7-620LM.
>
> The screen flickering is the one the coursor is leaving. In most cases,
> parts of the screen just blank for a very short moment. In some rare
> cases, the screen even stays blanked until I move the cursor back to
> that screen. No stability issues were observed, this seems to be a
> purely cosmetic issue.
>
> I bisected the issue to 43d59eda1f69631c267e06ab6b94ed3c14f1f6d1. As I
> knew the flickering was cursor-related, I tried the following minimal
> patch, which actually fixed the symptom, when applied to 4.4-rc8:
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f091ad1..1ef0c54 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1791,7 +1791,7 @@ static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
> {
> int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
>
> - if (!cstate->base.active || !pstate->visible)
> + if (!cstate->base.active)
> return 0;
>
> return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
>
>
> I have no idea at all if this is actually fixing anything or if it's
> just hiding the real bug. All I can say is that the flickering doesn't
> occur any longer.
>
> Jan
Hi Jan. I think the flicker you're seeing is caused by our current lack
of two-stage watermark updates on platforms that use ILK-style
watermarks. I have a patch series at
http://patchwork.freedesktop.org/bundle/mattrope/atomic_wm_ilk/ that's
supposed to address this, but it's still awaiting review at the moment
so it isn't yet available upstream. Now that folks are coming back from
holiday vacations and such, hopefully we'll get the review finished soon
and be able to merge the patches.
The change you propose above would cause us to calculate watermarks as
if the cursor plane was on full-time (even when it's actually off
because the cursor is on the other display), so your watermarks wouldn't
need to change when you move your mouse to the other display and you
wouldn't see a flicker at that point. If the review process for atomic
WM carries on too long, we may want to consider merging a patch like
yours as a short term workaround for the issue you're seeing. There
would still be plenty of other ways to trigger flickering (changing
cursor size, using sprite planes (e.g., via xvideo), etc., but at least
a cursor getting enabled/disabled wouldn't cause a flicker.
Thanks.
Matt
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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^ permalink raw reply [flat|nested] 29+ messages in thread* Re: Flicker caused by "drm/i915: Eliminate usage of plane_wm_parameters from ILK-style WM code (v2)"
2016-01-05 21:58 ` Matt Roper
@ 2016-01-06 0:46 ` Jan Niehusmann
0 siblings, 0 replies; 29+ messages in thread
From: Jan Niehusmann @ 2016-01-06 0:46 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
Hi Matt,
On Tue, Jan 05, 2016 at 01:58:19PM -0800, Matt Roper wrote:
> Hi Jan. I think the flicker you're seeing is caused by our current lack
> of two-stage watermark updates on platforms that use ILK-style
> watermarks. I have a patch series at
> http://patchwork.freedesktop.org/bundle/mattrope/atomic_wm_ilk/ that's
> supposed to address this, but it's still awaiting review at the moment
Yes, thanks! That patch set fixes the flickering, as well.
Applied the patches, some of them manually, to 4.4-rc8,
after re-appling the reverted watermark commits
from 2791a16ca43302d07ac74cbe7c048e367c4632c4 and
261a27d11fa1dec47c47ece6968eaaba55861eca.
I didn't do much testing, but the resulting kernel boots fine and the
flickering is gone.
Jan
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^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 03/15] drm/i915: Eliminate usage of pipe_wm_parameters from ILK-style WM (v2)
2015-09-24 22:53 [PATCH 00/15] Atomic watermark updates (v5) Matt Roper
2015-09-24 22:53 ` [PATCH 01/15] drm/i915: Drop redundant watermark programming Matt Roper
2015-09-24 22:53 ` [PATCH 02/15] drm/i915: Eliminate usage of plane_wm_parameters from ILK-style WM code (v2) Matt Roper
@ 2015-09-24 22:53 ` Matt Roper
2015-09-24 22:53 ` [PATCH 04/15] drm/i915: Determine I915_MAX_PLANES from plane enum Matt Roper
` (12 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Matt Roper @ 2015-09-24 22:53 UTC (permalink / raw)
To: intel-gfx
Just pull the info out of the CRTC state structure rather than staging
it in an additional structure.
Note that we use cstate->active rather than intel_crtc->active which may
appear to be a change in behavior. However since we're no longer trying
to recalculate watermarks during the "pipe off" stage of a modeset,
intel_crtc->active and cstate->active should always be identical when
watermarks are calculated (at least for ILK-style platforms).
v2: Clarify reasoning for cstate->active and add a WARN_ON to the code
to assert that it really is always identical to intel_crtc->active
as expected.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 84 ++++++++++++++---------------------------
1 file changed, 29 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bfea446..9e6e9c2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1795,12 +1795,6 @@ struct skl_pipe_wm_parameters {
struct intel_plane_wm_parameters cursor;
};
-struct ilk_pipe_wm_parameters {
- bool active;
- uint32_t pipe_htotal;
- uint32_t pixel_rate;
-};
-
struct ilk_wm_maximums {
uint16_t pri;
uint16_t spr;
@@ -1819,7 +1813,7 @@ struct intel_wm_config {
* For both WM_PIPE and WM_LP.
* mem_value must be in 0.1us units.
*/
-static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
+static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
const struct intel_plane_state *pstate,
uint32_t mem_value,
bool is_lp)
@@ -1827,16 +1821,16 @@ static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
uint32_t method1, method2;
- if (!params->active || !pstate->visible)
+ if (!cstate->base.active || !pstate->visible)
return 0;
- method1 = ilk_wm_method1(params->pixel_rate, bpp, mem_value);
+ method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
if (!is_lp)
return method1;
- method2 = ilk_wm_method2(params->pixel_rate,
- params->pipe_htotal,
+ method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
+ cstate->base.adjusted_mode.crtc_htotal,
drm_rect_width(&pstate->dst),
bpp,
mem_value);
@@ -1848,19 +1842,19 @@ static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
* For both WM_PIPE and WM_LP.
* mem_value must be in 0.1us units.
*/
-static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
+static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
const struct intel_plane_state *pstate,
uint32_t mem_value)
{
int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
uint32_t method1, method2;
- if (!params->active || !pstate->visible)
+ if (!cstate->base.active || !pstate->visible)
return 0;
- method1 = ilk_wm_method1(params->pixel_rate, bpp, mem_value);
- method2 = ilk_wm_method2(params->pixel_rate,
- params->pipe_htotal,
+ method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
+ method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
+ cstate->base.adjusted_mode.crtc_htotal,
drm_rect_width(&pstate->dst),
bpp,
mem_value);
@@ -1871,30 +1865,30 @@ static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
* For both WM_PIPE and WM_LP.
* mem_value must be in 0.1us units.
*/
-static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
+static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
const struct intel_plane_state *pstate,
uint32_t mem_value)
{
int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
- if (!params->active || !pstate->visible)
+ if (!cstate->base.active || !pstate->visible)
return 0;
- return ilk_wm_method2(params->pixel_rate,
- params->pipe_htotal,
+ return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
+ cstate->base.adjusted_mode.crtc_htotal,
drm_rect_width(&pstate->dst),
bpp,
mem_value);
}
/* Only for WM_LP. */
-static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
+static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
const struct intel_plane_state *pstate,
uint32_t pri_val)
{
int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
- if (!params->active || !pstate->visible)
+ if (!cstate->base.active || !pstate->visible)
return 0;
return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
@@ -2064,7 +2058,7 @@ static bool ilk_validate_wm_level(int level,
static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
const struct intel_crtc *intel_crtc,
int level,
- const struct ilk_pipe_wm_parameters *p,
+ struct intel_crtc_state *cstate,
struct intel_wm_level *result)
{
struct intel_plane *intel_plane;
@@ -2085,18 +2079,18 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
switch (intel_plane->base.type) {
case DRM_PLANE_TYPE_PRIMARY:
- result->pri_val = ilk_compute_pri_wm(p, pstate,
+ result->pri_val = ilk_compute_pri_wm(cstate, pstate,
pri_latency,
level);
- result->fbc_val = ilk_compute_fbc_wm(p, pstate,
+ result->fbc_val = ilk_compute_fbc_wm(cstate, pstate,
result->pri_val);
break;
case DRM_PLANE_TYPE_OVERLAY:
- result->spr_val = ilk_compute_spr_wm(p, pstate,
+ result->spr_val = ilk_compute_spr_wm(cstate, pstate,
spr_latency);
break;
case DRM_PLANE_TYPE_CURSOR:
- result->cur_val = ilk_compute_cur_wm(p, pstate,
+ result->cur_val = ilk_compute_cur_wm(cstate, pstate,
cur_latency);
break;
}
@@ -2360,19 +2354,6 @@ static void skl_setup_wm_latency(struct drm_device *dev)
intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
}
-static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
- struct ilk_pipe_wm_parameters *p)
-{
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-
- if (!intel_crtc->active)
- return;
-
- p->active = true;
- p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
- p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
-}
-
static void ilk_compute_wm_config(struct drm_device *dev,
struct intel_wm_config *config)
{
@@ -2392,10 +2373,10 @@ static void ilk_compute_wm_config(struct drm_device *dev,
}
/* Compute new watermarks for the pipe */
-static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
- const struct ilk_pipe_wm_parameters *params,
+static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate,
struct intel_pipe_wm *pipe_wm)
{
+ struct drm_crtc *crtc = cstate->base.crtc;
struct drm_device *dev = crtc->dev;
const struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -2420,8 +2401,7 @@ static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
(drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
-
- pipe_wm->pipe_enabled = params->active;
+ pipe_wm->pipe_enabled = cstate->base.active;
pipe_wm->sprites_enabled = sprstate->visible;
pipe_wm->sprites_scaled = config.sprites_scaled;
@@ -2433,7 +2413,7 @@ static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
if (config.sprites_scaled)
max_level = 0;
- ilk_compute_wm_level(dev_priv, intel_crtc, 0, params, &pipe_wm->wm[0]);
+ ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]);
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
@@ -2450,7 +2430,7 @@ static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
for (level = 1; level <= max_level; level++) {
struct intel_wm_level wm = {};
- ilk_compute_wm_level(dev_priv, intel_crtc, level, params, &wm);
+ ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm);
/*
* Disable any watermark level that exceeds the
@@ -3781,19 +3761,19 @@ skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
static void ilk_update_wm(struct drm_crtc *crtc)
{
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct ilk_wm_maximums max;
- struct ilk_pipe_wm_parameters params = {};
struct ilk_wm_values results = {};
enum intel_ddb_partitioning partitioning;
struct intel_pipe_wm pipe_wm = {};
struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
struct intel_wm_config config = {};
- ilk_compute_wm_parameters(crtc, ¶ms);
+ WARN_ON(cstate->base.active != intel_crtc->active);
- intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm);
+ intel_compute_pipe_wm(cstate, &pipe_wm);
if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
return;
@@ -3833,12 +3813,6 @@ ilk_update_sprite_wm(struct drm_plane *plane,
struct drm_device *dev = plane->dev;
struct intel_plane *intel_plane = to_intel_plane(plane);
- intel_plane->wm.enabled = enabled;
- intel_plane->wm.scaled = scaled;
- intel_plane->wm.horiz_pixels = sprite_width;
- intel_plane->wm.vert_pixels = sprite_width;
- intel_plane->wm.bytes_per_pixel = pixel_size;
-
/*
* IVB workaround: must disable low power watermarks for at least
* one frame before enabling scaling. LP watermarks can be re-enabled
--
2.1.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 04/15] drm/i915: Determine I915_MAX_PLANES from plane enum
2015-09-24 22:53 [PATCH 00/15] Atomic watermark updates (v5) Matt Roper
` (2 preceding siblings ...)
2015-09-24 22:53 ` [PATCH 03/15] drm/i915: Eliminate usage of pipe_wm_parameters from ILK-style WM (v2) Matt Roper
@ 2015-09-24 22:53 ` Matt Roper
2015-09-24 22:53 ` [PATCH 05/15] drm/i915/skl: Simplify wm structures slightly (v2) Matt Roper
` (11 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Matt Roper @ 2015-09-24 22:53 UTC (permalink / raw)
To: intel-gfx
Let the compiler figure out what I915_MAX_PLANES is from 'enum plane' so
that we don't need a separate #define.
While we're at it, add the cursor plane to the enum. This will cause
I915_MAX_PLANES to now include the cursor plane in its count (it didn't
previously). This change is safe since we currently only use this
value in array declarations (never in the actual code logic); we just
wind up allocating slightly more memory than we need to. A followup
patch will cause various parts of the code to start using the extra
array element where appropriate.
(This patch probably should have been squashed with the followup patch,
but I couldn't figure out how to get Coccinelle to modify enum
declarations...)
Suggested-by: Ander Conselvan De Oliveira <conselvan2@gmail.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2b5d587..eac9414 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -131,17 +131,17 @@ enum transcoder {
#define transcoder_name(t) ((t) + 'A')
/*
- * This is the maximum (across all platforms) number of planes (primary +
- * sprites) that can be active at the same time on one pipe.
- *
- * This value doesn't count the cursor plane.
+ * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
+ * number of planes per CRTC. Not all platforms really have this many planes,
+ * which means some arrays of size I915_MAX_PLANES may have unused entries
+ * between the topmost sprite plane and the cursor plane.
*/
-#define I915_MAX_PLANES 4
-
enum plane {
PLANE_A = 0,
PLANE_B,
PLANE_C,
+ PLANE_CURSOR,
+ I915_MAX_PLANES,
};
#define plane_name(p) ((p) + 'A')
--
2.1.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 05/15] drm/i915/skl: Simplify wm structures slightly (v2)
2015-09-24 22:53 [PATCH 00/15] Atomic watermark updates (v5) Matt Roper
` (3 preceding siblings ...)
2015-09-24 22:53 ` [PATCH 04/15] drm/i915: Determine I915_MAX_PLANES from plane enum Matt Roper
@ 2015-09-24 22:53 ` Matt Roper
2015-09-30 15:13 ` Daniel Vetter
2015-09-24 22:53 ` [PATCH 06/15] drm/i915/skl: Eliminate usage of pipe_wm_parameters from SKL-style WM (v3) Matt Roper
` (10 subsequent siblings)
15 siblings, 1 reply; 29+ messages in thread
From: Matt Roper @ 2015-09-24 22:53 UTC (permalink / raw)
To: intel-gfx
A bunch of SKL watermark-related structures have the cursor plane as a
separate entry from the rest of the planes. Since a previous patch
updated I915_MAX_PLANES such that those plane arrays now have a slot for
the cursor, update the code to use the new slot in the existing plane
arrays and kill off the cursor-specific structures.
There shouldn't be any functional change here; this is just shuffling
around how the data is stored in some of the data structures. The whole
patch is generated with Coccinelle via the following semantic patch:
@@ struct skl_pipe_wm_parameters WMP; @@
- WMP.cursor
+ WMP.plane[PLANE_CURSOR]
@@ struct skl_pipe_wm_parameters *WMP; @@
- WMP->cursor
+ WMP->plane[PLANE_CURSOR]
@@ @@
struct skl_pipe_wm_parameters {
...
- struct intel_plane_wm_parameters cursor;
...
};
@@
struct skl_ddb_allocation DDB;
expression E;
@@
- DDB.cursor[E]
+ DDB.plane[E][PLANE_CURSOR]
@@
struct skl_ddb_allocation *DDB;
expression E;
@@
- DDB->cursor[E]
+ DDB->plane[E][PLANE_CURSOR]
@@ @@
struct skl_ddb_allocation {
...
- struct skl_ddb_entry cursor[I915_MAX_PIPES];
...
};
@@
struct skl_wm_values WMV;
expression E1, E2;
@@
(
- WMV.cursor[E1][E2]
+ WMV.plane[E1][PLANE_CURSOR][E2]
|
- WMV.cursor_trans[E1]
+ WMV.plane_trans[E1][PLANE_CURSOR]
)
@@
struct skl_wm_values *WMV;
expression E1, E2;
@@
(
- WMV->cursor[E1][E2]
+ WMV->plane[E1][PLANE_CURSOR][E2]
|
- WMV->cursor_trans[E1]
+ WMV->plane_trans[E1][PLANE_CURSOR]
)
@@ @@
struct skl_wm_values {
...
- uint32_t cursor[I915_MAX_PIPES][8];
...
- uint32_t cursor_trans[I915_MAX_PIPES];
...
};
@@ struct skl_wm_level WML; @@
(
- WML.cursor_en
+ WML.plane_en[PLANE_CURSOR]
|
- WML.cursor_res_b
+ WML.plane_res_b[PLANE_CURSOR]
|
- WML.cursor_res_l
+ WML.plane_res_l[PLANE_CURSOR]
)
@@ struct skl_wm_level *WML; @@
(
- WML->cursor_en
+ WML->plane_en[PLANE_CURSOR]
|
- WML->cursor_res_b
+ WML->plane_res_b[PLANE_CURSOR]
|
- WML->cursor_res_l
+ WML->plane_res_l[PLANE_CURSOR]
)
@@ @@
struct skl_wm_level {
...
- bool cursor_en;
...
- uint16_t cursor_res_b;
- uint8_t cursor_res_l;
...
};
v2: Use a PLANE_CURSOR enum entry rather than making the code reference
I915_MAX_PLANES or I915_MAX_PLANES+1, which was confusing. (Ander)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 8 +---
drivers/gpu/drm/i915/intel_display.c | 4 +-
drivers/gpu/drm/i915/intel_pm.c | 93 +++++++++++++++++++-----------------
4 files changed, 52 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 5615d3d..03c196e 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3144,7 +3144,7 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
skl_ddb_entry_size(entry));
}
- entry = &ddb->cursor[pipe];
+ entry = &ddb->plane[pipe][PLANE_CURSOR];
seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
entry->end, skl_ddb_entry_size(entry));
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index eac9414..bd542cb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1588,8 +1588,7 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
struct skl_ddb_allocation {
struct skl_ddb_entry pipe[I915_MAX_PIPES];
struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
- struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* y-plane */
- struct skl_ddb_entry cursor[I915_MAX_PIPES];
+ struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
};
struct skl_wm_values {
@@ -1597,18 +1596,13 @@ struct skl_wm_values {
struct skl_ddb_allocation ddb;
uint32_t wm_linetime[I915_MAX_PIPES];
uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
- uint32_t cursor[I915_MAX_PIPES][8];
uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
- uint32_t cursor_trans[I915_MAX_PIPES];
};
struct skl_wm_level {
bool plane_en[I915_MAX_PLANES];
- bool cursor_en;
uint16_t plane_res_b[I915_MAX_PLANES];
uint8_t plane_res_l[I915_MAX_PLANES];
- uint16_t cursor_res_b;
- uint8_t cursor_res_l;
};
/*
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dea1f23..a3e62bc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12564,8 +12564,8 @@ static void check_wm_state(struct drm_device *dev)
}
/* cursor */
- hw_entry = &hw_ddb.cursor[pipe];
- sw_entry = &sw_ddb->cursor[pipe];
+ hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
+ sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
if (skl_ddb_entry_equal(hw_entry, sw_entry))
continue;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9e6e9c2..8829047 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1792,7 +1792,6 @@ struct skl_pipe_wm_parameters {
uint32_t pipe_htotal;
uint32_t pixel_rate; /* in KHz */
struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
- struct intel_plane_wm_parameters cursor;
};
struct ilk_wm_maximums {
@@ -2906,7 +2905,8 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
}
val = I915_READ(CUR_BUF_CFG(pipe));
- skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
+ skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
+ val);
}
}
@@ -2975,13 +2975,14 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
alloc_size = skl_ddb_entry_size(alloc);
if (alloc_size == 0) {
memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
- memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
+ memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
+ sizeof(ddb->plane[pipe][PLANE_CURSOR]));
return;
}
cursor_blocks = skl_cursor_allocation(config);
- ddb->cursor[pipe].start = alloc->end - cursor_blocks;
- ddb->cursor[pipe].end = alloc->end;
+ ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
+ ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
alloc_size -= cursor_blocks;
alloc->end -= cursor_blocks;
@@ -3120,8 +3121,8 @@ static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
sizeof(new_ddb->plane[pipe])))
return true;
- if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
- sizeof(new_ddb->cursor[pipe])))
+ if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR],
+ sizeof(new_ddb->plane[pipe][PLANE_CURSOR])))
return true;
return false;
@@ -3181,17 +3182,17 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
p->plane[0].rotation = crtc->primary->state->rotation;
fb = crtc->cursor->state->fb;
- p->cursor.y_bytes_per_pixel = 0;
+ p->plane[PLANE_CURSOR].y_bytes_per_pixel = 0;
if (fb) {
- p->cursor.enabled = true;
- p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
- p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
- p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
+ p->plane[PLANE_CURSOR].enabled = true;
+ p->plane[PLANE_CURSOR].bytes_per_pixel = fb->bits_per_pixel / 8;
+ p->plane[PLANE_CURSOR].horiz_pixels = crtc->cursor->state->crtc_w;
+ p->plane[PLANE_CURSOR].vert_pixels = crtc->cursor->state->crtc_h;
} else {
- p->cursor.enabled = false;
- p->cursor.bytes_per_pixel = 0;
- p->cursor.horiz_pixels = 64;
- p->cursor.vert_pixels = 64;
+ p->plane[PLANE_CURSOR].enabled = false;
+ p->plane[PLANE_CURSOR].bytes_per_pixel = 0;
+ p->plane[PLANE_CURSOR].horiz_pixels = 64;
+ p->plane[PLANE_CURSOR].vert_pixels = 64;
}
}
@@ -3305,11 +3306,12 @@ static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
&result->plane_res_l[i]);
}
- ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
- result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
+ ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][PLANE_CURSOR]);
+ result->plane_en[PLANE_CURSOR] = skl_compute_plane_wm(dev_priv, p,
+ &p->plane[PLANE_CURSOR],
ddb_blocks, level,
- &result->cursor_res_b,
- &result->cursor_res_l);
+ &result->plane_res_b[PLANE_CURSOR],
+ &result->plane_res_l[PLANE_CURSOR]);
}
static uint32_t
@@ -3337,7 +3339,7 @@ static void skl_compute_transition_wm(struct drm_crtc *crtc,
/* Until we know more, just disable transition WMs */
for (i = 0; i < intel_num_planes(intel_crtc); i++)
trans_wm->plane_en[i] = false;
- trans_wm->cursor_en = false;
+ trans_wm->plane_en[PLANE_CURSOR] = false;
}
static void skl_compute_pipe_wm(struct drm_crtc *crtc,
@@ -3386,13 +3388,13 @@ static void skl_compute_wm_results(struct drm_device *dev,
temp = 0;
- temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
- temp |= p_wm->wm[level].cursor_res_b;
+ temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
+ temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
- if (p_wm->wm[level].cursor_en)
+ if (p_wm->wm[level].plane_en[PLANE_CURSOR])
temp |= PLANE_WM_EN;
- r->cursor[pipe][level] = temp;
+ r->plane[pipe][PLANE_CURSOR][level] = temp;
}
@@ -3408,12 +3410,12 @@ static void skl_compute_wm_results(struct drm_device *dev,
}
temp = 0;
- temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
- temp |= p_wm->trans_wm.cursor_res_b;
- if (p_wm->trans_wm.cursor_en)
+ temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
+ temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
+ if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
temp |= PLANE_WM_EN;
- r->cursor_trans[pipe] = temp;
+ r->plane_trans[pipe][PLANE_CURSOR] = temp;
r->wm_linetime[pipe] = p_wm->linetime;
}
@@ -3447,12 +3449,13 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv,
I915_WRITE(PLANE_WM(pipe, i, level),
new->plane[pipe][i][level]);
I915_WRITE(CUR_WM(pipe, level),
- new->cursor[pipe][level]);
+ new->plane[pipe][PLANE_CURSOR][level]);
}
for (i = 0; i < intel_num_planes(crtc); i++)
I915_WRITE(PLANE_WM_TRANS(pipe, i),
new->plane_trans[pipe][i]);
- I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
+ I915_WRITE(CUR_WM_TRANS(pipe),
+ new->plane_trans[pipe][PLANE_CURSOR]);
for (i = 0; i < intel_num_planes(crtc); i++) {
skl_ddb_entry_write(dev_priv,
@@ -3464,7 +3467,7 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv,
}
skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
- &new->ddb.cursor[pipe]);
+ &new->ddb.plane[pipe][PLANE_CURSOR]);
}
}
@@ -3677,10 +3680,9 @@ static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
watermarks->wm_linetime[pipe] = 0;
memset(watermarks->plane[pipe], 0,
sizeof(uint32_t) * 8 * I915_MAX_PLANES);
- memset(watermarks->cursor[pipe], 0, sizeof(uint32_t) * 8);
memset(watermarks->plane_trans[pipe],
0, sizeof(uint32_t) * I915_MAX_PLANES);
- watermarks->cursor_trans[pipe] = 0;
+ watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
/* Clear ddb entries for pipe */
memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
@@ -3688,7 +3690,8 @@ static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
memset(&watermarks->ddb.y_plane[pipe], 0,
sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
- memset(&watermarks->ddb.cursor[pipe], 0, sizeof(struct skl_ddb_entry));
+ memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
+ sizeof(struct skl_ddb_entry));
}
@@ -3844,10 +3847,10 @@ static void skl_pipe_wm_active_state(uint32_t val,
(val >> PLANE_WM_LINES_SHIFT) &
PLANE_WM_LINES_MASK;
} else {
- active->wm[level].cursor_en = is_enabled;
- active->wm[level].cursor_res_b =
+ active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
+ active->wm[level].plane_res_b[PLANE_CURSOR] =
val & PLANE_WM_BLOCKS_MASK;
- active->wm[level].cursor_res_l =
+ active->wm[level].plane_res_l[PLANE_CURSOR] =
(val >> PLANE_WM_LINES_SHIFT) &
PLANE_WM_LINES_MASK;
}
@@ -3860,10 +3863,10 @@ static void skl_pipe_wm_active_state(uint32_t val,
(val >> PLANE_WM_LINES_SHIFT) &
PLANE_WM_LINES_MASK;
} else {
- active->trans_wm.cursor_en = is_enabled;
- active->trans_wm.cursor_res_b =
+ active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
+ active->trans_wm.plane_res_b[PLANE_CURSOR] =
val & PLANE_WM_BLOCKS_MASK;
- active->trans_wm.cursor_res_l =
+ active->trans_wm.plane_res_l[PLANE_CURSOR] =
(val >> PLANE_WM_LINES_SHIFT) &
PLANE_WM_LINES_MASK;
}
@@ -3889,12 +3892,12 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
for (i = 0; i < intel_num_planes(intel_crtc); i++)
hw->plane[pipe][i][level] =
I915_READ(PLANE_WM(pipe, i, level));
- hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
+ hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
}
for (i = 0; i < intel_num_planes(intel_crtc); i++)
hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
- hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
+ hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
if (!intel_crtc->active)
return;
@@ -3909,7 +3912,7 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
skl_pipe_wm_active_state(temp, active, false,
false, i, level);
}
- temp = hw->cursor[pipe][level];
+ temp = hw->plane[pipe][PLANE_CURSOR][level];
skl_pipe_wm_active_state(temp, active, false, true, i, level);
}
@@ -3918,7 +3921,7 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
skl_pipe_wm_active_state(temp, active, true, false, i, 0);
}
- temp = hw->cursor_trans[pipe];
+ temp = hw->plane_trans[pipe][PLANE_CURSOR];
skl_pipe_wm_active_state(temp, active, true, true, i, 0);
}
--
2.1.4
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^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 05/15] drm/i915/skl: Simplify wm structures slightly (v2)
2015-09-24 22:53 ` [PATCH 05/15] drm/i915/skl: Simplify wm structures slightly (v2) Matt Roper
@ 2015-09-30 15:13 ` Daniel Vetter
0 siblings, 0 replies; 29+ messages in thread
From: Daniel Vetter @ 2015-09-30 15:13 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Thu, Sep 24, 2015 at 03:53:10PM -0700, Matt Roper wrote:
> A bunch of SKL watermark-related structures have the cursor plane as a
> separate entry from the rest of the planes. Since a previous patch
> updated I915_MAX_PLANES such that those plane arrays now have a slot for
> the cursor, update the code to use the new slot in the existing plane
> arrays and kill off the cursor-specific structures.
>
> There shouldn't be any functional change here; this is just shuffling
> around how the data is stored in some of the data structures. The whole
> patch is generated with Coccinelle via the following semantic patch:
>
> @@ struct skl_pipe_wm_parameters WMP; @@
> - WMP.cursor
> + WMP.plane[PLANE_CURSOR]
>
> @@ struct skl_pipe_wm_parameters *WMP; @@
> - WMP->cursor
> + WMP->plane[PLANE_CURSOR]
>
> @@ @@
> struct skl_pipe_wm_parameters {
> ...
> - struct intel_plane_wm_parameters cursor;
> ...
> };
>
> @@
> struct skl_ddb_allocation DDB;
> expression E;
> @@
> - DDB.cursor[E]
> + DDB.plane[E][PLANE_CURSOR]
>
> @@
> struct skl_ddb_allocation *DDB;
> expression E;
> @@
> - DDB->cursor[E]
> + DDB->plane[E][PLANE_CURSOR]
>
> @@ @@
> struct skl_ddb_allocation {
> ...
> - struct skl_ddb_entry cursor[I915_MAX_PIPES];
> ...
> };
>
> @@
> struct skl_wm_values WMV;
> expression E1, E2;
> @@
> (
> - WMV.cursor[E1][E2]
> + WMV.plane[E1][PLANE_CURSOR][E2]
> |
> - WMV.cursor_trans[E1]
> + WMV.plane_trans[E1][PLANE_CURSOR]
> )
>
> @@
> struct skl_wm_values *WMV;
> expression E1, E2;
> @@
> (
> - WMV->cursor[E1][E2]
> + WMV->plane[E1][PLANE_CURSOR][E2]
> |
> - WMV->cursor_trans[E1]
> + WMV->plane_trans[E1][PLANE_CURSOR]
> )
>
> @@ @@
> struct skl_wm_values {
> ...
> - uint32_t cursor[I915_MAX_PIPES][8];
> ...
> - uint32_t cursor_trans[I915_MAX_PIPES];
> ...
> };
>
> @@ struct skl_wm_level WML; @@
> (
> - WML.cursor_en
> + WML.plane_en[PLANE_CURSOR]
> |
> - WML.cursor_res_b
> + WML.plane_res_b[PLANE_CURSOR]
> |
> - WML.cursor_res_l
> + WML.plane_res_l[PLANE_CURSOR]
> )
>
> @@ struct skl_wm_level *WML; @@
> (
> - WML->cursor_en
> + WML->plane_en[PLANE_CURSOR]
> |
> - WML->cursor_res_b
> + WML->plane_res_b[PLANE_CURSOR]
> |
> - WML->cursor_res_l
> + WML->plane_res_l[PLANE_CURSOR]
> )
>
> @@ @@
> struct skl_wm_level {
> ...
> - bool cursor_en;
> ...
> - uint16_t cursor_res_b;
> - uint8_t cursor_res_l;
> ...
> };
>
> v2: Use a PLANE_CURSOR enum entry rather than making the code reference
> I915_MAX_PLANES or I915_MAX_PLANES+1, which was confusing. (Ander)
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Merged up to this one here.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 8 +---
> drivers/gpu/drm/i915/intel_display.c | 4 +-
> drivers/gpu/drm/i915/intel_pm.c | 93 +++++++++++++++++++-----------------
> 4 files changed, 52 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 5615d3d..03c196e 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -3144,7 +3144,7 @@ static int i915_ddb_info(struct seq_file *m, void *unused)
> skl_ddb_entry_size(entry));
> }
>
> - entry = &ddb->cursor[pipe];
> + entry = &ddb->plane[pipe][PLANE_CURSOR];
> seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
> entry->end, skl_ddb_entry_size(entry));
> }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index eac9414..bd542cb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1588,8 +1588,7 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
> struct skl_ddb_allocation {
> struct skl_ddb_entry pipe[I915_MAX_PIPES];
> struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
> - struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* y-plane */
> - struct skl_ddb_entry cursor[I915_MAX_PIPES];
> + struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
> };
>
> struct skl_wm_values {
> @@ -1597,18 +1596,13 @@ struct skl_wm_values {
> struct skl_ddb_allocation ddb;
> uint32_t wm_linetime[I915_MAX_PIPES];
> uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
> - uint32_t cursor[I915_MAX_PIPES][8];
> uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
> - uint32_t cursor_trans[I915_MAX_PIPES];
> };
>
> struct skl_wm_level {
> bool plane_en[I915_MAX_PLANES];
> - bool cursor_en;
> uint16_t plane_res_b[I915_MAX_PLANES];
> uint8_t plane_res_l[I915_MAX_PLANES];
> - uint16_t cursor_res_b;
> - uint8_t cursor_res_l;
> };
>
> /*
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index dea1f23..a3e62bc 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -12564,8 +12564,8 @@ static void check_wm_state(struct drm_device *dev)
> }
>
> /* cursor */
> - hw_entry = &hw_ddb.cursor[pipe];
> - sw_entry = &sw_ddb->cursor[pipe];
> + hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
> + sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
>
> if (skl_ddb_entry_equal(hw_entry, sw_entry))
> continue;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9e6e9c2..8829047 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -1792,7 +1792,6 @@ struct skl_pipe_wm_parameters {
> uint32_t pipe_htotal;
> uint32_t pixel_rate; /* in KHz */
> struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
> - struct intel_plane_wm_parameters cursor;
> };
>
> struct ilk_wm_maximums {
> @@ -2906,7 +2905,8 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> }
>
> val = I915_READ(CUR_BUF_CFG(pipe));
> - skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
> + skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
> + val);
> }
> }
>
> @@ -2975,13 +2975,14 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
> alloc_size = skl_ddb_entry_size(alloc);
> if (alloc_size == 0) {
> memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
> - memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
> + memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
> + sizeof(ddb->plane[pipe][PLANE_CURSOR]));
> return;
> }
>
> cursor_blocks = skl_cursor_allocation(config);
> - ddb->cursor[pipe].start = alloc->end - cursor_blocks;
> - ddb->cursor[pipe].end = alloc->end;
> + ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
> + ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
>
> alloc_size -= cursor_blocks;
> alloc->end -= cursor_blocks;
> @@ -3120,8 +3121,8 @@ static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
> sizeof(new_ddb->plane[pipe])))
> return true;
>
> - if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
> - sizeof(new_ddb->cursor[pipe])))
> + if (memcmp(&new_ddb->plane[pipe][PLANE_CURSOR], &cur_ddb->plane[pipe][PLANE_CURSOR],
> + sizeof(new_ddb->plane[pipe][PLANE_CURSOR])))
> return true;
>
> return false;
> @@ -3181,17 +3182,17 @@ static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
> p->plane[0].rotation = crtc->primary->state->rotation;
>
> fb = crtc->cursor->state->fb;
> - p->cursor.y_bytes_per_pixel = 0;
> + p->plane[PLANE_CURSOR].y_bytes_per_pixel = 0;
> if (fb) {
> - p->cursor.enabled = true;
> - p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
> - p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
> - p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
> + p->plane[PLANE_CURSOR].enabled = true;
> + p->plane[PLANE_CURSOR].bytes_per_pixel = fb->bits_per_pixel / 8;
> + p->plane[PLANE_CURSOR].horiz_pixels = crtc->cursor->state->crtc_w;
> + p->plane[PLANE_CURSOR].vert_pixels = crtc->cursor->state->crtc_h;
> } else {
> - p->cursor.enabled = false;
> - p->cursor.bytes_per_pixel = 0;
> - p->cursor.horiz_pixels = 64;
> - p->cursor.vert_pixels = 64;
> + p->plane[PLANE_CURSOR].enabled = false;
> + p->plane[PLANE_CURSOR].bytes_per_pixel = 0;
> + p->plane[PLANE_CURSOR].horiz_pixels = 64;
> + p->plane[PLANE_CURSOR].vert_pixels = 64;
> }
> }
>
> @@ -3305,11 +3306,12 @@ static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
> &result->plane_res_l[i]);
> }
>
> - ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
> - result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
> + ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][PLANE_CURSOR]);
> + result->plane_en[PLANE_CURSOR] = skl_compute_plane_wm(dev_priv, p,
> + &p->plane[PLANE_CURSOR],
> ddb_blocks, level,
> - &result->cursor_res_b,
> - &result->cursor_res_l);
> + &result->plane_res_b[PLANE_CURSOR],
> + &result->plane_res_l[PLANE_CURSOR]);
> }
>
> static uint32_t
> @@ -3337,7 +3339,7 @@ static void skl_compute_transition_wm(struct drm_crtc *crtc,
> /* Until we know more, just disable transition WMs */
> for (i = 0; i < intel_num_planes(intel_crtc); i++)
> trans_wm->plane_en[i] = false;
> - trans_wm->cursor_en = false;
> + trans_wm->plane_en[PLANE_CURSOR] = false;
> }
>
> static void skl_compute_pipe_wm(struct drm_crtc *crtc,
> @@ -3386,13 +3388,13 @@ static void skl_compute_wm_results(struct drm_device *dev,
>
> temp = 0;
>
> - temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
> - temp |= p_wm->wm[level].cursor_res_b;
> + temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
> + temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
>
> - if (p_wm->wm[level].cursor_en)
> + if (p_wm->wm[level].plane_en[PLANE_CURSOR])
> temp |= PLANE_WM_EN;
>
> - r->cursor[pipe][level] = temp;
> + r->plane[pipe][PLANE_CURSOR][level] = temp;
>
> }
>
> @@ -3408,12 +3410,12 @@ static void skl_compute_wm_results(struct drm_device *dev,
> }
>
> temp = 0;
> - temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
> - temp |= p_wm->trans_wm.cursor_res_b;
> - if (p_wm->trans_wm.cursor_en)
> + temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
> + temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
> + if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
> temp |= PLANE_WM_EN;
>
> - r->cursor_trans[pipe] = temp;
> + r->plane_trans[pipe][PLANE_CURSOR] = temp;
>
> r->wm_linetime[pipe] = p_wm->linetime;
> }
> @@ -3447,12 +3449,13 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv,
> I915_WRITE(PLANE_WM(pipe, i, level),
> new->plane[pipe][i][level]);
> I915_WRITE(CUR_WM(pipe, level),
> - new->cursor[pipe][level]);
> + new->plane[pipe][PLANE_CURSOR][level]);
> }
> for (i = 0; i < intel_num_planes(crtc); i++)
> I915_WRITE(PLANE_WM_TRANS(pipe, i),
> new->plane_trans[pipe][i]);
> - I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
> + I915_WRITE(CUR_WM_TRANS(pipe),
> + new->plane_trans[pipe][PLANE_CURSOR]);
>
> for (i = 0; i < intel_num_planes(crtc); i++) {
> skl_ddb_entry_write(dev_priv,
> @@ -3464,7 +3467,7 @@ static void skl_write_wm_values(struct drm_i915_private *dev_priv,
> }
>
> skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
> - &new->ddb.cursor[pipe]);
> + &new->ddb.plane[pipe][PLANE_CURSOR]);
> }
> }
>
> @@ -3677,10 +3680,9 @@ static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
> watermarks->wm_linetime[pipe] = 0;
> memset(watermarks->plane[pipe], 0,
> sizeof(uint32_t) * 8 * I915_MAX_PLANES);
> - memset(watermarks->cursor[pipe], 0, sizeof(uint32_t) * 8);
> memset(watermarks->plane_trans[pipe],
> 0, sizeof(uint32_t) * I915_MAX_PLANES);
> - watermarks->cursor_trans[pipe] = 0;
> + watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
>
> /* Clear ddb entries for pipe */
> memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
> @@ -3688,7 +3690,8 @@ static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
> sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
> memset(&watermarks->ddb.y_plane[pipe], 0,
> sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
> - memset(&watermarks->ddb.cursor[pipe], 0, sizeof(struct skl_ddb_entry));
> + memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
> + sizeof(struct skl_ddb_entry));
>
> }
>
> @@ -3844,10 +3847,10 @@ static void skl_pipe_wm_active_state(uint32_t val,
> (val >> PLANE_WM_LINES_SHIFT) &
> PLANE_WM_LINES_MASK;
> } else {
> - active->wm[level].cursor_en = is_enabled;
> - active->wm[level].cursor_res_b =
> + active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
> + active->wm[level].plane_res_b[PLANE_CURSOR] =
> val & PLANE_WM_BLOCKS_MASK;
> - active->wm[level].cursor_res_l =
> + active->wm[level].plane_res_l[PLANE_CURSOR] =
> (val >> PLANE_WM_LINES_SHIFT) &
> PLANE_WM_LINES_MASK;
> }
> @@ -3860,10 +3863,10 @@ static void skl_pipe_wm_active_state(uint32_t val,
> (val >> PLANE_WM_LINES_SHIFT) &
> PLANE_WM_LINES_MASK;
> } else {
> - active->trans_wm.cursor_en = is_enabled;
> - active->trans_wm.cursor_res_b =
> + active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
> + active->trans_wm.plane_res_b[PLANE_CURSOR] =
> val & PLANE_WM_BLOCKS_MASK;
> - active->trans_wm.cursor_res_l =
> + active->trans_wm.plane_res_l[PLANE_CURSOR] =
> (val >> PLANE_WM_LINES_SHIFT) &
> PLANE_WM_LINES_MASK;
> }
> @@ -3889,12 +3892,12 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
> for (i = 0; i < intel_num_planes(intel_crtc); i++)
> hw->plane[pipe][i][level] =
> I915_READ(PLANE_WM(pipe, i, level));
> - hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
> + hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
> }
>
> for (i = 0; i < intel_num_planes(intel_crtc); i++)
> hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
> - hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
> + hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
>
> if (!intel_crtc->active)
> return;
> @@ -3909,7 +3912,7 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
> skl_pipe_wm_active_state(temp, active, false,
> false, i, level);
> }
> - temp = hw->cursor[pipe][level];
> + temp = hw->plane[pipe][PLANE_CURSOR][level];
> skl_pipe_wm_active_state(temp, active, false, true, i, level);
> }
>
> @@ -3918,7 +3921,7 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
> skl_pipe_wm_active_state(temp, active, true, false, i, 0);
> }
>
> - temp = hw->cursor_trans[pipe];
> + temp = hw->plane_trans[pipe][PLANE_CURSOR];
> skl_pipe_wm_active_state(temp, active, true, true, i, 0);
> }
>
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 06/15] drm/i915/skl: Eliminate usage of pipe_wm_parameters from SKL-style WM (v3)
2015-09-24 22:53 [PATCH 00/15] Atomic watermark updates (v5) Matt Roper
` (4 preceding siblings ...)
2015-09-24 22:53 ` [PATCH 05/15] drm/i915/skl: Simplify wm structures slightly (v2) Matt Roper
@ 2015-09-24 22:53 ` Matt Roper
2015-09-24 22:53 ` [PATCH 07/15] drm/i915/ivb: Move WaCxSRDisabledForSpriteScaling w/a to atomic check Matt Roper
` (9 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Matt Roper @ 2015-09-24 22:53 UTC (permalink / raw)
To: intel-gfx
Just pull the info out of the state structures rather than staging
it in an additional set of structures. To make this more
straightforward, we change the signature of several internal WM
functions to take the crtc state as a parameter.
v2:
- Don't forget to skip cursor planes on a loop in the DDB allocation
function to match original behavior. (Ander)
- Change a use of intel_crtc->active to cstate->active. They should
be identical, but it's better to be consistent. (Ander)
- Rework more function signatures to pass states rather than crtc for
consistency. (Ander)
v3:
- Add missing "+ 1" to skl_wm_plane_id()'s 'overlay' case. (Maarten)
- Packed formats should pass '0' to drm_format_plane_cpp(), not 1.
(Maarten)
- Drop unwanted WARN_ON() for disabled planes when calculating data
rate for SKL. (Maarten)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 326 +++++++++++++++++++---------------------
1 file changed, 151 insertions(+), 175 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8829047..7bfcc98 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1787,13 +1787,6 @@ static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
}
-struct skl_pipe_wm_parameters {
- bool active;
- uint32_t pipe_htotal;
- uint32_t pixel_rate; /* in KHz */
- struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
-};
-
struct ilk_wm_maximums {
uint16_t pri;
uint16_t spr;
@@ -2834,18 +2827,40 @@ static bool ilk_disable_lp_wm(struct drm_device *dev)
#define SKL_DDB_SIZE 896 /* in blocks */
#define BXT_DDB_SIZE 512
+/*
+ * Return the index of a plane in the SKL DDB and wm result arrays. Primary
+ * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
+ * other universal planes are in indices 1..n. Note that this may leave unused
+ * indices between the top "sprite" plane and the cursor.
+ */
+static int
+skl_wm_plane_id(const struct intel_plane *plane)
+{
+ switch (plane->base.type) {
+ case DRM_PLANE_TYPE_PRIMARY:
+ return 0;
+ case DRM_PLANE_TYPE_CURSOR:
+ return PLANE_CURSOR;
+ case DRM_PLANE_TYPE_OVERLAY:
+ return plane->plane + 1;
+ default:
+ MISSING_CASE(plane->base.type);
+ return plane->plane;
+ }
+}
+
static void
skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
- struct drm_crtc *for_crtc,
+ const struct intel_crtc_state *cstate,
const struct intel_wm_config *config,
- const struct skl_pipe_wm_parameters *params,
struct skl_ddb_entry *alloc /* out */)
{
+ struct drm_crtc *for_crtc = cstate->base.crtc;
struct drm_crtc *crtc;
unsigned int pipe_size, ddb_size;
int nth_active_pipe;
- if (!params->active) {
+ if (!cstate->base.active) {
alloc->start = 0;
alloc->end = 0;
return;
@@ -2911,19 +2926,29 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
}
static unsigned int
-skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
+skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
+ const struct drm_plane_state *pstate,
+ int y)
{
+ struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
+ struct drm_framebuffer *fb = pstate->fb;
/* for planar format */
- if (p->y_bytes_per_pixel) {
+ if (fb->pixel_format == DRM_FORMAT_NV12) {
if (y) /* y-plane data rate */
- return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
+ return intel_crtc->config->pipe_src_w *
+ intel_crtc->config->pipe_src_h *
+ drm_format_plane_cpp(fb->pixel_format, 0);
else /* uv-plane data rate */
- return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
+ return (intel_crtc->config->pipe_src_w/2) *
+ (intel_crtc->config->pipe_src_h/2) *
+ drm_format_plane_cpp(fb->pixel_format, 1);
}
/* for packed formats */
- return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
+ return intel_crtc->config->pipe_src_w *
+ intel_crtc->config->pipe_src_h *
+ drm_format_plane_cpp(fb->pixel_format, 0);
}
/*
@@ -2932,46 +2957,51 @@ skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
* 3 * 4096 * 8192 * 4 < 2^32
*/
static unsigned int
-skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
- const struct skl_pipe_wm_parameters *params)
+skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
{
+ struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
+ struct drm_device *dev = intel_crtc->base.dev;
+ const struct intel_plane *intel_plane;
unsigned int total_data_rate = 0;
- int plane;
- for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
- const struct intel_plane_wm_parameters *p;
+ for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
+ const struct drm_plane_state *pstate = intel_plane->base.state;
- p = ¶ms->plane[plane];
- if (!p->enabled)
+ if (pstate->fb == NULL)
continue;
- total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
- if (p->y_bytes_per_pixel) {
- total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
- }
+ /* packed/uv */
+ total_data_rate += skl_plane_relative_data_rate(cstate,
+ pstate,
+ 0);
+
+ if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
+ /* y-plane */
+ total_data_rate += skl_plane_relative_data_rate(cstate,
+ pstate,
+ 1);
}
return total_data_rate;
}
static void
-skl_allocate_pipe_ddb(struct drm_crtc *crtc,
+skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
const struct intel_wm_config *config,
- const struct skl_pipe_wm_parameters *params,
struct skl_ddb_allocation *ddb /* out */)
{
+ struct drm_crtc *crtc = cstate->base.crtc;
struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_plane *intel_plane;
enum pipe pipe = intel_crtc->pipe;
struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
uint16_t alloc_size, start, cursor_blocks;
uint16_t minimum[I915_MAX_PLANES];
uint16_t y_minimum[I915_MAX_PLANES];
unsigned int total_data_rate;
- int plane;
- skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
+ skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
alloc_size = skl_ddb_entry_size(alloc);
if (alloc_size == 0) {
memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
@@ -2988,17 +3018,20 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
alloc->end -= cursor_blocks;
/* 1. Allocate the mininum required blocks for each active plane */
- for_each_plane(dev_priv, pipe, plane) {
- const struct intel_plane_wm_parameters *p;
+ for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
+ struct drm_plane *plane = &intel_plane->base;
+ struct drm_framebuffer *fb = plane->fb;
+ int id = skl_wm_plane_id(intel_plane);
- p = ¶ms->plane[plane];
- if (!p->enabled)
+ if (fb == NULL)
+ continue;
+ if (plane->type == DRM_PLANE_TYPE_CURSOR)
continue;
- minimum[plane] = 8;
- alloc_size -= minimum[plane];
- y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
- alloc_size -= y_minimum[plane];
+ minimum[id] = 8;
+ alloc_size -= minimum[id];
+ y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
+ alloc_size -= y_minimum[id];
}
/*
@@ -3007,45 +3040,50 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
*
* FIXME: we may not allocate every single block here.
*/
- total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
+ total_data_rate = skl_get_total_relative_data_rate(cstate);
start = alloc->start;
- for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
- const struct intel_plane_wm_parameters *p;
+ for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
+ struct drm_plane *plane = &intel_plane->base;
+ struct drm_plane_state *pstate = intel_plane->base.state;
unsigned int data_rate, y_data_rate;
uint16_t plane_blocks, y_plane_blocks = 0;
+ int id = skl_wm_plane_id(intel_plane);
- p = ¶ms->plane[plane];
- if (!p->enabled)
+ if (pstate->fb == NULL)
+ continue;
+ if (plane->type == DRM_PLANE_TYPE_CURSOR)
continue;
- data_rate = skl_plane_relative_data_rate(p, 0);
+ data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
/*
* allocation for (packed formats) or (uv-plane part of planar format):
* promote the expression to 64 bits to avoid overflowing, the
* result is < available as data_rate / total_data_rate < 1
*/
- plane_blocks = minimum[plane];
+ plane_blocks = minimum[id];
plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
total_data_rate);
- ddb->plane[pipe][plane].start = start;
- ddb->plane[pipe][plane].end = start + plane_blocks;
+ ddb->plane[pipe][id].start = start;
+ ddb->plane[pipe][id].end = start + plane_blocks;
start += plane_blocks;
/*
* allocation for y_plane part of planar format:
*/
- if (p->y_bytes_per_pixel) {
- y_data_rate = skl_plane_relative_data_rate(p, 1);
- y_plane_blocks = y_minimum[plane];
+ if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
+ y_data_rate = skl_plane_relative_data_rate(cstate,
+ pstate,
+ 1);
+ y_plane_blocks = y_minimum[id];
y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
total_data_rate);
- ddb->y_plane[pipe][plane].start = start;
- ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
+ ddb->y_plane[pipe][id].start = start;
+ ddb->y_plane[pipe][id].end = start + y_plane_blocks;
start += y_plane_blocks;
}
@@ -3146,73 +3184,16 @@ static void skl_compute_wm_global_parameters(struct drm_device *dev,
}
}
-static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
- struct skl_pipe_wm_parameters *p)
-{
- struct drm_device *dev = crtc->dev;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
- struct drm_plane *plane;
- struct drm_framebuffer *fb;
- int i = 1; /* Index for sprite planes start */
-
- p->active = intel_crtc->active;
- if (p->active) {
- p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
- p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
-
- fb = crtc->primary->state->fb;
- /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
- if (fb) {
- p->plane[0].enabled = true;
- p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
- drm_format_plane_cpp(fb->pixel_format, 1) :
- drm_format_plane_cpp(fb->pixel_format, 0);
- p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
- drm_format_plane_cpp(fb->pixel_format, 0) : 0;
- p->plane[0].tiling = fb->modifier[0];
- } else {
- p->plane[0].enabled = false;
- p->plane[0].bytes_per_pixel = 0;
- p->plane[0].y_bytes_per_pixel = 0;
- p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
- }
- p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
- p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
- p->plane[0].rotation = crtc->primary->state->rotation;
-
- fb = crtc->cursor->state->fb;
- p->plane[PLANE_CURSOR].y_bytes_per_pixel = 0;
- if (fb) {
- p->plane[PLANE_CURSOR].enabled = true;
- p->plane[PLANE_CURSOR].bytes_per_pixel = fb->bits_per_pixel / 8;
- p->plane[PLANE_CURSOR].horiz_pixels = crtc->cursor->state->crtc_w;
- p->plane[PLANE_CURSOR].vert_pixels = crtc->cursor->state->crtc_h;
- } else {
- p->plane[PLANE_CURSOR].enabled = false;
- p->plane[PLANE_CURSOR].bytes_per_pixel = 0;
- p->plane[PLANE_CURSOR].horiz_pixels = 64;
- p->plane[PLANE_CURSOR].vert_pixels = 64;
- }
- }
-
- list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
- struct intel_plane *intel_plane = to_intel_plane(plane);
-
- if (intel_plane->pipe == pipe &&
- plane->type == DRM_PLANE_TYPE_OVERLAY)
- p->plane[i++] = intel_plane->wm;
- }
-}
-
static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
- struct skl_pipe_wm_parameters *p,
- struct intel_plane_wm_parameters *p_params,
+ struct intel_crtc_state *cstate,
+ struct intel_plane *intel_plane,
uint16_t ddb_allocation,
int level,
uint16_t *out_blocks, /* out */
uint8_t *out_lines /* out */)
{
+ struct drm_plane *plane = &intel_plane->base;
+ struct drm_framebuffer *fb = plane->state->fb;
uint32_t latency = dev_priv->wm.skl_latency[level];
uint32_t method1, method2;
uint32_t plane_bytes_per_line, plane_blocks_per_line;
@@ -3220,31 +3201,35 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
uint32_t selected_result;
uint8_t bytes_per_pixel;
- if (latency == 0 || !p->active || !p_params->enabled)
+ if (latency == 0 || !cstate->base.active || !fb)
return false;
- bytes_per_pixel = p_params->y_bytes_per_pixel ?
- p_params->y_bytes_per_pixel :
- p_params->bytes_per_pixel;
- method1 = skl_wm_method1(p->pixel_rate,
+ bytes_per_pixel = (fb->pixel_format == DRM_FORMAT_NV12) ?
+ drm_format_plane_cpp(DRM_FORMAT_NV12, 0) :
+ drm_format_plane_cpp(DRM_FORMAT_NV12, 1);
+ method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
bytes_per_pixel,
latency);
- method2 = skl_wm_method2(p->pixel_rate,
- p->pipe_htotal,
- p_params->horiz_pixels,
+ method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
+ cstate->base.adjusted_mode.crtc_htotal,
+ cstate->pipe_src_w,
bytes_per_pixel,
- p_params->tiling,
+ fb->modifier[0],
latency);
- plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
+ plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel;
plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
- if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
- p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
+ if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
+ fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
uint32_t min_scanlines = 4;
uint32_t y_tile_minimum;
- if (intel_rotation_90_or_270(p_params->rotation)) {
- switch (p_params->bytes_per_pixel) {
+ if (intel_rotation_90_or_270(plane->state->rotation)) {
+ int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
+ drm_format_plane_cpp(fb->pixel_format, 1) :
+ drm_format_plane_cpp(fb->pixel_format, 0);
+
+ switch (bpp) {
case 1:
min_scanlines = 16;
break;
@@ -3268,8 +3253,8 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
if (level >= 1 && level <= 7) {
- if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
- p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
+ if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
+ fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
res_lines += 4;
else
res_blocks++;
@@ -3286,84 +3271,80 @@ static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
struct skl_ddb_allocation *ddb,
- struct skl_pipe_wm_parameters *p,
- enum pipe pipe,
+ struct intel_crtc_state *cstate,
int level,
- int num_planes,
struct skl_wm_level *result)
{
+ struct drm_device *dev = dev_priv->dev;
+ struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
+ struct intel_plane *intel_plane;
uint16_t ddb_blocks;
- int i;
+ enum pipe pipe = intel_crtc->pipe;
+
+ for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
+ int i = skl_wm_plane_id(intel_plane);
- for (i = 0; i < num_planes; i++) {
ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
result->plane_en[i] = skl_compute_plane_wm(dev_priv,
- p, &p->plane[i],
+ cstate,
+ intel_plane,
ddb_blocks,
level,
&result->plane_res_b[i],
&result->plane_res_l[i]);
}
-
- ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][PLANE_CURSOR]);
- result->plane_en[PLANE_CURSOR] = skl_compute_plane_wm(dev_priv, p,
- &p->plane[PLANE_CURSOR],
- ddb_blocks, level,
- &result->plane_res_b[PLANE_CURSOR],
- &result->plane_res_l[PLANE_CURSOR]);
}
static uint32_t
-skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
+skl_compute_linetime_wm(struct intel_crtc_state *cstate)
{
- if (!to_intel_crtc(crtc)->active)
+ if (!cstate->base.active)
return 0;
- if (WARN_ON(p->pixel_rate == 0))
+ if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
return 0;
- return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
+ return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
+ skl_pipe_pixel_rate(cstate));
}
-static void skl_compute_transition_wm(struct drm_crtc *crtc,
- struct skl_pipe_wm_parameters *params,
+static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
struct skl_wm_level *trans_wm /* out */)
{
+ struct drm_crtc *crtc = cstate->base.crtc;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- int i;
+ struct intel_plane *intel_plane;
- if (!params->active)
+ if (!cstate->base.active)
return;
/* Until we know more, just disable transition WMs */
- for (i = 0; i < intel_num_planes(intel_crtc); i++)
+ for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
+ int i = skl_wm_plane_id(intel_plane);
+
trans_wm->plane_en[i] = false;
- trans_wm->plane_en[PLANE_CURSOR] = false;
+ }
}
-static void skl_compute_pipe_wm(struct drm_crtc *crtc,
+static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
struct skl_ddb_allocation *ddb,
- struct skl_pipe_wm_parameters *params,
struct skl_pipe_wm *pipe_wm)
{
- struct drm_device *dev = crtc->dev;
+ struct drm_device *dev = cstate->base.crtc->dev;
const struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int level, max_level = ilk_wm_max_level(dev);
for (level = 0; level <= max_level; level++) {
- skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
- level, intel_num_planes(intel_crtc),
- &pipe_wm->wm[level]);
+ skl_compute_wm_level(dev_priv, ddb, cstate,
+ level, &pipe_wm->wm[level]);
}
- pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
+ pipe_wm->linetime = skl_compute_linetime_wm(cstate);
- skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
+ skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
}
static void skl_compute_wm_results(struct drm_device *dev,
- struct skl_pipe_wm_parameters *p,
struct skl_pipe_wm *p_wm,
struct skl_wm_values *r,
struct intel_crtc *intel_crtc)
@@ -3607,16 +3588,15 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
}
static bool skl_update_pipe_wm(struct drm_crtc *crtc,
- struct skl_pipe_wm_parameters *params,
struct intel_wm_config *config,
struct skl_ddb_allocation *ddb, /* out */
struct skl_pipe_wm *pipe_wm /* out */)
{
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
- skl_compute_wm_pipe_parameters(crtc, params);
- skl_allocate_pipe_ddb(crtc, config, params, ddb);
- skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
+ skl_allocate_pipe_ddb(cstate, config, ddb);
+ skl_compute_pipe_wm(cstate, ddb, pipe_wm);
if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
return false;
@@ -3649,7 +3629,6 @@ static void skl_update_other_pipe_wm(struct drm_device *dev,
*/
list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
base.head) {
- struct skl_pipe_wm_parameters params = {};
struct skl_pipe_wm pipe_wm = {};
bool wm_changed;
@@ -3659,8 +3638,7 @@ static void skl_update_other_pipe_wm(struct drm_device *dev,
if (!intel_crtc->active)
continue;
- wm_changed = skl_update_pipe_wm(&intel_crtc->base,
- ¶ms, config,
+ wm_changed = skl_update_pipe_wm(&intel_crtc->base, config,
&r->ddb, &pipe_wm);
/*
@@ -3670,7 +3648,7 @@ static void skl_update_other_pipe_wm(struct drm_device *dev,
*/
WARN_ON(!wm_changed);
- skl_compute_wm_results(dev, ¶ms, &pipe_wm, r, intel_crtc);
+ skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
r->dirty[intel_crtc->pipe] = true;
}
}
@@ -3700,7 +3678,6 @@ static void skl_update_wm(struct drm_crtc *crtc)
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct skl_pipe_wm_parameters params = {};
struct skl_wm_values *results = &dev_priv->wm.skl_results;
struct skl_pipe_wm pipe_wm = {};
struct intel_wm_config config = {};
@@ -3713,11 +3690,10 @@ static void skl_update_wm(struct drm_crtc *crtc)
skl_compute_wm_global_parameters(dev, &config);
- if (!skl_update_pipe_wm(crtc, ¶ms, &config,
- &results->ddb, &pipe_wm))
+ if (!skl_update_pipe_wm(crtc, &config, &results->ddb, &pipe_wm))
return;
- skl_compute_wm_results(dev, ¶ms, &pipe_wm, results, intel_crtc);
+ skl_compute_wm_results(dev, &pipe_wm, results, intel_crtc);
results->dirty[intel_crtc->pipe] = true;
skl_update_other_pipe_wm(dev, crtc, &config, results);
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 07/15] drm/i915/ivb: Move WaCxSRDisabledForSpriteScaling w/a to atomic check
2015-09-24 22:53 [PATCH 00/15] Atomic watermark updates (v5) Matt Roper
` (5 preceding siblings ...)
2015-09-24 22:53 ` [PATCH 06/15] drm/i915/skl: Eliminate usage of pipe_wm_parameters from SKL-style WM (v3) Matt Roper
@ 2015-09-24 22:53 ` Matt Roper
2015-09-24 22:53 ` [PATCH 08/15] drm/i915: Drop intel_update_sprite_watermarks Matt Roper
` (8 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Matt Roper @ 2015-09-24 22:53 UTC (permalink / raw)
To: intel-gfx
Determine whether we need to apply this workaround at atomic check time
and just set a flag that will be used by the main watermark update
routine.
Moving this workaround into the atomic framework reduces
ilk_update_sprite_wm() to just a standard watermark update, so drop it
completely and just ensure that ilk_update_wm() is called whenever a
sprite plane is updated in a way that would affect watermarks.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/intel_atomic.c | 1 +
drivers/gpu/drm/i915/intel_display.c | 39 +++++++++++++++++++++++++++++-------
drivers/gpu/drm/i915/intel_drv.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 35 +++++++++++---------------------
4 files changed, 48 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index f1975f2..05b1203 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -94,6 +94,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
__drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->base);
crtc_state->update_pipe = false;
+ crtc_state->disable_lp_wm = false;
return &crtc_state->base;
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a3e62bc..7631cb4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11551,18 +11551,32 @@ retry:
static bool intel_wm_need_update(struct drm_plane *plane,
struct drm_plane_state *state)
{
- /* Update watermarks on tiling changes. */
+ struct intel_plane_state *new = to_intel_plane_state(state);
+ struct intel_plane_state *cur = to_intel_plane_state(plane->state);
+
+ /* Update watermarks on tiling or size changes. */
if (!plane->state->fb || !state->fb ||
plane->state->fb->modifier[0] != state->fb->modifier[0] ||
- plane->state->rotation != state->rotation)
- return true;
-
- if (plane->state->crtc_w != state->crtc_w)
+ plane->state->rotation != state->rotation ||
+ drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
+ drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
+ drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
+ drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
return true;
return false;
}
+static bool needs_scaling(struct intel_plane_state *state)
+{
+ int src_w = drm_rect_width(&state->src) >> 16;
+ int src_h = drm_rect_height(&state->src) >> 16;
+ int dst_w = drm_rect_width(&state->dst);
+ int dst_h = drm_rect_height(&state->dst);
+
+ return (src_w != dst_w || src_h != dst_h);
+}
+
int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
struct drm_plane_state *plane_state)
{
@@ -11578,7 +11592,6 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
bool mode_changed = needs_modeset(crtc_state);
bool was_crtc_enabled = crtc->state->active;
bool is_crtc_enabled = crtc_state->active;
-
bool turn_off, turn_on, visible, was_visible;
struct drm_framebuffer *fb = plane_state->fb;
@@ -11696,11 +11709,23 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
case DRM_PLANE_TYPE_CURSOR:
break;
case DRM_PLANE_TYPE_OVERLAY:
- if (turn_off && !mode_changed) {
+ /*
+ * WaCxSRDisabledForSpriteScaling:ivb
+ *
+ * cstate->update_wm was already set above, so this flag will
+ * take effect when we commit and program watermarks.
+ */
+ if (IS_IVYBRIDGE(dev) &&
+ needs_scaling(to_intel_plane_state(plane_state)) &&
+ !needs_scaling(old_plane_state)) {
+ to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
+ } else if (turn_off && !mode_changed) {
intel_crtc->atomic.wait_vblank = true;
intel_crtc->atomic.update_sprite_watermarks |=
1 << i;
}
+
+ break;
}
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c96289d..a2a0301 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -458,6 +458,9 @@ struct intel_crtc_state {
/* w/a for waiting 2 vblanks during crtc enable */
enum pipe hsw_workaround_pipe;
+
+ /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
+ bool disable_lp_wm;
};
struct vlv_wm_state {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7bfcc98..4681f02 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3752,6 +3752,18 @@ static void ilk_update_wm(struct drm_crtc *crtc)
WARN_ON(cstate->base.active != intel_crtc->active);
+ /*
+ * IVB workaround: must disable low power watermarks for at least
+ * one frame before enabling scaling. LP watermarks can be re-enabled
+ * when scaling is disabled.
+ *
+ * WaCxSRDisabledForSpriteScaling:ivb
+ */
+ if (cstate->disable_lp_wm) {
+ ilk_disable_lp_wm(dev);
+ intel_wait_for_vblank(dev, intel_crtc->pipe);
+ }
+
intel_compute_pipe_wm(cstate, &pipe_wm);
if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
@@ -3783,28 +3795,6 @@ static void ilk_update_wm(struct drm_crtc *crtc)
ilk_write_wm_values(dev_priv, &results);
}
-static void
-ilk_update_sprite_wm(struct drm_plane *plane,
- struct drm_crtc *crtc,
- uint32_t sprite_width, uint32_t sprite_height,
- int pixel_size, bool enabled, bool scaled)
-{
- struct drm_device *dev = plane->dev;
- struct intel_plane *intel_plane = to_intel_plane(plane);
-
- /*
- * IVB workaround: must disable low power watermarks for at least
- * one frame before enabling scaling. LP watermarks can be re-enabled
- * when scaling is disabled.
- *
- * WaCxSRDisabledForSpriteScaling:ivb
- */
- if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
- intel_wait_for_vblank(dev, intel_plane->pipe);
-
- ilk_update_wm(crtc);
-}
-
static void skl_pipe_wm_active_state(uint32_t val,
struct skl_pipe_wm *active,
bool is_transwm,
@@ -7145,7 +7135,6 @@ void intel_init_pm(struct drm_device *dev)
(!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
dev_priv->display.update_wm = ilk_update_wm;
- dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
} else {
DRM_DEBUG_KMS("Failed to read display plane latency. "
"Disable CxSR\n");
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 08/15] drm/i915: Drop intel_update_sprite_watermarks
2015-09-24 22:53 [PATCH 00/15] Atomic watermark updates (v5) Matt Roper
` (6 preceding siblings ...)
2015-09-24 22:53 ` [PATCH 07/15] drm/i915/ivb: Move WaCxSRDisabledForSpriteScaling w/a to atomic check Matt Roper
@ 2015-09-24 22:53 ` Matt Roper
2015-09-24 22:53 ` [PATCH 09/15] drm/i915: Refactor ilk_update_wm (v3) Matt Roper
` (7 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Matt Roper @ 2015-09-24 22:53 UTC (permalink / raw)
To: intel-gfx
The only platform that still has an update_sprite_wm entrypoint is SKL;
on SKL, intel_update_sprite_watermarks just updates intel_plane->wm and
then performs a regular watermark update. However intel_plane->wm is
only used to update a couple fields in intel_wm_config, and those fields
are never used by the SKL code, so on SKL an update_sprite_wm is
effectively identical to an update_wm call. Since we're already
ensuring that the regular intel_update_wm is called any time we'd try to
call intel_update_sprite_watermarks, the whole call is redundant and can
be dropped.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 4 ---
drivers/gpu/drm/i915/intel_display.c | 5 ----
drivers/gpu/drm/i915/intel_drv.h | 6 ----
drivers/gpu/drm/i915/intel_pm.c | 58 ------------------------------------
drivers/gpu/drm/i915/intel_sprite.c | 15 ----------
5 files changed, 88 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bd542cb..2baa308 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -628,10 +628,6 @@ struct drm_i915_display_funcs {
struct dpll *match_clock,
struct dpll *best_clock);
void (*update_wm)(struct drm_crtc *crtc);
- void (*update_sprite_wm)(struct drm_plane *plane,
- struct drm_crtc *crtc,
- uint32_t sprite_width, uint32_t sprite_height,
- int pixel_size, bool enable, bool scaled);
int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
/* Returns the active state of the crtc, and if the crtc is active,
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7631cb4..a8d781a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4757,7 +4757,6 @@ static void intel_post_plane_update(struct intel_crtc *crtc)
struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct drm_plane *plane;
if (atomic->wait_vblank)
intel_wait_for_vblank(dev, crtc->pipe);
@@ -4776,10 +4775,6 @@ static void intel_post_plane_update(struct intel_crtc *crtc)
if (atomic->post_enable_primary)
intel_post_enable_primary(&crtc->base);
- drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
- intel_update_sprite_watermarks(plane, &crtc->base,
- 0, 0, 0, false, false);
-
memset(atomic, 0, sizeof(*atomic));
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a2a0301..1b98210 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1390,12 +1390,6 @@ void intel_init_clock_gating(struct drm_device *dev);
void intel_suspend_hw(struct drm_device *dev);
int ilk_wm_max_level(const struct drm_device *dev);
void intel_update_watermarks(struct drm_crtc *crtc);
-void intel_update_sprite_watermarks(struct drm_plane *plane,
- struct drm_crtc *crtc,
- uint32_t sprite_width,
- uint32_t sprite_height,
- int pixel_size,
- bool enabled, bool scaled);
void intel_init_pm(struct drm_device *dev);
void intel_pm_setup(struct drm_device *dev);
void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4681f02..218ee02 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3170,18 +3170,9 @@ static void skl_compute_wm_global_parameters(struct drm_device *dev,
struct intel_wm_config *config)
{
struct drm_crtc *crtc;
- struct drm_plane *plane;
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
config->num_pipes_active += to_intel_crtc(crtc)->active;
-
- /* FIXME: I don't think we need those two global parameters on SKL */
- list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
- struct intel_plane *intel_plane = to_intel_plane(plane);
-
- config->sprites_enabled |= intel_plane->wm.enabled;
- config->sprites_scaled |= intel_plane->wm.scaled;
- }
}
static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
@@ -3704,39 +3695,6 @@ static void skl_update_wm(struct drm_crtc *crtc)
dev_priv->wm.skl_hw = *results;
}
-static void
-skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
- uint32_t sprite_width, uint32_t sprite_height,
- int pixel_size, bool enabled, bool scaled)
-{
- struct intel_plane *intel_plane = to_intel_plane(plane);
- struct drm_framebuffer *fb = plane->state->fb;
-
- intel_plane->wm.enabled = enabled;
- intel_plane->wm.scaled = scaled;
- intel_plane->wm.horiz_pixels = sprite_width;
- intel_plane->wm.vert_pixels = sprite_height;
- intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
-
- /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
- intel_plane->wm.bytes_per_pixel =
- (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
- drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
- intel_plane->wm.y_bytes_per_pixel =
- (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
- drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
-
- /*
- * Framebuffer can be NULL on plane disable, but it does not
- * matter for watermarks if we assume no tiling in that case.
- */
- if (fb)
- intel_plane->wm.tiling = fb->modifier[0];
- intel_plane->wm.rotation = plane->state->rotation;
-
- skl_update_wm(crtc);
-}
-
static void ilk_update_wm(struct drm_crtc *crtc)
{
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
@@ -4172,21 +4130,6 @@ void intel_update_watermarks(struct drm_crtc *crtc)
dev_priv->display.update_wm(crtc);
}
-void intel_update_sprite_watermarks(struct drm_plane *plane,
- struct drm_crtc *crtc,
- uint32_t sprite_width,
- uint32_t sprite_height,
- int pixel_size,
- bool enabled, bool scaled)
-{
- struct drm_i915_private *dev_priv = plane->dev->dev_private;
-
- if (dev_priv->display.update_sprite_wm)
- dev_priv->display.update_sprite_wm(plane, crtc,
- sprite_width, sprite_height,
- pixel_size, enabled, scaled);
-}
-
/**
* Lock protecting IPS related data structures
*/
@@ -7126,7 +7069,6 @@ void intel_init_pm(struct drm_device *dev)
dev_priv->display.init_clock_gating =
skl_init_clock_gating;
dev_priv->display.update_wm = skl_update_wm;
- dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
} else if (HAS_PCH_SPLIT(dev)) {
ilk_setup_wm_latency(dev);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 4349fde..be309a9 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -190,7 +190,6 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
const int pipe = intel_plane->pipe;
const int plane = intel_plane->plane + 1;
u32 plane_ctl, stride_div, stride;
- int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
const struct drm_intel_sprite_colorkey *key =
&to_intel_plane_state(drm_plane->state)->ckey;
unsigned long surf_addr;
@@ -209,10 +208,6 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
rotation = drm_plane->state->rotation;
plane_ctl |= skl_plane_ctl_rotation(rotation);
- intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h,
- pixel_size, true,
- src_w != crtc_w || src_h != crtc_h);
-
stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
fb->pixel_format);
@@ -294,8 +289,6 @@ skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
I915_WRITE(PLANE_SURF(pipe, plane), 0);
POSTING_READ(PLANE_SURF(pipe, plane));
-
- intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
}
static void
@@ -538,10 +531,6 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
sprctl |= SPRITE_PIPE_CSC_ENABLE;
- intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size,
- true,
- src_w != crtc_w || src_h != crtc_h);
-
/* Sizes are 0 based */
src_w--;
src_h--;
@@ -675,10 +664,6 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
if (IS_GEN6(dev))
dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
- intel_update_sprite_watermarks(plane, crtc, src_w, src_h,
- pixel_size, true,
- src_w != crtc_w || src_h != crtc_h);
-
/* Sizes are 0 based */
src_w--;
src_h--;
--
2.1.4
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 09/15] drm/i915: Refactor ilk_update_wm (v3)
2015-09-24 22:53 [PATCH 00/15] Atomic watermark updates (v5) Matt Roper
` (7 preceding siblings ...)
2015-09-24 22:53 ` [PATCH 08/15] drm/i915: Drop intel_update_sprite_watermarks Matt Roper
@ 2015-09-24 22:53 ` Matt Roper
2015-09-24 22:53 ` [PATCH 10/15] drm/i915: Calculate pipe watermarks into CRTC state (v3) Matt Roper
` (6 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Matt Roper @ 2015-09-24 22:53 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Split ilk_update_wm() into two parts; one doing the programming
and the other the calculations.
v2: Fix typo in commit message
v3 (by Matt): Heavily rebased for current codebase.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 64 ++++++++++++++++++++++-------------------
1 file changed, 35 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 218ee02..17f7353 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3695,39 +3695,14 @@ static void skl_update_wm(struct drm_crtc *crtc)
dev_priv->wm.skl_hw = *results;
}
-static void ilk_update_wm(struct drm_crtc *crtc)
+static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
{
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_device *dev = dev_priv->dev;
+ struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
struct ilk_wm_maximums max;
+ struct intel_wm_config config = {};
struct ilk_wm_values results = {};
enum intel_ddb_partitioning partitioning;
- struct intel_pipe_wm pipe_wm = {};
- struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
- struct intel_wm_config config = {};
-
- WARN_ON(cstate->base.active != intel_crtc->active);
-
- /*
- * IVB workaround: must disable low power watermarks for at least
- * one frame before enabling scaling. LP watermarks can be re-enabled
- * when scaling is disabled.
- *
- * WaCxSRDisabledForSpriteScaling:ivb
- */
- if (cstate->disable_lp_wm) {
- ilk_disable_lp_wm(dev);
- intel_wait_for_vblank(dev, intel_crtc->pipe);
- }
-
- intel_compute_pipe_wm(cstate, &pipe_wm);
-
- if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
- return;
-
- intel_crtc->wm.active = pipe_wm;
ilk_compute_wm_config(dev, &config);
@@ -3753,6 +3728,37 @@ static void ilk_update_wm(struct drm_crtc *crtc)
ilk_write_wm_values(dev_priv, &results);
}
+static void ilk_update_wm(struct drm_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
+ struct intel_pipe_wm pipe_wm = {};
+
+ WARN_ON(cstate->base.active != intel_crtc->active);
+
+ /*
+ * IVB workaround: must disable low power watermarks for at least
+ * one frame before enabling scaling. LP watermarks can be re-enabled
+ * when scaling is disabled.
+ *
+ * WaCxSRDisabledForSpriteScaling:ivb
+ */
+ if (cstate->disable_lp_wm) {
+ ilk_disable_lp_wm(crtc->dev);
+ intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
+ }
+
+ intel_compute_pipe_wm(cstate, &pipe_wm);
+
+ if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
+ return;
+
+ intel_crtc->wm.active = pipe_wm;
+
+ ilk_program_watermarks(dev_priv);
+}
+
static void skl_pipe_wm_active_state(uint32_t val,
struct skl_pipe_wm *active,
bool is_transwm,
--
2.1.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 10/15] drm/i915: Calculate pipe watermarks into CRTC state (v3)
2015-09-24 22:53 [PATCH 00/15] Atomic watermark updates (v5) Matt Roper
` (8 preceding siblings ...)
2015-09-24 22:53 ` [PATCH 09/15] drm/i915: Refactor ilk_update_wm (v3) Matt Roper
@ 2015-09-24 22:53 ` Matt Roper
2015-09-24 22:53 ` [PATCH 11/15] drm/i915: Calculate ILK-style watermarks during atomic check (v3) Matt Roper
` (5 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Matt Roper @ 2015-09-24 22:53 UTC (permalink / raw)
To: intel-gfx
A future patch will calculate these during the atomic 'check' phase
rather than at WM programming time, so let's store the watermark
values we're planning to use in the CRTC state; the values actually
active on the hardware remains in intel_crtc.
While we're at it, do some minor restructuring to keep ILK and SKL
values in a union.
v2: Don't move cxsr_allowed to state (Maarten)
v3: Only calculate watermarks in state. Still keep active watermarks in
intel_crtc itself. (Ville)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/intel_drv.h | 48 +++++++++++++++++++++++++---------------
drivers/gpu/drm/i915/intel_pm.c | 44 ++++++++++++++++++++++--------------
2 files changed, 57 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1b98210..598c4b1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -324,6 +324,21 @@ struct intel_crtc_scaler_state {
/* drm_mode->private_flags */
#define I915_MODE_FLAG_INHERITED 1
+struct intel_pipe_wm {
+ struct intel_wm_level wm[5];
+ uint32_t linetime;
+ bool fbc_wm_enabled;
+ bool pipe_enabled;
+ bool sprites_enabled;
+ bool sprites_scaled;
+};
+
+struct skl_pipe_wm {
+ struct skl_wm_level wm[8];
+ struct skl_wm_level trans_wm;
+ uint32_t linetime;
+};
+
struct intel_crtc_state {
struct drm_crtc_state base;
@@ -461,6 +476,17 @@ struct intel_crtc_state {
/* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
bool disable_lp_wm;
+
+ struct {
+ /*
+ * optimal watermarks, programmed post-vblank when this state
+ * is committed
+ */
+ union {
+ struct intel_pipe_wm ilk;
+ struct skl_pipe_wm skl;
+ } optimal;
+ } wm;
};
struct vlv_wm_state {
@@ -472,15 +498,6 @@ struct vlv_wm_state {
bool cxsr;
};
-struct intel_pipe_wm {
- struct intel_wm_level wm[5];
- uint32_t linetime;
- bool fbc_wm_enabled;
- bool pipe_enabled;
- bool sprites_enabled;
- bool sprites_scaled;
-};
-
struct intel_mmio_flip {
struct work_struct work;
struct drm_i915_private *i915;
@@ -488,12 +505,6 @@ struct intel_mmio_flip {
struct intel_crtc *crtc;
};
-struct skl_pipe_wm {
- struct skl_wm_level wm[8];
- struct skl_wm_level trans_wm;
- uint32_t linetime;
-};
-
/*
* Tracking of operations that need to be performed at the beginning/end of an
* atomic commit, outside the atomic section where interrupts are disabled.
@@ -561,9 +572,10 @@ struct intel_crtc {
/* per-pipe watermark state */
struct {
/* watermarks currently being used */
- struct intel_pipe_wm active;
- /* SKL wm values currently in use */
- struct skl_pipe_wm skl_active;
+ union {
+ struct intel_pipe_wm ilk;
+ struct skl_pipe_wm skl;
+ } active;
/* allow CxSR on this pipe */
bool cxsr_allowed;
} wm;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 17f7353..852a115 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2353,7 +2353,7 @@ static void ilk_compute_wm_config(struct drm_device *dev,
/* Compute the currently _active_ config */
for_each_intel_crtc(dev, intel_crtc) {
- const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
+ const struct intel_pipe_wm *wm = &intel_crtc->wm.active.ilk;
if (!wm->pipe_enabled)
continue;
@@ -2450,7 +2450,9 @@ static void ilk_merge_wm_level(struct drm_device *dev,
ret_wm->enable = true;
for_each_intel_crtc(dev, intel_crtc) {
- const struct intel_pipe_wm *active = &intel_crtc->wm.active;
+ const struct intel_crtc_state *cstate =
+ to_intel_crtc_state(intel_crtc->base.state);
+ const struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
const struct intel_wm_level *wm = &active->wm[level];
if (!active->pipe_enabled)
@@ -2598,14 +2600,15 @@ static void ilk_compute_wm_results(struct drm_device *dev,
/* LP0 register values */
for_each_intel_crtc(dev, intel_crtc) {
+ const struct intel_crtc_state *cstate =
+ to_intel_crtc_state(intel_crtc->base.state);
enum pipe pipe = intel_crtc->pipe;
- const struct intel_wm_level *r =
- &intel_crtc->wm.active.wm[0];
+ const struct intel_wm_level *r = &cstate->wm.optimal.ilk.wm[0];
if (WARN_ON(!r->enable))
continue;
- results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
+ results->wm_linetime[pipe] = cstate->wm.optimal.ilk.linetime;
results->wm_pipe[pipe] =
(r->pri_val << WM0_PIPE_PLANE_SHIFT) |
@@ -3589,10 +3592,10 @@ static bool skl_update_pipe_wm(struct drm_crtc *crtc,
skl_allocate_pipe_ddb(cstate, config, ddb);
skl_compute_pipe_wm(cstate, ddb, pipe_wm);
- if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
+ if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
return false;
- intel_crtc->wm.skl_active = *pipe_wm;
+ intel_crtc->wm.active.skl = *pipe_wm;
return true;
}
@@ -3670,7 +3673,8 @@ static void skl_update_wm(struct drm_crtc *crtc)
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct skl_wm_values *results = &dev_priv->wm.skl_results;
- struct skl_pipe_wm pipe_wm = {};
+ struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
+ struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
struct intel_wm_config config = {};
@@ -3681,10 +3685,10 @@ static void skl_update_wm(struct drm_crtc *crtc)
skl_compute_wm_global_parameters(dev, &config);
- if (!skl_update_pipe_wm(crtc, &config, &results->ddb, &pipe_wm))
+ if (!skl_update_pipe_wm(crtc, &config, &results->ddb, pipe_wm))
return;
- skl_compute_wm_results(dev, &pipe_wm, results, intel_crtc);
+ skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
results->dirty[intel_crtc->pipe] = true;
skl_update_other_pipe_wm(dev, crtc, &config, results);
@@ -3733,7 +3737,6 @@ static void ilk_update_wm(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = to_i915(crtc->dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
- struct intel_pipe_wm pipe_wm = {};
WARN_ON(cstate->base.active != intel_crtc->active);
@@ -3749,12 +3752,13 @@ static void ilk_update_wm(struct drm_crtc *crtc)
intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
}
- intel_compute_pipe_wm(cstate, &pipe_wm);
+ intel_compute_pipe_wm(cstate, &cstate->wm.optimal.ilk);
- if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
- return;
+ if (!memcmp(&intel_crtc->wm.active.ilk,
+ &cstate->wm.optimal.ilk,
+ sizeof(cstate->wm.optimal.ilk)));
- intel_crtc->wm.active = pipe_wm;
+ intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
ilk_program_watermarks(dev_priv);
}
@@ -3809,7 +3813,8 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
+ struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
+ struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
enum pipe pipe = intel_crtc->pipe;
int level, i, max_level;
uint32_t temp;
@@ -3853,6 +3858,8 @@ static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
temp = hw->plane_trans[pipe][PLANE_CURSOR];
skl_pipe_wm_active_state(temp, active, true, true, i, 0);
+
+ intel_crtc->wm.active.skl = *active;
}
void skl_wm_get_hw_state(struct drm_device *dev)
@@ -3872,7 +3879,8 @@ static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
struct drm_i915_private *dev_priv = dev->dev_private;
struct ilk_wm_values *hw = &dev_priv->wm.hw;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct intel_pipe_wm *active = &intel_crtc->wm.active;
+ struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
+ struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
enum pipe pipe = intel_crtc->pipe;
static const unsigned int wm0_pipe_reg[] = {
[PIPE_A] = WM0_PIPEA_ILK,
@@ -3911,6 +3919,8 @@ static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
for (level = 0; level <= max_level; level++)
active->wm[level].enable = true;
}
+
+ intel_crtc->wm.active.ilk = *active;
}
#define _FW_WM(value, plane) \
--
2.1.4
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 11/15] drm/i915: Calculate ILK-style watermarks during atomic check (v3)
2015-09-24 22:53 [PATCH 00/15] Atomic watermark updates (v5) Matt Roper
` (9 preceding siblings ...)
2015-09-24 22:53 ` [PATCH 10/15] drm/i915: Calculate pipe watermarks into CRTC state (v3) Matt Roper
@ 2015-09-24 22:53 ` Matt Roper
2015-09-24 22:53 ` [PATCH 12/15] drm/i915: Don't set plane visible during HW readout if CRTC is off Matt Roper
` (4 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Matt Roper @ 2015-09-24 22:53 UTC (permalink / raw)
To: intel-gfx
Calculate pipe watermarks during atomic calculation phase, based on the
contents of the atomic transaction's state structure. We still program
the watermarks at the same time we did before, but the computation now
happens much earlier.
While this patch isn't too exciting by itself, it paves the way for
future patches. The eventual goal (which will be realized in future
patches in this series) is to calculate multiple sets up watermark
values up front, and then program them at different times (pre- vs
post-vblank) on the platforms that need a two-step watermark update.
While we're at it, s/intel_compute_pipe_wm/ilk_compute_pipe_wm/ since
this function only applies to ILK-style watermarks and we have a
completely different function for SKL-style watermarks.
Note that the original code had a memcmp() in ilk_update_wm() to avoid
calling ilk_program_watermarks() if the watermarks hadn't changed. This
memcmp vanishes here, which means we may do some unnecessary result
generation and merging in cases where watermarks didn't change, but the
lower-level function ilk_write_wm_values already makes sure that we
don't actually try to program the watermark registers again.
v2: Squash a few commits from the original series together; no longer
leave pre-calculated wm's in a separate temporary structure since
it's easier to follow the logic if we just cut over to using the
pre-calculated values directly.
v3:
- Pass intel_crtc instead of drm_crtc to .compute_pipe_wm() entrypoint
and use intel_atomic_get_crtc_state() to avoid need for extra
casting. (Ander)
- Drop unused intel_check_crtc() function prototype. (Ander)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_display.c | 6 +++
drivers/gpu/drm/i915/intel_pm.c | 88 ++++++++++++++++++------------------
3 files changed, 51 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2baa308..156bcfe 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -627,6 +627,8 @@ struct drm_i915_display_funcs {
int target, int refclk,
struct dpll *match_clock,
struct dpll *best_clock);
+ int (*compute_pipe_wm)(struct intel_crtc *crtc,
+ struct drm_atomic_state *state);
void (*update_wm)(struct drm_crtc *crtc);
int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a8d781a..edfd3d8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11805,6 +11805,12 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
}
ret = 0;
+ if (dev_priv->display.compute_pipe_wm) {
+ ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
+ if (ret)
+ return ret;
+ }
+
if (INTEL_INFO(dev)->gen >= 9) {
if (mode_changed)
ret = skl_update_scaler_crtc(pipe_config);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 852a115..133a54e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2051,9 +2051,11 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
const struct intel_crtc *intel_crtc,
int level,
struct intel_crtc_state *cstate,
+ struct intel_plane_state *pristate,
+ struct intel_plane_state *sprstate,
+ struct intel_plane_state *curstate,
struct intel_wm_level *result)
{
- struct intel_plane *intel_plane;
uint16_t pri_latency = dev_priv->wm.pri_latency[level];
uint16_t spr_latency = dev_priv->wm.spr_latency[level];
uint16_t cur_latency = dev_priv->wm.cur_latency[level];
@@ -2065,29 +2067,11 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
cur_latency *= 5;
}
- for_each_intel_plane_on_crtc(dev_priv->dev, intel_crtc, intel_plane) {
- struct intel_plane_state *pstate =
- to_intel_plane_state(intel_plane->base.state);
-
- switch (intel_plane->base.type) {
- case DRM_PLANE_TYPE_PRIMARY:
- result->pri_val = ilk_compute_pri_wm(cstate, pstate,
- pri_latency,
- level);
- result->fbc_val = ilk_compute_fbc_wm(cstate, pstate,
- result->pri_val);
- break;
- case DRM_PLANE_TYPE_OVERLAY:
- result->spr_val = ilk_compute_spr_wm(cstate, pstate,
- spr_latency);
- break;
- case DRM_PLANE_TYPE_CURSOR:
- result->cur_val = ilk_compute_cur_wm(cstate, pstate,
- cur_latency);
- break;
- }
- }
-
+ result->pri_val = ilk_compute_pri_wm(cstate, pristate,
+ pri_latency, level);
+ result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
+ result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
+ result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
result->enable = true;
}
@@ -2365,15 +2349,18 @@ static void ilk_compute_wm_config(struct drm_device *dev,
}
/* Compute new watermarks for the pipe */
-static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate,
- struct intel_pipe_wm *pipe_wm)
+static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
+ struct drm_atomic_state *state)
{
- struct drm_crtc *crtc = cstate->base.crtc;
- struct drm_device *dev = crtc->dev;
+ struct intel_pipe_wm *pipe_wm;
+ struct drm_device *dev = intel_crtc->base.dev;
const struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_crtc_state *cstate = NULL;
struct intel_plane *intel_plane;
+ struct drm_plane_state *ps;
+ struct intel_plane_state *pristate = NULL;
struct intel_plane_state *sprstate = NULL;
+ struct intel_plane_state *curstate = NULL;
int level, max_level = ilk_wm_max_level(dev);
/* LP0 watermark maximums depend on this pipe alone */
struct intel_wm_config config = {
@@ -2381,11 +2368,24 @@ static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate,
};
struct ilk_wm_maximums max;
+ cstate = intel_atomic_get_crtc_state(state, intel_crtc);
+ if (IS_ERR(cstate))
+ return PTR_ERR(cstate);
+
+ pipe_wm = &cstate->wm.optimal.ilk;
+
for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
- if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) {
- sprstate = to_intel_plane_state(intel_plane->base.state);
- break;
- }
+ ps = drm_atomic_get_plane_state(state,
+ &intel_plane->base);
+ if (IS_ERR(ps))
+ return PTR_ERR(ps);
+
+ if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
+ pristate = to_intel_plane_state(ps);
+ else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
+ sprstate = to_intel_plane_state(ps);
+ else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
+ curstate = to_intel_plane_state(ps);
}
config.sprites_enabled = sprstate->visible;
@@ -2394,7 +2394,7 @@ static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate,
drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
pipe_wm->pipe_enabled = cstate->base.active;
- pipe_wm->sprites_enabled = sprstate->visible;
+ pipe_wm->sprites_enabled = config.sprites_enabled;
pipe_wm->sprites_scaled = config.sprites_scaled;
/* ILK/SNB: LP2+ watermarks only w/o sprites */
@@ -2405,24 +2405,27 @@ static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate,
if (config.sprites_scaled)
max_level = 0;
- ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]);
+ ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
+ pristate, sprstate, curstate, &pipe_wm->wm[0]);
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
- pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
+ pipe_wm->linetime = hsw_compute_linetime_wm(dev,
+ &intel_crtc->base);
/* LP0 watermarks always use 1/2 DDB partitioning */
ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
/* At least LP0 must be valid */
if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
- return false;
+ return -EINVAL;
ilk_compute_wm_reg_maximums(dev, 1, &max);
for (level = 1; level <= max_level; level++) {
struct intel_wm_level wm = {};
- ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm);
+ ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
+ pristate, sprstate, curstate, &wm);
/*
* Disable any watermark level that exceeds the
@@ -2435,7 +2438,7 @@ static bool intel_compute_pipe_wm(struct intel_crtc_state *cstate,
pipe_wm->wm[level] = wm;
}
- return true;
+ return 0;
}
/*
@@ -3752,12 +3755,6 @@ static void ilk_update_wm(struct drm_crtc *crtc)
intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
}
- intel_compute_pipe_wm(cstate, &cstate->wm.optimal.ilk);
-
- if (!memcmp(&intel_crtc->wm.active.ilk,
- &cstate->wm.optimal.ilk,
- sizeof(cstate->wm.optimal.ilk)));
-
intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
ilk_program_watermarks(dev_priv);
@@ -7093,6 +7090,7 @@ void intel_init_pm(struct drm_device *dev)
(!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
dev_priv->display.update_wm = ilk_update_wm;
+ dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
} else {
DRM_DEBUG_KMS("Failed to read display plane latency. "
"Disable CxSR\n");
--
2.1.4
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 12/15] drm/i915: Don't set plane visible during HW readout if CRTC is off
2015-09-24 22:53 [PATCH 00/15] Atomic watermark updates (v5) Matt Roper
` (10 preceding siblings ...)
2015-09-24 22:53 ` [PATCH 11/15] drm/i915: Calculate ILK-style watermarks during atomic check (v3) Matt Roper
@ 2015-09-24 22:53 ` Matt Roper
2015-09-24 22:53 ` [PATCH 13/15] drm/i915: Calculate watermark configuration during atomic check (v2) Matt Roper
` (3 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Matt Roper @ 2015-09-24 22:53 UTC (permalink / raw)
To: intel-gfx
We already ensure that pstate->visible = false when crtc->active = false
during runtime programming; make sure we follow the same logic when
reading out initial hardware state.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index edfd3d8..573198c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15146,7 +15146,7 @@ static void readout_plane_state(struct intel_crtc *crtc)
struct intel_plane_state *plane_state =
to_intel_plane_state(crtc->base.primary->state);
- plane_state->visible =
+ plane_state->visible = crtc->active &&
primary_get_hw_state(to_intel_plane(crtc->base.primary));
}
--
2.1.4
_______________________________________________
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 13/15] drm/i915: Calculate watermark configuration during atomic check (v2)
2015-09-24 22:53 [PATCH 00/15] Atomic watermark updates (v5) Matt Roper
` (11 preceding siblings ...)
2015-09-24 22:53 ` [PATCH 12/15] drm/i915: Don't set plane visible during HW readout if CRTC is off Matt Roper
@ 2015-09-24 22:53 ` Matt Roper
2015-09-24 22:53 ` [PATCH 14/15] drm/i915: Sanitize watermarks after hardware state readout Matt Roper
` (2 subsequent siblings)
15 siblings, 0 replies; 29+ messages in thread
From: Matt Roper @ 2015-09-24 22:53 UTC (permalink / raw)
To: intel-gfx
v2: Don't forget to actually check the cstate->active value when
tallying up the number of active CRTC's. (Ander)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 10 ++++++
drivers/gpu/drm/i915/intel_display.c | 52 +++++++++++++++++++++++++++--
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 64 +++++++-----------------------------
4 files changed, 72 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 156bcfe..8b7c8f9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1702,6 +1702,13 @@ struct i915_execbuffer_params {
struct drm_i915_gem_request *request;
};
+/* used in computing the new watermarks state */
+struct intel_wm_config {
+ unsigned int num_pipes_active;
+ bool sprites_enabled;
+ bool sprites_scaled;
+};
+
struct drm_i915_private {
struct drm_device *dev;
struct kmem_cache *objects;
@@ -1921,6 +1928,9 @@ struct drm_i915_private {
*/
uint16_t skl_latency[8];
+ /* Committed wm config */
+ struct intel_wm_config config;
+
/*
* The skl_wm_values structure is a bit too big for stack
* allocation, so we keep the staging struct where we store
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 573198c..e2a0777 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13016,6 +13016,45 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
return 0;
}
+/*
+ * Handle calculation of various watermark data at the end of the atomic check
+ * phase. The code here should be run after the per-crtc and per-plane 'check'
+ * handlers to ensure that all derived state has been updated.
+ */
+static void calc_watermark_data(struct drm_atomic_state *state)
+{
+ struct drm_device *dev = state->dev;
+ struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *cstate;
+ struct drm_plane *plane;
+ struct drm_plane_state *pstate;
+
+ /*
+ * Calculate watermark configuration details now that derived
+ * plane/crtc state is all properly updated.
+ */
+ drm_for_each_crtc(crtc, dev) {
+ cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
+ crtc->state;
+
+ if (cstate->active)
+ intel_state->wm_config.num_pipes_active++;
+ }
+ drm_for_each_legacy_plane(plane, dev) {
+ pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
+ plane->state;
+
+ if (!to_intel_plane_state(pstate)->visible)
+ continue;
+
+ intel_state->wm_config.sprites_enabled = true;
+ if (pstate->crtc_w != pstate->src_w >> 16 ||
+ pstate->crtc_h != pstate->src_h >> 16)
+ intel_state->wm_config.sprites_scaled = true;
+ }
+}
+
/**
* intel_atomic_check - validate state object
* @dev: drm device
@@ -13024,6 +13063,7 @@ static int intel_modeset_checks(struct drm_atomic_state *state)
static int intel_atomic_check(struct drm_device *dev,
struct drm_atomic_state *state)
{
+ struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
int ret, i;
@@ -13087,10 +13127,15 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
return ret;
} else
- to_intel_atomic_state(state)->cdclk =
- to_i915(state->dev)->cdclk_freq;
+ intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
- return drm_atomic_helper_check_planes(state->dev, state);
+ ret = drm_atomic_helper_check_planes(state->dev, state);
+ if (ret)
+ return ret;
+
+ calc_watermark_data(state);
+
+ return 0;
}
/**
@@ -13130,6 +13175,7 @@ static int intel_atomic_commit(struct drm_device *dev,
return ret;
drm_atomic_helper_swap_state(dev, state);
+ dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
for_each_crtc_in_state(state, crtc, crtc_state, i) {
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 598c4b1..07d5500 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -240,6 +240,7 @@ struct intel_atomic_state {
unsigned int cdclk;
bool dpll_set;
struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
+ struct intel_wm_config wm_config;
};
struct intel_plane_state {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 133a54e..f3652bb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1794,13 +1794,6 @@ struct ilk_wm_maximums {
uint16_t fbc;
};
-/* used in computing the new watermarks state */
-struct intel_wm_config {
- unsigned int num_pipes_active;
- bool sprites_enabled;
- bool sprites_scaled;
-};
-
/*
* For both WM_PIPE and WM_LP.
* mem_value must be in 0.1us units.
@@ -2330,24 +2323,6 @@ static void skl_setup_wm_latency(struct drm_device *dev)
intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
}
-static void ilk_compute_wm_config(struct drm_device *dev,
- struct intel_wm_config *config)
-{
- struct intel_crtc *intel_crtc;
-
- /* Compute the currently _active_ config */
- for_each_intel_crtc(dev, intel_crtc) {
- const struct intel_pipe_wm *wm = &intel_crtc->wm.active.ilk;
-
- if (!wm->pipe_enabled)
- continue;
-
- config->sprites_enabled |= wm->sprites_enabled;
- config->sprites_scaled |= wm->sprites_scaled;
- config->num_pipes_active++;
- }
-}
-
/* Compute new watermarks for the pipe */
static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
struct drm_atomic_state *state)
@@ -2993,11 +2968,12 @@ skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
static void
skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
- const struct intel_wm_config *config,
struct skl_ddb_allocation *ddb /* out */)
{
struct drm_crtc *crtc = cstate->base.crtc;
struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_wm_config *config = &dev_priv->wm.config;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_plane *intel_plane;
enum pipe pipe = intel_crtc->pipe;
@@ -3172,15 +3148,6 @@ static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
return false;
}
-static void skl_compute_wm_global_parameters(struct drm_device *dev,
- struct intel_wm_config *config)
-{
- struct drm_crtc *crtc;
-
- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
- config->num_pipes_active += to_intel_crtc(crtc)->active;
-}
-
static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
struct intel_crtc_state *cstate,
struct intel_plane *intel_plane,
@@ -3585,14 +3552,13 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
}
static bool skl_update_pipe_wm(struct drm_crtc *crtc,
- struct intel_wm_config *config,
struct skl_ddb_allocation *ddb, /* out */
struct skl_pipe_wm *pipe_wm /* out */)
{
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
- skl_allocate_pipe_ddb(cstate, config, ddb);
+ skl_allocate_pipe_ddb(cstate, ddb);
skl_compute_pipe_wm(cstate, ddb, pipe_wm);
if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
@@ -3605,7 +3571,6 @@ static bool skl_update_pipe_wm(struct drm_crtc *crtc,
static void skl_update_other_pipe_wm(struct drm_device *dev,
struct drm_crtc *crtc,
- struct intel_wm_config *config,
struct skl_wm_values *r)
{
struct intel_crtc *intel_crtc;
@@ -3635,7 +3600,7 @@ static void skl_update_other_pipe_wm(struct drm_device *dev,
if (!intel_crtc->active)
continue;
- wm_changed = skl_update_pipe_wm(&intel_crtc->base, config,
+ wm_changed = skl_update_pipe_wm(&intel_crtc->base,
&r->ddb, &pipe_wm);
/*
@@ -3678,7 +3643,6 @@ static void skl_update_wm(struct drm_crtc *crtc)
struct skl_wm_values *results = &dev_priv->wm.skl_results;
struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
- struct intel_wm_config config = {};
/* Clear all dirty flags */
@@ -3686,15 +3650,13 @@ static void skl_update_wm(struct drm_crtc *crtc)
skl_clear_wm(results, intel_crtc->pipe);
- skl_compute_wm_global_parameters(dev, &config);
-
- if (!skl_update_pipe_wm(crtc, &config, &results->ddb, pipe_wm))
+ if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
return;
skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
results->dirty[intel_crtc->pipe] = true;
- skl_update_other_pipe_wm(dev, crtc, &config, results);
+ skl_update_other_pipe_wm(dev, crtc, results);
skl_write_wm_values(dev_priv, results);
skl_flush_wm_values(dev_priv, results);
@@ -3707,20 +3669,18 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
struct drm_device *dev = dev_priv->dev;
struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
struct ilk_wm_maximums max;
- struct intel_wm_config config = {};
+ struct intel_wm_config *config = &dev_priv->wm.config;
struct ilk_wm_values results = {};
enum intel_ddb_partitioning partitioning;
- ilk_compute_wm_config(dev, &config);
-
- ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
- ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
+ ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_1_2, &max);
+ ilk_wm_merge(dev, config, &max, &lp_wm_1_2);
/* 5/6 split only in single pipe config on IVB+ */
if (INTEL_INFO(dev)->gen >= 7 &&
- config.num_pipes_active == 1 && config.sprites_enabled) {
- ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
- ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
+ config->num_pipes_active == 1 && config->sprites_enabled) {
+ ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_5_6, &max);
+ ilk_wm_merge(dev, config, &max, &lp_wm_5_6);
best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
} else {
--
2.1.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 14/15] drm/i915: Sanitize watermarks after hardware state readout
2015-09-24 22:53 [PATCH 00/15] Atomic watermark updates (v5) Matt Roper
` (12 preceding siblings ...)
2015-09-24 22:53 ` [PATCH 13/15] drm/i915: Calculate watermark configuration during atomic check (v2) Matt Roper
@ 2015-09-24 22:53 ` Matt Roper
2015-10-01 13:58 ` Jani Nikula
2015-09-24 22:53 ` [PATCH 15/15] drm/i915: Add two-stage ILK-style watermark programming (v5) Matt Roper
2015-09-30 15:20 ` [PATCH 00/15] Atomic watermark updates (v5) Daniel Vetter
15 siblings, 1 reply; 29+ messages in thread
From: Matt Roper @ 2015-09-24 22:53 UTC (permalink / raw)
To: intel-gfx
Although we can do a good job of reading out hardware state, the
graphics firmware may have programmed the watermarks in a creative way
that doesn't match how i915 would have chosen to program them. We
shouldn't trust the firmware's watermark programming, but should rather
re-calculate how we think WM's should be programmed and then shove those
values into the hardware.
We can do this pretty easily by creating a dummy top-level state,
running it through the check process to calculate all the values, and
then just programming the watermarks for each CRTC.
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
Maarten, does this solve the problem you were seeing on Ironlake? You
indicated that your firmware had sprite watermarks programmed even though
sprites themselves were off and I don't have any kind of system that can
reproduce that setup. I'm hoping this will patch will do the trick.
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_display.c | 51 ++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_pm.c | 14 +++++-----
3 files changed, 60 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8b7c8f9..a9bac1e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -629,6 +629,7 @@ struct drm_i915_display_funcs {
struct dpll *best_clock);
int (*compute_pipe_wm)(struct intel_crtc *crtc,
struct drm_atomic_state *state);
+ void (*program_watermarks)(struct intel_crtc_state *cstate);
void (*update_wm)(struct drm_crtc *crtc);
int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e2a0777..0c3783c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15310,6 +15310,54 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
}
}
+/*
+ * Calculate what we think the watermarks should be for the state we've read
+ * out of the hardware and then immediately program those watermarks so that
+ * we ensure the hardware settings match our internal state.
+ */
+static void sanitize_watermarks(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_atomic_state *state;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *cstate;
+ int ret;
+ int i;
+
+ /* Only supported on platforms that use atomic watermark design */
+ if (!dev_priv->display.program_watermarks)
+ return;
+
+ /*
+ * Calculate what we think WM's should be by creating a dummy state and
+ * running it through the atomic check code.
+ */
+ state = drm_atomic_helper_duplicate_state(dev,
+ dev->mode_config.acquire_ctx);
+ if (WARN_ON(IS_ERR(state)))
+ return;
+
+ ret = intel_atomic_check(dev, state);
+ if (ret) {
+ /*
+ * Just give up and leave watermarks untouched if we get an
+ * error back from 'check'
+ */
+ DRM_DEBUG_KMS("Could not determine valid watermarks for inherited state\n");
+ return;
+ }
+
+ /* Write calculated watermark values back */
+ to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
+ for_each_crtc_in_state(state, crtc, cstate, i) {
+ struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
+
+ dev_priv->display.program_watermarks(cs);
+ }
+
+ drm_atomic_state_free(state);
+}
+
/* Scan out the current hw modeset state,
* and sanitizes it to the current state
*/
@@ -15365,6 +15413,9 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
modeset_put_power_domains(dev_priv, put_domains);
}
intel_display_set_init_power(dev_priv, false);
+
+ /* Make sure hardware watermarks really match the state we read out */
+ sanitize_watermarks(dev);
}
void intel_display_resume(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f3652bb..988893e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3664,15 +3664,19 @@ static void skl_update_wm(struct drm_crtc *crtc)
dev_priv->wm.skl_hw = *results;
}
-static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
+static void ilk_program_watermarks(struct intel_crtc_state *cstate)
{
- struct drm_device *dev = dev_priv->dev;
+ struct drm_crtc *crtc = cstate->base.crtc;
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
struct ilk_wm_maximums max;
struct intel_wm_config *config = &dev_priv->wm.config;
struct ilk_wm_values results = {};
enum intel_ddb_partitioning partitioning;
+ to_intel_crtc(crtc)->wm.active.ilk = cstate->wm.optimal.ilk;
+
ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_1_2, &max);
ilk_wm_merge(dev, config, &max, &lp_wm_1_2);
@@ -3697,7 +3701,6 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
static void ilk_update_wm(struct drm_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
@@ -3715,9 +3718,7 @@ static void ilk_update_wm(struct drm_crtc *crtc)
intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
}
- intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
-
- ilk_program_watermarks(dev_priv);
+ ilk_program_watermarks(cstate);
}
static void skl_pipe_wm_active_state(uint32_t val,
@@ -7051,6 +7052,7 @@ void intel_init_pm(struct drm_device *dev)
dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
dev_priv->display.update_wm = ilk_update_wm;
dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
+ dev_priv->display.program_watermarks = ilk_program_watermarks;
} else {
DRM_DEBUG_KMS("Failed to read display plane latency. "
"Disable CxSR\n");
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 14/15] drm/i915: Sanitize watermarks after hardware state readout
2015-09-24 22:53 ` [PATCH 14/15] drm/i915: Sanitize watermarks after hardware state readout Matt Roper
@ 2015-10-01 13:58 ` Jani Nikula
2015-10-01 16:12 ` Daniel Vetter
2015-10-01 16:53 ` [PATCH] drm/i915: Convert hsw_compute_linetime_wm to use in-flight state Matt Roper
0 siblings, 2 replies; 29+ messages in thread
From: Jani Nikula @ 2015-10-01 13:58 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: Daniel Vetter
On Fri, 25 Sep 2015, Matt Roper <matthew.d.roper@intel.com> wrote:
> Although we can do a good job of reading out hardware state, the
> graphics firmware may have programmed the watermarks in a creative way
> that doesn't match how i915 would have chosen to program them. We
> shouldn't trust the firmware's watermark programming, but should rather
> re-calculate how we think WM's should be programmed and then shove those
> values into the hardware.
>
> We can do this pretty easily by creating a dummy top-level state,
> running it through the check process to calculate all the values, and
> then just programming the watermarks for each CRTC.
>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Bisect tells me this patch, i.e.
commit c103f2b83dfa3b6fb6b5819ae0362fee6cf4b242
Author: Matt Roper <matthew.d.roper@intel.com>
Date: Thu Sep 24 15:53:19 2015 -0700
drm/i915: Sanitize watermarks after hardware state readout
gives me black screen on a BDW NUC pciid=0x1616.
Daniel, please drop it.
BR,
Jani.
> ---
> Maarten, does this solve the problem you were seeing on Ironlake? You
> indicated that your firmware had sprite watermarks programmed even though
> sprites themselves were off and I don't have any kind of system that can
> reproduce that setup. I'm hoping this will patch will do the trick.
>
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_display.c | 51 ++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_pm.c | 14 +++++-----
> 3 files changed, 60 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 8b7c8f9..a9bac1e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -629,6 +629,7 @@ struct drm_i915_display_funcs {
> struct dpll *best_clock);
> int (*compute_pipe_wm)(struct intel_crtc *crtc,
> struct drm_atomic_state *state);
> + void (*program_watermarks)(struct intel_crtc_state *cstate);
> void (*update_wm)(struct drm_crtc *crtc);
> int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
> void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e2a0777..0c3783c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15310,6 +15310,54 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> }
> }
>
> +/*
> + * Calculate what we think the watermarks should be for the state we've read
> + * out of the hardware and then immediately program those watermarks so that
> + * we ensure the hardware settings match our internal state.
> + */
> +static void sanitize_watermarks(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct drm_atomic_state *state;
> + struct drm_crtc *crtc;
> + struct drm_crtc_state *cstate;
> + int ret;
> + int i;
> +
> + /* Only supported on platforms that use atomic watermark design */
> + if (!dev_priv->display.program_watermarks)
> + return;
> +
> + /*
> + * Calculate what we think WM's should be by creating a dummy state and
> + * running it through the atomic check code.
> + */
> + state = drm_atomic_helper_duplicate_state(dev,
> + dev->mode_config.acquire_ctx);
> + if (WARN_ON(IS_ERR(state)))
> + return;
> +
> + ret = intel_atomic_check(dev, state);
> + if (ret) {
> + /*
> + * Just give up and leave watermarks untouched if we get an
> + * error back from 'check'
> + */
> + DRM_DEBUG_KMS("Could not determine valid watermarks for inherited state\n");
> + return;
> + }
> +
> + /* Write calculated watermark values back */
> + to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
> + for_each_crtc_in_state(state, crtc, cstate, i) {
> + struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
> +
> + dev_priv->display.program_watermarks(cs);
> + }
> +
> + drm_atomic_state_free(state);
> +}
> +
> /* Scan out the current hw modeset state,
> * and sanitizes it to the current state
> */
> @@ -15365,6 +15413,9 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
> modeset_put_power_domains(dev_priv, put_domains);
> }
> intel_display_set_init_power(dev_priv, false);
> +
> + /* Make sure hardware watermarks really match the state we read out */
> + sanitize_watermarks(dev);
> }
>
> void intel_display_resume(struct drm_device *dev)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f3652bb..988893e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3664,15 +3664,19 @@ static void skl_update_wm(struct drm_crtc *crtc)
> dev_priv->wm.skl_hw = *results;
> }
>
> -static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
> +static void ilk_program_watermarks(struct intel_crtc_state *cstate)
> {
> - struct drm_device *dev = dev_priv->dev;
> + struct drm_crtc *crtc = cstate->base.crtc;
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
> struct ilk_wm_maximums max;
> struct intel_wm_config *config = &dev_priv->wm.config;
> struct ilk_wm_values results = {};
> enum intel_ddb_partitioning partitioning;
>
> + to_intel_crtc(crtc)->wm.active.ilk = cstate->wm.optimal.ilk;
> +
> ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_1_2, &max);
> ilk_wm_merge(dev, config, &max, &lp_wm_1_2);
>
> @@ -3697,7 +3701,6 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
>
> static void ilk_update_wm(struct drm_crtc *crtc)
> {
> - struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
>
> @@ -3715,9 +3718,7 @@ static void ilk_update_wm(struct drm_crtc *crtc)
> intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
> }
>
> - intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
> -
> - ilk_program_watermarks(dev_priv);
> + ilk_program_watermarks(cstate);
> }
>
> static void skl_pipe_wm_active_state(uint32_t val,
> @@ -7051,6 +7052,7 @@ void intel_init_pm(struct drm_device *dev)
> dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
> dev_priv->display.update_wm = ilk_update_wm;
> dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
> + dev_priv->display.program_watermarks = ilk_program_watermarks;
> } else {
> DRM_DEBUG_KMS("Failed to read display plane latency. "
> "Disable CxSR\n");
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 14/15] drm/i915: Sanitize watermarks after hardware state readout
2015-10-01 13:58 ` Jani Nikula
@ 2015-10-01 16:12 ` Daniel Vetter
2015-10-01 16:53 ` [PATCH] drm/i915: Convert hsw_compute_linetime_wm to use in-flight state Matt Roper
1 sibling, 0 replies; 29+ messages in thread
From: Daniel Vetter @ 2015-10-01 16:12 UTC (permalink / raw)
To: Jani Nikula; +Cc: Daniel Vetter, intel-gfx
On Thu, Oct 01, 2015 at 04:58:38PM +0300, Jani Nikula wrote:
> On Fri, 25 Sep 2015, Matt Roper <matthew.d.roper@intel.com> wrote:
> > Although we can do a good job of reading out hardware state, the
> > graphics firmware may have programmed the watermarks in a creative way
> > that doesn't match how i915 would have chosen to program them. We
> > shouldn't trust the firmware's watermark programming, but should rather
> > re-calculate how we think WM's should be programmed and then shove those
> > values into the hardware.
> >
> > We can do this pretty easily by creating a dummy top-level state,
> > running it through the check process to calculate all the values, and
> > then just programming the watermarks for each CRTC.
> >
> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>
> Bisect tells me this patch, i.e.
>
> commit c103f2b83dfa3b6fb6b5819ae0362fee6cf4b242
> Author: Matt Roper <matthew.d.roper@intel.com>
> Date: Thu Sep 24 15:53:19 2015 -0700
>
> drm/i915: Sanitize watermarks after hardware state readout
>
> gives me black screen on a BDW NUC pciid=0x1616.
>
> Daniel, please drop it.
Done, plus the next patch due to conflicts. Matt, I'll reapply them as
soon as we have a fix for this boot issue.
-Daniel
>
> BR,
> Jani.
>
>
> > ---
> > Maarten, does this solve the problem you were seeing on Ironlake? You
> > indicated that your firmware had sprite watermarks programmed even though
> > sprites themselves were off and I don't have any kind of system that can
> > reproduce that setup. I'm hoping this will patch will do the trick.
> >
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/intel_display.c | 51 ++++++++++++++++++++++++++++++++++++
> > drivers/gpu/drm/i915/intel_pm.c | 14 +++++-----
> > 3 files changed, 60 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 8b7c8f9..a9bac1e 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -629,6 +629,7 @@ struct drm_i915_display_funcs {
> > struct dpll *best_clock);
> > int (*compute_pipe_wm)(struct intel_crtc *crtc,
> > struct drm_atomic_state *state);
> > + void (*program_watermarks)(struct intel_crtc_state *cstate);
> > void (*update_wm)(struct drm_crtc *crtc);
> > int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
> > void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index e2a0777..0c3783c 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -15310,6 +15310,54 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
> > }
> > }
> >
> > +/*
> > + * Calculate what we think the watermarks should be for the state we've read
> > + * out of the hardware and then immediately program those watermarks so that
> > + * we ensure the hardware settings match our internal state.
> > + */
> > +static void sanitize_watermarks(struct drm_device *dev)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > + struct drm_atomic_state *state;
> > + struct drm_crtc *crtc;
> > + struct drm_crtc_state *cstate;
> > + int ret;
> > + int i;
> > +
> > + /* Only supported on platforms that use atomic watermark design */
> > + if (!dev_priv->display.program_watermarks)
> > + return;
> > +
> > + /*
> > + * Calculate what we think WM's should be by creating a dummy state and
> > + * running it through the atomic check code.
> > + */
> > + state = drm_atomic_helper_duplicate_state(dev,
> > + dev->mode_config.acquire_ctx);
> > + if (WARN_ON(IS_ERR(state)))
> > + return;
> > +
> > + ret = intel_atomic_check(dev, state);
> > + if (ret) {
> > + /*
> > + * Just give up and leave watermarks untouched if we get an
> > + * error back from 'check'
> > + */
> > + DRM_DEBUG_KMS("Could not determine valid watermarks for inherited state\n");
> > + return;
> > + }
> > +
> > + /* Write calculated watermark values back */
> > + to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
> > + for_each_crtc_in_state(state, crtc, cstate, i) {
> > + struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
> > +
> > + dev_priv->display.program_watermarks(cs);
> > + }
> > +
> > + drm_atomic_state_free(state);
> > +}
> > +
> > /* Scan out the current hw modeset state,
> > * and sanitizes it to the current state
> > */
> > @@ -15365,6 +15413,9 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
> > modeset_put_power_domains(dev_priv, put_domains);
> > }
> > intel_display_set_init_power(dev_priv, false);
> > +
> > + /* Make sure hardware watermarks really match the state we read out */
> > + sanitize_watermarks(dev);
> > }
> >
> > void intel_display_resume(struct drm_device *dev)
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index f3652bb..988893e 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3664,15 +3664,19 @@ static void skl_update_wm(struct drm_crtc *crtc)
> > dev_priv->wm.skl_hw = *results;
> > }
> >
> > -static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
> > +static void ilk_program_watermarks(struct intel_crtc_state *cstate)
> > {
> > - struct drm_device *dev = dev_priv->dev;
> > + struct drm_crtc *crtc = cstate->base.crtc;
> > + struct drm_device *dev = crtc->dev;
> > + struct drm_i915_private *dev_priv = to_i915(dev);
> > struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
> > struct ilk_wm_maximums max;
> > struct intel_wm_config *config = &dev_priv->wm.config;
> > struct ilk_wm_values results = {};
> > enum intel_ddb_partitioning partitioning;
> >
> > + to_intel_crtc(crtc)->wm.active.ilk = cstate->wm.optimal.ilk;
> > +
> > ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_1_2, &max);
> > ilk_wm_merge(dev, config, &max, &lp_wm_1_2);
> >
> > @@ -3697,7 +3701,6 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
> >
> > static void ilk_update_wm(struct drm_crtc *crtc)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> > struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
> >
> > @@ -3715,9 +3718,7 @@ static void ilk_update_wm(struct drm_crtc *crtc)
> > intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
> > }
> >
> > - intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
> > -
> > - ilk_program_watermarks(dev_priv);
> > + ilk_program_watermarks(cstate);
> > }
> >
> > static void skl_pipe_wm_active_state(uint32_t val,
> > @@ -7051,6 +7052,7 @@ void intel_init_pm(struct drm_device *dev)
> > dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
> > dev_priv->display.update_wm = ilk_update_wm;
> > dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
> > + dev_priv->display.program_watermarks = ilk_program_watermarks;
> > } else {
> > DRM_DEBUG_KMS("Failed to read display plane latency. "
> > "Disable CxSR\n");
> > --
> > 2.1.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Jani Nikula, Intel Open Source Technology Center
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread* [PATCH] drm/i915: Convert hsw_compute_linetime_wm to use in-flight state
2015-10-01 13:58 ` Jani Nikula
2015-10-01 16:12 ` Daniel Vetter
@ 2015-10-01 16:53 ` Matt Roper
2015-10-06 14:34 ` Jani Nikula
1 sibling, 1 reply; 29+ messages in thread
From: Matt Roper @ 2015-10-01 16:53 UTC (permalink / raw)
To: intel-gfx
When watermark calculation was moved up to the atomic check phase, the
code was updated to calculate based on in-flight atomic state rather
than already-committed state. However the hsw_compute_linetime_wm()
didn't get updated and continued to pull values out of the
currently-committed CRTC state. On platforms that call this function
(HSW/BDW only), this will cause problems when we go to enable the CRTC
since we'll pull the current mode (off) rather than the mode we're
calculating for and wind up with a divide by zero error.
This was an oversight in commit:
commit a28170f3389f4e42db95e595b0d86384a79de696
Author: Matt Roper <matthew.d.roper@intel.com>
Date: Thu Sep 24 15:53:16 2015 -0700
drm/i915: Calculate ILK-style watermarks during atomic check (v3)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 01fe1b0..637c8b5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2047,14 +2047,19 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
}
static uint32_t
-hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
+hsw_compute_linetime_wm(struct drm_device *dev,
+ struct intel_crtc_state *cstate)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
+ const struct drm_display_mode *adjusted_mode =
+ &cstate->base.adjusted_mode;
u32 linetime, ips_linetime;
- if (!intel_crtc->active)
+ if (!cstate->base.active)
+ return 0;
+ if (WARN_ON(adjusted_mode->crtc_clock == 0))
+ return 0;
+ if (WARN_ON(dev_priv->cdclk_freq == 0))
return 0;
/* The WM are computed with base on how long it takes to fill a single
@@ -2362,8 +2367,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
pristate, sprstate, curstate, &pipe_wm->wm[0]);
if (IS_HASWELL(dev) || IS_BROADWELL(dev))
- pipe_wm->linetime = hsw_compute_linetime_wm(dev,
- &intel_crtc->base);
+ pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate);
/* LP0 watermarks always use 1/2 DDB partitioning */
ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH] drm/i915: Convert hsw_compute_linetime_wm to use in-flight state
2015-10-01 16:53 ` [PATCH] drm/i915: Convert hsw_compute_linetime_wm to use in-flight state Matt Roper
@ 2015-10-06 14:34 ` Jani Nikula
0 siblings, 0 replies; 29+ messages in thread
From: Jani Nikula @ 2015-10-06 14:34 UTC (permalink / raw)
To: Matt Roper, intel-gfx
[-- Attachment #1: Type: text/plain, Size: 1212 bytes --]
On Thu, 01 Oct 2015, Matt Roper <matthew.d.roper@intel.com> wrote:
> When watermark calculation was moved up to the atomic check phase, the
> code was updated to calculate based on in-flight atomic state rather
> than already-committed state. However the hsw_compute_linetime_wm()
> didn't get updated and continued to pull values out of the
> currently-committed CRTC state. On platforms that call this function
> (HSW/BDW only), this will cause problems when we go to enable the CRTC
> since we'll pull the current mode (off) rather than the mode we're
> calculating for and wind up with a divide by zero error.
>
> This was an oversight in commit:
>
> commit a28170f3389f4e42db95e595b0d86384a79de696
> Author: Matt Roper <matthew.d.roper@intel.com>
> Date: Thu Sep 24 15:53:16 2015 -0700
>
> drm/i915: Calculate ILK-style watermarks during atomic check (v3)
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Matt, current nightly + "drm/i915: Sanitize watermarks after hardware
state readout" + this still oopses my BDW at boot. dmesg attached.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
[-- Attachment #2: dmesg --]
[-- Type: text/plain, Size: 67658 bytes --]
[ 0.000000] Initializing cgroup subsys cpuset
[ 0.000000] Initializing cgroup subsys cpu
[ 0.000000] Initializing cgroup subsys cpuacct
[ 0.000000] Linux version 4.3.0-rc4-bisect-00536-g400a6b9 (jani@nukke) (gcc version 4.9.2 (Debian 4.9.2-10) ) #86 SMP Wed Oct 7 01:27:22 EEST 2015
[ 0.000000] Command line: BOOT_IMAGE=/boot/vmlinuz-4.3.0-rc4-bisect-00536-g400a6b9 root=UUID=181461f1-6b98-43c3-8984-05f81ca9f77e ro log_buf_len=4M drm.debug=14 quiet
[ 0.000000] x86/fpu: xstate_offset[2]: 0240, xstate_sizes[2]: 0100
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x01: 'x87 floating point registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x02: 'SSE registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x04: 'AVX registers'
[ 0.000000] x86/fpu: Enabled xstate features 0x7, context size is 0x340 bytes, using 'standard' format.
[ 0.000000] x86/fpu: Using 'eager' FPU context switches.
[ 0.000000] e820: BIOS-provided physical RAM map:
[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000057fff] usable
[ 0.000000] BIOS-e820: [mem 0x0000000000058000-0x0000000000058fff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000059000-0x000000000009efff] usable
[ 0.000000] BIOS-e820: [mem 0x000000000009f000-0x000000000009ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x00000000d132efff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000d132f000-0x00000000d1809fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000d180a000-0x00000000d9324fff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000d9325000-0x00000000d9383fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000d9384000-0x00000000d93a6fff] ACPI data
[ 0.000000] BIOS-e820: [mem 0x00000000d93a7000-0x00000000d9cd6fff] ACPI NVS
[ 0.000000] BIOS-e820: [mem 0x00000000d9cd7000-0x00000000d9fa2fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000d9fa3000-0x00000000d9ffefff] type 20
[ 0.000000] BIOS-e820: [mem 0x00000000d9fff000-0x00000000d9ffffff] usable
[ 0.000000] BIOS-e820: [mem 0x00000000db000000-0x00000000df7fffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000f8000000-0x00000000fbffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec00fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fed00000-0x00000000fed03fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fed1c000-0x00000000fed1ffff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved
[ 0.000000] BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved
[ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000021f7fffff] usable
[ 0.000000] NX (Execute Disable) protection: active
[ 0.000000] efi: EFI v2.40 by American Megatrends
[ 0.000000] efi: ACPI=0xd938b000 ACPI 2.0=0xd938b000 SMBIOS=0xf05b0 MPS=0xfd640
[ 0.000000] SMBIOS 2.8 present.
[ 0.000000] DMI: \xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff \xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff/NUC5i3RYB, BIOS RYBDWi35.86A.0130.2014.1203.1639 12/03/2014
[ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
[ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable
[ 0.000000] e820: last_pfn = 0x21f800 max_arch_pfn = 0x400000000
[ 0.000000] MTRR default type: uncachable
[ 0.000000] MTRR fixed ranges enabled:
[ 0.000000] 00000-9FFFF write-back
[ 0.000000] A0000-BFFFF uncachable
[ 0.000000] C0000-FFFFF write-protect
[ 0.000000] MTRR variable ranges enabled:
[ 0.000000] 0 base 0000000000 mask 7F80000000 write-back
[ 0.000000] 1 base 0080000000 mask 7FC0000000 write-back
[ 0.000000] 2 base 00C0000000 mask 7FF0000000 write-back
[ 0.000000] 3 base 00D0000000 mask 7FF8000000 write-back
[ 0.000000] 4 base 00D8000000 mask 7FFE000000 write-back
[ 0.000000] 5 base 0100000000 mask 7F00000000 write-back
[ 0.000000] 6 base 0200000000 mask 7FE0000000 write-back
[ 0.000000] 7 base 021F800000 mask 7FFF800000 uncachable
[ 0.000000] 8 disabled
[ 0.000000] 9 disabled
[ 0.000000] x86/PAT: Configuration [0-7]: WB WC UC- UC WB WC UC- WT
[ 0.000000] e820: update [mem 0xda000000-0xffffffff] usable ==> reserved
[ 0.000000] e820: last_pfn = 0xda000 max_arch_pfn = 0x400000000
[ 0.000000] found SMP MP-table at [mem 0x000fd830-0x000fd83f] mapped at [ffff8800000fd830]
[ 0.000000] Base memory trampoline at [ffff880000097000] 97000 size 24576
[ 0.000000] Using GB pages for direct mapping
[ 0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff]
[ 0.000000] [mem 0x00000000-0x000fffff] page 4k
[ 0.000000] BRK [0x01b25000, 0x01b25fff] PGTABLE
[ 0.000000] BRK [0x01b26000, 0x01b26fff] PGTABLE
[ 0.000000] BRK [0x01b27000, 0x01b27fff] PGTABLE
[ 0.000000] init_memory_mapping: [mem 0x21f600000-0x21f7fffff]
[ 0.000000] [mem 0x21f600000-0x21f7fffff] page 2M
[ 0.000000] BRK [0x01b28000, 0x01b28fff] PGTABLE
[ 0.000000] init_memory_mapping: [mem 0x200000000-0x21f5fffff]
[ 0.000000] [mem 0x200000000-0x21f5fffff] page 2M
[ 0.000000] init_memory_mapping: [mem 0x1e0000000-0x1ffffffff]
[ 0.000000] [mem 0x1e0000000-0x1ffffffff] page 1G
[ 0.000000] init_memory_mapping: [mem 0x00100000-0xd132efff]
[ 0.000000] [mem 0x00100000-0x001fffff] page 4k
[ 0.000000] [mem 0x00200000-0x3fffffff] page 2M
[ 0.000000] [mem 0x40000000-0xbfffffff] page 1G
[ 0.000000] [mem 0xc0000000-0xd11fffff] page 2M
[ 0.000000] [mem 0xd1200000-0xd132efff] page 4k
[ 0.000000] init_memory_mapping: [mem 0xd180a000-0xd9324fff]
[ 0.000000] [mem 0xd180a000-0xd19fffff] page 4k
[ 0.000000] [mem 0xd1a00000-0xd91fffff] page 2M
[ 0.000000] [mem 0xd9200000-0xd9324fff] page 4k
[ 0.000000] BRK [0x01b29000, 0x01b29fff] PGTABLE
[ 0.000000] BRK [0x01b2a000, 0x01b2afff] PGTABLE
[ 0.000000] init_memory_mapping: [mem 0xd9fff000-0xd9ffffff]
[ 0.000000] [mem 0xd9fff000-0xd9ffffff] page 4k
[ 0.000000] init_memory_mapping: [mem 0x100000000-0x1dfffffff]
[ 0.000000] [mem 0x100000000-0x1dfffffff] page 1G
[ 0.000000] log_buf_len: 4194304 bytes
[ 0.000000] early log buf free: 124928(95%)
[ 0.000000] RAMDISK: [mem 0x37704000-0x37b79fff]
[ 0.000000] ACPI: Early table checksum verification disabled
[ 0.000000] ACPI: RSDP 0x00000000D938B000 000024 (v02 INTEL )
[ 0.000000] ACPI: XSDT 0x00000000D938B090 00009C (v01 INTEL NUC5i3RY 00000082 AMI 00010013)
[ 0.000000] ACPI: FACP 0x00000000D939EDA8 00010C (v05 INTEL NUC5i3RY 00000082 AMI 00010013)
[ 0.000000] ACPI: DSDT 0x00000000D938B1B8 013BEA (v02 INTEL NUC5i3RY 00000082 INTL 20120913)
[ 0.000000] ACPI: FACS 0x00000000D9CD5F80 000040
[ 0.000000] ACPI: APIC 0x00000000D939EEB8 000084 (v03 INTEL NUC5i3RY 00000082 AMI 00010013)
[ 0.000000] ACPI: FPDT 0x00000000D939EF40 000044 (v01 INTEL NUC5i3RY 00000082 AMI 00010013)
[ 0.000000] ACPI: FIDT 0x00000000D939EF88 00009C (v01 INTEL NUC5i3RY 00000082 AMI 00010013)
[ 0.000000] ACPI: MCFG 0x00000000D939F028 00003C (v01 INTEL NUC5i3RY 00000082 MSFT 00000097)
[ 0.000000] ACPI: HPET 0x00000000D939F068 000038 (v01 INTEL NUC5i3RY 00000082 AMI. 00000005)
[ 0.000000] ACPI: SSDT 0x00000000D939F0A0 000315 (v01 INTEL NUC5i3RY 00000082 INTL 20120913)
[ 0.000000] ACPI: UEFI 0x00000000D939F3B8 000042 (v01 INTEL NUC5i3RY 00000082 00000000)
[ 0.000000] ACPI: SSDT 0x00000000D939F400 000C7D (v02 INTEL NUC5i3RY 00000082 INTL 20120913)
[ 0.000000] ACPI: ASF! 0x00000000D93A0080 0000A0 (v32 INTEL NUC5i3RY 00000082 TFSM 000F4240)
[ 0.000000] ACPI: SSDT 0x00000000D93A0120 000539 (v02 INTEL NUC5i3RY 00000082 INTL 20120913)
[ 0.000000] ACPI: SSDT 0x00000000D93A0660 000B74 (v02 INTEL NUC5i3RY 00000082 INTL 20120913)
[ 0.000000] ACPI: SSDT 0x00000000D93A11D8 005BEF (v02 INTEL NUC5i3RY 00000082 INTL 20120913)
[ 0.000000] ACPI: DMAR 0x00000000D93A6DC8 0000D4 (v01 INTEL NUC5i3RY 00000082 INTL 00000001)
[ 0.000000] ACPI: BGRT 0x00000000D93A6EA0 000038 (v01 INTEL NUC5i3RY 00000082 AMI 00010013)
[ 0.000000] ACPI: Local APIC address 0xfee00000
[ 0.000000] No NUMA configuration found
[ 0.000000] Faking a node at [mem 0x0000000000000000-0x000000021f7fffff]
[ 0.000000] NODE_DATA(0) allocated [mem 0x21f3f9000-0x21f3fcfff]
[ 0.000000] [ffffea0000000000-ffffea00087fffff] PMD -> [ffff880216a00000-ffff88021e9fffff] on node 0
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x0000000000001000-0x0000000000ffffff]
[ 0.000000] DMA32 [mem 0x0000000001000000-0x00000000ffffffff]
[ 0.000000] Normal [mem 0x0000000100000000-0x000000021f7fffff]
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000000001000-0x0000000000057fff]
[ 0.000000] node 0: [mem 0x0000000000059000-0x000000000009efff]
[ 0.000000] node 0: [mem 0x0000000000100000-0x00000000d132efff]
[ 0.000000] node 0: [mem 0x00000000d180a000-0x00000000d9324fff]
[ 0.000000] node 0: [mem 0x00000000d9fff000-0x00000000d9ffffff]
[ 0.000000] node 0: [mem 0x0000000100000000-0x000000021f7fffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000000001000-0x000000021f7fffff]
[ 0.000000] On node 0 totalpages: 2065896
[ 0.000000] DMA zone: 64 pages used for memmap
[ 0.000000] DMA zone: 25 pages reserved
[ 0.000000] DMA zone: 3997 pages, LIFO batch:0
[ 0.000000] DMA32 zone: 13818 pages used for memmap
[ 0.000000] DMA32 zone: 884299 pages, LIFO batch:31
[ 0.000000] Normal zone: 18400 pages used for memmap
[ 0.000000] Normal zone: 1177600 pages, LIFO batch:31
[ 0.000000] Reserving Intel graphics stolen memory at 0xdb800000-0xdf7fffff
[ 0.000000] ACPI: PM-Timer IO Port: 0x1808
[ 0.000000] ACPI: Local APIC address 0xfee00000
[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] dfl dfl lint[0x0])
[ 0.000000] ACPI: NMI not connected to LINT 1!
[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x02] dfl dfl lint[0x0])
[ 0.000000] ACPI: NMI not connected to LINT 1!
[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x03] dfl dfl lint[0x0])
[ 0.000000] ACPI: NMI not connected to LINT 1!
[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x04] dfl dfl lint[0x0])
[ 0.000000] ACPI: NMI not connected to LINT 1!
[ 0.000000] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-39
[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
[ 0.000000] ACPI: IRQ0 used by override.
[ 0.000000] ACPI: IRQ9 used by override.
[ 0.000000] Using ACPI (MADT) for SMP configuration information
[ 0.000000] ACPI: HPET id: 0x8086a701 base: 0xfed00000
[ 0.000000] smpboot: Allowing 4 CPUs, 0 hotplug CPUs
[ 0.000000] PM: Registered nosave memory: [mem 0x00000000-0x00000fff]
[ 0.000000] PM: Registered nosave memory: [mem 0x00058000-0x00058fff]
[ 0.000000] PM: Registered nosave memory: [mem 0x0009f000-0x0009ffff]
[ 0.000000] PM: Registered nosave memory: [mem 0x000a0000-0x000fffff]
[ 0.000000] PM: Registered nosave memory: [mem 0xd132f000-0xd1809fff]
[ 0.000000] PM: Registered nosave memory: [mem 0xd9325000-0xd9383fff]
[ 0.000000] PM: Registered nosave memory: [mem 0xd9384000-0xd93a6fff]
[ 0.000000] PM: Registered nosave memory: [mem 0xd93a7000-0xd9cd6fff]
[ 0.000000] PM: Registered nosave memory: [mem 0xd9cd7000-0xd9fa2fff]
[ 0.000000] PM: Registered nosave memory: [mem 0xd9fa3000-0xd9ffefff]
[ 0.000000] PM: Registered nosave memory: [mem 0xda000000-0xdaffffff]
[ 0.000000] PM: Registered nosave memory: [mem 0xdb000000-0xdf7fffff]
[ 0.000000] PM: Registered nosave memory: [mem 0xdf800000-0xf7ffffff]
[ 0.000000] PM: Registered nosave memory: [mem 0xf8000000-0xfbffffff]
[ 0.000000] PM: Registered nosave memory: [mem 0xfc000000-0xfebfffff]
[ 0.000000] PM: Registered nosave memory: [mem 0xfec00000-0xfec00fff]
[ 0.000000] PM: Registered nosave memory: [mem 0xfec01000-0xfecfffff]
[ 0.000000] PM: Registered nosave memory: [mem 0xfed00000-0xfed03fff]
[ 0.000000] PM: Registered nosave memory: [mem 0xfed04000-0xfed1bfff]
[ 0.000000] PM: Registered nosave memory: [mem 0xfed1c000-0xfed1ffff]
[ 0.000000] PM: Registered nosave memory: [mem 0xfed20000-0xfedfffff]
[ 0.000000] PM: Registered nosave memory: [mem 0xfee00000-0xfee00fff]
[ 0.000000] PM: Registered nosave memory: [mem 0xfee01000-0xfeffffff]
[ 0.000000] PM: Registered nosave memory: [mem 0xff000000-0xffffffff]
[ 0.000000] e820: [mem 0xdf800000-0xf7ffffff] available for PCI devices
[ 0.000000] Booting paravirtualized kernel on bare hardware
[ 0.000000] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645519600211568 ns
[ 0.000000] setup_percpu: NR_CPUS:512 nr_cpumask_bits:512 nr_cpu_ids:4 nr_node_ids:1
[ 0.000000] PERCPU: Embedded 32 pages/cpu @ffff88021f000000 s93848 r8192 d29032 u524288
[ 0.000000] pcpu-alloc: s93848 r8192 d29032 u524288 alloc=1*2097152
[ 0.000000] pcpu-alloc: [0] 0 1 2 3
[ 0.000000] Built 1 zonelists in Node order, mobility grouping on. Total pages: 2033589
[ 0.000000] Policy zone: Normal
[ 0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-4.3.0-rc4-bisect-00536-g400a6b9 root=UUID=181461f1-6b98-43c3-8984-05f81ca9f77e ro log_buf_len=4M drm.debug=14 quiet
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.000000] Calgary: detecting Calgary via BIOS EBDA area
[ 0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing!
[ 0.000000] Memory: 7968052K/8263584K available (5331K kernel code, 1095K rwdata, 1880K rodata, 1248K init, 844K bss, 295532K reserved, 0K cma-reserved)
[ 0.000000] Hierarchical RCU implementation.
[ 0.000000] Build-time adjustment of leaf fanout to 64.
[ 0.000000] RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=4.
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=4
[ 0.000000] NR_IRQS:33024 nr_irqs:728 16
[ 0.000000] Console: colour dummy device 80x25
[ 0.000000] console [tty0] enabled
[ 0.000000] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 133484882848 ns
[ 0.000000] hpet clockevent registered
[ 0.000000] tsc: Fast TSC calibration using PIT
[ 0.000000] spurious 8259A interrupt: IRQ7.
[ 0.000000] tsc: Detected 2095.147 MHz processor
[ 0.000029] Calibrating delay loop (skipped), value calculated using timer frequency.. 4190.29 BogoMIPS (lpj=8380588)
[ 0.000032] pid_max: default: 32768 minimum: 301
[ 0.000037] ACPI: Core revision 20150818
[ 0.018777] ACPI: 6 ACPI AML tables successfully acquired and loaded
[ 0.019590] Security Framework initialized
[ 0.019592] Yama: becoming mindful.
[ 0.019597] AppArmor: AppArmor disabled by boot time parameter
[ 0.020090] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes)
[ 0.021774] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes)
[ 0.022524] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes)
[ 0.022534] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes)
[ 0.022747] Initializing cgroup subsys io
[ 0.022752] Initializing cgroup subsys memory
[ 0.022761] Initializing cgroup subsys devices
[ 0.022763] Initializing cgroup subsys freezer
[ 0.022765] Initializing cgroup subsys net_cls
[ 0.022767] Initializing cgroup subsys perf_event
[ 0.022769] Initializing cgroup subsys net_prio
[ 0.022793] CPU: Physical Processor ID: 0
[ 0.022794] CPU: Processor Core ID: 0
[ 0.022798] ENERGY_PERF_BIAS: Set to 'normal', was 'performance'
[ 0.022799] ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)
[ 0.023859] mce: CPU supports 7 MCE banks
[ 0.023872] CPU0: Thermal monitoring enabled (TM1)
[ 0.023880] process: using mwait in idle threads
[ 0.023883] Last level iTLB entries: 4KB 64, 2MB 8, 4MB 8
[ 0.023884] Last level dTLB entries: 4KB 64, 2MB 0, 4MB 0, 1GB 4
[ 0.024226] Freeing SMP alternatives memory: 20K (ffffffff81a4b000 - ffffffff81a50000)
[ 0.027753] ftrace: allocating 22871 entries in 90 pages
[ 0.037189] DMAR: Host address width 39
[ 0.037191] DMAR: DRHD base: 0x000000fed90000 flags: 0x0
[ 0.037201] DMAR: dmar0: reg_base_addr fed90000 ver 1:0 cap 1c0000c40660462 ecap 7e1ff0505e
[ 0.037203] DMAR: DRHD base: 0x000000fed91000 flags: 0x1
[ 0.037207] DMAR: dmar1: reg_base_addr fed91000 ver 1:0 cap d2008c20660462 ecap f010da
[ 0.037209] DMAR: RMRR base: 0x000000d9efc000 end: 0x000000d9f0afff
[ 0.037210] DMAR: RMRR base: 0x000000db000000 end: 0x000000df7fffff
[ 0.037211] DMAR: ANDD device: 2 name: \_SB.PCI0.SDHC
[ 0.037214] DMAR-IR: IOAPIC id 2 under DRHD base 0xfed91000 IOMMU 1
[ 0.037215] DMAR-IR: HPET id 0 under DRHD base 0xfed91000
[ 0.037216] DMAR-IR: x2apic is disabled because BIOS sets x2apic opt out bit.
[ 0.037217] DMAR-IR: Use 'intremap=no_x2apic_optout' to override the BIOS setting.
[ 0.037653] DMAR-IR: Enabled IRQ remapping in xapic mode
[ 0.037654] x2apic: IRQ remapping doesn't support X2APIC mode
[ 0.038284] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
[ 0.077994] TSC deadline timer enabled
[ 0.077997] smpboot: CPU0: Intel(R) Core(TM) i3-5010U CPU @ 2.10GHz (family: 0x6, model: 0x3d, stepping: 0x4)
[ 0.078021] Performance Events: PEBS fmt2+, 16-deep LBR, Broadwell events, full-width counters, Intel PMU driver.
[ 0.078041] ... version: 3
[ 0.078042] ... bit width: 48
[ 0.078043] ... generic registers: 4
[ 0.078044] ... value mask: 0000ffffffffffff
[ 0.078045] ... max period: 0000ffffffffffff
[ 0.078045] ... fixed-purpose events: 3
[ 0.078046] ... event mask: 000000070000000f
[ 0.078534] x86: Booting SMP configuration:
[ 0.078535] .... node #0, CPUs: #1
[ 0.082140] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter.
[ 0.082214] #2 #3
[ 0.089502] x86: Booted up 1 node, 4 CPUs
[ 0.089505] smpboot: Total of 4 processors activated (16761.17 BogoMIPS)
[ 0.093277] devtmpfs: initialized
[ 0.095792] PM: Registering ACPI NVS region [mem 0xd93a7000-0xd9cd6fff] (9633792 bytes)
[ 0.096039] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 0.096119] pinctrl core: initialized pinctrl subsystem
[ 0.096261] NET: Registered protocol family 16
[ 0.105120] cpuidle: using governor ladder
[ 0.117115] cpuidle: using governor menu
[ 0.117190] ACPI FADT declares the system doesn't support PCIe ASPM, so disable it
[ 0.117191] ACPI: bus type PCI registered
[ 0.117193] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
[ 0.117249] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xf8000000-0xfbffffff] (base 0xf8000000)
[ 0.117251] PCI: MMCONFIG at [mem 0xf8000000-0xfbffffff] reserved in E820
[ 0.117259] PCI: Using configuration type 1 for base access
[ 0.129433] ACPI: Added _OSI(Module Device)
[ 0.129435] ACPI: Added _OSI(Processor Device)
[ 0.129436] ACPI: Added _OSI(3.0 _SCP Extensions)
[ 0.129437] ACPI: Added _OSI(Processor Aggregator Device)
[ 0.134660] ACPI: Executed 18 blocks of module-level executable AML code
[ 0.139585] ACPI: Dynamic OEM Table Load:
[ 0.139591] ACPI: SSDT 0xFFFF880214CC4C00 0003D3 (v02 PmRef Cpu0Cst 00003001 INTL 20120913)
[ 0.140397] ACPI: Dynamic OEM Table Load:
[ 0.140402] ACPI: SSDT 0xFFFF880214CA6800 0005AA (v02 PmRef ApIst 00003000 INTL 20120913)
[ 0.141282] ACPI: Dynamic OEM Table Load:
[ 0.141285] ACPI: SSDT 0xFFFF880214CCFC00 000119 (v02 PmRef ApCst 00003000 INTL 20120913)
[ 0.142862] ACPI: Interpreter enabled
[ 0.142871] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S1_] (20150818/hwxface-580)
[ 0.142878] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S2_] (20150818/hwxface-580)
[ 0.142894] ACPI: (supports S0 S3 S4 S5)
[ 0.142895] ACPI: Using IOAPIC for interrupt routing
[ 0.142927] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
[ 0.145165] ACPI: Power Resource [PG00] (on)
[ 0.145588] ACPI: Power Resource [PG01] (on)
[ 0.145998] ACPI: Power Resource [PG02] (on)
[ 0.156885] ACPI: Power Resource [FN00] (off)
[ 0.156966] ACPI: Power Resource [FN01] (off)
[ 0.157046] ACPI: Power Resource [FN02] (off)
[ 0.157123] ACPI: Power Resource [FN03] (off)
[ 0.157207] ACPI: Power Resource [FN04] (off)
[ 0.158250] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-3e])
[ 0.158256] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI]
[ 0.158383] \_SB_.PCI0:_OSC invalid UUID
[ 0.158384] _OSC request data:1 1f 0
[ 0.158388] acpi PNP0A08:00: _OSC failed (AE_ERROR); disabling ASPM
[ 0.158888] PCI host bridge to bus 0000:00
[ 0.158891] pci_bus 0000:00: root bus resource [bus 00-3e]
[ 0.158893] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window]
[ 0.158894] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window]
[ 0.158896] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
[ 0.158898] pci_bus 0000:00: root bus resource [mem 0xdf800000-0xfeafffff window]
[ 0.158905] pci 0000:00:00.0: [8086:1604] type 00 class 0x060000
[ 0.159005] pci 0000:00:02.0: [8086:1616] type 00 class 0x030000
[ 0.159020] pci 0000:00:02.0: reg 0x10: [mem 0xf6000000-0xf6ffffff 64bit]
[ 0.159026] pci 0000:00:02.0: reg 0x18: [mem 0xe0000000-0xefffffff 64bit pref]
[ 0.159031] pci 0000:00:02.0: reg 0x20: [io 0xf000-0xf03f]
[ 0.159119] pci 0000:00:03.0: [8086:160c] type 00 class 0x040300
[ 0.159132] pci 0000:00:03.0: reg 0x10: [mem 0xf7134000-0xf7137fff 64bit]
[ 0.159237] pci 0000:00:14.0: [8086:9cb1] type 00 class 0x0c0330
[ 0.159261] pci 0000:00:14.0: reg 0x10: [mem 0xf7120000-0xf712ffff 64bit]
[ 0.159309] pci 0000:00:14.0: PME# supported from D3hot D3cold
[ 0.159365] pci 0000:00:14.0: System wakeup disabled by ACPI
[ 0.159405] pci 0000:00:16.0: [8086:9cba] type 00 class 0x078000
[ 0.159433] pci 0000:00:16.0: reg 0x10: [mem 0xf713d000-0xf713d01f 64bit]
[ 0.159488] pci 0000:00:16.0: PME# supported from D0 D3hot D3cold
[ 0.159595] pci 0000:00:19.0: [8086:15a3] type 00 class 0x020000
[ 0.159617] pci 0000:00:19.0: reg 0x10: [mem 0xf7100000-0xf711ffff]
[ 0.159625] pci 0000:00:19.0: reg 0x14: [mem 0xf713b000-0xf713bfff]
[ 0.159632] pci 0000:00:19.0: reg 0x18: [io 0xf080-0xf09f]
[ 0.159675] pci 0000:00:19.0: PME# supported from D0 D3hot D3cold
[ 0.159730] pci 0000:00:19.0: System wakeup disabled by ACPI
[ 0.159768] pci 0000:00:1b.0: [8086:9ca0] type 00 class 0x040300
[ 0.159789] pci 0000:00:1b.0: reg 0x10: [mem 0xf7130000-0xf7133fff 64bit]
[ 0.159828] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
[ 0.159893] pci 0000:00:1b.0: System wakeup disabled by ACPI
[ 0.159937] pci 0000:00:1c.0: [8086:9c90] type 01 class 0x060400
[ 0.160001] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
[ 0.160084] pci 0000:00:1c.0: System wakeup disabled by ACPI
[ 0.160129] pci 0000:00:1c.3: [8086:9c96] type 01 class 0x060400
[ 0.160198] pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold
[ 0.160280] pci 0000:00:1c.3: System wakeup disabled by ACPI
[ 0.160323] pci 0000:00:1d.0: [8086:9ca6] type 00 class 0x0c0320
[ 0.160350] pci 0000:00:1d.0: reg 0x10: [mem 0xf713a000-0xf713a3ff]
[ 0.160419] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold
[ 0.160476] pci 0000:00:1d.0: System wakeup disabled by ACPI
[ 0.160517] pci 0000:00:1f.0: [8086:9cc3] type 00 class 0x060100
[ 0.160696] pci 0000:00:1f.2: [8086:9c83] type 00 class 0x010601
[ 0.160715] pci 0000:00:1f.2: reg 0x10: [io 0xf0d0-0xf0d7]
[ 0.160722] pci 0000:00:1f.2: reg 0x14: [io 0xf0c0-0xf0c3]
[ 0.160729] pci 0000:00:1f.2: reg 0x18: [io 0xf0b0-0xf0b7]
[ 0.160736] pci 0000:00:1f.2: reg 0x1c: [io 0xf0a0-0xf0a3]
[ 0.160742] pci 0000:00:1f.2: reg 0x20: [io 0xf060-0xf07f]
[ 0.160749] pci 0000:00:1f.2: reg 0x24: [mem 0xf7139000-0xf71397ff]
[ 0.160774] pci 0000:00:1f.2: PME# supported from D3hot
[ 0.160851] pci 0000:00:1f.3: [8086:9ca2] type 00 class 0x0c0500
[ 0.160866] pci 0000:00:1f.3: reg 0x10: [mem 0xf7138000-0xf71380ff 64bit]
[ 0.160885] pci 0000:00:1f.3: reg 0x20: [io 0xf040-0xf05f]
[ 0.161064] acpiphp: Slot [1] registered
[ 0.161076] pci 0000:00:1c.0: PCI bridge to [bus 01]
[ 0.161376] pci 0000:02:00.0: [8086:095a] type 00 class 0x028000
[ 0.161483] pci 0000:02:00.0: reg 0x10: [mem 0xf7000000-0xf7001fff 64bit]
[ 0.161709] pci 0000:02:00.0: PME# supported from D0 D3hot D3cold
[ 0.161818] pci 0000:02:00.0: System wakeup disabled by ACPI
[ 0.169474] pci 0000:00:1c.3: PCI bridge to [bus 02]
[ 0.169480] pci 0000:00:1c.3: bridge window [mem 0xf7000000-0xf70fffff]
[ 0.170367] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 10 *11 12 14 15)
[ 0.170422] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 10 11 12 14 15) *0, disabled.
[ 0.170476] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 *5 6 10 11 12 14 15)
[ 0.170528] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 *5 6 10 11 12 14 15)
[ 0.170581] ACPI: PCI Interrupt Link [LNKE] (IRQs *3 4 5 6 10 11 12 14 15)
[ 0.170633] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 11 12 14 15) *0, disabled.
[ 0.170685] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 *4 5 6 10 11 12 14 15)
[ 0.170737] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 *11 12 14 15)
[ 0.171077] ACPI: Enabled 4 GPEs in block 00 to 7F
[ 0.171178] vgaarb: setting as boot device: PCI:0000:00:02.0
[ 0.171180] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none
[ 0.171182] vgaarb: loaded
[ 0.171184] vgaarb: bridge control possible 0000:00:02.0
[ 0.171287] PCI: Using ACPI for IRQ routing
[ 0.172589] PCI: pci_cache_line_size set to 64 bytes
[ 0.172909] e820: reserve RAM buffer [mem 0x00058000-0x0005ffff]
[ 0.172910] e820: reserve RAM buffer [mem 0x0009f000-0x0009ffff]
[ 0.172911] e820: reserve RAM buffer [mem 0xd132f000-0xd3ffffff]
[ 0.172912] e820: reserve RAM buffer [mem 0xd9325000-0xdbffffff]
[ 0.172914] e820: reserve RAM buffer [mem 0xda000000-0xdbffffff]
[ 0.172915] e820: reserve RAM buffer [mem 0x21f800000-0x21fffffff]
[ 0.173059] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0
[ 0.173064] hpet0: 8 comparators, 64-bit 14.318180 MHz counter
[ 0.175090] clocksource: Switched to clocksource hpet
[ 0.180244] pnp: PnP ACPI init
[ 0.180420] system 00:00: [io 0x0a00-0x0a0f] has been reserved
[ 0.180424] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 0.180669] pnp 00:01: [dma 0 disabled]
[ 0.180701] pnp 00:01: Plug and Play ACPI device, IDs NTN0530 (active)
[ 0.180789] system 00:02: [io 0x0680-0x069f] has been reserved
[ 0.180791] system 00:02: [io 0xffff] has been reserved
[ 0.180793] system 00:02: [io 0xffff] has been reserved
[ 0.180795] system 00:02: [io 0xffff] has been reserved
[ 0.180797] system 00:02: [io 0x1800-0x18fe] could not be reserved
[ 0.180799] system 00:02: [io 0x164e-0x164f] has been reserved
[ 0.180801] system 00:02: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 0.180843] pnp 00:03: Plug and Play ACPI device, IDs PNP0b00 (active)
[ 0.180880] system 00:04: [io 0x1854-0x1857] has been reserved
[ 0.180882] system 00:04: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active)
[ 0.181080] system 00:05: [mem 0xfed1c000-0xfed1ffff] has been reserved
[ 0.181082] system 00:05: [mem 0xfed10000-0xfed17fff] has been reserved
[ 0.181084] system 00:05: [mem 0xfed18000-0xfed18fff] has been reserved
[ 0.181086] system 00:05: [mem 0xfed19000-0xfed19fff] has been reserved
[ 0.181089] system 00:05: [mem 0xf8000000-0xfbffffff] has been reserved
[ 0.181091] system 00:05: [mem 0xfed20000-0xfed3ffff] has been reserved
[ 0.181093] system 00:05: [mem 0xfed90000-0xfed93fff] could not be reserved
[ 0.181095] system 00:05: [mem 0xfed45000-0xfed8ffff] has been reserved
[ 0.181097] system 00:05: [mem 0xff000000-0xffffffff] has been reserved
[ 0.181099] system 00:05: [mem 0xfee00000-0xfeefffff] could not be reserved
[ 0.181102] system 00:05: [mem 0xf7fe0000-0xf7feffff] has been reserved
[ 0.181104] system 00:05: [mem 0xf7ff0000-0xf7ffffff] has been reserved
[ 0.181106] system 00:05: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 0.181693] system 00:06: [mem 0xfe104000-0xfe104fff] has been reserved
[ 0.181695] system 00:06: [mem 0xfe106000-0xfe106fff] has been reserved
[ 0.181697] system 00:06: [mem 0xfe10e000-0xfe10efff] has been reserved
[ 0.181699] system 00:06: [mem 0xfe112000-0xfe112fff] has been reserved
[ 0.181701] system 00:06: [mem 0xfe111000-0xfe111007] has been reserved
[ 0.181703] system 00:06: [mem 0xfe111014-0xfe111fff] has been reserved
[ 0.181706] system 00:06: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 0.182226] pnp: PnP ACPI: found 7 devices
[ 0.188488] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns
[ 0.188517] pci 0000:00:1c.0: PCI bridge to [bus 01]
[ 0.188530] pci 0000:00:1c.3: PCI bridge to [bus 02]
[ 0.188535] pci 0000:00:1c.3: bridge window [mem 0xf7000000-0xf70fffff]
[ 0.188543] pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7 window]
[ 0.188545] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff window]
[ 0.188546] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff window]
[ 0.188548] pci_bus 0000:00: resource 7 [mem 0xdf800000-0xfeafffff window]
[ 0.188550] pci_bus 0000:02: resource 1 [mem 0xf7000000-0xf70fffff]
[ 0.188607] NET: Registered protocol family 2
[ 0.188768] TCP established hash table entries: 65536 (order: 7, 524288 bytes)
[ 0.188906] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
[ 0.189028] TCP: Hash tables configured (established 65536 bind 65536)
[ 0.189053] UDP hash table entries: 4096 (order: 5, 131072 bytes)
[ 0.189080] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes)
[ 0.189155] NET: Registered protocol family 1
[ 0.189171] pci 0000:00:02.0: Video device with shadowed ROM
[ 0.207292] PCI: CLS 64 bytes, default 64
[ 0.207335] Unpacking initramfs...
[ 0.292828] Freeing initrd memory: 4568K (ffff880037704000 - ffff880037b7a000)
[ 0.292850] DMAR: ACPI device "INT3436:00" under DMAR at fed91000 as 00:17.0
[ 0.292859] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
[ 0.292861] software IO TLB [mem 0xc9821000-0xcd821000] (64MB) mapped at [ffff8800c9821000-ffff8800cd820fff]
[ 0.292920] RAPL PMU detected, API unit is 2^-32 Joules, 4 fixed counters 655360 ms ovfl timer
[ 0.292922] hw unit of domain pp0-core 2^-14 Joules
[ 0.292923] hw unit of domain package 2^-14 Joules
[ 0.292924] hw unit of domain dram 2^-14 Joules
[ 0.292924] hw unit of domain pp1-gpu 2^-14 Joules
[ 0.293040] microcode: CPU0 sig=0x306d4, pf=0x40, revision=0x16
[ 0.293049] microcode: CPU1 sig=0x306d4, pf=0x40, revision=0x16
[ 0.293056] microcode: CPU2 sig=0x306d4, pf=0x40, revision=0x16
[ 0.293064] microcode: CPU3 sig=0x306d4, pf=0x40, revision=0x16
[ 0.293115] microcode: Microcode Update Driver: v2.00 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
[ 0.293173] simple-framebuffer simple-framebuffer.0: framebuffer at 0xe0000000, 0x1fa4000 bytes, mapped to 0xffffc90002000000
[ 0.293175] simple-framebuffer simple-framebuffer.0: format=a8r8g8b8, mode=3840x2160x32, linelength=15360
[ 0.310965] Console: switching to colour frame buffer device 480x135
[ 0.328585] simple-framebuffer simple-framebuffer.0: fb0: simplefb registered!
[ 0.328833] futex hash table entries: 1024 (order: 4, 65536 bytes)
[ 0.328866] audit: initializing netlink subsys (disabled)
[ 0.328882] audit: type=2000 audit(1444170630.320:1): initialized
[ 0.329299] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[ 0.329318] zbud: loaded
[ 0.329459] VFS: Disk quotas dquot_6.6.0
[ 0.329478] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[ 0.329905] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252)
[ 0.329935] io scheduler noop registered
[ 0.329938] io scheduler deadline registered
[ 0.329952] io scheduler cfq registered (default)
[ 0.330294] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
[ 0.330301] pciehp: PCI Express Hot Plug Controller Driver version: 0.4
[ 0.330324] intel_idle: MWAIT substates: 0x11142120
[ 0.330325] intel_idle: v0.4 model 0x3D
[ 0.330326] intel_idle: lapic_timer_reliable_states 0xffffffff
[ 0.330592] GHES: HEST is not enabled!
[ 0.330655] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 0.351165] serial8250: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A
[ 0.351618] Linux agpgart interface v0.103
[ 0.351668] AMD IOMMUv2 driver by Joerg Roedel <jroedel@suse.de>
[ 0.351669] AMD IOMMUv2 functionality not available on this system
[ 0.352021] i8042: PNP: No PS/2 controller found. Probing ports directly.
[ 0.355118] serio: i8042 KBD port at 0x60,0x64 irq 1
[ 0.355122] serio: i8042 AUX port at 0x60,0x64 irq 12
[ 0.355239] mousedev: PS/2 mouse device common for all mice
[ 0.355294] rtc_cmos 00:03: RTC can wake from S4
[ 0.355429] rtc_cmos 00:03: rtc core: registered rtc_cmos as rtc0
[ 0.355458] rtc_cmos 00:03: alarms up to one month, y3k, 242 bytes nvram, hpet irqs
[ 0.355470] Intel P-state driver initializing.
[ 0.355601] ledtrig-cpu: registered to indicate activity on CPUs
[ 0.357003] NET: Registered protocol family 10
[ 0.357401] mip6: Mobile IPv6
[ 0.357423] NET: Registered protocol family 17
[ 0.358154] registered taskstats version 1
[ 0.358201] zswap: loaded using pool lzo/zbud
[ 0.359289] console [netcon0] enabled
[ 0.359295] netconsole: network logging started
[ 0.359360] rtc_cmos 00:03: setting system clock to 2015-10-06 22:30:30 UTC (1444170630)
[ 0.359572] PM: Hibernation image not present or could not be loaded.
[ 0.360227] Freeing unused kernel memory: 1248K (ffffffff81913000 - ffffffff81a4b000)
[ 0.360230] Write protecting the kernel read-only data: 8192k
[ 0.360952] Freeing unused kernel memory: 800K (ffff880001538000 - ffff880001600000)
[ 0.361111] Freeing unused kernel memory: 168K (ffff8800017d6000 - ffff880001800000)
[ 0.372213] systemd-udevd[75]: starting version 215
[ 0.372480] random: systemd-udevd urandom read with 5 bits of entropy available
[ 0.382953] sdhci: Secure Digital Host Controller Interface driver
[ 0.382956] sdhci: Copyright(c) Pierre Ossman
[ 0.382991] hidraw: raw HID events driver (C) Jiri Kosina
[ 0.392549] thermal LNXTHERM:00: registered as thermal_zone0
[ 0.392552] ACPI: Thermal Zone [TZ00] (28 C)
[ 0.393143] thermal LNXTHERM:01: registered as thermal_zone1
[ 0.393147] ACPI: Thermal Zone [TZ01] (30 C)
[ 0.394510] ACPI: bus type USB registered
[ 0.394533] usbcore: registered new interface driver usbfs
[ 0.394542] usbcore: registered new interface driver hub
[ 0.394566] usbcore: registered new device driver usb
[ 0.395068] pps_core: LinuxPPS API ver. 1 registered
[ 0.395071] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 0.395428] PTP clock support registered
[ 0.395622] xhci_hcd 0000:00:14.0: xHCI Host Controller
[ 0.395628] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 1
[ 0.395714] xhci_hcd 0000:00:14.0: hcc params 0x200077c1 hci version 0x100 quirks 0x00009810
[ 0.395719] xhci_hcd 0000:00:14.0: cache line size of 64 is not supported
[ 0.395900] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
[ 0.395902] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 0.395904] usb usb1: Product: xHCI Host Controller
[ 0.395905] usb usb1: Manufacturer: Linux 4.3.0-rc4-bisect-00536-g400a6b9 xhci-hcd
[ 0.395906] usb usb1: SerialNumber: 0000:00:14.0
[ 0.396038] hub 1-0:1.0: USB hub found
[ 0.396051] hub 1-0:1.0: 11 ports detected
[ 0.396297] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 0.396514] ehci-pci: EHCI PCI platform driver
[ 0.396527] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
[ 0.396529] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
[ 0.400000] SCSI subsystem initialized
[ 0.401731] xhci_hcd 0000:00:14.0: xHCI Host Controller
[ 0.401739] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 2
[ 0.401789] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
[ 0.401792] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 0.401794] usb usb2: Product: xHCI Host Controller
[ 0.401797] usb usb2: Manufacturer: Linux 4.3.0-rc4-bisect-00536-g400a6b9 xhci-hcd
[ 0.401799] usb usb2: SerialNumber: 0000:00:14.0
[ 0.401928] libata version 3.00 loaded.
[ 0.401964] hub 2-0:1.0: USB hub found
[ 0.401977] hub 2-0:1.0: 4 ports detected
[ 0.404210] ehci-pci 0000:00:1d.0: EHCI Host Controller
[ 0.404218] ehci-pci 0000:00:1d.0: new USB bus registered, assigned bus number 3
[ 0.404233] ehci-pci 0000:00:1d.0: debug port 2
[ 0.408133] ehci-pci 0000:00:1d.0: cache line size of 64 is not supported
[ 0.408393] ehci-pci 0000:00:1d.0: irq 23, io mem 0xf713a000
[ 0.419276] ehci-pci 0000:00:1d.0: USB 2.0 started, EHCI 1.00
[ 0.419333] usb usb3: New USB device found, idVendor=1d6b, idProduct=0002
[ 0.419335] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 0.419337] usb usb3: Product: EHCI Host Controller
[ 0.419339] usb usb3: Manufacturer: Linux 4.3.0-rc4-bisect-00536-g400a6b9 ehci_hcd
[ 0.419340] usb usb3: SerialNumber: 0000:00:1d.0
[ 0.419551] hub 3-0:1.0: USB hub found
[ 0.419557] hub 3-0:1.0: 2 ports detected
[ 0.419888] e1000e 0000:00:19.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode
[ 0.590451] e1000e 0000:00:19.0 eth0: registered PHC clock
[ 0.590454] e1000e 0000:00:19.0 eth0: (PCI Express:2.5GT/s:Width x1) b8:ae:ed:72:2e:00
[ 0.590456] e1000e 0000:00:19.0 eth0: Intel(R) PRO/1000 Network Connection
[ 0.590482] e1000e 0000:00:19.0 eth0: MAC: 11, PHY: 12, PBA No: FFFFFF-0FF
[ 0.590617] ahci 0000:00:1f.2: version 3.0
[ 0.603416] ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 4 ports 6 Gbps 0x1 impl SATA mode
[ 0.603420] ahci 0000:00:1f.2: flags: 64bit ncq pm led clo only pio slum part deso sadm sds apst
[ 0.603963] scsi host0: ahci
[ 0.604087] scsi host1: ahci
[ 0.604245] scsi host2: ahci
[ 0.604350] scsi host3: ahci
[ 0.604412] ata1: SATA max UDMA/133 abar m2048@0xf7139000 port 0xf7139100 irq 44
[ 0.604414] ata2: DUMMY
[ 0.604416] ata3: DUMMY
[ 0.604417] ata4: DUMMY
[ 0.711413] usb 1-1: new low-speed USB device number 2 using xhci_hcd
[ 0.731422] usb 3-1: new high-speed USB device number 2 using ehci-pci
[ 0.845865] usb 1-1: New USB device found, idVendor=04b3, idProduct=3025
[ 0.845868] usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 0.845870] usb 1-1: Product: USB NetVista Full Width Keyboard.
[ 0.845871] usb 1-1: Manufacturer: LITE-ON Technology
[ 0.846030] usb 1-1: ep 0x81 - rounding interval to 128 microframes, ep desc says 192 microframes
[ 0.851404] usbcore: registered new interface driver usbhid
[ 0.851406] usbhid: USB HID core driver
[ 0.851876] input: LITE-ON Technology USB NetVista Full Width Keyboard. as /devices/pci0000:00/0000:00:14.0/usb1/1-1/1-1:1.0/0003:04B3:3025.0001/input/input2
[ 0.863828] usb 3-1: New USB device found, idVendor=8087, idProduct=8001
[ 0.863831] usb 3-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[ 0.864112] hub 3-1:1.0: USB hub found
[ 0.864174] hub 3-1:1.0: 8 ports detected
[ 0.907676] hid-generic 0003:04B3:3025.0001: input,hidraw0: USB HID v1.10 Keyboard [LITE-ON Technology USB NetVista Full Width Keyboard.] on usb-0000:00:14.0-1/input0
[ 0.923535] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 0.926506] ata1.00: ATA-10: INTEL SSDSC2BW240H6, RG20, max UDMA/133
[ 0.926509] ata1.00: 468862128 sectors, multi 16: LBA48 NCQ (depth 31/32), AA
[ 0.939850] ata1.00: configured for UDMA/133
[ 0.940114] scsi 0:0:0:0: Direct-Access ATA INTEL SSDSC2BW24 RG20 PQ: 0 ANSI: 5
[ 0.941859] sd 0:0:0:0: [sda] 468862128 512-byte logical blocks: (240 GB/223 GiB)
[ 0.941950] sd 0:0:0:0: [sda] Write Protect is off
[ 0.941953] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 0.941975] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[ 0.942909] sda: sda1 sda2 sda3
[ 0.943197] sd 0:0:0:0: [sda] Attached SCSI disk
[ 0.943635] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 0.964000] PM: Starting manual resume from disk
[ 0.964005] PM: Hibernation image partition 8:3 present
[ 0.964006] PM: Looking for hibernation image.
[ 0.964159] PM: Image not found (code -22)
[ 0.964161] PM: Hibernation image not present or could not be loaded.
[ 1.000364] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: (null)
[ 1.015552] usb 1-2: new low-speed USB device number 3 using xhci_hcd
[ 1.084367] fuse init (API version 7.23)
[ 1.100774] systemd-udevd[182]: starting version 215
[ 1.158381] input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input3
[ 1.158388] ACPI: Sleep Button [SLPB]
[ 1.158459] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input4
[ 1.158463] ACPI: Power Button [PWRB]
[ 1.158562] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input5
[ 1.158565] ACPI: Power Button [PWRF]
[ 1.172872] nuvoton-cir 00:01: IR PNP Port not valid!
[ 1.173185] nuvoton-cir 00:01: disabled
[ 1.189305] EXT4-fs (sda2): re-mounted. Opts: errors=remount-ro
[ 1.193907] ACPI Warning: SystemIO range 0x000000000000F040-0x000000000000F05F conflicts with OpRegion 0x000000000000F040-0x000000000000F04F (\_SB_.PCI0.SBUS.SMBI) (20150818/utaddress-254)
[ 1.193916] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
[ 1.194322] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
[ 1.194817] EFI Variables Facility v0.08 2004-May-17
[ 1.203273] [drm] Initialized drm 1.1.0 20060810
[ 1.209042] usb 1-2: New USB device found, idVendor=046d, idProduct=c52a
[ 1.209048] usb 1-2: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 1.209051] usb 1-2: Product: 2.4GHz Cordless Desktop
[ 1.209053] usb 1-2: Manufacturer: Logitech
[ 1.209168] usb 1-2: ep 0x81 - rounding interval to 64 microframes, ep desc says 80 microframes
[ 1.209174] usb 1-2: ep 0x82 - rounding interval to 64 microframes, ep desc says 80 microframes
[ 1.210091] input: PC Speaker as /devices/platform/pcspkr/input/input8
[ 1.214270] input: Logitech 2.4GHz Cordless Desktop as /devices/pci0000:00/0000:00:14.0/usb1/1-2/1-2:1.0/0003:046D:C52A.0002/input/input9
[ 1.214295] snd_hda_intel 0000:00:03.0: enabling device (0000 -> 0002)
[ 1.214688] snd_hda_intel 0000:00:1b.0: enabling device (0000 -> 0002)
[ 1.226143] AVX2 version of gcm_enc/dec engaged.
[ 1.226146] AES CTR mode by8 optimization enabled
[ 1.226445] [drm:i915_dump_device_info] i915 device info: gen=8, pciid=0x1616 rev=0x09 flags=is_mobile,need_gfx_hws,has_fbc,has_hotplug,has_llc,has_ddi,has_fpga_dbg,
[ 1.226472] [drm:intel_detect_pch] Found LynxPoint LP PCH
[ 1.226546] [drm] Memory usable by graphics device = 4096M
[ 1.226549] [drm:i915_gem_gtt_init] GMADR size = 256M
[ 1.226551] [drm:i915_gem_gtt_init] GTT stolen size = 64M
[ 1.226553] [drm:i915_gem_gtt_init] ppgtt mode: 2
[ 1.226556] checking generic (e0000000 1fa4000) vs hw (e0000000 10000000)
[ 1.226557] fb: switching to inteldrmfb from simple
[ 1.226615] Console: switching to colour dummy device 80x25
[ 1.226856] [drm] Replacing VGA console driver
[ 1.227177] [drm:intel_opregion_setup] graphic opregion physical addr: 0xd9cd0018
[ 1.227187] [drm:intel_opregion_setup] Public ACPI methods supported
[ 1.227189] [drm:intel_opregion_setup] SWSCI supported
[ 1.227650] snd_hda_codec_realtek hdaudioC1D0: autoconfig for ALC283: line_outs=1 (0x21/0x0/0x0/0x0/0x0) type:hp
[ 1.227655] snd_hda_codec_realtek hdaudioC1D0: speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
[ 1.227658] snd_hda_codec_realtek hdaudioC1D0: hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
[ 1.227660] snd_hda_codec_realtek hdaudioC1D0: mono: mono_out=0x0
[ 1.227662] snd_hda_codec_realtek hdaudioC1D0: inputs:
[ 1.227664] snd_hda_codec_realtek hdaudioC1D0: Mic=0x19
[ 1.234367] [drm:swsci_setup] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00700483
[ 1.234371] [drm:intel_opregion_setup] ASLE supported
[ 1.234634] [drm:intel_device_info_runtime_init] slice total: 1
[ 1.234637] [drm:intel_device_info_runtime_init] subslice total: 3
[ 1.234639] [drm:intel_device_info_runtime_init] subslice per slice: 3
[ 1.234640] [drm:intel_device_info_runtime_init] EU total: 24
[ 1.234642] [drm:intel_device_info_runtime_init] EU per subslice: 8
[ 1.234644] [drm:intel_device_info_runtime_init] has slice power gating: n
[ 1.234646] [drm:intel_device_info_runtime_init] has subslice power gating: n
[ 1.234647] [drm:intel_device_info_runtime_init] has EU power gating: n
[ 1.234649] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[ 1.234651] [drm] Driver supports precise vblank timestamp query.
[ 1.234654] [drm:init_vbt_defaults] Set default to SSC at 120000 kHz
[ 1.234657] [drm:validate_vbt] Using VBT from OpRegion: $VBT HASWELL d
[ 1.234660] [drm:parse_general_features] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 0 fdi_rx_polarity_inverted 0
[ 1.234662] [drm:parse_general_definitions] crt_ddc_bus_pin: 2
[ 1.234665] [drm:parse_lfp_panel_data] DRRS supported mode is static
[ 1.234668] [drm:parse_lfp_panel_data] Found panel mode in BIOS VBT tables:
[ 1.234672] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
[ 1.234674] [drm:parse_lfp_panel_data] VBT initial LVDS value 300
[ 1.234676] [drm:parse_lfp_backlight] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255
[ 1.234679] [drm:parse_sdvo_panel_data] Found SDVO panel mode in BIOS VBT tables:
[ 1.234683] [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x8 0xa
[ 1.234685] [drm:parse_sdvo_device_mapping] No SDVO device info is found in VBT
[ 1.234687] [drm:parse_driver_features] DRRS State Enabled:1
[ 1.234691] [drm:parse_ddi_port] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
[ 1.234693] [drm:parse_ddi_port] VBT HDMI level shift for port A: 0
[ 1.234695] [drm:parse_ddi_port] Port B VBT info: DP:0 HDMI:1 DVI:1 EDP:0 CRT:0
[ 1.234697] [drm:parse_ddi_port] VBT HDMI level shift for port B: 6
[ 1.234699] [drm:parse_ddi_port] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
[ 1.234701] [drm:parse_ddi_port] VBT HDMI level shift for port C: 6
[ 1.234712] [drm:intel_dsm_pci_probe] no _DSM method for intel device
[ 1.234720] [drm:i915_gem_init_stolen] Memory reserved for graphics device: 65536K, usable: 64512K
[ 1.234723] [drm:intel_power_well_enable] enabling always-on
[ 1.234725] [drm:intel_power_well_enable] enabling display
[ 1.234813] [drm:intel_print_wm_latency] Primary WM0 latency 20 (2.0 usec)
[ 1.234815] [drm:intel_print_wm_latency] Primary WM1 latency 50 (25.0 usec)
[ 1.234817] [drm:intel_print_wm_latency] Primary WM2 latency 90 (45.0 usec)
[ 1.234819] [drm:intel_print_wm_latency] Primary WM3 latency 130 (65.0 usec)
[ 1.234822] [drm:intel_print_wm_latency] Primary WM4 latency 160 (80.0 usec)
[ 1.234824] [drm:intel_print_wm_latency] Sprite WM0 latency 20 (2.0 usec)
[ 1.234826] [drm:intel_print_wm_latency] Sprite WM1 latency 50 (25.0 usec)
[ 1.234827] [drm:intel_print_wm_latency] Sprite WM2 latency 90 (45.0 usec)
[ 1.234829] [drm:intel_print_wm_latency] Sprite WM3 latency 130 (65.0 usec)
[ 1.234831] [drm:intel_print_wm_latency] Sprite WM4 latency 160 (80.0 usec)
[ 1.234833] [drm:intel_print_wm_latency] Cursor WM0 latency 20 (2.0 usec)
[ 1.234834] [drm:intel_print_wm_latency] Cursor WM1 latency 50 (25.0 usec)
[ 1.234836] [drm:intel_print_wm_latency] Cursor WM2 latency 90 (45.0 usec)
[ 1.234838] [drm:intel_print_wm_latency] Cursor WM3 latency 130 (65.0 usec)
[ 1.234840] [drm:intel_print_wm_latency] Cursor WM4 latency 160 (80.0 usec)
[ 1.234843] [drm:intel_modeset_init] 3 display pipes available.
[ 1.234863] [drm:intel_update_cdclk] Current CD clock rate: 540000 kHz
[ 1.234865] [drm:intel_update_max_cdclk] Max CD clock rate: 540000 kHz
[ 1.234866] [drm:intel_update_max_cdclk] Max dotclock rate: 540000 kHz
[ 1.234872] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
[ 1.235242] [drm:intel_dp_init_connector] Adding DP connector on port C
[ 1.235278] [drm:intel_dp_aux_init] registering DPDDC-C bus for card0-DP-1
[ 1.241429] [drm:intel_modeset_readout_hw_state] [CRTC:21] hw state readout: enabled
[ 1.241433] [drm:intel_modeset_readout_hw_state] [CRTC:25] hw state readout: disabled
[ 1.241435] [drm:intel_modeset_readout_hw_state] [CRTC:29] hw state readout: disabled
[ 1.241437] [drm:intel_modeset_readout_hw_state] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
[ 1.241439] [drm:intel_modeset_readout_hw_state] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
[ 1.241442] [drm:intel_modeset_readout_hw_state] [ENCODER:31:TMDS-31] hw state readout: disabled, pipe A
[ 1.241447] [drm:intel_modeset_readout_hw_state] [ENCODER:36:TMDS-36] hw state readout: enabled, pipe A
[ 1.241450] [drm:intel_modeset_readout_hw_state] [ENCODER:38:DP MST-38] hw state readout: disabled, pipe A
[ 1.241452] [drm:intel_modeset_readout_hw_state] [ENCODER:39:DP MST-39] hw state readout: disabled, pipe B
[ 1.241454] [drm:intel_modeset_readout_hw_state] [ENCODER:40:DP MST-40] hw state readout: disabled, pipe C
[ 1.241457] [drm:intel_modeset_readout_hw_state] [CONNECTOR:32:HDMI-A-1] hw state readout: disabled
[ 1.241461] [drm:intel_modeset_readout_hw_state] [CONNECTOR:37:DP-1] hw state readout: enabled
[ 1.241464] [drm:intel_modeset_readout_hw_state] [CONNECTOR:41:HDMI-A-2] hw state readout: disabled
[ 1.241482] [drm:intel_dump_pipe_config] [CRTC:21][setup_hw_state] config ffff8802145c5000 for pipe A
[ 1.241484] [drm:intel_dump_pipe_config] cpu_transcoder: A
[ 1.241486] [drm:intel_dump_pipe_config] pipe bpp: 30, dithering: 0
[ 1.241488] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[ 1.241491] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m: 7653148, gmch_n: 8388608, link_m: 510209, link_n: 524288, tu: 64
[ 1.241494] [drm:intel_dump_pipe_config] dp: 1, lanes: 4, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[ 1.241496] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[ 1.241497] [drm:intel_dump_pipe_config] requested mode:
[ 1.241501] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 262749 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9
[ 1.241503] [drm:intel_dump_pipe_config] adjusted mode:
[ 1.241506] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 262749 3840 3888 3920 4000 2160 2163 2168 2191 0x40 0x9
[ 1.241509] [drm:intel_dump_crtc_timings] crtc timings: 262749 3840 3888 3920 4000 2160 2163 2168 2191, type: 0x40 flags: 0x9
[ 1.241511] [drm:intel_dump_pipe_config] port clock: 270000
[ 1.241513] [drm:intel_dump_pipe_config] pipe src size: 3840x2160
[ 1.241515] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
[ 1.241517] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[ 1.241519] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x0f000870, enabled
[ 1.241521] [drm:intel_dump_pipe_config] ips: 0
[ 1.241522] [drm:intel_dump_pipe_config] double wide: 0
[ 1.241524] [drm:intel_dump_pipe_config] ddi_pll_sel: 536870912; dpll_hw_state: wrpll: 0x0
[ 1.241526] [drm:intel_dump_pipe_config] planes on this crtc
[ 1.241528] [drm:intel_dump_pipe_config] STANDARD PLANE:18 plane: 0.0 idx: 0 disabled, scaler_id = 0
[ 1.241531] [drm:intel_dump_pipe_config] CURSOR PLANE:20 plane: 0.1 idx: 1 disabled, scaler_id = 0
[ 1.241533] [drm:intel_dump_pipe_config] STANDARD PLANE:22 plane: 0.1 idx: 2 disabled, scaler_id = 0
[ 1.241537] [drm:intel_dump_pipe_config] [CRTC:25][setup_hw_state] config ffff880213a72000 for pipe B
[ 1.241539] [drm:intel_dump_pipe_config] cpu_transcoder: B
[ 1.241540] [drm:intel_dump_pipe_config] pipe bpp: 0, dithering: 0
[ 1.241543] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[ 1.241545] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[ 1.241547] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[ 1.241549] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[ 1.241550] [drm:intel_dump_pipe_config] requested mode:
[ 1.241553] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
[ 1.241555] [drm:intel_dump_pipe_config] adjusted mode:
[ 1.241558] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
[ 1.241561] [drm:intel_dump_crtc_timings] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
[ 1.241563] [drm:intel_dump_pipe_config] port clock: 0
[ 1.241564] [drm:intel_dump_pipe_config] pipe src size: 0x0
[ 1.241566] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
[ 1.241568] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[ 1.241571] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[ 1.241572] [drm:intel_dump_pipe_config] ips: 0
[ 1.241574] [drm:intel_dump_pipe_config] double wide: 0
[ 1.241576] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: wrpll: 0x0
[ 1.241577] [drm:intel_dump_pipe_config] planes on this crtc
[ 1.241580] [drm:intel_dump_pipe_config] STANDARD PLANE:23 plane: 1.0 idx: 3 disabled, scaler_id = 0
[ 1.241582] [drm:intel_dump_pipe_config] CURSOR PLANE:24 plane: 1.2 idx: 4 disabled, scaler_id = 0
[ 1.241584] [drm:intel_dump_pipe_config] STANDARD PLANE:26 plane: 1.1 idx: 5 disabled, scaler_id = 0
[ 1.241588] [drm:intel_dump_pipe_config] [CRTC:29][setup_hw_state] config ffff880213a6c000 for pipe C
[ 1.241589] [drm:intel_dump_pipe_config] cpu_transcoder: C
[ 1.241591] [drm:intel_dump_pipe_config] pipe bpp: 0, dithering: 0
[ 1.241593] [drm:intel_dump_pipe_config] fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[ 1.241596] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0
[ 1.241598] [drm:intel_dump_pipe_config] dp: 0, lanes: 0, gmch_m2: 0, gmch_n2: 0, link_m2: 0, link_n2: 0, tu2: 0
[ 1.241600] [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
[ 1.241601] [drm:intel_dump_pipe_config] requested mode:
[ 1.241604] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
[ 1.241605] [drm:intel_dump_pipe_config] adjusted mode:
[ 1.241608] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
[ 1.241611] [drm:intel_dump_crtc_timings] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
[ 1.241612] [drm:intel_dump_pipe_config] port clock: 0
[ 1.241614] [drm:intel_dump_pipe_config] pipe src size: 0x0
[ 1.241616] [drm:intel_dump_pipe_config] num_scalers: 0, scaler_users: 0x0, scaler_id: 0
[ 1.241618] [drm:intel_dump_pipe_config] gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000
[ 1.241620] [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
[ 1.241622] [drm:intel_dump_pipe_config] ips: 0
[ 1.241623] [drm:intel_dump_pipe_config] double wide: 0
[ 1.241625] [drm:intel_dump_pipe_config] ddi_pll_sel: 0; dpll_hw_state: wrpll: 0x0
[ 1.241626] [drm:intel_dump_pipe_config] planes on this crtc
[ 1.241628] [drm:intel_dump_pipe_config] STANDARD PLANE:27 plane: 2.0 idx: 6 disabled, scaler_id = 0
[ 1.241630] [drm:intel_dump_pipe_config] CURSOR PLANE:28 plane: 2.3 idx: 7 disabled, scaler_id = 0
[ 1.241632] [drm:intel_dump_pipe_config] STANDARD PLANE:30 plane: 2.1 idx: 8 disabled, scaler_id = 0
[ 1.241671] divide error: 0000 [#1] SMP
[ 1.241677] Modules linked in: snd_hda_codec_realtek(+) aesni_intel(+) snd_hda_codec_generic aes_x86_64 glue_helper i915(+) lrw gf128mul ablk_helper cryptd snd_hda_intel snd_hda_codec i2c_algo_bit snd_hwdep pcspkr snd_hda_core drm_kms_helper mei_me snd_pcm drm snd_timer mei snd psmouse soundcore lpc_ich serio_raw shpchp efivars mfd_core i2c_i801 tpm_tis tpm battery nuvoton_cir rc_core video i2c_designware_platform i2c_designware_core acpi_pad button processor fuse autofs4 ext4 crc16 mbcache jbd2 sg sd_mod hid_generic usbhid ahci libahci libata scsi_mod ehci_pci ehci_hcd e1000e xhci_pci ptp pps_core xhci_hcd usbcore usb_common fan thermal i2c_hid i2c_core sdhci_acpi sdhci hid mmc_core
[ 1.241748] CPU: 3 PID: 251 Comm: modprobe Not tainted 4.3.0-rc4-bisect-00536-g400a6b9 #86
[ 1.241752] Hardware name: \xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff \xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff\xffffffff/NUC5i3RYB, BIOS RYBDWi35.86A.0130.2014.1203.1639 12/03/2014
[ 1.241756] task: ffff8802138343c0 ti: ffff8802145b0000 task.ti: ffff8802145b0000
[ 1.241760] RIP: 0010:[<ffffffffa04e591a>] [<ffffffffa04e591a>] ilk_compute_wm_level.isra.29+0x14a/0x2c0 [i915]
[ 1.241796] RSP: 0018:ffff8802145b36f8 EFLAGS: 00010206
[ 1.241799] RAX: 000000000000007f RBX: ffff880213e73700 RCX: 0000000000000000
[ 1.241802] RDX: 0000000000000000 RSI: 0000000000000080 RDI: 000000000004025d
[ 1.241809] RBP: ffff880213e73400 R08: 000000000f000870 R09: ffff8800d873d280
[ 1.241814] R10: ffff8800d873d340 R11: 0000000000000002 R12: 0000000000000000
[ 1.241820] R13: ffff8800d873d1c0 R14: 0000000000000014 R15: 0000000000000014
[ 1.241825] FS: 00007fd01ed0f700(0000) GS:ffff88021f180000(0000) knlGS:0000000000000000
[ 1.241833] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 1.241838] CR2: 00007fc2fcae9000 CR3: 00000002147e2000 CR4: 00000000003406e0
[ 1.241843] Stack:
[ 1.241847] ffffffff00000014 0000000000000000 ffff8800d873d340 ffff8800d873d280
[ 1.241857] 00000000ffffffff ffff8800d43bd800 ffff880213e73400 ffff880213e73700
[ 1.241867] ffff8800d873d340 ffff8800d8701000 ffff8800d43bdb60 ffffffffa04e6804
[ 1.241876] Call Trace:
[ 1.241910] [<ffffffffa04e6804>] ? ilk_compute_pipe_wm+0x174/0x470 [i915]
[ 1.241920] [<ffffffff810ad04c>] ? mutex_optimistic_spin+0xec/0x1c0
[ 1.241963] [<ffffffffa0546f4c>] ? intel_crtc_atomic_check+0x10c/0x1f0 [i915]
[ 1.241971] [<ffffffffa0441a94>] ? drm_atomic_helper_check_planes+0x134/0x1b0 [drm_kms_helper]
[ 1.242009] [<ffffffffa054a016>] ? intel_atomic_check+0x9a6/0xfd0 [i915]
[ 1.242022] [<ffffffffa03b8dd3>] ? drm_atomic_get_connector_state+0x93/0x110 [drm]
[ 1.242063] [<ffffffffa054e7c3>] ? intel_modeset_setup_hw_state+0x9f3/0xe60 [i915]
[ 1.242077] [<ffffffffa03b7fe7>] ? drm_modeset_lock_all_crtcs+0x87/0xa0 [drm]
[ 1.242118] [<ffffffffa05507bb>] ? intel_modeset_init+0xa4b/0x19b0 [i915]
[ 1.242159] [<ffffffffa0587f22>] ? i915_driver_load+0xe82/0x1640 [i915]
[ 1.242169] [<ffffffffa03a391c>] ? drm_dev_register+0x9c/0xb0 [drm]
[ 1.242176] [<ffffffffa03a5c69>] ? drm_get_pci_dev+0x89/0x1e0 [drm]
[ 1.242184] [<ffffffff812fa34f>] ? local_pci_probe+0x3f/0xa0
[ 1.242190] [<ffffffff812fb738>] ? pci_device_probe+0xd8/0x120
[ 1.242198] [<ffffffff813cc554>] ? driver_probe_device+0x214/0x490
[ 1.242205] [<ffffffff813cc84b>] ? __driver_attach+0x7b/0x80
[ 1.242213] [<ffffffff813cc7d0>] ? driver_probe_device+0x490/0x490
[ 1.242220] [<ffffffff813ca3ca>] ? bus_for_each_dev+0x5a/0x90
[ 1.242227] [<ffffffff813cba95>] ? bus_add_driver+0x1e5/0x280
[ 1.242234] [<ffffffffa05e3000>] ? 0xffffffffa05e3000
[ 1.242241] [<ffffffff813cd137>] ? driver_register+0x57/0xd0
[ 1.242249] [<ffffffff8100213e>] ? do_one_initcall+0xce/0x1f0
[ 1.242257] [<ffffffff81147b60>] ? do_init_module+0x5a/0x1e0
[ 1.242264] [<ffffffff810e48c6>] ? load_module+0x2166/0x2610
[ 1.242268] [<ffffffff810e0b10>] ? __symbol_put+0x30/0x30
[ 1.242273] [<ffffffff810e4f26>] ? SyS_finit_module+0x76/0xa0
[ 1.242278] [<ffffffff8152fbf6>] ? entry_SYSCALL_64_fastpath+0x16/0x75
[ 1.242282] Code: c2 c1 f8 03 31 d2 84 c9 74 26 41 80 bd 80 00 00 00 00 74 1c 41 8b 4d 68 41 2b 4d 60 0f b6 c0 c1 e6 06 31 d2 0f af c8 8d 44 31 ff <f7> f1 8d 50 02 89 53 10 c6 03 01 48 83 c4 28 5b 5d 41 5c 41 5d
[ 1.242316] RIP [<ffffffffa04e591a>] ilk_compute_wm_level.isra.29+0x14a/0x2c0 [i915]
[ 1.242350] RSP <ffff8802145b36f8>
[ 1.242363] ---[ end trace 82dc4436b00d09dc ]---
[ 1.242472] snd_hda_intel 0000:00:03.0: failed to add i915 component master (-19)
[ 1.244231] Adding 8262652k swap on /dev/sda3. Priority:-1 extents:1 across:8262652k SSFS
[ 1.246076] iTCO_vendor_support: vendor-support=0
[ 1.246473] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.11
[ 1.246522] iTCO_wdt: Found a Wildcat Point_LP TCO device (Version=2, TCOBASE=0x1860)
[ 1.246643] iTCO_wdt: initialized. heartbeat=30 sec (nowayout=0)
[ 1.264569] FAT-fs (sda1): utf8 is not a recommended IO charset for FAT filesystems, filesystem will be case sensitive!
[ 1.268017] hid-generic 0003:046D:C52A.0002: input,hidraw1: USB HID v1.11 Keyboard [Logitech 2.4GHz Cordless Desktop] on usb-0000:00:14.0-2/input0
[ 1.272299] input: HDA Digital PCBeep as /devices/pci0000:00/0000:00:1b.0/sound/card1/input10
[ 1.273205] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input11
[ 1.273302] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input12
[ 1.275968] input: Logitech 2.4GHz Cordless Desktop as /devices/pci0000:00/0000:00:14.0/usb1/1-2/1-2:1.1/0003:046D:C52A.0003/input/input13
[ 1.284598] systemd-journald[183]: Received request to flush runtime journal from PID 1
[ 1.291693] tsc: Refined TSC clocksource calibration: 2095.149 MHz
[ 1.291703] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x1e3349f83e9, max_idle_ns: 440795233330 ns
[ 1.327802] intel_rapl: Found RAPL domain package
[ 1.327814] intel_rapl: Found RAPL domain core
[ 1.327821] intel_rapl: Found RAPL domain uncore
[ 1.327827] intel_rapl: Found RAPL domain dram
[ 1.332022] hid-generic 0003:046D:C52A.0003: input,hiddev0,hidraw2: USB HID v1.11 Mouse [Logitech 2.4GHz Cordless Desktop] on usb-0000:00:14.0-2/input1
[ 1.389808] RPC: Registered named UNIX socket transport module.
[ 1.389814] RPC: Registered udp transport module.
[ 1.389817] RPC: Registered tcp transport module.
[ 1.389820] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 1.392181] FS-Cache: Loaded
[ 1.397132] FS-Cache: Netfs 'nfs' registered for caching
[ 1.402597] Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
[ 1.443771] usb 1-7: new full-speed USB device number 4 using xhci_hcd
[ 1.515720] cfg80211: World regulatory domain updated:
[ 1.515730] cfg80211: DFS Master region: unset
[ 1.515733] cfg80211: (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp), (dfs_cac_time)
[ 1.515745] cfg80211: (2402000 KHz - 2472000 KHz @ 40000 KHz), (N/A, 2000 mBm), (N/A)
[ 1.515754] cfg80211: (2457000 KHz - 2482000 KHz @ 40000 KHz), (N/A, 2000 mBm), (N/A)
[ 1.515763] cfg80211: (2474000 KHz - 2494000 KHz @ 20000 KHz), (N/A, 2000 mBm), (N/A)
[ 1.515772] cfg80211: (5170000 KHz - 5250000 KHz @ 80000 KHz, 160000 KHz AUTO), (N/A, 2000 mBm), (N/A)
[ 1.515825] cfg80211: (5250000 KHz - 5330000 KHz @ 80000 KHz, 160000 KHz AUTO), (N/A, 2000 mBm), (0 s)
[ 1.515833] cfg80211: (5490000 KHz - 5730000 KHz @ 160000 KHz), (N/A, 2000 mBm), (0 s)
[ 1.515839] cfg80211: (5735000 KHz - 5835000 KHz @ 80000 KHz), (N/A, 2000 mBm), (N/A)
[ 1.515846] cfg80211: (57240000 KHz - 63720000 KHz @ 2160000 KHz), (N/A, 0 mBm), (N/A)
[ 1.573063] usb 1-7: New USB device found, idVendor=8087, idProduct=0a2a
[ 1.573070] usb 1-7: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[ 1.588528] Bluetooth: Core ver 2.20
[ 1.588551] NET: Registered protocol family 31
[ 1.588556] Bluetooth: HCI device and connection manager initialized
[ 1.588563] Bluetooth: HCI socket layer initialized
[ 1.588568] Bluetooth: L2CAP socket layer initialized
[ 1.588578] Bluetooth: SCO socket layer initialized
[ 1.591790] usbcore: registered new interface driver btusb
[ 1.608657] Bluetooth: hci0: read Intel version: 370810011003110e00
[ 1.608908] bluetooth hci0: Direct firmware load for intel/ibt-hw-37.8.10-fw-1.10.3.11.e.bseq failed with error -2
[ 1.608914] Bluetooth: hci0 failed to open Intel firmware file: intel/ibt-hw-37.8.10-fw-1.10.3.11.e.bseq(-2)
[ 1.608924] bluetooth hci0: Direct firmware load for intel/ibt-hw-37.8.bseq failed with error -2
[ 1.608929] Bluetooth: hci0 failed to open default Intel fw file: intel/ibt-hw-37.8.bseq
[ 1.668953] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[ 1.668960] Bluetooth: BNEP filters: protocol multicast
[ 1.668965] Bluetooth: BNEP socket layer initialized
[ 2.292348] clocksource: Switched to clocksource tsc
[ 4.627274] e1000e: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: Rx/Tx
[ 7.646272] random: nonblocking pool is initialized
[-- Attachment #3: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 15/15] drm/i915: Add two-stage ILK-style watermark programming (v5)
2015-09-24 22:53 [PATCH 00/15] Atomic watermark updates (v5) Matt Roper
` (13 preceding siblings ...)
2015-09-24 22:53 ` [PATCH 14/15] drm/i915: Sanitize watermarks after hardware state readout Matt Roper
@ 2015-09-24 22:53 ` Matt Roper
2015-09-30 15:20 ` [PATCH 00/15] Atomic watermark updates (v5) Daniel Vetter
15 siblings, 0 replies; 29+ messages in thread
From: Matt Roper @ 2015-09-24 22:53 UTC (permalink / raw)
To: intel-gfx
In addition to calculating final watermarks, let's also pre-calculate a
set of intermediate watermark values at atomic check time. These
intermediate watermarks are a combination of the watermarks for the old
state and the new state; they should satisfy the requirements of both
states which means they can be programmed immediately when we commit the
atomic state (without waiting for a vblank). Once the vblank does
happen, we can then re-program watermarks to the more optimal final
value.
v2: Significant rebasing/rewriting.
v3:
- Move 'need_postvbl_update' flag to CRTC state (Daniel)
- Don't forget to check intermediate watermark values for validity
(Maarten)
- Don't due async watermark optimization; just do it at the end of the
atomic transaction, after waiting for vblanks. We do want it to be
async eventually, but adding that now will cause more trouble for
Maarten's in-progress work. (Maarten)
- Don't allocate space in crtc_state for intermediate watermarks on
platforms that don't need it (gen9+).
- Move WaCxSRDisabledForSpriteScaling:ivb into intel_begin_crtc_commit
now that ilk_update_wm is gone.
v4:
- Add a wm_mutex to cover updates to intel_crtc->active and the
need_postvbl_update flag. Since we don't have async yet it isn't
terribly important yet, but might as well add it now.
- Change interface to program watermarks. Platforms will now expose
.initial_watermarks() and .optimize_watermarks() functions to do
watermark programming. These should lock wm_mutex, copy the
appropriate state values into intel_crtc->active, and then call
the internal program watermarks function.
v5:
- Skip intermediate watermark calculation/check during initial hardware
readout since we don't trust the existing HW values (and don't have
valid values of our own yet).
- Don't try to call .optimize_watermarks() on platforms that don't have
atomic watermarks yet. (Maarten)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by(v4): Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/intel_atomic.c | 1 +
drivers/gpu/drm/i915/intel_display.c | 91 +++++++++++++++++++-
drivers/gpu/drm/i915/intel_drv.h | 31 ++++++-
drivers/gpu/drm/i915/intel_pm.c | 160 ++++++++++++++++++++++++-----------
5 files changed, 233 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a9bac1e..e9d9a47 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -629,7 +629,11 @@ struct drm_i915_display_funcs {
struct dpll *best_clock);
int (*compute_pipe_wm)(struct intel_crtc *crtc,
struct drm_atomic_state *state);
- void (*program_watermarks)(struct intel_crtc_state *cstate);
+ int (*compute_intermediate_wm)(struct drm_device *dev,
+ struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *newstate);
+ void (*initial_watermarks)(struct intel_crtc_state *cstate);
+ void (*optimize_watermarks)(struct intel_crtc_state *cstate);
void (*update_wm)(struct drm_crtc *crtc);
int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index 05b1203..28630f8 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -95,6 +95,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
crtc_state->update_pipe = false;
crtc_state->disable_lp_wm = false;
+ crtc_state->wm.need_postvbl_update = false;
return &crtc_state->base;
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0c3783c..fb32800 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11650,6 +11650,12 @@ int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
intel_crtc->atomic.update_wm_pre = true;
}
+ /* Pre-gen9 platforms need two-step watermark updates */
+ if ((intel_crtc->atomic.update_wm_pre || intel_crtc->atomic.update_wm_post) &&
+ INTEL_INFO(dev)->gen < 9 &&
+ dev_priv->display.optimize_watermarks)
+ to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
+
if (visible || was_visible)
intel_crtc->atomic.fb_bits |=
to_intel_plane(plane)->frontbuffer_bit;
@@ -11807,8 +11813,29 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
ret = 0;
if (dev_priv->display.compute_pipe_wm) {
ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
- if (ret)
+ if (ret) {
+ DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
return ret;
+ }
+ }
+
+ if (dev_priv->display.compute_intermediate_wm &&
+ !to_intel_atomic_state(state)->skip_intermediate_wm) {
+ if (WARN_ON(!dev_priv->display.compute_pipe_wm))
+ return 0;
+
+ /*
+ * Calculate 'intermediate' watermarks that satisfy both the
+ * old state and the new state. We can program these
+ * immediately.
+ */
+ ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
+ intel_crtc,
+ pipe_config);
+ if (ret) {
+ DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
+ return ret;
+ }
}
if (INTEL_INFO(dev)->gen >= 9) {
@@ -13161,6 +13188,7 @@ static int intel_atomic_commit(struct drm_device *dev,
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_crtc *crtc;
struct drm_crtc_state *crtc_state;
+ struct intel_crtc_state *intel_cstate;
int ret = 0;
int i;
bool any_ms = false;
@@ -13239,6 +13267,21 @@ static int intel_atomic_commit(struct drm_device *dev,
/* FIXME: add subpixel order */
drm_atomic_helper_wait_for_vblanks(dev, state);
+
+ /*
+ * Now that the vblank has passed, we can go ahead and program the
+ * optimal watermarks on platforms that need two-step watermark
+ * programming.
+ *
+ * TODO: Move this (and other cleanup) to an async worker eventually.
+ */
+ for_each_crtc_in_state(state, crtc, crtc_state, i) {
+ intel_cstate = to_intel_crtc_state(crtc->state);
+
+ if (dev_priv->display.optimize_watermarks)
+ dev_priv->display.optimize_watermarks(intel_cstate);
+ }
+
drm_atomic_helper_cleanup_planes(dev, state);
if (any_ms)
@@ -13567,13 +13610,44 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
struct drm_crtc_state *old_crtc_state)
{
struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
struct intel_crtc_state *old_intel_state =
to_intel_crtc_state(old_crtc_state);
bool modeset = needs_modeset(crtc->state);
- if (intel_crtc->atomic.update_wm_pre)
+ /*
+ * IVB workaround: must disable low power watermarks for at least
+ * one frame before enabling scaling. LP watermarks can be re-enabled
+ * when scaling is disabled.
+ *
+ * WaCxSRDisabledForSpriteScaling:ivb
+ */
+ if (cstate->disable_lp_wm) {
+ ilk_disable_lp_wm(crtc->dev);
+ intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
+ }
+
+ /*
+ * For platforms that support atomic watermarks, program the
+ * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
+ * will be the intermediate values that are safe for both pre- and
+ * post- vblank; when vblank happens, the 'active' values will be set
+ * to the final 'target' values and we'll do this again to get the
+ * optimal watermarks. For gen9+ platforms, the values we program here
+ * will be the final target values which will get automatically latched
+ * at vblank time; no further programming will be necessary.
+ *
+ * If a platform hasn't been transitioned to atomic watermarks yet,
+ * we'll continue to update watermarks the old way, if flags tell
+ * us to.
+ */
+ if (dev_priv->display.initial_watermarks != NULL) {
+ dev_priv->display.initial_watermarks(cstate);
+ } else if (intel_crtc->atomic.update_wm_pre) {
intel_update_watermarks(crtc);
+ }
/* Perform vblank evasion around commit operation */
if (crtc->state->active)
@@ -13915,6 +13989,7 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
intel_crtc->cursor_size = ~0;
intel_crtc->wm.cxsr_allowed = true;
+ mutex_init(&intel_crtc->wm.wm_mutex);
BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
@@ -15325,7 +15400,7 @@ static void sanitize_watermarks(struct drm_device *dev)
int i;
/* Only supported on platforms that use atomic watermark design */
- if (!dev_priv->display.program_watermarks)
+ if (!dev_priv->display.optimize_watermarks)
return;
/*
@@ -15337,6 +15412,13 @@ static void sanitize_watermarks(struct drm_device *dev)
if (WARN_ON(IS_ERR(state)))
return;
+ /*
+ * Hardware readout is the only time we don't want to calculate
+ * intermediate watermarks (since we don't trust the current
+ * watermarks).
+ */
+ to_intel_atomic_state(state)->skip_intermediate_wm = true;
+
ret = intel_atomic_check(dev, state);
if (ret) {
/*
@@ -15352,7 +15434,8 @@ static void sanitize_watermarks(struct drm_device *dev)
for_each_crtc_in_state(state, crtc, cstate, i) {
struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
- dev_priv->display.program_watermarks(cs);
+ cs->wm.need_postvbl_update = true;
+ dev_priv->display.optimize_watermarks(cs);
}
drm_atomic_state_free(state);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 07d5500..a8b7bbd 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -241,6 +241,12 @@ struct intel_atomic_state {
bool dpll_set;
struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
struct intel_wm_config wm_config;
+
+ /*
+ * Current watermarks can't be trusted during hardware readout, so
+ * don't bother calculating intermediate watermarks.
+ */
+ bool skip_intermediate_wm;
};
struct intel_plane_state {
@@ -480,13 +486,29 @@ struct intel_crtc_state {
struct {
/*
- * optimal watermarks, programmed post-vblank when this state
- * is committed
+ * Optimal watermarks, programmed post-vblank when this state
+ * is committed.
*/
union {
struct intel_pipe_wm ilk;
struct skl_pipe_wm skl;
} optimal;
+
+ /*
+ * Intermediate watermarks; these can be programmed immediately
+ * since they satisfy both the current configuration we're
+ * switching away from and the new configuration we're switching
+ * to.
+ */
+ struct intel_pipe_wm intermediate;
+
+ /*
+ * Platforms with two-step watermark programming will need to
+ * update watermark programming post-vblank to switch from the
+ * safe intermediate watermarks to the optimal final
+ * watermarks.
+ */
+ bool need_postvbl_update;
} wm;
};
@@ -577,8 +599,12 @@ struct intel_crtc {
struct intel_pipe_wm ilk;
struct skl_pipe_wm skl;
} active;
+
/* allow CxSR on this pipe */
bool cxsr_allowed;
+
+ /* Protects active and need_postvbl_update */
+ struct mutex wm_mutex;
} wm;
int scanline_offset;
@@ -1428,6 +1454,7 @@ void skl_wm_get_hw_state(struct drm_device *dev);
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
struct skl_ddb_allocation *ddb /* out */);
uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
+bool ilk_disable_lp_wm(struct drm_device *dev);
/* intel_sdvo.c */
bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 988893e..42bcf95 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2323,6 +2323,29 @@ static void skl_setup_wm_latency(struct drm_device *dev)
intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
}
+static bool ilk_validate_pipe_wm(struct drm_device *dev,
+ struct intel_pipe_wm *pipe_wm)
+{
+ /* LP0 watermark maximums depend on this pipe alone */
+ const struct intel_wm_config config = {
+ .num_pipes_active = 1,
+ .sprites_enabled = pipe_wm->sprites_enabled,
+ .sprites_scaled = pipe_wm->sprites_scaled,
+ };
+ struct ilk_wm_maximums max;
+
+ /* LP0 watermarks always use 1/2 DDB partitioning */
+ ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
+
+ /* At least LP0 must be valid */
+ if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
+ DRM_DEBUG_KMS("LP0 watermark invalid\n");
+ return false;
+ }
+
+ return true;
+}
+
/* Compute new watermarks for the pipe */
static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
struct drm_atomic_state *state)
@@ -2337,10 +2360,6 @@ static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
struct intel_plane_state *sprstate = NULL;
struct intel_plane_state *curstate = NULL;
int level, max_level = ilk_wm_max_level(dev);
- /* LP0 watermark maximums depend on this pipe alone */
- struct intel_wm_config config = {
- .num_pipes_active = 1,
- };
struct ilk_wm_maximums max;
cstate = intel_atomic_get_crtc_state(state, intel_crtc);
@@ -2363,21 +2382,18 @@ static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
curstate = to_intel_plane_state(ps);
}
- config.sprites_enabled = sprstate->visible;
- config.sprites_scaled = sprstate->visible &&
+ pipe_wm->pipe_enabled = cstate->base.active;
+ pipe_wm->sprites_enabled = sprstate->visible;
+ pipe_wm->sprites_scaled = sprstate->visible &&
(drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
- pipe_wm->pipe_enabled = cstate->base.active;
- pipe_wm->sprites_enabled = config.sprites_enabled;
- pipe_wm->sprites_scaled = config.sprites_scaled;
-
/* ILK/SNB: LP2+ watermarks only w/o sprites */
if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
max_level = 1;
/* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
- if (config.sprites_scaled)
+ if (pipe_wm->sprites_scaled)
max_level = 0;
ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
@@ -2387,12 +2403,8 @@ static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
pipe_wm->linetime = hsw_compute_linetime_wm(dev,
&intel_crtc->base);
- /* LP0 watermarks always use 1/2 DDB partitioning */
- ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
-
- /* At least LP0 must be valid */
- if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
- return -EINVAL;
+ if (!ilk_validate_pipe_wm(dev, pipe_wm))
+ return false;
ilk_compute_wm_reg_maximums(dev, 1, &max);
@@ -2417,6 +2429,59 @@ static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
}
/*
+ * Build a set of 'intermediate' watermark values that satisfy both the old
+ * state and the new state. These can be programmed to the hardware
+ * immediately.
+ */
+static int ilk_compute_intermediate_wm(struct drm_device *dev,
+ struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *newstate)
+{
+ struct intel_pipe_wm *a = &newstate->wm.intermediate;
+ struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
+ int level, max_level = ilk_wm_max_level(dev);
+
+ /*
+ * Start with the final, target watermarks, then combine with the
+ * currently active watermarks to get values that are safe both before
+ * and after the vblank.
+ */
+ *a = newstate->wm.optimal.ilk;
+ a->pipe_enabled |= b->pipe_enabled;
+ a->sprites_enabled |= b->sprites_enabled;
+ a->sprites_scaled |= b->sprites_scaled;
+
+ for (level = 0; level <= max_level; level++) {
+ struct intel_wm_level *a_wm = &a->wm[level];
+ const struct intel_wm_level *b_wm = &b->wm[level];
+
+ a_wm->enable &= b_wm->enable;
+ a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
+ a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
+ a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
+ a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
+ }
+
+ /*
+ * We need to make sure that these merged watermark values are
+ * actually a valid configuration themselves. If they're not,
+ * there's no safe way to transition from the old state to
+ * the new state, so we need to fail the atomic transaction.
+ */
+ if (!ilk_validate_pipe_wm(dev, a))
+ return -EINVAL;
+
+ /*
+ * If our intermediate WM are identical to the final WM, then we can
+ * omit the post-vblank programming; only update if it's different.
+ */
+ if (memcmp(a, &newstate->wm.optimal.ilk, sizeof *a) != 0)
+ newstate->wm.need_postvbl_update = false;
+
+ return 0;
+}
+
+/*
* Merge the watermarks from all active pipes for a specific level.
*/
static void ilk_merge_wm_level(struct drm_device *dev,
@@ -2428,9 +2493,7 @@ static void ilk_merge_wm_level(struct drm_device *dev,
ret_wm->enable = true;
for_each_intel_crtc(dev, intel_crtc) {
- const struct intel_crtc_state *cstate =
- to_intel_crtc_state(intel_crtc->base.state);
- const struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
+ const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
const struct intel_wm_level *wm = &active->wm[level];
if (!active->pipe_enabled)
@@ -2578,15 +2641,13 @@ static void ilk_compute_wm_results(struct drm_device *dev,
/* LP0 register values */
for_each_intel_crtc(dev, intel_crtc) {
- const struct intel_crtc_state *cstate =
- to_intel_crtc_state(intel_crtc->base.state);
enum pipe pipe = intel_crtc->pipe;
- const struct intel_wm_level *r = &cstate->wm.optimal.ilk.wm[0];
+ const struct intel_wm_level *r = &intel_crtc->wm.active.ilk.wm[0];
if (WARN_ON(!r->enable))
continue;
- results->wm_linetime[pipe] = cstate->wm.optimal.ilk.linetime;
+ results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
results->wm_pipe[pipe] =
(r->pri_val << WM0_PIPE_PLANE_SHIFT) |
@@ -2793,7 +2854,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
dev_priv->wm.hw = *results;
}
-static bool ilk_disable_lp_wm(struct drm_device *dev)
+bool ilk_disable_lp_wm(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3664,19 +3725,15 @@ static void skl_update_wm(struct drm_crtc *crtc)
dev_priv->wm.skl_hw = *results;
}
-static void ilk_program_watermarks(struct intel_crtc_state *cstate)
+static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
{
- struct drm_crtc *crtc = cstate->base.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_device *dev = dev_priv->dev;
struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
struct ilk_wm_maximums max;
struct intel_wm_config *config = &dev_priv->wm.config;
struct ilk_wm_values results = {};
enum intel_ddb_partitioning partitioning;
- to_intel_crtc(crtc)->wm.active.ilk = cstate->wm.optimal.ilk;
-
ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_1_2, &max);
ilk_wm_merge(dev, config, &max, &lp_wm_1_2);
@@ -3699,26 +3756,29 @@ static void ilk_program_watermarks(struct intel_crtc_state *cstate)
ilk_write_wm_values(dev_priv, &results);
}
-static void ilk_update_wm(struct drm_crtc *crtc)
+static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
{
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
+ struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+ struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
- WARN_ON(cstate->base.active != intel_crtc->active);
+ mutex_lock(&intel_crtc->wm.wm_mutex);
+ intel_crtc->wm.active.ilk = cstate->wm.intermediate;
+ ilk_program_watermarks(dev_priv);
+ mutex_unlock(&intel_crtc->wm.wm_mutex);
+}
- /*
- * IVB workaround: must disable low power watermarks for at least
- * one frame before enabling scaling. LP watermarks can be re-enabled
- * when scaling is disabled.
- *
- * WaCxSRDisabledForSpriteScaling:ivb
- */
- if (cstate->disable_lp_wm) {
- ilk_disable_lp_wm(crtc->dev);
- intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
- }
+static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
+{
+ struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+ struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
- ilk_program_watermarks(cstate);
+ mutex_lock(&intel_crtc->wm.wm_mutex);
+ if (cstate->wm.need_postvbl_update) {
+ intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
+ ilk_program_watermarks(dev_priv);
+ cstate->wm.need_postvbl_update = false;
+ }
+ mutex_unlock(&intel_crtc->wm.wm_mutex);
}
static void skl_pipe_wm_active_state(uint32_t val,
@@ -7050,9 +7110,11 @@ void intel_init_pm(struct drm_device *dev)
dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
(!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
- dev_priv->display.update_wm = ilk_update_wm;
dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
- dev_priv->display.program_watermarks = ilk_program_watermarks;
+ dev_priv->display.compute_intermediate_wm =
+ ilk_compute_intermediate_wm;
+ dev_priv->display.initial_watermarks = ilk_initial_watermarks;
+ dev_priv->display.optimize_watermarks = ilk_optimize_watermarks;
} else {
DRM_DEBUG_KMS("Failed to read display plane latency. "
"Disable CxSR\n");
--
2.1.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 00/15] Atomic watermark updates (v5)
2015-09-24 22:53 [PATCH 00/15] Atomic watermark updates (v5) Matt Roper
` (14 preceding siblings ...)
2015-09-24 22:53 ` [PATCH 15/15] drm/i915: Add two-stage ILK-style watermark programming (v5) Matt Roper
@ 2015-09-30 15:20 ` Daniel Vetter
2015-09-30 22:21 ` Zanoni, Paulo R
15 siblings, 1 reply; 29+ messages in thread
From: Daniel Vetter @ 2015-09-30 15:20 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Thu, Sep 24, 2015 at 03:53:05PM -0700, Matt Roper wrote:
> Previous version of the series was here:
> http://lists.freedesktop.org/archives/intel-gfx/2015-September/075883.html
>
> Pretty minimal changes since the last series:
> * General rebasing on di-nightly
> * Some minor SKL-specific bugfixes on patch #6 based on Maarten's review of
> v4 of this series.
> * Added a new patch #14 to try to sanitize watermarks after hardware state
> readout. Once we've read general state out of the hardware, we should
> recalculate what we think the watermarks for that state should be and not
> just trust whatever the system firmware happens to have programmed them to.
> * Added Maarten's r-b to all patches except the new #14; he gave it on his
> feedback to patch #6 of the last revision of the series and I didn't notice
> that it applied to the whole series until I re-read his feedback. :-)
Pulled in all into dinq, thanks!
-Daniel
>
> Matt Roper (14):
> drm/i915: Drop redundant watermark programming
> drm/i915: Eliminate usage of plane_wm_parameters from ILK-style WM
> code (v2)
> drm/i915: Eliminate usage of pipe_wm_parameters from ILK-style WM (v2)
> drm/i915: Determine I915_MAX_PLANES from plane enum
> drm/i915/skl: Simplify wm structures slightly (v2)
> drm/i915/skl: Eliminate usage of pipe_wm_parameters from SKL-style WM
> (v3)
> drm/i915/ivb: Move WaCxSRDisabledForSpriteScaling w/a to atomic check
> drm/i915: Drop intel_update_sprite_watermarks
> drm/i915: Calculate pipe watermarks into CRTC state (v3)
> drm/i915: Calculate ILK-style watermarks during atomic check (v3)
> drm/i915: Don't set plane visible during HW readout if CRTC is off
> drm/i915: Calculate watermark configuration during atomic check (v2)
> drm/i915: Sanitize watermarks after hardware state readout
> drm/i915: Add two-stage ILK-style watermark programming (v5)
>
> Ville Syrjälä (1):
> drm/i915: Refactor ilk_update_wm (v3)
>
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 41 +-
> drivers/gpu/drm/i915/intel_atomic.c | 2 +
> drivers/gpu/drm/i915/intel_display.c | 255 +++++++++--
> drivers/gpu/drm/i915/intel_drv.h | 85 +++-
> drivers/gpu/drm/i915/intel_pm.c | 855 ++++++++++++++++-------------------
> drivers/gpu/drm/i915/intel_sprite.c | 15 -
> 7 files changed, 707 insertions(+), 548 deletions(-)
>
> --
> 2.1.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 00/15] Atomic watermark updates (v5)
2015-09-30 15:20 ` [PATCH 00/15] Atomic watermark updates (v5) Daniel Vetter
@ 2015-09-30 22:21 ` Zanoni, Paulo R
2015-10-01 23:03 ` [PATCH] fixup! drm/i915/skl: Eliminate usage of pipe_wm_parameters from SKL-style WM (v3) Matt Roper
0 siblings, 1 reply; 29+ messages in thread
From: Zanoni, Paulo R @ 2015-09-30 22:21 UTC (permalink / raw)
To: daniel, Roper, Matthew D; +Cc: intel-gfx
Em Qua, 2015-09-30 às 17:20 +0200, Daniel Vetter escreveu:
> On Thu, Sep 24, 2015 at 03:53:05PM -0700, Matt Roper wrote:
> > Previous version of the series was here:
> > http://lists.freedesktop.org/archives/intel-gfx/2015-September/07
> > 5883.html
> >
> > Pretty minimal changes since the last series:
> > * General rebasing on di-nightly
> > * Some minor SKL-specific bugfixes on patch #6 based on Maarten's
> > review of
> > v4 of this series.
> > * Added a new patch #14 to try to sanitize watermarks after
> > hardware state
> > readout. Once we've read general state out of the hardware, we
> > should
> > recalculate what we think the watermarks for that state should
> > be and not
> > just trust whatever the system firmware happens to have
> > programmed them to.
> > * Added Maarten's r-b to all patches except the new #14; he gave
> > it on his
> > feedback to patch #6 of the last revision of the series and I
> > didn't notice
> > that it applied to the whole series until I re-read his
> > feedback. :-)
>
> Pulled in all into dinq, thanks!
And it's causing problems on my SKL machine. It gives me a new
DRM_ERROR about DDB state mismatch, and I'm getting FIFO underruns
sometimes (and due to the underruns, FBC works 0% of the times and
gives us nice black screens).
I tried bisecting the underruns but since they don't happen 100% of the
times I got lost very quickly. It *seems* that "drm/i915: Drop
intel_update_sprite_watermarks" is still a good commit, and the
intermittent problems (and DRM_ERROR) start after that, but I'm not
even 100% sure.
In case you want to try to reproduce the problem, my SKL machine has a
3200x1800 eDP panel.
I'm glad we don't have PRTS to catch these things :)
Thanks,
Paulo
> -Daniel
>
> >
> > Matt Roper (14):
> > drm/i915: Drop redundant watermark programming
> > drm/i915: Eliminate usage of plane_wm_parameters from ILK-style
> > WM
> > code (v2)
> > drm/i915: Eliminate usage of pipe_wm_parameters from ILK-style WM
> > (v2)
> > drm/i915: Determine I915_MAX_PLANES from plane enum
> > drm/i915/skl: Simplify wm structures slightly (v2)
> > drm/i915/skl: Eliminate usage of pipe_wm_parameters from SKL
> > -style WM
> > (v3)
> > drm/i915/ivb: Move WaCxSRDisabledForSpriteScaling w/a to atomic
> > check
> > drm/i915: Drop intel_update_sprite_watermarks
> > drm/i915: Calculate pipe watermarks into CRTC state (v3)
> > drm/i915: Calculate ILK-style watermarks during atomic check (v3)
> > drm/i915: Don't set plane visible during HW readout if CRTC is
> > off
> > drm/i915: Calculate watermark configuration during atomic check
> > (v2)
> > drm/i915: Sanitize watermarks after hardware state readout
> > drm/i915: Add two-stage ILK-style watermark programming (v5)
> >
> > Ville Syrjälä (1):
> > drm/i915: Refactor ilk_update_wm (v3)
> >
> > drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> > drivers/gpu/drm/i915/i915_drv.h | 41 +-
> > drivers/gpu/drm/i915/intel_atomic.c | 2 +
> > drivers/gpu/drm/i915/intel_display.c | 255 +++++++++--
> > drivers/gpu/drm/i915/intel_drv.h | 85 +++-
> > drivers/gpu/drm/i915/intel_pm.c | 855 ++++++++++++++++-------
> > ------------
> > drivers/gpu/drm/i915/intel_sprite.c | 15 -
> > 7 files changed, 707 insertions(+), 548 deletions(-)
> >
> > --
> > 2.1.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH] fixup! drm/i915/skl: Eliminate usage of pipe_wm_parameters from SKL-style WM (v3)
2015-09-30 22:21 ` Zanoni, Paulo R
@ 2015-10-01 23:03 ` Matt Roper
2015-10-02 18:43 ` Zanoni, Paulo R
0 siblings, 1 reply; 29+ messages in thread
From: Matt Roper @ 2015-10-01 23:03 UTC (permalink / raw)
To: intel-gfx
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
Paulo, I'm not positive that this is the cause of the issues you're seeing, but
I did find this unwanted behavior change while re-reading all the SKL watermark
code. Could you give this a try and see if it improves your situation at all?
drivers/gpu/drm/i915/intel_pm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3857592..22c97f2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2951,6 +2951,9 @@ skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
if (pstate->fb == NULL)
continue;
+ if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
+ continue;
+
/* packed/uv */
total_data_rate += skl_plane_relative_data_rate(cstate,
pstate,
--
2.1.4
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^ permalink raw reply related [flat|nested] 29+ messages in thread
* Re: [PATCH] fixup! drm/i915/skl: Eliminate usage of pipe_wm_parameters from SKL-style WM (v3)
2015-10-01 23:03 ` [PATCH] fixup! drm/i915/skl: Eliminate usage of pipe_wm_parameters from SKL-style WM (v3) Matt Roper
@ 2015-10-02 18:43 ` Zanoni, Paulo R
2015-10-06 10:13 ` [PATCH] fixup! drm/i915/skl: Eliminate usage of pipe_wm_parameters from SKL-style WM (v3) [regression] Daniel Vetter
0 siblings, 1 reply; 29+ messages in thread
From: Zanoni, Paulo R @ 2015-10-02 18:43 UTC (permalink / raw)
To: Roper, Matthew D, intel-gfx; +Cc: Vetter, Daniel
Em Qui, 2015-10-01 às 16:03 -0700, Matt Roper escreveu:
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> Paulo, I'm not positive that this is the cause of the issues you're
> seeing, but
> I did find this unwanted behavior change while re-reading all the SKL
> watermark
> code. Could you give this a try and see if it improves your
> situation at all?
Thanks for the patch, but unfortunately this doesn't solve the problems
I'm seeing.
For my normal work activities I'm carrying a patch that reverts the
following commits:
drm/i915: Calculate watermark configuration during atomic check (v2)
drm/i915: Don't set plane visible during HW readout if CRTC is off
drm/i915: Calculate ILK-style watermarks during atomic check (v3)
drm/i915: Calculate pipe watermarks into CRTC state (v3)
drm/i915: Refactor ilk_update_wm (v3)
drm/i915: Drop intel_update_sprite_watermarks
So I guess the sprite update thing is very likely the first bad commit.
I'm also noticing that the screen stays black for _way_ too much time
during boot, but I'm not sure it's caused by the watermark series:
might be something else on -nightly.
Thanks,
Paulo
>
> drivers/gpu/drm/i915/intel_pm.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c
> index 3857592..22c97f2 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2951,6 +2951,9 @@ skl_get_total_relative_data_rate(const struct
> intel_crtc_state *cstate)
> if (pstate->fb == NULL)
> continue;
>
> + if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
> + continue;
> +
> /* packed/uv */
> total_data_rate +=
> skl_plane_relative_data_rate(cstate,
> psta
> te,
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^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH] fixup! drm/i915/skl: Eliminate usage of pipe_wm_parameters from SKL-style WM (v3) [regression]
2015-10-02 18:43 ` Zanoni, Paulo R
@ 2015-10-06 10:13 ` Daniel Vetter
0 siblings, 0 replies; 29+ messages in thread
From: Daniel Vetter @ 2015-10-06 10:13 UTC (permalink / raw)
To: Zanoni, Paulo R; +Cc: Vetter, Daniel, intel-gfx
Another regression for Jairo to track. Also this one is bisected too
(although not 100% confirmed).
-Daniel
On Fri, Oct 2, 2015 at 8:43 PM, Zanoni, Paulo R <paulo.r.zanoni@intel.com> wrote:
> Em Qui, 2015-10-01 às 16:03 -0700, Matt Roper escreveu:
>> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> ---
>> Paulo, I'm not positive that this is the cause of the issues you're
>> seeing, but
>> I did find this unwanted behavior change while re-reading all the SKL
>> watermark
>> code. Could you give this a try and see if it improves your
>> situation at all?
>
> Thanks for the patch, but unfortunately this doesn't solve the problems
> I'm seeing.
>
> For my normal work activities I'm carrying a patch that reverts the
> following commits:
>
> drm/i915: Calculate watermark configuration during atomic check (v2)
> drm/i915: Don't set plane visible during HW readout if CRTC is off
> drm/i915: Calculate ILK-style watermarks during atomic check (v3)
> drm/i915: Calculate pipe watermarks into CRTC state (v3)
> drm/i915: Refactor ilk_update_wm (v3)
> drm/i915: Drop intel_update_sprite_watermarks
>
> So I guess the sprite update thing is very likely the first bad commit.
> I'm also noticing that the screen stays black for _way_ too much time
> during boot, but I'm not sure it's caused by the watermark series:
> might be something else on -nightly.
>
> Thanks,
> Paulo
>
>>
>> drivers/gpu/drm/i915/intel_pm.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c
>> b/drivers/gpu/drm/i915/intel_pm.c
>> index 3857592..22c97f2 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -2951,6 +2951,9 @@ skl_get_total_relative_data_rate(const struct
>> intel_crtc_state *cstate)
>> if (pstate->fb == NULL)
>> continue;
>>
>> + if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
>> + continue;
>> +
>> /* packed/uv */
>> total_data_rate +=
>> skl_plane_relative_data_rate(cstate,
>> psta
>> te,
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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