[PATCH 00/12] Gen9: Changes to add/merge/update/remove WA

[PATCH 00/12] Gen9: Changes to add/merge/update/remove WA

[Arun Siluvery]

Changes that add new WA, merge WA that are applied for the same register,
update stepping checks and remove pre-production ones .

Arun Siluvery (12):
  drm/i915/gen9: Handle error returned by gen9_init_workarounds
  drm/i915/gen9: Add WaOCLCoherentLineFlush
  drm/i915/gen9: Merge two WA as they part of same register
  drm/i915/gen9: Merge HALF_SLICE_CHICKEN3 WA
  drm/i915/bxt: update WaSetHDCunitClckGatingDisable
  drm/i915/bxt: Add WaStoreMultiplePTEenable name
  drm/i915/bxt: Update stepping check for WaDisableSDEUnitClockGating
  drm/i915/skl: Remove WaDisableSDEUnitClockGating
  drm/i915/skl: Remove WaSetGAPSunitClckGateDisable
  drm/i915/skl: Remove WaDisableVFUnitClockGating
  drm/i915/skl: Remove
    WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken
  drm/i915:skl: Remove WaDisablePowerCompilerClockGating

 drivers/gpu/drm/i915/i915_reg.h         |  2 --
 drivers/gpu/drm/i915/intel_lrc.c        |  5 ++-
 drivers/gpu/drm/i915/intel_pm.c         | 48 ++++++++++++--------------
 drivers/gpu/drm/i915/intel_ringbuffer.c | 61 ++++++++++++++++-----------------
 4 files changed, 52 insertions(+), 64 deletions(-)

-- 
1.9.1

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[PATCH 01/12] drm/i915/gen9: Handle error returned by gen9_init_workarounds

[Arun Siluvery]

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index fdff606..6671800 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1026,10 +1026,13 @@ static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
 
 static int skl_init_workarounds(struct intel_engine_cs *ring)
 {
+	int ret;
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	gen9_init_workarounds(ring);
+	ret = gen9_init_workarounds(ring);
+	if (ret)
+		return ret;
 
 	/* WaDisablePowerCompilerClockGating:skl */
 	if (INTEL_REVID(dev) == SKL_REVID_B0)
@@ -1066,10 +1069,13 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
 
 static int bxt_init_workarounds(struct intel_engine_cs *ring)
 {
+	int ret;
 	struct drm_device *dev = ring->dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 
-	gen9_init_workarounds(ring);
+	ret = gen9_init_workarounds(ring);
+	if (ret)
+		return ret;
 
 	/* WaDisableThreadStallDopClockGating:bxt */
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
-- 
1.9.1

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[PATCH 02/12] drm/i915/gen9: Add WaOCLCoherentLineFlush

[Arun Siluvery]

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ab5ac5e..093a5e4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -63,6 +63,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
 	/* WaDisableKillLogic:bxt,skl */
 	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 		   ECOCHK_DIS_TLB);
+
+	/* WaOCLCoherentLineFlush:skl,bxt */
+	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
+				    GEN8_LQSC_FLUSH_COHERENT_LINES));
 }
 
 static void skl_init_clock_gating(struct drm_device *dev)
-- 
1.9.1

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[PATCH 03/12] drm/i915/gen9: Merge two WA as they part of same register

[Arun Siluvery]

Merge Wa4x4STCOptimizationDisable and WaDisablePartialResolveInVc to save
an entry in WA array.

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 6671800..ad16ef4 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -946,10 +946,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	}
 
 	/* Wa4x4STCOptimizationDisable:skl,bxt */
-	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
-
 	/* WaDisablePartialResolveInVc:skl,bxt */
-	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
+	WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
+					 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 
 	/* WaCcsTlbPrefetchDisable:skl,bxt */
 	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
-- 
1.9.1

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[PATCH 04/12] drm/i915/gen9: Merge HALF_SLICE_CHICKEN3 WA

[Arun Siluvery]

Merge WaDisableSamplerPowerBypassForSOPingPong and another WA which has no name
as they are part of same register. This will save an entry in WA array.

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index ad16ef4..963b3ca 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -914,9 +914,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 
-	/* Syncing dependencies between camera and graphics:skl,bxt */
-	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
-			  GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
+	/* WA: Syncing dependencies between camera and graphics:skl,bxt */
+	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
+	tmp = GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC;
+	if (IS_SKYLAKE(dev) ||
+	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
+		tmp |= GEN8_SAMPLER_POWER_BYPASS_DIS;
+	}
+	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, tmp);
 
 	if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
 	    INTEL_REVID(dev) == SKL_REVID_B0)) ||
@@ -967,13 +972,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 		tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
 	WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
 
-	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
-	if (IS_SKYLAKE(dev) ||
-	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
-		WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
-				  GEN8_SAMPLER_POWER_BYPASS_DIS);
-	}
-
 	/* WaDisableSTUnitPowerOptimization:skl,bxt */
 	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 
-- 
1.9.1

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[PATCH 05/12] drm/i915/bxt: update WaSetHDCunitClckGatingDisable

[Arun Siluvery]

The implementation for this WA is same as WaSetHdcUnitClockGatingDisableInUcgctl6.
Both of them are for BXT:A0 except that WaSetHdcUnitClockGatingDisableInUcgctl6
is applicable only when either SS0 or SS2 is active but if we apply the former WA
then the latter one also gets applied irrespective of which SS is enabled.

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 093a5e4..c73d37d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -124,12 +124,17 @@ static void bxt_init_clock_gating(struct drm_device *dev)
 	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
 		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 
-	/*
-	 * FIXME:
-	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
+	/* WaSetHDCunitClckGatingDisable:bxt */
+	/* WaSetHdcUnitClockGatingDisableInUcgctl6:bxt */
+	/* The implementation is same for both of these WA except that
+	 * WaSetHdcUnitClockGatingDisableInUcgctl6 is only applicable when
+	 * either SS0 or SS2 is active but if we apply the first one then the
+	 * second one also gets applied irrespective of which SS is enabled.
 	 */
-	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
+	if (INTEL_REVID(dev) == BXT_REVID_A0) {
+		I915_WRITE(GEN8_UCGCTL6, (I915_READ(GEN8_UCGCTL6) |
+					  GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ));
+	}
 
 	if (INTEL_REVID(dev) == BXT_REVID_A0) {
 		/*
-- 
1.9.1

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[PATCH 06/12] drm/i915/bxt: Add WaStoreMultiplePTEenable name

[Arun Siluvery]

Updated WA with the name.

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c73d37d..9151a2b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -136,13 +136,10 @@ static void bxt_init_clock_gating(struct drm_device *dev)
 					  GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ));
 	}
 
-	if (INTEL_REVID(dev) == BXT_REVID_A0) {
-		/*
-		 * Hardware specification requires this bit to be
-		 * set to 1 for A0
-		 */
+	/* WaStoreMultiplePTEenable:bxt */
+	/* This is a requirement according to Hardware specification */
+	if (INTEL_REVID(dev) == BXT_REVID_A0)
 		I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
-	}
 
 	/* WaSetClckGatingDisableMedia:bxt */
 	if (INTEL_REVID(dev) == BXT_REVID_A0) {
-- 
1.9.1

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[PATCH 07/12] drm/i915/bxt: Update stepping check for WaDisableSDEUnitClockGating

[Arun Siluvery]

It is also applicable for B0.

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9151a2b..be39f7ad 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -121,8 +121,10 @@ static void bxt_init_clock_gating(struct drm_device *dev)
 	gen9_init_clock_gating(dev);
 
 	/* WaDisableSDEUnitClockGating:bxt */
-	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+	if (INTEL_REVID(dev) >= BXT_REVID_A0) {
+		I915_WRITE(GEN8_UCGCTL6, (I915_READ(GEN8_UCGCTL6) |
+					  GEN8_SDEUNIT_CLOCK_GATE_DISABLE));
+	}
 
 	/* WaSetHDCunitClckGatingDisable:bxt */
 	/* WaSetHdcUnitClockGatingDisableInUcgctl6:bxt */
-- 
1.9.1

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[PATCH 08/12] drm/i915/skl: Remove WaDisableSDEUnitClockGating

[Arun Siluvery]

Dropping it because it is for pre-production stepping.

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index be39f7ad..a6ee0d3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -77,12 +77,10 @@ static void skl_init_clock_gating(struct drm_device *dev)
 
 	if (INTEL_REVID(dev) <= SKL_REVID_B0) {
 		/*
-		 * WaDisableSDEUnitClockGating:skl
 		 * WaSetGAPSunitClckGateDisable:skl
 		 */
 		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-			   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
-			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+			   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE);
 
 		/* WaDisableVFUnitClockGating:skl */
 		I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
-- 
1.9.1

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[PATCH 09/12] drm/i915/skl: Remove WaSetGAPSunitClckGateDisable

[Arun Siluvery]

Dropping it because it is for pre-production stepping, also removed
bit definition in i915_reg as it is not used anywhere else.

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 -
 drivers/gpu/drm/i915/intel_pm.c | 6 ------
 2 files changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 085ffa2..ef3d71f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6705,7 +6705,6 @@ enum skl_disp_power_wells {
 #define GEN6_RSTCTL				0x9420
 
 #define GEN8_UCGCTL6				0x9430
-#define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1<<24)
 #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1<<14)
 #define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a6ee0d3..65c60bc 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -76,12 +76,6 @@ static void skl_init_clock_gating(struct drm_device *dev)
 	gen9_init_clock_gating(dev);
 
 	if (INTEL_REVID(dev) <= SKL_REVID_B0) {
-		/*
-		 * WaSetGAPSunitClckGateDisable:skl
-		 */
-		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
-			   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE);
-
 		/* WaDisableVFUnitClockGating:skl */
 		I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
 			   GEN6_VFUNIT_CLOCK_GATE_DISABLE);
-- 
1.9.1

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[PATCH 10/12] drm/i915/skl: Remove WaDisableVFUnitClockGating

[Arun Siluvery]

Dropping it because it is for pre-production stepping, also removed
bit definition in i915_reg.h as it is not used anywhere else.

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 1 -
 drivers/gpu/drm/i915/intel_pm.c | 6 ------
 2 files changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ef3d71f..b510fdc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6688,7 +6688,6 @@ enum skl_disp_power_wells {
 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
 
 #define GEN6_UCGCTL2				0x9404
-# define GEN6_VFUNIT_CLOCK_GATE_DISABLE			(1 << 31)
 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)
 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE		(1 << 22)
 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 65c60bc..88acb3e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -75,12 +75,6 @@ static void skl_init_clock_gating(struct drm_device *dev)
 
 	gen9_init_clock_gating(dev);
 
-	if (INTEL_REVID(dev) <= SKL_REVID_B0) {
-		/* WaDisableVFUnitClockGating:skl */
-		I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
-			   GEN6_VFUNIT_CLOCK_GATE_DISABLE);
-	}
-
 	if (INTEL_REVID(dev) <= SKL_REVID_D0) {
 		/* WaDisableHDCInvalidation:skl */
 		I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
-- 
1.9.1

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[PATCH 11/12] drm/i915/skl: Remove WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken

[Arun Siluvery]

Dropping it as it is for pre-production stepping.

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c        |  5 ++---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++++++++++------------
 2 files changed, 13 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 256167b..e3baffd 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1352,9 +1352,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
 	struct drm_device *dev = ring->dev;
 	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
 
-	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
-	if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
-	    (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
+	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
+	if (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)) {
 		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
 		wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
 		wa_ctx_emit(batch, index,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 963b3ca..d5fdbc8 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -931,18 +931,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
 				  GEN9_DG_MIRROR_FIX_ENABLE);
 	}
 
-	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
-	    (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
-		/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
-		WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
-				  GEN9_RHWO_OPTIMIZATION_DISABLE);
-		/*
-		 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
-		 * but we do that in per ctx batchbuffer as there is an issue
-		 * with this register not getting restored on ctx restore
-		 */
-	}
-
 	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
 	    IS_BROXTON(dev)) {
 		/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
@@ -1085,6 +1073,17 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
 			GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
 	}
 
+	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
+	if (INTEL_REVID(dev) < BXT_REVID_B0) {
+		WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
+				  GEN9_RHWO_OPTIMIZATION_DISABLE);
+		/*
+		 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
+		 * but we do that in per ctx batchbuffer as there is an issue
+		 * with this register not getting restored on ctx restore
+		 */
+	}
+
 	return 0;
 }
 
-- 
1.9.1

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[PATCH 12/12] drm/i915:skl: Remove WaDisablePowerCompilerClockGating

[Arun Siluvery]

Dropping it because it is for pre-production stepping.

Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ringbuffer.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index d5fdbc8..2a33b9d 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1019,11 +1019,6 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
 	if (ret)
 		return ret;
 
-	/* WaDisablePowerCompilerClockGating:skl */
-	if (INTEL_REVID(dev) == SKL_REVID_B0)
-		WA_SET_BIT_MASKED(HIZ_CHICKEN,
-				  BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
-
 	if (INTEL_REVID(dev) <= SKL_REVID_D0) {
 		/*
 		 *Use Force Non-Coherent whenever executing a 3D context. This
-- 
1.9.1

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Re: [PATCH 02/12] drm/i915/gen9: Add WaOCLCoherentLineFlush

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:36PM +0100, Arun Siluvery wrote:
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ab5ac5e..093a5e4 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -63,6 +63,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
>  	/* WaDisableKillLogic:bxt,skl */
>  	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
>  		   ECOCHK_DIS_TLB);
> +
> +	/* WaOCLCoherentLineFlush:skl,bxt */
> +	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
> +				    GEN8_LQSC_FLUSH_COHERENT_LINES));

According to Bspec + w/a db this should be done for BDW too (actually
BSpec shows it for BDW only?). If that's the case, then we should be
able to kill gen8_emit_flush_coherentl3_wa(), no? Well, as long as
someone goes and adds the DC flush to the normal post batch flush.

>  }
>  
>  static void skl_init_clock_gating(struct drm_device *dev)
> -- 
> 1.9.1
> 
> _______________________________________________
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH 04/12] drm/i915/gen9: Merge HALF_SLICE_CHICKEN3 WA

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:38PM +0100, Arun Siluvery wrote:
> Merge WaDisableSamplerPowerBypassForSOPingPong and another WA which has no name
> as they are part of same register. This will save an entry in WA array.
> 
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 18 ++++++++----------
>  1 file changed, 8 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index ad16ef4..963b3ca 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -914,9 +914,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>  	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>  			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
>  
> -	/* Syncing dependencies between camera and graphics:skl,bxt */
> -	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> -			  GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
> +	/* WA: Syncing dependencies between camera and graphics:skl,bxt */
> +	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
> +	tmp = GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC;
> +	if (IS_SKYLAKE(dev) ||
> +	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
> +		tmp |= GEN8_SAMPLER_POWER_BYPASS_DIS;
> +	}
> +	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, tmp);

I really dislike these platform+stepping checks in the shared codepath.
If there's any difference between the platforms, IMO the w/a should go into
the per-platform function.

>  
>  	if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
>  	    INTEL_REVID(dev) == SKL_REVID_B0)) ||
> @@ -967,13 +972,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>  		tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
>  	WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
>  
> -	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
> -	if (IS_SKYLAKE(dev) ||
> -	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
> -		WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> -				  GEN8_SAMPLER_POWER_BYPASS_DIS);
> -	}
> -
>  	/* WaDisableSTUnitPowerOptimization:skl,bxt */
>  	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
>  
> -- 
> 1.9.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH 07/12] drm/i915/bxt: Update stepping check for WaDisableSDEUnitClockGating

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:41PM +0100, Arun Siluvery wrote:
> It is also applicable for B0.
> 
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9151a2b..be39f7ad 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -121,8 +121,10 @@ static void bxt_init_clock_gating(struct drm_device *dev)
>  	gen9_init_clock_gating(dev);
>  
>  	/* WaDisableSDEUnitClockGating:bxt */
> -	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> -		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> +	if (INTEL_REVID(dev) >= BXT_REVID_A0) {

I don't see a point in such a check. We don't have anything older than A
stepping anyway, so this will always be true.

Also BSpec says it's FROM_A0, w/a database says UNTIL_A0. Would be nice
to know which is correct...

> +		I915_WRITE(GEN8_UCGCTL6, (I915_READ(GEN8_UCGCTL6) |
> +					  GEN8_SDEUNIT_CLOCK_GATE_DISABLE));
> +	}
>  
>  	/* WaSetHDCunitClckGatingDisable:bxt */
>  	/* WaSetHdcUnitClockGatingDisableInUcgctl6:bxt */
> -- 
> 1.9.1
> 
> _______________________________________________
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH 12/12] drm/i915:skl: Remove WaDisablePowerCompilerClockGating

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:46PM +0100, Arun Siluvery wrote:
> Dropping it because it is for pre-production stepping.
> 
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 5 -----
>  1 file changed, 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index d5fdbc8..2a33b9d 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1019,11 +1019,6 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
>  	if (ret)
>  		return ret;
>  
> -	/* WaDisablePowerCompilerClockGating:skl */
> -	if (INTEL_REVID(dev) == SKL_REVID_B0)
> -		WA_SET_BIT_MASKED(HIZ_CHICKEN,
> -				  BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
> -

Yes. However Bspec shows this to be valid for BXT until B0. The register
description OTOH says SKL:B only, as does the w/a database. I'm too lazy
to start hsd trawling now, so maybe you can figure out what's going on there?

>  	if (INTEL_REVID(dev) <= SKL_REVID_D0) {
>  		/*
>  		 *Use Force Non-Coherent whenever executing a 3D context. This
> -- 
> 1.9.1
> 
> _______________________________________________
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-- 
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Re: [PATCH 05/12] drm/i915/bxt: update WaSetHDCunitClckGatingDisable

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:39PM +0100, Arun Siluvery wrote:
> The implementation for this WA is same as WaSetHdcUnitClockGatingDisableInUcgctl6.
> Both of them are for BXT:A0 except that WaSetHdcUnitClockGatingDisableInUcgctl6
> is applicable only when either SS0 or SS2 is active but if we apply the former WA
> then the latter one also gets applied irrespective of which SS is enabled.
> 
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 15 ++++++++++-----
>  1 file changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 093a5e4..c73d37d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -124,12 +124,17 @@ static void bxt_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>  		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>  
> -	/*
> -	 * FIXME:
> -	 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
> +	/* WaSetHDCunitClckGatingDisable:bxt */
> +	/* WaSetHdcUnitClockGatingDisableInUcgctl6:bxt */
> +	/* The implementation is same for both of these WA except that
> +	 * WaSetHdcUnitClockGatingDisableInUcgctl6 is only applicable when
> +	 * either SS0 or SS2 is active but if we apply the first one then the
> +	 * second one also gets applied irrespective of which SS is enabled.
>  	 */
> -	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> -		   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
> +	if (INTEL_REVID(dev) == BXT_REVID_A0) {
> +		I915_WRITE(GEN8_UCGCTL6, (I915_READ(GEN8_UCGCTL6) |
> +					  GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ));
> +	}

Again BSpec seems confused. It says this applies to BXT from A0, and SKL
from C0. The register description only says to do it for 3x6 BXT, and
w/a db says both workarounds are for BXT until A0. Quite a nice mess.

>  
>  	if (INTEL_REVID(dev) == BXT_REVID_A0) {
>  		/*
> -- 
> 1.9.1
> 
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Re: [PATCH 06/12] drm/i915/bxt: Add WaStoreMultiplePTEenable name

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:40PM +0100, Arun Siluvery wrote:
> Updated WA with the name.
> 
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 9 +++------
>  1 file changed, 3 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c73d37d..9151a2b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -136,13 +136,10 @@ static void bxt_init_clock_gating(struct drm_device *dev)
>  					  GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ));
>  	}
>  
> -	if (INTEL_REVID(dev) == BXT_REVID_A0) {
> -		/*
> -		 * Hardware specification requires this bit to be
> -		 * set to 1 for A0
> -		 */
> +	/* WaStoreMultiplePTEenable:bxt */
> +	/* This is a requirement according to Hardware specification */
> +	if (INTEL_REVID(dev) == BXT_REVID_A0)
>  		I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
> -	}
>  
>  	/* WaSetClckGatingDisableMedia:bxt */
>  	if (INTEL_REVID(dev) == BXT_REVID_A0) {
> -- 
> 1.9.1
> 
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-- 
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Re: [PATCH 08/12] drm/i915/skl: Remove WaDisableSDEUnitClockGating

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:42PM +0100, Arun Siluvery wrote:
> Dropping it because it is for pre-production stepping.
> 
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index be39f7ad..a6ee0d3 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -77,12 +77,10 @@ static void skl_init_clock_gating(struct drm_device *dev)
>  
>  	if (INTEL_REVID(dev) <= SKL_REVID_B0) {
>  		/*
> -		 * WaDisableSDEUnitClockGating:skl
>  		 * WaSetGAPSunitClckGateDisable:skl
>  		 */
>  		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> -			   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
> -			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> +			   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE);

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Not that BXT has the same with another name
WaSetSDEunitClckGatingDisable. We seem to have the "wrong" name in the
code for BXT. Also it could apparently use an A0 check.

>  
>  		/* WaDisableVFUnitClockGating:skl */
>  		I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
> -- 
> 1.9.1
> 
> _______________________________________________
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-- 
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Re: [PATCH 09/12] drm/i915/skl: Remove WaSetGAPSunitClckGateDisable

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:43PM +0100, Arun Siluvery wrote:
> Dropping it because it is for pre-production stepping, also removed
> bit definition in i915_reg as it is not used anywhere else.
> 
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 1 -
>  drivers/gpu/drm/i915/intel_pm.c | 6 ------
>  2 files changed, 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 085ffa2..ef3d71f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6705,7 +6705,6 @@ enum skl_disp_power_wells {
>  #define GEN6_RSTCTL				0x9420
>  
>  #define GEN8_UCGCTL6				0x9430
> -#define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1<<24)
>  #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1<<14)
>  #define   GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1<<28)

I would keep the bit define.

> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index a6ee0d3..65c60bc 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -76,12 +76,6 @@ static void skl_init_clock_gating(struct drm_device *dev)
>  	gen9_init_clock_gating(dev);
>  
>  	if (INTEL_REVID(dev) <= SKL_REVID_B0) {
> -		/*
> -		 * WaSetGAPSunitClckGateDisable:skl
> -		 */
> -		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> -			   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE);
> -

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

But again BSpec is confused. It says BXT until B0 would also need this,
whereas w/a db doesn't have it fot BXT.

>  		/* WaDisableVFUnitClockGating:skl */
>  		I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
>  			   GEN6_VFUNIT_CLOCK_GATE_DISABLE);
> -- 
> 1.9.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 10/12] drm/i915/skl: Remove WaDisableVFUnitClockGating

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:44PM +0100, Arun Siluvery wrote:
> Dropping it because it is for pre-production stepping, also removed
> bit definition in i915_reg.h as it is not used anywhere else.
> 
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 1 -
>  drivers/gpu/drm/i915/intel_pm.c | 6 ------
>  2 files changed, 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ef3d71f..b510fdc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6688,7 +6688,6 @@ enum skl_disp_power_wells {
>  # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
>  
>  #define GEN6_UCGCTL2				0x9404
> -# define GEN6_VFUNIT_CLOCK_GATE_DISABLE			(1 << 31)

Again, I would keep the define.

>  # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)
>  # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE		(1 << 22)
>  # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 65c60bc..88acb3e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -75,12 +75,6 @@ static void skl_init_clock_gating(struct drm_device *dev)
>  
>  	gen9_init_clock_gating(dev);
>  
> -	if (INTEL_REVID(dev) <= SKL_REVID_B0) {
> -		/* WaDisableVFUnitClockGating:skl */
> -		I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
> -			   GEN6_VFUNIT_CLOCK_GATE_DISABLE);
> -	}
> -

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>  	if (INTEL_REVID(dev) <= SKL_REVID_D0) {
>  		/* WaDisableHDCInvalidation:skl */
>  		I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
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Re: [PATCH 03/12] drm/i915/gen9: Merge two WA as they part of same register

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:37PM +0100, Arun Siluvery wrote:
> Merge Wa4x4STCOptimizationDisable and WaDisablePartialResolveInVc to save
> an entry in WA array.
> 
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 6671800..ad16ef4 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -946,10 +946,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>  	}
>  
>  	/* Wa4x4STCOptimizationDisable:skl,bxt */
> -	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
> -
>  	/* WaDisablePartialResolveInVc:skl,bxt */
> -	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
> +	WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
> +					 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
>  
>  	/* WaCcsTlbPrefetchDisable:skl,bxt */
>  	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
_______________________________________________
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Re: [PATCH 01/12] drm/i915/gen9: Handle error returned by gen9_init_workarounds

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:35PM +0100, Arun Siluvery wrote:
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index fdff606..6671800 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1026,10 +1026,13 @@ static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
>  
>  static int skl_init_workarounds(struct intel_engine_cs *ring)
>  {
> +	int ret;
>  	struct drm_device *dev = ring->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	gen9_init_workarounds(ring);
> +	ret = gen9_init_workarounds(ring);
> +	if (ret)
> +		return ret;
>  
>  	/* WaDisablePowerCompilerClockGating:skl */
>  	if (INTEL_REVID(dev) == SKL_REVID_B0)
> @@ -1066,10 +1069,13 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
>  
>  static int bxt_init_workarounds(struct intel_engine_cs *ring)
>  {
> +	int ret;
>  	struct drm_device *dev = ring->dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> -	gen9_init_workarounds(ring);
> +	ret = gen9_init_workarounds(ring);
> +	if (ret)
> +		return ret;
>  
>  	/* WaDisableThreadStallDopClockGating:bxt */
>  	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Intel OTC
_______________________________________________
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Re: [PATCH 11/12] drm/i915/skl: Remove WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 02:33:45PM +0100, Arun Siluvery wrote:
> Dropping it as it is for pre-production stepping.
> 
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lrc.c        |  5 ++---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++++++++++------------
>  2 files changed, 13 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 256167b..e3baffd 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1352,9 +1352,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
>  	struct drm_device *dev = ring->dev;
>  	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
>  
> -	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> -	if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
> -	    (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
> +	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
> +	if (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)) {
>  		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
>  		wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
>  		wa_ctx_emit(batch, index,

Looks like we have some duplicated defines and whatnot. See
WaDisableMaskBasedCammingInRCC:skl,bxt in gen9_init_workarounds().
Maybe you can figure out why we have the same stuff in two places?

> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 963b3ca..d5fdbc8 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -931,18 +931,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>  				  GEN9_DG_MIRROR_FIX_ENABLE);
>  	}
>  
> -	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
> -	    (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
> -		/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> -		WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> -				  GEN9_RHWO_OPTIMIZATION_DISABLE);
> -		/*
> -		 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
> -		 * but we do that in per ctx batchbuffer as there is an issue
> -		 * with this register not getting restored on ctx restore
> -		 */
> -	}
> -
>  	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
>  	    IS_BROXTON(dev)) {
>  		/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
> @@ -1085,6 +1073,17 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
>  			GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
>  	}
>  
> +	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
> +	if (INTEL_REVID(dev) < BXT_REVID_B0) {
> +		WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> +				  GEN9_RHWO_OPTIMIZATION_DISABLE);
> +		/*
> +		 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
> +		 * but we do that in per ctx batchbuffer as there is an issue
> +		 * with this register not getting restored on ctx restore
> +		 */
> +	}
> +


>  	return 0;
>  }
>  
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 11/12] drm/i915/skl: Remove WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken

[Ville Syrjälä]

On Fri, Sep 25, 2015 at 09:34:13PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 25, 2015 at 02:33:45PM +0100, Arun Siluvery wrote:
> > Dropping it as it is for pre-production stepping.
> > 
> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_lrc.c        |  5 ++---
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++++++++++------------
> >  2 files changed, 13 insertions(+), 15 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> > index 256167b..e3baffd 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -1352,9 +1352,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
> >  	struct drm_device *dev = ring->dev;
> >  	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
> >  
> > -	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> > -	if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
> > -	    (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
> > +	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
> > +	if (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)) {
> >  		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
> >  		wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
> >  		wa_ctx_emit(batch, index,
> 
> Looks like we have some duplicated defines and whatnot. See
> WaDisableMaskBasedCammingInRCC:skl,bxt in gen9_init_workarounds().
> Maybe you can figure out why we have the same stuff in two places?

Oh and there's also 
WaDisablePixelMaskBasedCammingInRcpbe
which we seem to be missing...

> 
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 963b3ca..d5fdbc8 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -931,18 +931,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> >  				  GEN9_DG_MIRROR_FIX_ENABLE);
> >  	}
> >  
> > -	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
> > -	    (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
> > -		/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
> > -		WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> > -				  GEN9_RHWO_OPTIMIZATION_DISABLE);
> > -		/*
> > -		 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
> > -		 * but we do that in per ctx batchbuffer as there is an issue
> > -		 * with this register not getting restored on ctx restore
> > -		 */
> > -	}
> > -
> >  	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
> >  	    IS_BROXTON(dev)) {
> >  		/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
> > @@ -1085,6 +1073,17 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
> >  			GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> >  	}
> >  
> > +	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
> > +	if (INTEL_REVID(dev) < BXT_REVID_B0) {
> > +		WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> > +				  GEN9_RHWO_OPTIMIZATION_DISABLE);
> > +		/*
> > +		 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
> > +		 * but we do that in per ctx batchbuffer as there is an issue
> > +		 * with this register not getting restored on ctx restore
> > +		 */
> > +	}
> > +
> 
> 
> >  	return 0;
> >  }
> >  
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Intel OTC
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Re: [PATCH 11/12] drm/i915/skl: Remove WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken

[Arun Siluvery]

On 25/09/2015 19:34, Ville Syrjälä wrote:
> On Fri, Sep 25, 2015 at 02:33:45PM +0100, Arun Siluvery wrote:
>> Dropping it as it is for pre-production stepping.
>>
>> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_lrc.c        |  5 ++---
>>   drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++++++++++------------
>>   2 files changed, 13 insertions(+), 15 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
>> index 256167b..e3baffd 100644
>> --- a/drivers/gpu/drm/i915/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/intel_lrc.c
>> @@ -1352,9 +1352,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
>>   	struct drm_device *dev = ring->dev;
>>   	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
>>
>> -	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
>> -	if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) ||
>> -	    (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) {
>> +	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
>> +	if (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0)) {
>>   		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
>>   		wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
>>   		wa_ctx_emit(batch, index,
>
> Looks like we have some duplicated defines and whatnot. See
> WaDisableMaskBasedCammingInRCC:skl,bxt in gen9_init_workarounds().
> Maybe you can figure out why we have the same stuff in two places?
Yes I noticed that and I was not completely sure about 
WaDisableMaskBasedCammingInRCC. I will check again and update accordingly.

regards
Arun

>
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index 963b3ca..d5fdbc8 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -931,18 +931,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>>   				  GEN9_DG_MIRROR_FIX_ENABLE);
>>   	}
>>
>> -	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
>> -	    (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0)) {
>> -		/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
>> -		WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
>> -				  GEN9_RHWO_OPTIMIZATION_DISABLE);
>> -		/*
>> -		 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
>> -		 * but we do that in per ctx batchbuffer as there is an issue
>> -		 * with this register not getting restored on ctx restore
>> -		 */
>> -	}
>> -
>>   	if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) >= SKL_REVID_C0) ||
>>   	    IS_BROXTON(dev)) {
>>   		/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
>> @@ -1085,6 +1073,17 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring)
>>   			GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
>>   	}
>>
>> +	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
>> +	if (INTEL_REVID(dev) < BXT_REVID_B0) {
>> +		WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
>> +				  GEN9_RHWO_OPTIMIZATION_DISABLE);
>> +		/*
>> +		 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
>> +		 * but we do that in per ctx batchbuffer as there is an issue
>> +		 * with this register not getting restored on ctx restore
>> +		 */
>> +	}
>> +
>
>
>>   	return 0;
>>   }
>>
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>

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Re: [PATCH 04/12] drm/i915/gen9: Merge HALF_SLICE_CHICKEN3 WA

[Jani Nikula]

On Fri, 25 Sep 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Fri, Sep 25, 2015 at 02:33:38PM +0100, Arun Siluvery wrote:
>> Merge WaDisableSamplerPowerBypassForSOPingPong and another WA which has no name
>> as they are part of same register. This will save an entry in WA array.
>> 
>> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_ringbuffer.c | 18 ++++++++----------
>>  1 file changed, 8 insertions(+), 10 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index ad16ef4..963b3ca 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -914,9 +914,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>>  	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
>>  			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
>>  
>> -	/* Syncing dependencies between camera and graphics:skl,bxt */
>> -	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
>> -			  GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
>> +	/* WA: Syncing dependencies between camera and graphics:skl,bxt */
>> +	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
>> +	tmp = GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC;
>> +	if (IS_SKYLAKE(dev) ||
>> +	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
>> +		tmp |= GEN8_SAMPLER_POWER_BYPASS_DIS;
>> +	}
>> +	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, tmp);
>
> I really dislike these platform+stepping checks in the shared codepath.
> If there's any difference between the platforms, IMO the w/a should go into
> the per-platform function.

Agreed, also on a more generic level than these specific functions.

BR,
Jani.

>
>>  
>>  	if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) == SKL_REVID_A0 ||
>>  	    INTEL_REVID(dev) == SKL_REVID_B0)) ||
>> @@ -967,13 +972,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
>>  		tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
>>  	WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
>>  
>> -	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
>> -	if (IS_SKYLAKE(dev) ||
>> -	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
>> -		WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
>> -				  GEN8_SAMPLER_POWER_BYPASS_DIS);
>> -	}
>> -
>>  	/* WaDisableSTUnitPowerOptimization:skl,bxt */
>>  	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
>>  
>> -- 
>> 1.9.1
>> 
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> -- 
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Re: [PATCH 07/12] drm/i915/bxt: Update stepping check for WaDisableSDEUnitClockGating

[Imre Deak]

On pe, 2015-09-25 at 14:33 +0100, Arun Siluvery wrote:
> It is also applicable for B0.
> 
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9151a2b..be39f7ad 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -121,8 +121,10 @@ static void bxt_init_clock_gating(struct drm_device *dev)
>  	gen9_init_clock_gating(dev);
>  
>  	/* WaDisableSDEUnitClockGating:bxt */
> -	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> -		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> +	if (INTEL_REVID(dev) >= BXT_REVID_A0) {

This check looks redundant.

> +		I915_WRITE(GEN8_UCGCTL6, (I915_READ(GEN8_UCGCTL6) |
> +					  GEN8_SDEUNIT_CLOCK_GATE_DISABLE));
> +	}
>  
>  	/* WaSetHDCunitClckGatingDisable:bxt */
>  	/* WaSetHdcUnitClockGatingDisableInUcgctl6:bxt */


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Re: [PATCH 07/12] drm/i915/bxt: Update stepping check for WaDisableSDEUnitClockGating

[Arun Siluvery]

On 28/09/2015 12:06, Imre Deak wrote:
> On pe, 2015-09-25 at 14:33 +0100, Arun Siluvery wrote:
>> It is also applicable for B0.
>>
>> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_pm.c | 6 ++++--
>>   1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 9151a2b..be39f7ad 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -121,8 +121,10 @@ static void bxt_init_clock_gating(struct drm_device *dev)
>>   	gen9_init_clock_gating(dev);
>>
>>   	/* WaDisableSDEUnitClockGating:bxt */
>> -	I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
>> -		   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>> +	if (INTEL_REVID(dev) >= BXT_REVID_A0) {
>
> This check looks redundant.
>
Yes, I am removing it in v2.

regards
Arun

>> +		I915_WRITE(GEN8_UCGCTL6, (I915_READ(GEN8_UCGCTL6) |
>> +					  GEN8_SDEUNIT_CLOCK_GATE_DISABLE));
>> +	}
>>
>>   	/* WaSetHDCunitClckGatingDisable:bxt */
>>   	/* WaSetHdcUnitClockGatingDisableInUcgctl6:bxt */
>
>
>

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Re: [PATCH 00/12] Gen9: Changes to add/merge/update/remove WA

[Arun Siluvery]

On 25/09/2015 14:33, Arun Siluvery wrote:
> Changes that add new WA, merge WA that are applied for the same register,
> update stepping checks and remove pre-production ones .
>
> Arun Siluvery (12):
>    drm/i915/gen9: Handle error returned by gen9_init_workarounds
>    drm/i915/gen9: Add WaOCLCoherentLineFlush
>    drm/i915/gen9: Merge two WA as they part of same register
>    drm/i915/gen9: Merge HALF_SLICE_CHICKEN3 WA
>    drm/i915/bxt: update WaSetHDCunitClckGatingDisable
>    drm/i915/bxt: Add WaStoreMultiplePTEenable name
>    drm/i915/bxt: Update stepping check for WaDisableSDEUnitClockGating
>    drm/i915/skl: Remove WaDisableSDEUnitClockGating
>    drm/i915/skl: Remove WaSetGAPSunitClckGateDisable
>    drm/i915/skl: Remove WaDisableVFUnitClockGating
>    drm/i915/skl: Remove
>      WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken
>    drm/i915:skl: Remove WaDisablePowerCompilerClockGating
>
>   drivers/gpu/drm/i915/i915_reg.h         |  2 --
>   drivers/gpu/drm/i915/intel_lrc.c        |  5 ++-
>   drivers/gpu/drm/i915/intel_pm.c         | 48 ++++++++++++--------------
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 61 ++++++++++++++++-----------------
>   4 files changed, 52 insertions(+), 64 deletions(-)
>

Hi Daniel,

Some of the patches in this series are reviewed but I am seeing some 
inconsistency with patch 9 (WaSetGAPSunitClckGateDisable) and in the 
process of getting it clarified. I will re-post all patches again with 
r-b tags for appropriate patches.

regards
Arun

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Re: [PATCH 01/12] drm/i915/gen9: Handle error returned by gen9_init_workarounds

[Daniel Vetter]

On Fri, Sep 25, 2015 at 08:47:55PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 25, 2015 at 02:33:35PM +0100, Arun Siluvery wrote:
> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Queued for -next, thanks for the patch.
-Daniel

> 
> > ---
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++++++++--
> >  1 file changed, 8 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index fdff606..6671800 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -1026,10 +1026,13 @@ static int skl_tune_iz_hashing(struct intel_engine_cs *ring)
> >  
> >  static int skl_init_workarounds(struct intel_engine_cs *ring)
> >  {
> > +	int ret;
> >  	struct drm_device *dev = ring->dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  
> > -	gen9_init_workarounds(ring);
> > +	ret = gen9_init_workarounds(ring);
> > +	if (ret)
> > +		return ret;
> >  
> >  	/* WaDisablePowerCompilerClockGating:skl */
> >  	if (INTEL_REVID(dev) == SKL_REVID_B0)
> > @@ -1066,10 +1069,13 @@ static int skl_init_workarounds(struct intel_engine_cs *ring)
> >  
> >  static int bxt_init_workarounds(struct intel_engine_cs *ring)
> >  {
> > +	int ret;
> >  	struct drm_device *dev = ring->dev;
> >  	struct drm_i915_private *dev_priv = dev->dev_private;
> >  
> > -	gen9_init_workarounds(ring);
> > +	ret = gen9_init_workarounds(ring);
> > +	if (ret)
> > +		return ret;
> >  
> >  	/* WaDisableThreadStallDopClockGating:bxt */
> >  	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
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> Intel OTC
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
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Re: [PATCH 03/12] drm/i915/gen9: Merge two WA as they part of same register

[Daniel Vetter]

On Fri, Sep 25, 2015 at 08:47:11PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 25, 2015 at 02:33:37PM +0100, Arun Siluvery wrote:
> > Merge Wa4x4STCOptimizationDisable and WaDisablePartialResolveInVc to save
> > an entry in WA array.
> > 
> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Queued for -next, thanks for the patch.
-Daniel

> 
> > ---
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 5 ++---
> >  1 file changed, 2 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 6671800..ad16ef4 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -946,10 +946,9 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> >  	}
> >  
> >  	/* Wa4x4STCOptimizationDisable:skl,bxt */
> > -	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
> > -
> >  	/* WaDisablePartialResolveInVc:skl,bxt */
> > -	WA_SET_BIT_MASKED(CACHE_MODE_1, GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
> > +	WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
> > +					 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
> >  
> >  	/* WaCcsTlbPrefetchDisable:skl,bxt */
> >  	WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
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> Intel OTC
> _______________________________________________
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Re: [PATCH 04/12] drm/i915/gen9: Merge HALF_SLICE_CHICKEN3 WA

[Daniel Vetter]

On Mon, Sep 28, 2015 at 11:47:06AM +0300, Jani Nikula wrote:
> On Fri, 25 Sep 2015, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Fri, Sep 25, 2015 at 02:33:38PM +0100, Arun Siluvery wrote:
> >> Merge WaDisableSamplerPowerBypassForSOPingPong and another WA which has no name
> >> as they are part of same register. This will save an entry in WA array.
> >> 
> >> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/intel_ringbuffer.c | 18 ++++++++----------
> >>  1 file changed, 8 insertions(+), 10 deletions(-)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> >> index ad16ef4..963b3ca 100644
> >> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> >> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> >> @@ -914,9 +914,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
> >>  	WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> >>  			  PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
> >>  
> >> -	/* Syncing dependencies between camera and graphics:skl,bxt */
> >> -	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> >> -			  GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
> >> +	/* WA: Syncing dependencies between camera and graphics:skl,bxt */
> >> +	/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
> >> +	tmp = GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC;
> >> +	if (IS_SKYLAKE(dev) ||
> >> +	    (IS_BROXTON(dev) && INTEL_REVID(dev) <= BXT_REVID_B0)) {
> >> +		tmp |= GEN8_SAMPLER_POWER_BYPASS_DIS;
> >> +	}
> >> +	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, tmp);
> >
> > I really dislike these platform+stepping checks in the shared codepath.
> > If there's any difference between the platforms, IMO the w/a should go into
> > the per-platform function.
> 
> Agreed, also on a more generic level than these specific functions.

Concurred, sharing code just to reduce the line count is a bad idea, code
should only be shared if it actually does the same thing. Better to be
verbose than accidentally break things.
-Daniel
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Re: [PATCH 06/12] drm/i915/bxt: Add WaStoreMultiplePTEenable name

[Daniel Vetter]

On Fri, Sep 25, 2015 at 08:34:19PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 25, 2015 at 02:33:40PM +0100, Arun Siluvery wrote:
> > Updated WA with the name.
> > 
> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Queued for -next, thanks for the patch.
-Daniel
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Re: [PATCH 08/12] drm/i915/skl: Remove WaDisableSDEUnitClockGating

[Daniel Vetter]

On Fri, Sep 25, 2015 at 08:39:39PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 25, 2015 at 02:33:42PM +0100, Arun Siluvery wrote:
> > Dropping it because it is for pre-production stepping.
> > 
> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 4 +---
> >  1 file changed, 1 insertion(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index be39f7ad..a6ee0d3 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -77,12 +77,10 @@ static void skl_init_clock_gating(struct drm_device *dev)
> >  
> >  	if (INTEL_REVID(dev) <= SKL_REVID_B0) {
> >  		/*
> > -		 * WaDisableSDEUnitClockGating:skl
> >  		 * WaSetGAPSunitClckGateDisable:skl
> >  		 */
> >  		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
> > -			   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
> > -			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> > +			   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE);
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Queued for -next, thanks for the patch.
-Daniel

> 
> Not that BXT has the same with another name
> WaSetSDEunitClckGatingDisable. We seem to have the "wrong" name in the
> code for BXT. Also it could apparently use an A0 check.
> 
> >  
> >  		/* WaDisableVFUnitClockGating:skl */
> >  		I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
> > -- 
> > 1.9.1
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
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Re: [PATCH 10/12] drm/i915/skl: Remove WaDisableVFUnitClockGating

[Daniel Vetter]

On Fri, Sep 25, 2015 at 08:45:25PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 25, 2015 at 02:33:44PM +0100, Arun Siluvery wrote:
> > Dropping it because it is for pre-production stepping, also removed
> > bit definition in i915_reg.h as it is not used anywhere else.
> > 
> > Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 1 -
> >  drivers/gpu/drm/i915/intel_pm.c | 6 ------
> >  2 files changed, 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index ef3d71f..b510fdc 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6688,7 +6688,6 @@ enum skl_disp_power_wells {
> >  # define GEN6_CSUNIT_CLOCK_GATE_DISABLE			(1 << 7)
> >  
> >  #define GEN6_UCGCTL2				0x9404
> > -# define GEN6_VFUNIT_CLOCK_GATE_DISABLE			(1 << 31)
> 
> Again, I would keep the define.

I kept them both (but forgot to mention in my previous reply).

> 
> >  # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE		(1 << 30)
> >  # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE		(1 << 22)
> >  # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE		(1 << 13)
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 65c60bc..88acb3e 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -75,12 +75,6 @@ static void skl_init_clock_gating(struct drm_device *dev)
> >  
> >  	gen9_init_clock_gating(dev);
> >  
> > -	if (INTEL_REVID(dev) <= SKL_REVID_B0) {
> > -		/* WaDisableVFUnitClockGating:skl */
> > -		I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
> > -			   GEN6_VFUNIT_CLOCK_GATE_DISABLE);
> > -	}
> > -
> 
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Queued for -next, thanks for the patch.
-Daniel
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Re: [PATCH 00/12] Gen9: Changes to add/merge/update/remove WA

[Daniel Vetter]

On Mon, Sep 28, 2015 at 12:21:36PM +0100, Arun Siluvery wrote:
> On 25/09/2015 14:33, Arun Siluvery wrote:
> >Changes that add new WA, merge WA that are applied for the same register,
> >update stepping checks and remove pre-production ones .
> >
> >Arun Siluvery (12):
> >   drm/i915/gen9: Handle error returned by gen9_init_workarounds
> >   drm/i915/gen9: Add WaOCLCoherentLineFlush
> >   drm/i915/gen9: Merge two WA as they part of same register
> >   drm/i915/gen9: Merge HALF_SLICE_CHICKEN3 WA
> >   drm/i915/bxt: update WaSetHDCunitClckGatingDisable
> >   drm/i915/bxt: Add WaStoreMultiplePTEenable name
> >   drm/i915/bxt: Update stepping check for WaDisableSDEUnitClockGating
> >   drm/i915/skl: Remove WaDisableSDEUnitClockGating
> >   drm/i915/skl: Remove WaSetGAPSunitClckGateDisable
> >   drm/i915/skl: Remove WaDisableVFUnitClockGating
> >   drm/i915/skl: Remove
> >     WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken
> >   drm/i915:skl: Remove WaDisablePowerCompilerClockGating
> >
> >  drivers/gpu/drm/i915/i915_reg.h         |  2 --
> >  drivers/gpu/drm/i915/intel_lrc.c        |  5 ++-
> >  drivers/gpu/drm/i915/intel_pm.c         | 48 ++++++++++++--------------
> >  drivers/gpu/drm/i915/intel_ringbuffer.c | 61 ++++++++++++++++-----------------
> >  4 files changed, 52 insertions(+), 64 deletions(-)
> >
> 
> Hi Daniel,
> 
> Some of the patches in this series are reviewed but I am seeing some
> inconsistency with patch 9 (WaSetGAPSunitClckGateDisable) and in the process
> of getting it clarified. I will re-post all patches again with r-b tags for
> appropriate patches.

I just pulled in a bunch which were reviewed (including minor bikesheds to
keep #defines on 2 patches). Please don't resend those. But yes please
chase the bspec inconsistencies and please file bspec bugs where the docs
are wrong.
-Daniel
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Re: [PATCH 02/12] drm/i915/gen9: Add WaOCLCoherentLineFlush

[Arun Siluvery]

On 25/09/2015 18:09, Ville Syrjälä wrote:
> On Fri, Sep 25, 2015 at 02:33:36PM +0100, Arun Siluvery wrote:
>> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index ab5ac5e..093a5e4 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -63,6 +63,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
>>   	/* WaDisableKillLogic:bxt,skl */
>>   	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
>>   		   ECOCHK_DIS_TLB);
>> +
>> +	/* WaOCLCoherentLineFlush:skl,bxt */
>> +	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
>> +				    GEN8_LQSC_FLUSH_COHERENT_LINES));
>
> According to Bspec + w/a db this should be done for BDW too (actually
> BSpec shows it for BDW only?). If that's the case, then we should be
> able to kill gen8_emit_flush_coherentl3_wa(), no? Well, as long as
> someone goes and adds the DC flush to the normal post batch flush.
>
Yes this is applicable for BDW also but I wanted to keep only Gen9 
patches in this series. I will send separate patch for BDW.
We would still need gen8_emit_flush_coherentl3_wa() because WA requires 
that the flush need to happen from the WA batch itself during context 
switch.

regards
Arun

>>   }
>>
>>   static void skl_init_clock_gating(struct drm_device *dev)
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>

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Re: [PATCH 02/12] drm/i915/gen9: Add WaOCLCoherentLineFlush

[Ville Syrjälä]

On Mon, Sep 28, 2015 at 04:51:52PM +0100, Arun Siluvery wrote:
> On 25/09/2015 18:09, Ville Syrjälä wrote:
> > On Fri, Sep 25, 2015 at 02:33:36PM +0100, Arun Siluvery wrote:
> >> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/intel_pm.c | 4 ++++
> >>   1 file changed, 4 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >> index ab5ac5e..093a5e4 100644
> >> --- a/drivers/gpu/drm/i915/intel_pm.c
> >> +++ b/drivers/gpu/drm/i915/intel_pm.c
> >> @@ -63,6 +63,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
> >>   	/* WaDisableKillLogic:bxt,skl */
> >>   	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
> >>   		   ECOCHK_DIS_TLB);
> >> +
> >> +	/* WaOCLCoherentLineFlush:skl,bxt */
> >> +	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
> >> +				    GEN8_LQSC_FLUSH_COHERENT_LINES));
> >
> > According to Bspec + w/a db this should be done for BDW too (actually
> > BSpec shows it for BDW only?). If that's the case, then we should be
> > able to kill gen8_emit_flush_coherentl3_wa(), no? Well, as long as
> > someone goes and adds the DC flush to the normal post batch flush.
> >
> Yes this is applicable for BDW also but I wanted to keep only Gen9 
> patches in this series. I will send separate patch for BDW.
> We would still need gen8_emit_flush_coherentl3_wa() because WA requires 
> that the flush need to happen from the WA batch itself during context 
> switch.

If we already flush all coherent lines out from DC after each batch,
how can there still be coherent lines in the DC on a context switch?

But spelling that out made me think that mid-batch preemption would
still need it I suppose. But w/o preemption I see no reason why it
would be needed.

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH 02/12] drm/i915/gen9: Add WaOCLCoherentLineFlush

[Arun Siluvery]

On 28/09/2015 17:02, Ville Syrjälä wrote:
> On Mon, Sep 28, 2015 at 04:51:52PM +0100, Arun Siluvery wrote:
>> On 25/09/2015 18:09, Ville Syrjälä wrote:
>>> On Fri, Sep 25, 2015 at 02:33:36PM +0100, Arun Siluvery wrote:
>>>> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>>>>    1 file changed, 4 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>>> index ab5ac5e..093a5e4 100644
>>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>>> @@ -63,6 +63,10 @@ static void gen9_init_clock_gating(struct drm_device *dev)
>>>>    	/* WaDisableKillLogic:bxt,skl */
>>>>    	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
>>>>    		   ECOCHK_DIS_TLB);
>>>> +
>>>> +	/* WaOCLCoherentLineFlush:skl,bxt */
>>>> +	I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
>>>> +				    GEN8_LQSC_FLUSH_COHERENT_LINES));
>>>
>>> According to Bspec + w/a db this should be done for BDW too (actually
>>> BSpec shows it for BDW only?). If that's the case, then we should be
>>> able to kill gen8_emit_flush_coherentl3_wa(), no? Well, as long as
>>> someone goes and adds the DC flush to the normal post batch flush.
>>>
>> Yes this is applicable for BDW also but I wanted to keep only Gen9
>> patches in this series. I will send separate patch for BDW.
>> We would still need gen8_emit_flush_coherentl3_wa() because WA requires
>> that the flush need to happen from the WA batch itself during context
>> switch.
>
> If we already flush all coherent lines out from DC after each batch,
> how can there still be coherent lines in the DC on a context switch?
>
> But spelling that out made me think that mid-batch preemption would
> still need it I suppose. But w/o preemption I see no reason why it
> would be needed.
>
Yes, this is to account preemption case (sorry I should've mentioned 
earlier). Most of the workarounds in WA batch are to account for 
preemption related issues.

regards
Arun


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