[PATCH 1/2] dt: update Tegra XUSB padctl binding for Tegra210

[PATCH 1/2] dt: update Tegra XUSB padctl binding for Tegra210

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Tegra210 introduces some new options for pad muxing. Document these in
the XUSB padctl binding.

Be more explicit about the valid values for the compatible property, and
in particular point out that Tegra210 isn't fully backwards-compatible
with Tegra124, since some registers have moved about.

Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../pinctrl/nvidia,tegra124-xusb-padctl.txt        | 34 +++++++++++++++-------
 1 file changed, 24 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt
index 30676ded85bb..3952d893635c 100644
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt
@@ -13,9 +13,12 @@ how to describe and reference PHYs in device trees.
 
 Required properties:
 --------------------
-- compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
-  Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
-  "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
+- compatible: Valid options are:
+  Tegra124: "nvidia,tegra124-xusb-padctl".
+  Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia-tegra124-xusb-padctl".
+  Tegra210: "nvidia-tegra210-xusb-padctl".
+    Note that Tegra210 is not backwards-compatible with Tegra124 due to some
+    registers having been moved.
 - reg: Physical base address and length of the controller's registers.
 - resets: Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
@@ -45,18 +48,21 @@ Unspecified is represented as an absent property, and off/on are represented
 as integer values 0 and 1.
 
 Required properties:
-- nvidia,lanes: An array of strings. Each string is the name of a lane.
+- nvidia,lanes: An array of strings. Each string is the name of a lane (pad).
+  Valid values for lanes are listed below.
 
 Optional properties:
-- nvidia,function: A string that is the name of the function (pad) that the
-  pin or group should be assigned to. Valid values for function names are
-  listed below.
+- nvidia,function: A string that is the name of the function (IO controller)
+  that the pin or group should be assigned to. Valid values for function names
+  are  listed below.
 - nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes)
 
 Note that not all of these properties are valid for all lanes. Lanes can be
 divided into three groups:
 
-  - otg-0, otg-1, otg-2:
+  - otg-0, otg-1, otg-2, otg-3, usb2-bias:
+
+    (otg-3, usb2-bias are valid on Tegra210 only.)
 
     Valid functions for this group are: "snps", "xusb", "uart", "rsvd".
 
@@ -64,13 +70,21 @@ divided into three groups:
 
   - ulpi-0, hsic-0, hsic-1:
 
+    (ulpi-0 is valid on Tegra124 and Tegra132 only.)
+
     Valid functions for this group are: "snps", "xusb".
 
     The nvidia,iddq property does not apply to this group.
 
-  - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sata-0:
+  - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6, sata-0:
+
+    (pcie-5, pcie-6 are valid on Tegra210 only.)
+
+    On Tegra124, Tegra132, valid functions for this group are: "pcie", "usb3",
+    "sata", "rsvd".
 
-    Valid functions for this group are: "pcie", "usb3", "sata", "rsvd".
+    On Tegra210, valid functions for this group are "pcie-x1", "usb3",
+    "sata", "pcie-x4".
 
 
 Example:
-- 
1.9.1

[PATCH 1/2] dt: update Tegra XUSB padctl binding for Tegra210

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Tegra210 introduces some new options for pad muxing. Document these in
the XUSB padctl binding.

Be more explicit about the valid values for the compatible property, and
in particular point out that Tegra210 isn't fully backwards-compatible
with Tegra124, since some registers have moved about.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 .../pinctrl/nvidia,tegra124-xusb-padctl.txt        | 34 +++++++++++++++-------
 1 file changed, 24 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt
index 30676ded85bb..3952d893635c 100644
--- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt
@@ -13,9 +13,12 @@ how to describe and reference PHYs in device trees.
 
 Required properties:
 --------------------
-- compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
-  Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
-  "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
+- compatible: Valid options are:
+  Tegra124: "nvidia,tegra124-xusb-padctl".
+  Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia-tegra124-xusb-padctl".
+  Tegra210: "nvidia-tegra210-xusb-padctl".
+    Note that Tegra210 is not backwards-compatible with Tegra124 due to some
+    registers having been moved.
 - reg: Physical base address and length of the controller's registers.
 - resets: Must contain an entry for each entry in reset-names.
   See ../reset/reset.txt for details.
@@ -45,18 +48,21 @@ Unspecified is represented as an absent property, and off/on are represented
 as integer values 0 and 1.
 
 Required properties:
-- nvidia,lanes: An array of strings. Each string is the name of a lane.
+- nvidia,lanes: An array of strings. Each string is the name of a lane (pad).
+  Valid values for lanes are listed below.
 
 Optional properties:
-- nvidia,function: A string that is the name of the function (pad) that the
-  pin or group should be assigned to. Valid values for function names are
-  listed below.
+- nvidia,function: A string that is the name of the function (IO controller)
+  that the pin or group should be assigned to. Valid values for function names
+  are  listed below.
 - nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes)
 
 Note that not all of these properties are valid for all lanes. Lanes can be
 divided into three groups:
 
-  - otg-0, otg-1, otg-2:
+  - otg-0, otg-1, otg-2, otg-3, usb2-bias:
+
+    (otg-3, usb2-bias are valid on Tegra210 only.)
 
     Valid functions for this group are: "snps", "xusb", "uart", "rsvd".
 
@@ -64,13 +70,21 @@ divided into three groups:
 
   - ulpi-0, hsic-0, hsic-1:
 
+    (ulpi-0 is valid on Tegra124 and Tegra132 only.)
+
     Valid functions for this group are: "snps", "xusb".
 
     The nvidia,iddq property does not apply to this group.
 
-  - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sata-0:
+  - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6, sata-0:
+
+    (pcie-5, pcie-6 are valid on Tegra210 only.)
+
+    On Tegra124, Tegra132, valid functions for this group are: "pcie", "usb3",
+    "sata", "rsvd".
 
-    Valid functions for this group are: "pcie", "usb3", "sata", "rsvd".
+    On Tegra210, valid functions for this group are "pcie-x1", "usb3",
+    "sata", "pcie-x4".
 
 
 Example:
-- 
1.9.1

[PATCH 2/2] dt: update Tegra PCIe binding for Tegra210

[Stephen Warren]

From: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>

Reword the description of the ranges property so it is correct
irrespective of how many #address-cells the PCI node's parent uses.

Be more explicit about the valid values for the compatible property, and
in particular point out that Tegra210 isn't fully backwards-compatible due
to the introduction of some HW bugs whose workarounds are not present in
drivers written solely for previous chips. with Tegra124,

Still "TODO" is to fill in a complete "Power supplies for Tegra210"
section. My main use-case for the binding is U-Boot, which doesn't use
regulator bindings at present, so I have not yet researched this aspect
of the hardware.

Signed-off-by: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
 .../bindings/pci/nvidia,tegra20-pcie.txt           | 27 +++++++++++++++-------
 1 file changed, 19 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
index 75321ae23c08..3d92934a079c 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
@@ -1,10 +1,15 @@
 NVIDIA Tegra PCIe controller
 
 Required properties:
-- compatible: For Tegra20, must contain "nvidia,tegra20-pcie".  For Tegra30,
-  "nvidia,tegra30-pcie".  For Tegra124, must contain "nvidia,tegra124-pcie".
-  Otherwise, must contain "nvidia,<chip>-pcie", plus one of the above, where
-  <chip> is tegra132 or tegra210.
+- compatible: Valid options are:
+  Tegra20: "nvidia,tegra20-pcie".
+  Tegra30: "nvidia,tegra30-pcie".
+  Tegra124: "nvidia,tegra124-pcie".
+  Tegra132: "nvidia,tegra132-pcie", "nvidia,tegra124-pcie".
+  Tegra210: "nvidia,tegra210-pcie".
+    Note that Tegra210 is not backwards-compatible with Tegra124 due to the
+    introduction of some HW bugs whose workarounds are not present in drivers
+    written solely for previous chips.
 - device_type: Must be "pci"
 - reg: A list of physical base address and length for each set of controller
   registers. Must contain an entry for each entry in the reg-names property.
@@ -27,10 +32,16 @@ Required properties:
     CPU address space
 - #size-cells: Size representation for root ports (must be 2)
 - ranges: Describes the translation of addresses for root ports and standard
-  PCI regions. The entries must be 6 cells each, where the first three cells
-  correspond to the address as described for the #address-cells property
-  above, the fourth cell is the physical CPU address to translate to and the
-  fifth and six cells are as described for the #size-cells property above.
+  PCI regions. The entries must be (na_pcie + na_parent + ns_pcie) cells each,
+  where:
+    na_pcie refers to #address-cells in the PCIe controller,
+    na_parent refers to #address-cells in the PCIe controller's parent node,
+    ns_pcie refers to #size-cells in the PCIe controller,
+  The first na_pcie cells correspond to the address as described for the
+  #address-cells property. The next na_parent cells contain the physical CPU
+  address to translate to and the final ns_pcie cells are as described for the
+  #size-cells property above.
+  Multiple entries must be present:
   - The first two entries are expected to translate the addresses for the root
     port registers, which are referenced by the assigned-addresses property of
     the root port nodes (see below).
-- 
1.9.1

[PATCH 2/2] dt: update Tegra PCIe binding for Tegra210

[Stephen Warren]

From: Stephen Warren <swarren@nvidia.com>

Reword the description of the ranges property so it is correct
irrespective of how many #address-cells the PCI node's parent uses.

Be more explicit about the valid values for the compatible property, and
in particular point out that Tegra210 isn't fully backwards-compatible due
to the introduction of some HW bugs whose workarounds are not present in
drivers written solely for previous chips. with Tegra124,

Still "TODO" is to fill in a complete "Power supplies for Tegra210"
section. My main use-case for the binding is U-Boot, which doesn't use
regulator bindings at present, so I have not yet researched this aspect
of the hardware.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 .../bindings/pci/nvidia,tegra20-pcie.txt           | 27 +++++++++++++++-------
 1 file changed, 19 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
index 75321ae23c08..3d92934a079c 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
@@ -1,10 +1,15 @@
 NVIDIA Tegra PCIe controller
 
 Required properties:
-- compatible: For Tegra20, must contain "nvidia,tegra20-pcie".  For Tegra30,
-  "nvidia,tegra30-pcie".  For Tegra124, must contain "nvidia,tegra124-pcie".
-  Otherwise, must contain "nvidia,<chip>-pcie", plus one of the above, where
-  <chip> is tegra132 or tegra210.
+- compatible: Valid options are:
+  Tegra20: "nvidia,tegra20-pcie".
+  Tegra30: "nvidia,tegra30-pcie".
+  Tegra124: "nvidia,tegra124-pcie".
+  Tegra132: "nvidia,tegra132-pcie", "nvidia,tegra124-pcie".
+  Tegra210: "nvidia,tegra210-pcie".
+    Note that Tegra210 is not backwards-compatible with Tegra124 due to the
+    introduction of some HW bugs whose workarounds are not present in drivers
+    written solely for previous chips.
 - device_type: Must be "pci"
 - reg: A list of physical base address and length for each set of controller
   registers. Must contain an entry for each entry in the reg-names property.
@@ -27,10 +32,16 @@ Required properties:
     CPU address space
 - #size-cells: Size representation for root ports (must be 2)
 - ranges: Describes the translation of addresses for root ports and standard
-  PCI regions. The entries must be 6 cells each, where the first three cells
-  correspond to the address as described for the #address-cells property
-  above, the fourth cell is the physical CPU address to translate to and the
-  fifth and six cells are as described for the #size-cells property above.
+  PCI regions. The entries must be (na_pcie + na_parent + ns_pcie) cells each,
+  where:
+    na_pcie refers to #address-cells in the PCIe controller,
+    na_parent refers to #address-cells in the PCIe controller's parent node,
+    ns_pcie refers to #size-cells in the PCIe controller,
+  The first na_pcie cells correspond to the address as described for the
+  #address-cells property. The next na_parent cells contain the physical CPU
+  address to translate to and the final ns_pcie cells are as described for the
+  #size-cells property above.
+  Multiple entries must be present:
   - The first two entries are expected to translate the addresses for the root
     port registers, which are referenced by the assigned-addresses property of
     the root port nodes (see below).
-- 
1.9.1