[PATCH v2 0/5] Armada 38x SDHCI driver improvements

[PATCH v2 0/5] Armada 38x SDHCI driver improvements

[Marcin Wojtas]

Hi,

I send a second round of remaining A38x SDHCI patches. After lots of
discussions I changed card detection mechanism to SW polling in order
to satisfy all A388-GP revisions. Any remarks will be welcome.

Best regards,
Marcin

Changes:
v1 -> v2
* enable SW polling as card detection
* in resume function change condition for mbus windows reconfiguration 

Marcin Wojtas (5):
  mmc: sdhci-pxav3: enable proper resuming on Armada 38x SoC
  mmc: sdhci-pxav3: enable usage of DAT3 pin as HW card detect
  ARM: mvebu: set SW polling as SDHCI card detection on A388-GP
  mmc: sdhci: add init_card callback to sdhci
  mmc: sdhci-pxav3: enable modifying MMC_CARD bit during card
    initialization

 .../devicetree/bindings/mmc/sdhci-pxa.txt          |  5 ++
 arch/arm/boot/dts/armada-388-gp.dts                |  2 +-
 drivers/mmc/host/sdhci-pxav3.c                     | 94 +++++++++++++++++-----
 drivers/mmc/host/sdhci.c                           | 14 +++-
 drivers/mmc/host/sdhci.h                           |  4 +
 5 files changed, 95 insertions(+), 24 deletions(-)

-- 
1.8.3.1

[PATCH v2 0/5] Armada 38x SDHCI driver improvements

[Marcin Wojtas]

Hi,

I send a second round of remaining A38x SDHCI patches. After lots of
discussions I changed card detection mechanism to SW polling in order
to satisfy all A388-GP revisions. Any remarks will be welcome.

Best regards,
Marcin

Changes:
v1 -> v2
* enable SW polling as card detection
* in resume function change condition for mbus windows reconfiguration 

Marcin Wojtas (5):
  mmc: sdhci-pxav3: enable proper resuming on Armada 38x SoC
  mmc: sdhci-pxav3: enable usage of DAT3 pin as HW card detect
  ARM: mvebu: set SW polling as SDHCI card detection on A388-GP
  mmc: sdhci: add init_card callback to sdhci
  mmc: sdhci-pxav3: enable modifying MMC_CARD bit during card
    initialization

 .../devicetree/bindings/mmc/sdhci-pxa.txt          |  5 ++
 arch/arm/boot/dts/armada-388-gp.dts                |  2 +-
 drivers/mmc/host/sdhci-pxav3.c                     | 94 +++++++++++++++++-----
 drivers/mmc/host/sdhci.c                           | 14 +++-
 drivers/mmc/host/sdhci.h                           |  4 +
 5 files changed, 95 insertions(+), 24 deletions(-)

-- 
1.8.3.1

[PATCH v2 1/5] mmc: sdhci-pxav3: enable proper resuming on Armada 38x SoC

[Marcin Wojtas]

When resuming from suspend on Armada 38x SoC MBus windows have to be
re-configured and for that purpose mv_conf_mbus_windows function needed
rework. MBus windows register base address obtaining was moved to
armada_38x_quirks function in order to be kept in pxa global structure,
because it is used during a resume.

This commit fixes resuming from suspend by calling MBus windows
configuration routine and therefore enabling proper DMA operation.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 drivers/mmc/host/sdhci-pxav3.c | 38 +++++++++++++++++++-------------------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index f5edf9d..76b9a70 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -63,6 +63,7 @@ struct sdhci_pxa {
 	struct clk *clk_io;
 	u8	power_mode;
 	void __iomem *sdio3_conf_reg;
+	void __iomem *mbus_win_regs;
 };
 
 /*
@@ -81,30 +82,16 @@ struct sdhci_pxa {
 #define SDIO3_CONF_CLK_INV	BIT(0)
 #define SDIO3_CONF_SD_FB_CLK	BIT(2)
 
-static int mv_conf_mbus_windows(struct platform_device *pdev,
+static int mv_conf_mbus_windows(struct device *dev, void __iomem *regs,
 				const struct mbus_dram_target_info *dram)
 {
 	int i;
-	void __iomem *regs;
-	struct resource *res;
 
 	if (!dram) {
-		dev_err(&pdev->dev, "no mbus dram info\n");
-		return -EINVAL;
-	}
-
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-	if (!res) {
-		dev_err(&pdev->dev, "cannot get mbus registers\n");
+		dev_err(dev, "no mbus dram info\n");
 		return -EINVAL;
 	}
 
-	regs = ioremap(res->start, resource_size(res));
-	if (!regs) {
-		dev_err(&pdev->dev, "cannot map mbus registers\n");
-		return -ENOMEM;
-	}
-
 	for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
 		writel(0, regs + SDHCI_WINDOW_CTRL(i));
 		writel(0, regs + SDHCI_WINDOW_BASE(i));
@@ -122,8 +109,6 @@ static int mv_conf_mbus_windows(struct platform_device *pdev,
 		writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
 	}
 
-	iounmap(regs);
-
 	return 0;
 }
 
@@ -135,6 +120,14 @@ static int armada_38x_quirks(struct platform_device *pdev,
 	struct sdhci_pxa *pxa = pltfm_host->priv;
 	struct resource *res;
 
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mbus");
+	pxa->mbus_win_regs = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(pxa->mbus_win_regs)) {
+		dev_err(mmc_dev(host->mmc),
+			"failed to obtain MBus windows register base\n");
+		return PTR_ERR(pxa->mbus_win_regs);
+	}
+
 	host->quirks &= ~SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
 	host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
@@ -403,7 +396,8 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
 		ret = armada_38x_quirks(pdev, host);
 		if (ret < 0)
 			goto err_mbus_win;
-		ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
+		ret = mv_conf_mbus_windows(&pdev->dev, pxa->mbus_win_regs,
+					   mv_mbus_dram_info());
 		if (ret < 0)
 			goto err_mbus_win;
 	}
@@ -520,6 +514,12 @@ static int sdhci_pxav3_resume(struct device *dev)
 {
 	int ret;
 	struct sdhci_host *host = dev_get_drvdata(dev);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_pxa *pxa = pltfm_host->priv;
+
+	if (pxa->mbus_win_regs)
+		ret = mv_conf_mbus_windows(dev, pxa->mbus_win_regs,
+					   mv_mbus_dram_info());
 
 	pm_runtime_get_sync(dev);
 	ret = sdhci_resume_host(host);
-- 
1.8.3.1

[PATCH v2 1/5] mmc: sdhci-pxav3: enable proper resuming on Armada 38x SoC

[Marcin Wojtas]

When resuming from suspend on Armada 38x SoC MBus windows have to be
re-configured and for that purpose mv_conf_mbus_windows function needed
rework. MBus windows register base address obtaining was moved to
armada_38x_quirks function in order to be kept in pxa global structure,
because it is used during a resume.

This commit fixes resuming from suspend by calling MBus windows
configuration routine and therefore enabling proper DMA operation.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 drivers/mmc/host/sdhci-pxav3.c | 38 +++++++++++++++++++-------------------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index f5edf9d..76b9a70 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -63,6 +63,7 @@ struct sdhci_pxa {
 	struct clk *clk_io;
 	u8	power_mode;
 	void __iomem *sdio3_conf_reg;
+	void __iomem *mbus_win_regs;
 };
 
 /*
@@ -81,30 +82,16 @@ struct sdhci_pxa {
 #define SDIO3_CONF_CLK_INV	BIT(0)
 #define SDIO3_CONF_SD_FB_CLK	BIT(2)
 
-static int mv_conf_mbus_windows(struct platform_device *pdev,
+static int mv_conf_mbus_windows(struct device *dev, void __iomem *regs,
 				const struct mbus_dram_target_info *dram)
 {
 	int i;
-	void __iomem *regs;
-	struct resource *res;
 
 	if (!dram) {
-		dev_err(&pdev->dev, "no mbus dram info\n");
-		return -EINVAL;
-	}
-
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-	if (!res) {
-		dev_err(&pdev->dev, "cannot get mbus registers\n");
+		dev_err(dev, "no mbus dram info\n");
 		return -EINVAL;
 	}
 
-	regs = ioremap(res->start, resource_size(res));
-	if (!regs) {
-		dev_err(&pdev->dev, "cannot map mbus registers\n");
-		return -ENOMEM;
-	}
-
 	for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
 		writel(0, regs + SDHCI_WINDOW_CTRL(i));
 		writel(0, regs + SDHCI_WINDOW_BASE(i));
@@ -122,8 +109,6 @@ static int mv_conf_mbus_windows(struct platform_device *pdev,
 		writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
 	}
 
-	iounmap(regs);
-
 	return 0;
 }
 
@@ -135,6 +120,14 @@ static int armada_38x_quirks(struct platform_device *pdev,
 	struct sdhci_pxa *pxa = pltfm_host->priv;
 	struct resource *res;
 
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mbus");
+	pxa->mbus_win_regs = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(pxa->mbus_win_regs)) {
+		dev_err(mmc_dev(host->mmc),
+			"failed to obtain MBus windows register base\n");
+		return PTR_ERR(pxa->mbus_win_regs);
+	}
+
 	host->quirks &= ~SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
 	host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
@@ -403,7 +396,8 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
 		ret = armada_38x_quirks(pdev, host);
 		if (ret < 0)
 			goto err_mbus_win;
-		ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
+		ret = mv_conf_mbus_windows(&pdev->dev, pxa->mbus_win_regs,
+					   mv_mbus_dram_info());
 		if (ret < 0)
 			goto err_mbus_win;
 	}
@@ -520,6 +514,12 @@ static int sdhci_pxav3_resume(struct device *dev)
 {
 	int ret;
 	struct sdhci_host *host = dev_get_drvdata(dev);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_pxa *pxa = pltfm_host->priv;
+
+	if (pxa->mbus_win_regs)
+		ret = mv_conf_mbus_windows(dev, pxa->mbus_win_regs,
+					   mv_mbus_dram_info());
 
 	pm_runtime_get_sync(dev);
 	ret = sdhci_resume_host(host);
-- 
1.8.3.1

[PATCH v2 1/5] mmc: sdhci-pxav3: enable proper resuming on Armada 38x SoC

[Marcin Wojtas]

When resuming from suspend on Armada 38x SoC MBus windows have to be
re-configured and for that purpose mv_conf_mbus_windows function needed
rework. MBus windows register base address obtaining was moved to
armada_38x_quirks function in order to be kept in pxa global structure,
because it is used during a resume.

This commit fixes resuming from suspend by calling MBus windows
configuration routine and therefore enabling proper DMA operation.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 drivers/mmc/host/sdhci-pxav3.c | 38 +++++++++++++++++++-------------------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index f5edf9d..76b9a70 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -63,6 +63,7 @@ struct sdhci_pxa {
 	struct clk *clk_io;
 	u8	power_mode;
 	void __iomem *sdio3_conf_reg;
+	void __iomem *mbus_win_regs;
 };
 
 /*
@@ -81,30 +82,16 @@ struct sdhci_pxa {
 #define SDIO3_CONF_CLK_INV	BIT(0)
 #define SDIO3_CONF_SD_FB_CLK	BIT(2)
 
-static int mv_conf_mbus_windows(struct platform_device *pdev,
+static int mv_conf_mbus_windows(struct device *dev, void __iomem *regs,
 				const struct mbus_dram_target_info *dram)
 {
 	int i;
-	void __iomem *regs;
-	struct resource *res;
 
 	if (!dram) {
-		dev_err(&pdev->dev, "no mbus dram info\n");
-		return -EINVAL;
-	}
-
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-	if (!res) {
-		dev_err(&pdev->dev, "cannot get mbus registers\n");
+		dev_err(dev, "no mbus dram info\n");
 		return -EINVAL;
 	}
 
-	regs = ioremap(res->start, resource_size(res));
-	if (!regs) {
-		dev_err(&pdev->dev, "cannot map mbus registers\n");
-		return -ENOMEM;
-	}
-
 	for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
 		writel(0, regs + SDHCI_WINDOW_CTRL(i));
 		writel(0, regs + SDHCI_WINDOW_BASE(i));
@@ -122,8 +109,6 @@ static int mv_conf_mbus_windows(struct platform_device *pdev,
 		writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
 	}
 
-	iounmap(regs);
-
 	return 0;
 }
 
@@ -135,6 +120,14 @@ static int armada_38x_quirks(struct platform_device *pdev,
 	struct sdhci_pxa *pxa = pltfm_host->priv;
 	struct resource *res;
 
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mbus");
+	pxa->mbus_win_regs = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(pxa->mbus_win_regs)) {
+		dev_err(mmc_dev(host->mmc),
+			"failed to obtain MBus windows register base\n");
+		return PTR_ERR(pxa->mbus_win_regs);
+	}
+
 	host->quirks &= ~SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
 	host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
@@ -403,7 +396,8 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
 		ret = armada_38x_quirks(pdev, host);
 		if (ret < 0)
 			goto err_mbus_win;
-		ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
+		ret = mv_conf_mbus_windows(&pdev->dev, pxa->mbus_win_regs,
+					   mv_mbus_dram_info());
 		if (ret < 0)
 			goto err_mbus_win;
 	}
@@ -520,6 +514,12 @@ static int sdhci_pxav3_resume(struct device *dev)
 {
 	int ret;
 	struct sdhci_host *host = dev_get_drvdata(dev);
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_pxa *pxa = pltfm_host->priv;
+
+	if (pxa->mbus_win_regs)
+		ret = mv_conf_mbus_windows(dev, pxa->mbus_win_regs,
+					   mv_mbus_dram_info());
 
 	pm_runtime_get_sync(dev);
 	ret = sdhci_resume_host(host);
-- 
1.8.3.1

[PATCH v2 2/5] mmc: sdhci-pxav3: enable usage of DAT3 pin as HW card detect

[Marcin Wojtas]

Marvell Armada 38x SDHCI controller enable using DAT3 pin as a hardware
card detection. According to the SD sdandard this signal can be used for
this purpose combined with a pull-up resistor, implying inverted (active
low) polarization of a card detect. MMC standard does not support this
feature and does not operate with such connectivity of DAT3.

When using DAT3-based detection Armada 38x SDIO IP expects its internal
clock to be always on, which had to be ensured twofold:
- Each time controller is reset by updating appropriate registers. On the
  occasion of adding new register @0x104, register @0x100 name is modified
  in order to the be aligned with Armada 38x documentation.
- Leaving the clock enabled despite power-down. For this purpose a new
  quirk had to be added to SDHCI subsystem - SDHCI_QUIRK2_KEEP_INT_CLK_ON.

In addition to the changes above this commit adds a new property to Armada
38x SDHCI node ('dat3-cd') with an according binding documentation update.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 .../devicetree/bindings/mmc/sdhci-pxa.txt          |  5 +++
 drivers/mmc/host/sdhci-pxav3.c                     | 38 ++++++++++++++++++++--
 drivers/mmc/host/sdhci.c                           |  5 ++-
 drivers/mmc/host/sdhci.h                           |  3 ++
 4 files changed, 47 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
index 3d1b449..ffd6b14 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
+++ b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
@@ -23,6 +23,11 @@ Required properties:
 
 Optional properties:
 - mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning.
+- dat3-cd: use DAT3 pin as hardware card detect - option available for
+  "marvell,armada-380-sdhci" only. The detection is supposed to work with
+  active high polarity, which implies usage of "cd-inverted" property.
+  Note that according to the specifications DAT3-based card detection can be
+  used with SD cards only. MMC standard doesn't support this feature.
 
 Example:
 
diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index 76b9a70..352c5eb 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -46,10 +46,14 @@
 #define SDCLK_DELAY_SHIFT	9
 #define SDCLK_DELAY_MASK	0x1f
 
-#define SD_CFG_FIFO_PARAM       0x100
+#define SD_EXTRA_PARAM_REG	0x100
 #define SDCFG_GEN_PAD_CLK_ON	(1<<6)
 #define SDCFG_GEN_PAD_CLK_CNT_MASK	0xFF
 #define SDCFG_GEN_PAD_CLK_CNT_SHIFT	24
+#define SD_FIFO_PARAM_REG	0x104
+#define SD_USE_DAT3		BIT(7)
+#define SD_OVRRD_CLK_OEN	BIT(11)
+#define SD_FORCE_CLK_ON		BIT(12)
 
 #define SD_SPI_MODE          0x108
 #define SD_CE_ATA_1          0x10C
@@ -163,6 +167,15 @@ static int armada_38x_quirks(struct platform_device *pdev,
 	}
 	host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING);
 
+	/*
+	 * The interface clock enable is also used as control
+	 * for the A38x SDIO IP, so it can't be powered down
+	 * when using HW-based card detection.
+	 */
+	if (of_property_read_bool(np, "dat3-cd") &&
+	    !of_property_read_bool(np, "broken-cd"))
+		host->quirks2 |= SDHCI_QUIRK2_KEEP_INT_CLK_ON;
+
 	return 0;
 }
 
@@ -170,6 +183,8 @@ static void pxav3_reset(struct sdhci_host *host, u8 mask)
 {
 	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
 	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
+	struct device_node *np = pdev->dev.of_node;
+	u32 reg_val;
 
 	sdhci_reset(host, mask);
 
@@ -187,6 +202,22 @@ static void pxav3_reset(struct sdhci_host *host, u8 mask)
 			tmp |= SDCLK_SEL;
 			writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
 		}
+
+		if (of_device_is_compatible(np, "marvell,armada-380-sdhci") &&
+		    host->quirks2 & SDHCI_QUIRK2_KEEP_INT_CLK_ON) {
+			reg_val = sdhci_readl(host, SD_FIFO_PARAM_REG);
+			reg_val |= SD_USE_DAT3 | SD_OVRRD_CLK_OEN |
+				   SD_FORCE_CLK_ON;
+			sdhci_writel(host, reg_val, SD_FIFO_PARAM_REG);
+
+			/*
+			 * For HW detection based on DAT3 pin keep internal
+			 * clk switched on after controller reset.
+			 */
+			reg_val = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
+			reg_val |= SDHCI_CLOCK_INT_EN;
+			sdhci_writel(host, reg_val, SDHCI_CLOCK_CONTROL);
+		}
 	}
 }
 
@@ -214,9 +245,9 @@ static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
 		writew(tmp, host->ioaddr + SD_CE_ATA_2);
 
 		/* start sending the 74 clocks */
-		tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
+		tmp = readw(host->ioaddr + SD_EXTRA_PARAM_REG);
 		tmp |= SDCFG_GEN_PAD_CLK_ON;
-		writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
+		writew(tmp, host->ioaddr + SD_EXTRA_PARAM_REG);
 
 		/* slowest speed is about 100KHz or 10usec per clock */
 		udelay(740);
@@ -410,6 +441,7 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
 		sdhci_get_of_property(pdev);
 		pdata = pxav3_get_mmc_pdata(dev);
 		pdev->dev.platform_data = pdata;
+
 	} else if (pdata) {
 		/* on-chip device */
 		if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 64b7fdb..cfed695 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1159,7 +1159,10 @@ void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 
 	host->mmc->actual_clock = 0;
 
-	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+	/* Some controllers need to keep internal clk always enabled */
+	if (host->quirks2 & SDHCI_QUIRK2_KEEP_INT_CLK_ON)
+		clk = SDHCI_CLOCK_INT_EN;
+	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 
 	if (clock == 0)
 		return;
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 7c02ff4..c751b78 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -412,6 +412,9 @@ struct sdhci_host {
 #define SDHCI_QUIRK2_ACMD23_BROKEN			(1<<14)
 /* Broken Clock divider zero in controller */
 #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN		(1<<15)
+/* Do not disable internal clk on power-off */
+#define SDHCI_QUIRK2_KEEP_INT_CLK_ON			(1<<16)
+
 
 	int irq;		/* Device IRQ */
 	void __iomem *ioaddr;	/* Mapped address */
-- 
1.8.3.1

[PATCH v2 2/5] mmc: sdhci-pxav3: enable usage of DAT3 pin as HW card detect

[Marcin Wojtas]

Marvell Armada 38x SDHCI controller enable using DAT3 pin as a hardware
card detection. According to the SD sdandard this signal can be used for
this purpose combined with a pull-up resistor, implying inverted (active
low) polarization of a card detect. MMC standard does not support this
feature and does not operate with such connectivity of DAT3.

When using DAT3-based detection Armada 38x SDIO IP expects its internal
clock to be always on, which had to be ensured twofold:
- Each time controller is reset by updating appropriate registers. On the
  occasion of adding new register @0x104, register @0x100 name is modified
  in order to the be aligned with Armada 38x documentation.
- Leaving the clock enabled despite power-down. For this purpose a new
  quirk had to be added to SDHCI subsystem - SDHCI_QUIRK2_KEEP_INT_CLK_ON.

In addition to the changes above this commit adds a new property to Armada
38x SDHCI node ('dat3-cd') with an according binding documentation update.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 .../devicetree/bindings/mmc/sdhci-pxa.txt          |  5 +++
 drivers/mmc/host/sdhci-pxav3.c                     | 38 ++++++++++++++++++++--
 drivers/mmc/host/sdhci.c                           |  5 ++-
 drivers/mmc/host/sdhci.h                           |  3 ++
 4 files changed, 47 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
index 3d1b449..ffd6b14 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
+++ b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
@@ -23,6 +23,11 @@ Required properties:
 
 Optional properties:
 - mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning.
+- dat3-cd: use DAT3 pin as hardware card detect - option available for
+  "marvell,armada-380-sdhci" only. The detection is supposed to work with
+  active high polarity, which implies usage of "cd-inverted" property.
+  Note that according to the specifications DAT3-based card detection can be
+  used with SD cards only. MMC standard doesn't support this feature.
 
 Example:
 
diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index 76b9a70..352c5eb 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -46,10 +46,14 @@
 #define SDCLK_DELAY_SHIFT	9
 #define SDCLK_DELAY_MASK	0x1f
 
-#define SD_CFG_FIFO_PARAM       0x100
+#define SD_EXTRA_PARAM_REG	0x100
 #define SDCFG_GEN_PAD_CLK_ON	(1<<6)
 #define SDCFG_GEN_PAD_CLK_CNT_MASK	0xFF
 #define SDCFG_GEN_PAD_CLK_CNT_SHIFT	24
+#define SD_FIFO_PARAM_REG	0x104
+#define SD_USE_DAT3		BIT(7)
+#define SD_OVRRD_CLK_OEN	BIT(11)
+#define SD_FORCE_CLK_ON		BIT(12)
 
 #define SD_SPI_MODE          0x108
 #define SD_CE_ATA_1          0x10C
@@ -163,6 +167,15 @@ static int armada_38x_quirks(struct platform_device *pdev,
 	}
 	host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING);
 
+	/*
+	 * The interface clock enable is also used as control
+	 * for the A38x SDIO IP, so it can't be powered down
+	 * when using HW-based card detection.
+	 */
+	if (of_property_read_bool(np, "dat3-cd") &&
+	    !of_property_read_bool(np, "broken-cd"))
+		host->quirks2 |= SDHCI_QUIRK2_KEEP_INT_CLK_ON;
+
 	return 0;
 }
 
@@ -170,6 +183,8 @@ static void pxav3_reset(struct sdhci_host *host, u8 mask)
 {
 	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
 	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
+	struct device_node *np = pdev->dev.of_node;
+	u32 reg_val;
 
 	sdhci_reset(host, mask);
 
@@ -187,6 +202,22 @@ static void pxav3_reset(struct sdhci_host *host, u8 mask)
 			tmp |= SDCLK_SEL;
 			writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
 		}
+
+		if (of_device_is_compatible(np, "marvell,armada-380-sdhci") &&
+		    host->quirks2 & SDHCI_QUIRK2_KEEP_INT_CLK_ON) {
+			reg_val = sdhci_readl(host, SD_FIFO_PARAM_REG);
+			reg_val |= SD_USE_DAT3 | SD_OVRRD_CLK_OEN |
+				   SD_FORCE_CLK_ON;
+			sdhci_writel(host, reg_val, SD_FIFO_PARAM_REG);
+
+			/*
+			 * For HW detection based on DAT3 pin keep internal
+			 * clk switched on after controller reset.
+			 */
+			reg_val = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
+			reg_val |= SDHCI_CLOCK_INT_EN;
+			sdhci_writel(host, reg_val, SDHCI_CLOCK_CONTROL);
+		}
 	}
 }
 
@@ -214,9 +245,9 @@ static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
 		writew(tmp, host->ioaddr + SD_CE_ATA_2);
 
 		/* start sending the 74 clocks */
-		tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
+		tmp = readw(host->ioaddr + SD_EXTRA_PARAM_REG);
 		tmp |= SDCFG_GEN_PAD_CLK_ON;
-		writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
+		writew(tmp, host->ioaddr + SD_EXTRA_PARAM_REG);
 
 		/* slowest speed is about 100KHz or 10usec per clock */
 		udelay(740);
@@ -410,6 +441,7 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
 		sdhci_get_of_property(pdev);
 		pdata = pxav3_get_mmc_pdata(dev);
 		pdev->dev.platform_data = pdata;
+
 	} else if (pdata) {
 		/* on-chip device */
 		if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 64b7fdb..cfed695 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1159,7 +1159,10 @@ void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 
 	host->mmc->actual_clock = 0;
 
-	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+	/* Some controllers need to keep internal clk always enabled */
+	if (host->quirks2 & SDHCI_QUIRK2_KEEP_INT_CLK_ON)
+		clk = SDHCI_CLOCK_INT_EN;
+	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 
 	if (clock == 0)
 		return;
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 7c02ff4..c751b78 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -412,6 +412,9 @@ struct sdhci_host {
 #define SDHCI_QUIRK2_ACMD23_BROKEN			(1<<14)
 /* Broken Clock divider zero in controller */
 #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN		(1<<15)
+/* Do not disable internal clk on power-off */
+#define SDHCI_QUIRK2_KEEP_INT_CLK_ON			(1<<16)
+
 
 	int irq;		/* Device IRQ */
 	void __iomem *ioaddr;	/* Mapped address */
-- 
1.8.3.1

[PATCH v2 3/5] ARM: mvebu: set SW polling as SDHCI card detection on A388-GP

[Marcin Wojtas]

The newest revisions of A388-GP (v1.5 and higher) support only
DAT3-based card detection. Revisions < v1.5 based on GPIO detection
via I2C expander, but this solution is supposed to be deprecated on
new boards. In order to satisfy all type of hardware this commit
changes card detection to use software polling mechanism.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 arch/arm/boot/dts/armada-388-gp.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts
index 391dea9..403a86b 100644
--- a/arch/arm/boot/dts/armada-388-gp.dts
+++ b/arch/arm/boot/dts/armada-388-gp.dts
@@ -213,8 +213,8 @@
 			sdhci@d8000 {
 				pinctrl-names = "default";
 				pinctrl-0 = <&sdhci_pins>;
-				cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
 				no-1-8-v;
+				broken-cd;
 				wp-inverted;
 				bus-width = <8>;
 				status = "okay";
-- 
1.8.3.1

[PATCH v2 3/5] ARM: mvebu: set SW polling as SDHCI card detection on A388-GP

[Marcin Wojtas]

The newest revisions of A388-GP (v1.5 and higher) support only
DAT3-based card detection. Revisions < v1.5 based on GPIO detection
via I2C expander, but this solution is supposed to be deprecated on
new boards. In order to satisfy all type of hardware this commit
changes card detection to use software polling mechanism.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 arch/arm/boot/dts/armada-388-gp.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts
index 391dea9..403a86b 100644
--- a/arch/arm/boot/dts/armada-388-gp.dts
+++ b/arch/arm/boot/dts/armada-388-gp.dts
@@ -213,8 +213,8 @@
 			sdhci at d8000 {
 				pinctrl-names = "default";
 				pinctrl-0 = <&sdhci_pins>;
-				cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
 				no-1-8-v;
+				broken-cd;
 				wp-inverted;
 				bus-width = <8>;
 				status = "okay";
-- 
1.8.3.1

[PATCH v2 4/5] mmc: sdhci: add init_card callback to sdhci

[Marcin Wojtas]

Some sdhci hosts may require handling quirks during card initialization at
the time when its type is already known. Hence a new callback (init_card)
is added in sdhci_ops.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 drivers/mmc/host/sdhci.c | 9 +++++++++
 drivers/mmc/host/sdhci.h | 1 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index cfed695..a1c308d 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -2200,6 +2200,14 @@ static void sdhci_card_event(struct mmc_host *mmc)
 	spin_unlock_irqrestore(&host->lock, flags);
 }
 
+static void sdhci_init_card(struct mmc_host *mmc, struct mmc_card *card)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+
+	if (host->ops->init_card)
+		host->ops->init_card(host, card);
+}
+
 static const struct mmc_host_ops sdhci_ops = {
 	.request	= sdhci_request,
 	.post_req	= sdhci_post_req,
@@ -2215,6 +2223,7 @@ static const struct mmc_host_ops sdhci_ops = {
 	.select_drive_strength		= sdhci_select_drive_strength,
 	.card_event			= sdhci_card_event,
 	.card_busy	= sdhci_card_busy,
+	.init_card	= sdhci_init_card,
 };
 
 /*****************************************************************************\
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index c751b78..365c860 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -547,6 +547,7 @@ struct sdhci_ops {
 					 struct mmc_card *card,
 					 unsigned int max_dtr, int host_drv,
 					 int card_drv, int *drv_type);
+	void	(*init_card)(struct sdhci_host *host, struct mmc_card *card);
 };
 
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
-- 
1.8.3.1

[PATCH v2 4/5] mmc: sdhci: add init_card callback to sdhci

[Marcin Wojtas]

Some sdhci hosts may require handling quirks during card initialization at
the time when its type is already known. Hence a new callback (init_card)
is added in sdhci_ops.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 drivers/mmc/host/sdhci.c | 9 +++++++++
 drivers/mmc/host/sdhci.h | 1 +
 2 files changed, 10 insertions(+)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index cfed695..a1c308d 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -2200,6 +2200,14 @@ static void sdhci_card_event(struct mmc_host *mmc)
 	spin_unlock_irqrestore(&host->lock, flags);
 }
 
+static void sdhci_init_card(struct mmc_host *mmc, struct mmc_card *card)
+{
+	struct sdhci_host *host = mmc_priv(mmc);
+
+	if (host->ops->init_card)
+		host->ops->init_card(host, card);
+}
+
 static const struct mmc_host_ops sdhci_ops = {
 	.request	= sdhci_request,
 	.post_req	= sdhci_post_req,
@@ -2215,6 +2223,7 @@ static const struct mmc_host_ops sdhci_ops = {
 	.select_drive_strength		= sdhci_select_drive_strength,
 	.card_event			= sdhci_card_event,
 	.card_busy	= sdhci_card_busy,
+	.init_card	= sdhci_init_card,
 };
 
 /*****************************************************************************\
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index c751b78..365c860 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -547,6 +547,7 @@ struct sdhci_ops {
 					 struct mmc_card *card,
 					 unsigned int max_dtr, int host_drv,
 					 int card_drv, int *drv_type);
+	void	(*init_card)(struct sdhci_host *host, struct mmc_card *card);
 };
 
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
-- 
1.8.3.1

[PATCH v2 5/5] mmc: sdhci-pxav3: enable modifying MMC_CARD bit during card initialization

[Marcin Wojtas]

On Marvell Armada 38x SoC's the MMC_CARD bit in SD_CE_ATA_1 register must
be set to 0x1 when a MMC card is supposed to work in DDR mode, or when
commands CMD11, CMD14 and CMD20 are used.

This commit enables the above for all MMC cards by modifying the host
registers during card initialization. It is done by using init_card()
callback.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 drivers/mmc/host/sdhci-pxav3.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index 352c5eb..9bdeeb1 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -57,6 +57,7 @@
 
 #define SD_SPI_MODE          0x108
 #define SD_CE_ATA_1          0x10C
+#define SDCE_MMC_CARD		BIT(28)
 
 #define SD_CE_ATA_2          0x10E
 #define SDCE_MISC_INT		(1<<2)
@@ -221,6 +222,22 @@ static void pxav3_reset(struct sdhci_host *host, u8 mask)
 	}
 }
 
+static void pxav3_init_card(struct sdhci_host *host, struct mmc_card *card)
+{
+	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
+	struct device_node *np = pdev->dev.of_node;
+	u32 reg_val;
+
+	if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
+		reg_val = sdhci_readl(host, SD_CE_ATA_1);
+		if (mmc_card_mmc(card))
+			reg_val |= SDCE_MMC_CARD;
+		else
+			reg_val &= ~SDCE_MMC_CARD;
+		sdhci_writel(host, reg_val, SD_CE_ATA_1);
+	}
+}
+
 #define MAX_WAIT_COUNT 5
 static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
 {
@@ -338,6 +355,7 @@ static const struct sdhci_ops pxav3_sdhci_ops = {
 	.set_bus_width = sdhci_set_bus_width,
 	.reset = pxav3_reset,
 	.set_uhs_signaling = pxav3_set_uhs_signaling,
+	.init_card = pxav3_init_card,
 };
 
 static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
-- 
1.8.3.1

[PATCH v2 5/5] mmc: sdhci-pxav3: enable modifying MMC_CARD bit during card initialization

[Marcin Wojtas]

On Marvell Armada 38x SoC's the MMC_CARD bit in SD_CE_ATA_1 register must
be set to 0x1 when a MMC card is supposed to work in DDR mode, or when
commands CMD11, CMD14 and CMD20 are used.

This commit enables the above for all MMC cards by modifying the host
registers during card initialization. It is done by using init_card()
callback.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
 drivers/mmc/host/sdhci-pxav3.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
index 352c5eb..9bdeeb1 100644
--- a/drivers/mmc/host/sdhci-pxav3.c
+++ b/drivers/mmc/host/sdhci-pxav3.c
@@ -57,6 +57,7 @@
 
 #define SD_SPI_MODE          0x108
 #define SD_CE_ATA_1          0x10C
+#define SDCE_MMC_CARD		BIT(28)
 
 #define SD_CE_ATA_2          0x10E
 #define SDCE_MISC_INT		(1<<2)
@@ -221,6 +222,22 @@ static void pxav3_reset(struct sdhci_host *host, u8 mask)
 	}
 }
 
+static void pxav3_init_card(struct sdhci_host *host, struct mmc_card *card)
+{
+	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
+	struct device_node *np = pdev->dev.of_node;
+	u32 reg_val;
+
+	if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
+		reg_val = sdhci_readl(host, SD_CE_ATA_1);
+		if (mmc_card_mmc(card))
+			reg_val |= SDCE_MMC_CARD;
+		else
+			reg_val &= ~SDCE_MMC_CARD;
+		sdhci_writel(host, reg_val, SD_CE_ATA_1);
+	}
+}
+
 #define MAX_WAIT_COUNT 5
 static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
 {
@@ -338,6 +355,7 @@ static const struct sdhci_ops pxav3_sdhci_ops = {
 	.set_bus_width = sdhci_set_bus_width,
 	.reset = pxav3_reset,
 	.set_uhs_signaling = pxav3_set_uhs_signaling,
+	.init_card = pxav3_init_card,
 };
 
 static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
-- 
1.8.3.1

Re: [PATCH v2 3/5] ARM: mvebu: set SW polling as SDHCI card detection on A388-GP

[Thomas Petazzoni]

Dear Marcin Wojtas,

On Fri,  9 Oct 2015 03:03:53 +0200, Marcin Wojtas wrote:
> The newest revisions of A388-GP (v1.5 and higher) support only
> DAT3-based card detection. Revisions < v1.5 based on GPIO detection
> via I2C expander, but this solution is supposed to be deprecated on
> new boards. In order to satisfy all type of hardware this commit
> changes card detection to use software polling mechanism.
> 
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Can we add a comment on the DT that explains why SW polling is used,
and which other mechanism can be used depending on the board revision?

Thanks,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCH v2 3/5] ARM: mvebu: set SW polling as SDHCI card detection on A388-GP

[Thomas Petazzoni]

Dear Marcin Wojtas,

On Fri,  9 Oct 2015 03:03:53 +0200, Marcin Wojtas wrote:
> The newest revisions of A388-GP (v1.5 and higher) support only
> DAT3-based card detection. Revisions < v1.5 based on GPIO detection
> via I2C expander, but this solution is supposed to be deprecated on
> new boards. In order to satisfy all type of hardware this commit
> changes card detection to use software polling mechanism.
> 
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>

Can we add a comment on the DT that explains why SW polling is used,
and which other mechanism can be used depending on the board revision?

Thanks,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v2 3/5] ARM: mvebu: set SW polling as SDHCI card detection on A388-GP

[Marcin Wojtas]

Hi Thomas,


2015-10-09 9:52 GMT+02:00 Thomas Petazzoni
<thomas.petazzoni@free-electrons.com>:
> Dear Marcin Wojtas,
>
> On Fri,  9 Oct 2015 03:03:53 +0200, Marcin Wojtas wrote:
>> The newest revisions of A388-GP (v1.5 and higher) support only
>> DAT3-based card detection. Revisions < v1.5 based on GPIO detection
>> via I2C expander, but this solution is supposed to be deprecated on
>> new boards. In order to satisfy all type of hardware this commit
>> changes card detection to use software polling mechanism.
>>
>> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>
> Can we add a comment on the DT that explains why SW polling is used,
> and which other mechanism can be used depending on the board revision?

Sure, good idea. Do you think the below would be sufficient?
sdhci@d8000 {
    pinctrl-names = "default";
    pinctrl-0 = <&sdhci_pins>;
    no-1-8-v;
    /*
     * A388-GP board v1.5 and higher replace
     * hitherto card detection method based on GPIO
     * with the one using DAT3 pin. As they are
     * incompatible, software-based polling is
     * enabled with 'broken-cd' property. For boards
     * older than v1.5 it can be replaced with:
     * 'cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;',
     * whereas for the newer ones following can be
     * used instead:
     * 'dat3-cd;'
     * 'cd-inverted;'
     */
broken-cd;
wp-inverted;
bus-width = <8>;
status = "okay";
};

Best regards,
Marcin

[PATCH v2 3/5] ARM: mvebu: set SW polling as SDHCI card detection on A388-GP

[Marcin Wojtas]

Hi Thomas,


2015-10-09 9:52 GMT+02:00 Thomas Petazzoni
<thomas.petazzoni@free-electrons.com>:
> Dear Marcin Wojtas,
>
> On Fri,  9 Oct 2015 03:03:53 +0200, Marcin Wojtas wrote:
>> The newest revisions of A388-GP (v1.5 and higher) support only
>> DAT3-based card detection. Revisions < v1.5 based on GPIO detection
>> via I2C expander, but this solution is supposed to be deprecated on
>> new boards. In order to satisfy all type of hardware this commit
>> changes card detection to use software polling mechanism.
>>
>> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>
> Can we add a comment on the DT that explains why SW polling is used,
> and which other mechanism can be used depending on the board revision?

Sure, good idea. Do you think the below would be sufficient?
sdhci at d8000 {
    pinctrl-names = "default";
    pinctrl-0 = <&sdhci_pins>;
    no-1-8-v;
    /*
     * A388-GP board v1.5 and higher replace
     * hitherto card detection method based on GPIO
     * with the one using DAT3 pin. As they are
     * incompatible, software-based polling is
     * enabled with 'broken-cd' property. For boards
     * older than v1.5 it can be replaced with:
     * 'cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;',
     * whereas for the newer ones following can be
     * used instead:
     * 'dat3-cd;'
     * 'cd-inverted;'
     */
broken-cd;
wp-inverted;
bus-width = <8>;
status = "okay";
};

Best regards,
Marcin

Re: [PATCH v2 2/5] mmc: sdhci-pxav3: enable usage of DAT3 pin as HW card detect

[Jisheng Zhang]

On Fri, 9 Oct 2015 03:03:52 +0200
Marcin Wojtas <mw@semihalf.com> wrote:

> Marvell Armada 38x SDHCI controller enable using DAT3 pin as a hardware
> card detection. According to the SD sdandard this signal can be used for
> this purpose combined with a pull-up resistor, implying inverted (active
> low) polarization of a card detect. MMC standard does not support this
> feature and does not operate with such connectivity of DAT3.
> 
> When using DAT3-based detection Armada 38x SDIO IP expects its internal
> clock to be always on, which had to be ensured twofold:

What happen if runtime suspend disables its core clk and axi clk? I guess
dat3-based detection isn't compatible with runtime pm. If so, do we also
need to disable runtime pm in probe function?

> - Each time controller is reset by updating appropriate registers. On the
>   occasion of adding new register @0x104, register @0x100 name is modified
>   in order to the be aligned with Armada 38x documentation.
> - Leaving the clock enabled despite power-down. For this purpose a new
>   quirk had to be added to SDHCI subsystem - SDHCI_QUIRK2_KEEP_INT_CLK_ON.

As seen from other mails, Ulf calls for no more quirks...

Thanks,
Jisheng

> 
> In addition to the changes above this commit adds a new property to Armada
> 38x SDHCI node ('dat3-cd') with an according binding documentation update.
> 
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
>  .../devicetree/bindings/mmc/sdhci-pxa.txt          |  5 +++
>  drivers/mmc/host/sdhci-pxav3.c                     | 38 ++++++++++++++++++++--
>  drivers/mmc/host/sdhci.c                           |  5 ++-
>  drivers/mmc/host/sdhci.h                           |  3 ++
>  4 files changed, 47 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
> index 3d1b449..ffd6b14 100644
> --- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
> +++ b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
> @@ -23,6 +23,11 @@ Required properties:
>  
>  Optional properties:
>  - mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning.
> +- dat3-cd: use DAT3 pin as hardware card detect - option available for
> +  "marvell,armada-380-sdhci" only. The detection is supposed to work with
> +  active high polarity, which implies usage of "cd-inverted" property.
> +  Note that according to the specifications DAT3-based card detection can be
> +  used with SD cards only. MMC standard doesn't support this feature.
>  
>  Example:
>  
> diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
> index 76b9a70..352c5eb 100644
> --- a/drivers/mmc/host/sdhci-pxav3.c
> +++ b/drivers/mmc/host/sdhci-pxav3.c
> @@ -46,10 +46,14 @@
>  #define SDCLK_DELAY_SHIFT	9
>  #define SDCLK_DELAY_MASK	0x1f
>  
> -#define SD_CFG_FIFO_PARAM       0x100
> +#define SD_EXTRA_PARAM_REG	0x100
>  #define SDCFG_GEN_PAD_CLK_ON	(1<<6)
>  #define SDCFG_GEN_PAD_CLK_CNT_MASK	0xFF
>  #define SDCFG_GEN_PAD_CLK_CNT_SHIFT	24
> +#define SD_FIFO_PARAM_REG	0x104
> +#define SD_USE_DAT3		BIT(7)
> +#define SD_OVRRD_CLK_OEN	BIT(11)
> +#define SD_FORCE_CLK_ON		BIT(12)
>  
>  #define SD_SPI_MODE          0x108
>  #define SD_CE_ATA_1          0x10C
> @@ -163,6 +167,15 @@ static int armada_38x_quirks(struct platform_device *pdev,
>  	}
>  	host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING);
>  
> +	/*
> +	 * The interface clock enable is also used as control
> +	 * for the A38x SDIO IP, so it can't be powered down
> +	 * when using HW-based card detection.
> +	 */
> +	if (of_property_read_bool(np, "dat3-cd") &&
> +	    !of_property_read_bool(np, "broken-cd"))
> +		host->quirks2 |= SDHCI_QUIRK2_KEEP_INT_CLK_ON;
> +
>  	return 0;
>  }
>  
> @@ -170,6 +183,8 @@ static void pxav3_reset(struct sdhci_host *host, u8 mask)
>  {
>  	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
>  	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
> +	struct device_node *np = pdev->dev.of_node;
> +	u32 reg_val;
>  
>  	sdhci_reset(host, mask);
>  
> @@ -187,6 +202,22 @@ static void pxav3_reset(struct sdhci_host *host, u8 mask)
>  			tmp |= SDCLK_SEL;
>  			writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>  		}
> +
> +		if (of_device_is_compatible(np, "marvell,armada-380-sdhci") &&
> +		    host->quirks2 & SDHCI_QUIRK2_KEEP_INT_CLK_ON) {
> +			reg_val = sdhci_readl(host, SD_FIFO_PARAM_REG);
> +			reg_val |= SD_USE_DAT3 | SD_OVRRD_CLK_OEN |
> +				   SD_FORCE_CLK_ON;
> +			sdhci_writel(host, reg_val, SD_FIFO_PARAM_REG);
> +
> +			/*
> +			 * For HW detection based on DAT3 pin keep internal
> +			 * clk switched on after controller reset.
> +			 */
> +			reg_val = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
> +			reg_val |= SDHCI_CLOCK_INT_EN;
> +			sdhci_writel(host, reg_val, SDHCI_CLOCK_CONTROL);
> +		}
>  	}
>  }
>  
> @@ -214,9 +245,9 @@ static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
>  		writew(tmp, host->ioaddr + SD_CE_ATA_2);
>  
>  		/* start sending the 74 clocks */
> -		tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
> +		tmp = readw(host->ioaddr + SD_EXTRA_PARAM_REG);
>  		tmp |= SDCFG_GEN_PAD_CLK_ON;
> -		writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
> +		writew(tmp, host->ioaddr + SD_EXTRA_PARAM_REG);
>  
>  		/* slowest speed is about 100KHz or 10usec per clock */
>  		udelay(740);
> @@ -410,6 +441,7 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
>  		sdhci_get_of_property(pdev);
>  		pdata = pxav3_get_mmc_pdata(dev);
>  		pdev->dev.platform_data = pdata;
> +
>  	} else if (pdata) {
>  		/* on-chip device */
>  		if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 64b7fdb..cfed695 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1159,7 +1159,10 @@ void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
>  
>  	host->mmc->actual_clock = 0;
>  
> -	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
> +	/* Some controllers need to keep internal clk always enabled */
> +	if (host->quirks2 & SDHCI_QUIRK2_KEEP_INT_CLK_ON)
> +		clk = SDHCI_CLOCK_INT_EN;
> +	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
>  
>  	if (clock == 0)
>  		return;
> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
> index 7c02ff4..c751b78 100644
> --- a/drivers/mmc/host/sdhci.h
> +++ b/drivers/mmc/host/sdhci.h
> @@ -412,6 +412,9 @@ struct sdhci_host {
>  #define SDHCI_QUIRK2_ACMD23_BROKEN			(1<<14)
>  /* Broken Clock divider zero in controller */
>  #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN		(1<<15)
> +/* Do not disable internal clk on power-off */
> +#define SDHCI_QUIRK2_KEEP_INT_CLK_ON			(1<<16)
> +
>  
>  	int irq;		/* Device IRQ */
>  	void __iomem *ioaddr;	/* Mapped address */

Re: [PATCH v2 2/5] mmc: sdhci-pxav3: enable usage of DAT3 pin as HW card detect

[Jisheng Zhang]

On Fri, 9 Oct 2015 03:03:52 +0200
Marcin Wojtas <mw@semihalf.com> wrote:

> Marvell Armada 38x SDHCI controller enable using DAT3 pin as a hardware
> card detection. According to the SD sdandard this signal can be used for
> this purpose combined with a pull-up resistor, implying inverted (active
> low) polarization of a card detect. MMC standard does not support this
> feature and does not operate with such connectivity of DAT3.
> 
> When using DAT3-based detection Armada 38x SDIO IP expects its internal
> clock to be always on, which had to be ensured twofold:

What happen if runtime suspend disables its core clk and axi clk? I guess
dat3-based detection isn't compatible with runtime pm. If so, do we also
need to disable runtime pm in probe function?

> - Each time controller is reset by updating appropriate registers. On the
>   occasion of adding new register @0x104, register @0x100 name is modified
>   in order to the be aligned with Armada 38x documentation.
> - Leaving the clock enabled despite power-down. For this purpose a new
>   quirk had to be added to SDHCI subsystem - SDHCI_QUIRK2_KEEP_INT_CLK_ON.

As seen from other mails, Ulf calls for no more quirks...

Thanks,
Jisheng

> 
> In addition to the changes above this commit adds a new property to Armada
> 38x SDHCI node ('dat3-cd') with an according binding documentation update.
> 
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
>  .../devicetree/bindings/mmc/sdhci-pxa.txt          |  5 +++
>  drivers/mmc/host/sdhci-pxav3.c                     | 38 ++++++++++++++++++++--
>  drivers/mmc/host/sdhci.c                           |  5 ++-
>  drivers/mmc/host/sdhci.h                           |  3 ++
>  4 files changed, 47 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
> index 3d1b449..ffd6b14 100644
> --- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
> +++ b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
> @@ -23,6 +23,11 @@ Required properties:
>  
>  Optional properties:
>  - mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning.
> +- dat3-cd: use DAT3 pin as hardware card detect - option available for
> +  "marvell,armada-380-sdhci" only. The detection is supposed to work with
> +  active high polarity, which implies usage of "cd-inverted" property.
> +  Note that according to the specifications DAT3-based card detection can be
> +  used with SD cards only. MMC standard doesn't support this feature.
>  
>  Example:
>  
> diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
> index 76b9a70..352c5eb 100644
> --- a/drivers/mmc/host/sdhci-pxav3.c
> +++ b/drivers/mmc/host/sdhci-pxav3.c
> @@ -46,10 +46,14 @@
>  #define SDCLK_DELAY_SHIFT	9
>  #define SDCLK_DELAY_MASK	0x1f
>  
> -#define SD_CFG_FIFO_PARAM       0x100
> +#define SD_EXTRA_PARAM_REG	0x100
>  #define SDCFG_GEN_PAD_CLK_ON	(1<<6)
>  #define SDCFG_GEN_PAD_CLK_CNT_MASK	0xFF
>  #define SDCFG_GEN_PAD_CLK_CNT_SHIFT	24
> +#define SD_FIFO_PARAM_REG	0x104
> +#define SD_USE_DAT3		BIT(7)
> +#define SD_OVRRD_CLK_OEN	BIT(11)
> +#define SD_FORCE_CLK_ON		BIT(12)
>  
>  #define SD_SPI_MODE          0x108
>  #define SD_CE_ATA_1          0x10C
> @@ -163,6 +167,15 @@ static int armada_38x_quirks(struct platform_device *pdev,
>  	}
>  	host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING);
>  
> +	/*
> +	 * The interface clock enable is also used as control
> +	 * for the A38x SDIO IP, so it can't be powered down
> +	 * when using HW-based card detection.
> +	 */
> +	if (of_property_read_bool(np, "dat3-cd") &&
> +	    !of_property_read_bool(np, "broken-cd"))
> +		host->quirks2 |= SDHCI_QUIRK2_KEEP_INT_CLK_ON;
> +
>  	return 0;
>  }
>  
> @@ -170,6 +183,8 @@ static void pxav3_reset(struct sdhci_host *host, u8 mask)
>  {
>  	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
>  	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
> +	struct device_node *np = pdev->dev.of_node;
> +	u32 reg_val;
>  
>  	sdhci_reset(host, mask);
>  
> @@ -187,6 +202,22 @@ static void pxav3_reset(struct sdhci_host *host, u8 mask)
>  			tmp |= SDCLK_SEL;
>  			writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>  		}
> +
> +		if (of_device_is_compatible(np, "marvell,armada-380-sdhci") &&
> +		    host->quirks2 & SDHCI_QUIRK2_KEEP_INT_CLK_ON) {
> +			reg_val = sdhci_readl(host, SD_FIFO_PARAM_REG);
> +			reg_val |= SD_USE_DAT3 | SD_OVRRD_CLK_OEN |
> +				   SD_FORCE_CLK_ON;
> +			sdhci_writel(host, reg_val, SD_FIFO_PARAM_REG);
> +
> +			/*
> +			 * For HW detection based on DAT3 pin keep internal
> +			 * clk switched on after controller reset.
> +			 */
> +			reg_val = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
> +			reg_val |= SDHCI_CLOCK_INT_EN;
> +			sdhci_writel(host, reg_val, SDHCI_CLOCK_CONTROL);
> +		}
>  	}
>  }
>  
> @@ -214,9 +245,9 @@ static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
>  		writew(tmp, host->ioaddr + SD_CE_ATA_2);
>  
>  		/* start sending the 74 clocks */
> -		tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
> +		tmp = readw(host->ioaddr + SD_EXTRA_PARAM_REG);
>  		tmp |= SDCFG_GEN_PAD_CLK_ON;
> -		writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
> +		writew(tmp, host->ioaddr + SD_EXTRA_PARAM_REG);
>  
>  		/* slowest speed is about 100KHz or 10usec per clock */
>  		udelay(740);
> @@ -410,6 +441,7 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
>  		sdhci_get_of_property(pdev);
>  		pdata = pxav3_get_mmc_pdata(dev);
>  		pdev->dev.platform_data = pdata;
> +
>  	} else if (pdata) {
>  		/* on-chip device */
>  		if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 64b7fdb..cfed695 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1159,7 +1159,10 @@ void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
>  
>  	host->mmc->actual_clock = 0;
>  
> -	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
> +	/* Some controllers need to keep internal clk always enabled */
> +	if (host->quirks2 & SDHCI_QUIRK2_KEEP_INT_CLK_ON)
> +		clk = SDHCI_CLOCK_INT_EN;
> +	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
>  
>  	if (clock == 0)
>  		return;
> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
> index 7c02ff4..c751b78 100644
> --- a/drivers/mmc/host/sdhci.h
> +++ b/drivers/mmc/host/sdhci.h
> @@ -412,6 +412,9 @@ struct sdhci_host {
>  #define SDHCI_QUIRK2_ACMD23_BROKEN			(1<<14)
>  /* Broken Clock divider zero in controller */
>  #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN		(1<<15)
> +/* Do not disable internal clk on power-off */
> +#define SDHCI_QUIRK2_KEEP_INT_CLK_ON			(1<<16)
> +
>  
>  	int irq;		/* Device IRQ */
>  	void __iomem *ioaddr;	/* Mapped address */

[PATCH v2 2/5] mmc: sdhci-pxav3: enable usage of DAT3 pin as HW card detect

[Jisheng Zhang]

On Fri, 9 Oct 2015 03:03:52 +0200
Marcin Wojtas <mw@semihalf.com> wrote:

> Marvell Armada 38x SDHCI controller enable using DAT3 pin as a hardware
> card detection. According to the SD sdandard this signal can be used for
> this purpose combined with a pull-up resistor, implying inverted (active
> low) polarization of a card detect. MMC standard does not support this
> feature and does not operate with such connectivity of DAT3.
> 
> When using DAT3-based detection Armada 38x SDIO IP expects its internal
> clock to be always on, which had to be ensured twofold:

What happen if runtime suspend disables its core clk and axi clk? I guess
dat3-based detection isn't compatible with runtime pm. If so, do we also
need to disable runtime pm in probe function?

> - Each time controller is reset by updating appropriate registers. On the
>   occasion of adding new register @0x104, register @0x100 name is modified
>   in order to the be aligned with Armada 38x documentation.
> - Leaving the clock enabled despite power-down. For this purpose a new
>   quirk had to be added to SDHCI subsystem - SDHCI_QUIRK2_KEEP_INT_CLK_ON.

As seen from other mails, Ulf calls for no more quirks...

Thanks,
Jisheng

> 
> In addition to the changes above this commit adds a new property to Armada
> 38x SDHCI node ('dat3-cd') with an according binding documentation update.
> 
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
>  .../devicetree/bindings/mmc/sdhci-pxa.txt          |  5 +++
>  drivers/mmc/host/sdhci-pxav3.c                     | 38 ++++++++++++++++++++--
>  drivers/mmc/host/sdhci.c                           |  5 ++-
>  drivers/mmc/host/sdhci.h                           |  3 ++
>  4 files changed, 47 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
> index 3d1b449..ffd6b14 100644
> --- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
> +++ b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
> @@ -23,6 +23,11 @@ Required properties:
>  
>  Optional properties:
>  - mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning.
> +- dat3-cd: use DAT3 pin as hardware card detect - option available for
> +  "marvell,armada-380-sdhci" only. The detection is supposed to work with
> +  active high polarity, which implies usage of "cd-inverted" property.
> +  Note that according to the specifications DAT3-based card detection can be
> +  used with SD cards only. MMC standard doesn't support this feature.
>  
>  Example:
>  
> diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c
> index 76b9a70..352c5eb 100644
> --- a/drivers/mmc/host/sdhci-pxav3.c
> +++ b/drivers/mmc/host/sdhci-pxav3.c
> @@ -46,10 +46,14 @@
>  #define SDCLK_DELAY_SHIFT	9
>  #define SDCLK_DELAY_MASK	0x1f
>  
> -#define SD_CFG_FIFO_PARAM       0x100
> +#define SD_EXTRA_PARAM_REG	0x100
>  #define SDCFG_GEN_PAD_CLK_ON	(1<<6)
>  #define SDCFG_GEN_PAD_CLK_CNT_MASK	0xFF
>  #define SDCFG_GEN_PAD_CLK_CNT_SHIFT	24
> +#define SD_FIFO_PARAM_REG	0x104
> +#define SD_USE_DAT3		BIT(7)
> +#define SD_OVRRD_CLK_OEN	BIT(11)
> +#define SD_FORCE_CLK_ON		BIT(12)
>  
>  #define SD_SPI_MODE          0x108
>  #define SD_CE_ATA_1          0x10C
> @@ -163,6 +167,15 @@ static int armada_38x_quirks(struct platform_device *pdev,
>  	}
>  	host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING);
>  
> +	/*
> +	 * The interface clock enable is also used as control
> +	 * for the A38x SDIO IP, so it can't be powered down
> +	 * when using HW-based card detection.
> +	 */
> +	if (of_property_read_bool(np, "dat3-cd") &&
> +	    !of_property_read_bool(np, "broken-cd"))
> +		host->quirks2 |= SDHCI_QUIRK2_KEEP_INT_CLK_ON;
> +
>  	return 0;
>  }
>  
> @@ -170,6 +183,8 @@ static void pxav3_reset(struct sdhci_host *host, u8 mask)
>  {
>  	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
>  	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
> +	struct device_node *np = pdev->dev.of_node;
> +	u32 reg_val;
>  
>  	sdhci_reset(host, mask);
>  
> @@ -187,6 +202,22 @@ static void pxav3_reset(struct sdhci_host *host, u8 mask)
>  			tmp |= SDCLK_SEL;
>  			writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
>  		}
> +
> +		if (of_device_is_compatible(np, "marvell,armada-380-sdhci") &&
> +		    host->quirks2 & SDHCI_QUIRK2_KEEP_INT_CLK_ON) {
> +			reg_val = sdhci_readl(host, SD_FIFO_PARAM_REG);
> +			reg_val |= SD_USE_DAT3 | SD_OVRRD_CLK_OEN |
> +				   SD_FORCE_CLK_ON;
> +			sdhci_writel(host, reg_val, SD_FIFO_PARAM_REG);
> +
> +			/*
> +			 * For HW detection based on DAT3 pin keep internal
> +			 * clk switched on after controller reset.
> +			 */
> +			reg_val = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
> +			reg_val |= SDHCI_CLOCK_INT_EN;
> +			sdhci_writel(host, reg_val, SDHCI_CLOCK_CONTROL);
> +		}
>  	}
>  }
>  
> @@ -214,9 +245,9 @@ static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
>  		writew(tmp, host->ioaddr + SD_CE_ATA_2);
>  
>  		/* start sending the 74 clocks */
> -		tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
> +		tmp = readw(host->ioaddr + SD_EXTRA_PARAM_REG);
>  		tmp |= SDCFG_GEN_PAD_CLK_ON;
> -		writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
> +		writew(tmp, host->ioaddr + SD_EXTRA_PARAM_REG);
>  
>  		/* slowest speed is about 100KHz or 10usec per clock */
>  		udelay(740);
> @@ -410,6 +441,7 @@ static int sdhci_pxav3_probe(struct platform_device *pdev)
>  		sdhci_get_of_property(pdev);
>  		pdata = pxav3_get_mmc_pdata(dev);
>  		pdev->dev.platform_data = pdata;
> +
>  	} else if (pdata) {
>  		/* on-chip device */
>  		if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 64b7fdb..cfed695 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1159,7 +1159,10 @@ void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
>  
>  	host->mmc->actual_clock = 0;
>  
> -	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
> +	/* Some controllers need to keep internal clk always enabled */
> +	if (host->quirks2 & SDHCI_QUIRK2_KEEP_INT_CLK_ON)
> +		clk = SDHCI_CLOCK_INT_EN;
> +	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
>  
>  	if (clock == 0)
>  		return;
> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
> index 7c02ff4..c751b78 100644
> --- a/drivers/mmc/host/sdhci.h
> +++ b/drivers/mmc/host/sdhci.h
> @@ -412,6 +412,9 @@ struct sdhci_host {
>  #define SDHCI_QUIRK2_ACMD23_BROKEN			(1<<14)
>  /* Broken Clock divider zero in controller */
>  #define SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN		(1<<15)
> +/* Do not disable internal clk on power-off */
> +#define SDHCI_QUIRK2_KEEP_INT_CLK_ON			(1<<16)
> +
>  
>  	int irq;		/* Device IRQ */
>  	void __iomem *ioaddr;	/* Mapped address */

Re: [PATCH v2 2/5] mmc: sdhci-pxav3: enable usage of DAT3 pin as HW card detect

[Russell King - ARM Linux]

On Fri, Oct 09, 2015 at 08:13:56PM +0800, Jisheng Zhang wrote:
> On Fri, 9 Oct 2015 03:03:52 +0200
> Marcin Wojtas <mw@semihalf.com> wrote:
> 
> > Marvell Armada 38x SDHCI controller enable using DAT3 pin as a hardware
> > card detection. According to the SD sdandard this signal can be used for
> > this purpose combined with a pull-up resistor, implying inverted (active
> > low) polarization of a card detect. MMC standard does not support this
> > feature and does not operate with such connectivity of DAT3.
> > 
> > When using DAT3-based detection Armada 38x SDIO IP expects its internal
> > clock to be always on, which had to be ensured twofold:
> 
> What happen if runtime suspend disables its core clk and axi clk? I guess
> dat3-based detection isn't compatible with runtime pm. If so, do we also
> need to disable runtime pm in probe function?
> 
> > - Each time controller is reset by updating appropriate registers. On the
> >   occasion of adding new register @0x104, register @0x100 name is modified
> >   in order to the be aligned with Armada 38x documentation.
> > - Leaving the clock enabled despite power-down. For this purpose a new
> >   quirk had to be added to SDHCI subsystem - SDHCI_QUIRK2_KEEP_INT_CLK_ON.
> 
> As seen from other mails, Ulf calls for no more quirks...

Absolutely.

You have host->ops->set_clock, which you currently have set to
sdhci_set_clock().  If you need to do something different, please replace
that method with your own version - its fine to either wrap sdhci_set_clock()
or replace it entirely.

sdhci_set_clock() may benefit from being factored a little, so that it's
easier to replace parts of it.

-- 
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

[PATCH v2 2/5] mmc: sdhci-pxav3: enable usage of DAT3 pin as HW card detect

[Russell King - ARM Linux]

On Fri, Oct 09, 2015 at 08:13:56PM +0800, Jisheng Zhang wrote:
> On Fri, 9 Oct 2015 03:03:52 +0200
> Marcin Wojtas <mw@semihalf.com> wrote:
> 
> > Marvell Armada 38x SDHCI controller enable using DAT3 pin as a hardware
> > card detection. According to the SD sdandard this signal can be used for
> > this purpose combined with a pull-up resistor, implying inverted (active
> > low) polarization of a card detect. MMC standard does not support this
> > feature and does not operate with such connectivity of DAT3.
> > 
> > When using DAT3-based detection Armada 38x SDIO IP expects its internal
> > clock to be always on, which had to be ensured twofold:
> 
> What happen if runtime suspend disables its core clk and axi clk? I guess
> dat3-based detection isn't compatible with runtime pm. If so, do we also
> need to disable runtime pm in probe function?
> 
> > - Each time controller is reset by updating appropriate registers. On the
> >   occasion of adding new register @0x104, register @0x100 name is modified
> >   in order to the be aligned with Armada 38x documentation.
> > - Leaving the clock enabled despite power-down. For this purpose a new
> >   quirk had to be added to SDHCI subsystem - SDHCI_QUIRK2_KEEP_INT_CLK_ON.
> 
> As seen from other mails, Ulf calls for no more quirks...

Absolutely.

You have host->ops->set_clock, which you currently have set to
sdhci_set_clock().  If you need to do something different, please replace
that method with your own version - its fine to either wrap sdhci_set_clock()
or replace it entirely.

sdhci_set_clock() may benefit from being factored a little, so that it's
easier to replace parts of it.

-- 
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.

Re: [PATCH v2 3/5] ARM: mvebu: set SW polling as SDHCI card detection on A388-GP

[Andrew Lunn]

On Fri, Oct 09, 2015 at 03:03:53AM +0200, Marcin Wojtas wrote:
> The newest revisions of A388-GP (v1.5 and higher) support only
> DAT3-based card detection. Revisions < v1.5 based on GPIO detection
> via I2C expander, but this solution is supposed to be deprecated on
> new boards. In order to satisfy all type of hardware this commit
> changes card detection to use software polling mechanism.

Hi Marcin

Thanks for going with broken-cd and not introducing a regression for
older boards. As others have said, a comment would be good, but
otherwise:

Acked-by: Andrew Lunn <andrew@lunn.ch>

Thanks
	Andrew

> 
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
>  arch/arm/boot/dts/armada-388-gp.dts | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts
> index 391dea9..403a86b 100644
> --- a/arch/arm/boot/dts/armada-388-gp.dts
> +++ b/arch/arm/boot/dts/armada-388-gp.dts
> @@ -213,8 +213,8 @@
>  			sdhci@d8000 {
>  				pinctrl-names = "default";
>  				pinctrl-0 = <&sdhci_pins>;
> -				cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
>  				no-1-8-v;
> +				broken-cd;
>  				wp-inverted;
>  				bus-width = <8>;
>  				status = "okay";
> -- 
> 1.8.3.1
> 

[PATCH v2 3/5] ARM: mvebu: set SW polling as SDHCI card detection on A388-GP

[Andrew Lunn]

On Fri, Oct 09, 2015 at 03:03:53AM +0200, Marcin Wojtas wrote:
> The newest revisions of A388-GP (v1.5 and higher) support only
> DAT3-based card detection. Revisions < v1.5 based on GPIO detection
> via I2C expander, but this solution is supposed to be deprecated on
> new boards. In order to satisfy all type of hardware this commit
> changes card detection to use software polling mechanism.

Hi Marcin

Thanks for going with broken-cd and not introducing a regression for
older boards. As others have said, a comment would be good, but
otherwise:

Acked-by: Andrew Lunn <andrew@lunn.ch>

Thanks
	Andrew

> 
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
>  arch/arm/boot/dts/armada-388-gp.dts | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts
> index 391dea9..403a86b 100644
> --- a/arch/arm/boot/dts/armada-388-gp.dts
> +++ b/arch/arm/boot/dts/armada-388-gp.dts
> @@ -213,8 +213,8 @@
>  			sdhci at d8000 {
>  				pinctrl-names = "default";
>  				pinctrl-0 = <&sdhci_pins>;
> -				cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
>  				no-1-8-v;
> +				broken-cd;
>  				wp-inverted;
>  				bus-width = <8>;
>  				status = "okay";
> -- 
> 1.8.3.1
> 

Re: [PATCH v2 2/5] mmc: sdhci-pxav3: enable usage of DAT3 pin as HW card detect

[Marcin Wojtas]

Jisheng,


>>
>> When using DAT3-based detection Armada 38x SDIO IP expects its internal
>> clock to be always on, which had to be ensured twofold:
>
> What happen if runtime suspend disables its core clk and axi clk? I guess
> dat3-based detection isn't compatible with runtime pm. If so, do we also
> need to disable runtime pm in probe function?

Is runtime resume supposed to be triggered by card detection? Is there
a way to manually trigger runtime suspend and resume of sdhci? Anyway
coreclk is not a problem, as it's not used by A38x.

>
>> - Each time controller is reset by updating appropriate registers. On the
>>   occasion of adding new register @0x104, register @0x100 name is modified
>>   in order to the be aligned with Armada 38x documentation.
>> - Leaving the clock enabled despite power-down. For this purpose a new
>>   quirk had to be added to SDHCI subsystem - SDHCI_QUIRK2_KEEP_INT_CLK_ON.
>
> As seen from other mails, Ulf calls for no more quirks...
>

Ok, I'll try to find another solution.

Best regards,
Marcin

[PATCH v2 2/5] mmc: sdhci-pxav3: enable usage of DAT3 pin as HW card detect

[Marcin Wojtas]

Jisheng,


>>
>> When using DAT3-based detection Armada 38x SDIO IP expects its internal
>> clock to be always on, which had to be ensured twofold:
>
> What happen if runtime suspend disables its core clk and axi clk? I guess
> dat3-based detection isn't compatible with runtime pm. If so, do we also
> need to disable runtime pm in probe function?

Is runtime resume supposed to be triggered by card detection? Is there
a way to manually trigger runtime suspend and resume of sdhci? Anyway
coreclk is not a problem, as it's not used by A38x.

>
>> - Each time controller is reset by updating appropriate registers. On the
>>   occasion of adding new register @0x104, register @0x100 name is modified
>>   in order to the be aligned with Armada 38x documentation.
>> - Leaving the clock enabled despite power-down. For this purpose a new
>>   quirk had to be added to SDHCI subsystem - SDHCI_QUIRK2_KEEP_INT_CLK_ON.
>
> As seen from other mails, Ulf calls for no more quirks...
>

Ok, I'll try to find another solution.

Best regards,
Marcin

Re: [PATCH v2 2/5] mmc: sdhci-pxav3: enable usage of DAT3 pin as HW card detect

[Jisheng Zhang]

Hi Marcin,

On Fri, 9 Oct 2015 16:45:25 +0200
Marcin Wojtas <mw@semihalf.com> wrote:

> Jisheng,
> 
> 
> >>
> >> When using DAT3-based detection Armada 38x SDIO IP expects its internal
> >> clock to be always on, which had to be ensured twofold:
> >
> > What happen if runtime suspend disables its core clk and axi clk? I guess
> > dat3-based detection isn't compatible with runtime pm. If so, do we also
> > need to disable runtime pm in probe function?
> 
> Is runtime resume supposed to be triggered by card detection? Is there

I think so. Take marvell berlin for example, card insert => gpio interrupt
or => sdhci runtime resume.

> a way to manually trigger runtime suspend and resume of sdhci? Anyway

If runtime-pm is builtin and the host driver supports runtime-pm (sdhci-pxav3
supports runtime-pm well), when there's no sdhc transactions, runtime suspend
will be triggered automatically after some time (50ms?)

> coreclk is not a problem, as it's not used by A38x.

I checked A38x dts files, it's <&gateclk 17>. So the question is: what will
happen if <&gateclk 17> is disabled in runtime suspend? Is the dat3-based
CD still works? In theory, it should not work any more.

> 
> >
> >> - Each time controller is reset by updating appropriate registers. On the
> >>   occasion of adding new register @0x104, register @0x100 name is modified
> >>   in order to the be aligned with Armada 38x documentation.
> >> - Leaving the clock enabled despite power-down. For this purpose a new
> >>   quirk had to be added to SDHCI subsystem - SDHCI_QUIRK2_KEEP_INT_CLK_ON.
> >
> > As seen from other mails, Ulf calls for no more quirks...
> >
> 
> Ok, I'll try to find another solution.
> 
> Best regards,
> Marcin

[PATCH v2 2/5] mmc: sdhci-pxav3: enable usage of DAT3 pin as HW card detect

[Jisheng Zhang]

Hi Marcin,

On Fri, 9 Oct 2015 16:45:25 +0200
Marcin Wojtas <mw@semihalf.com> wrote:

> Jisheng,
> 
> 
> >>
> >> When using DAT3-based detection Armada 38x SDIO IP expects its internal
> >> clock to be always on, which had to be ensured twofold:
> >
> > What happen if runtime suspend disables its core clk and axi clk? I guess
> > dat3-based detection isn't compatible with runtime pm. If so, do we also
> > need to disable runtime pm in probe function?
> 
> Is runtime resume supposed to be triggered by card detection? Is there

I think so. Take marvell berlin for example, card insert => gpio interrupt
or => sdhci runtime resume.

> a way to manually trigger runtime suspend and resume of sdhci? Anyway

If runtime-pm is builtin and the host driver supports runtime-pm (sdhci-pxav3
supports runtime-pm well), when there's no sdhc transactions, runtime suspend
will be triggered automatically after some time (50ms?)

> coreclk is not a problem, as it's not used by A38x.

I checked A38x dts files, it's <&gateclk 17>. So the question is: what will
happen if <&gateclk 17> is disabled in runtime suspend? Is the dat3-based
CD still works? In theory, it should not work any more.

> 
> >
> >> - Each time controller is reset by updating appropriate registers. On the
> >>   occasion of adding new register @0x104, register @0x100 name is modified
> >>   in order to the be aligned with Armada 38x documentation.
> >> - Leaving the clock enabled despite power-down. For this purpose a new
> >>   quirk had to be added to SDHCI subsystem - SDHCI_QUIRK2_KEEP_INT_CLK_ON.
> >
> > As seen from other mails, Ulf calls for no more quirks...
> >
> 
> Ok, I'll try to find another solution.
> 
> Best regards,
> Marcin

Re: [PATCH v2 2/5] mmc: sdhci-pxav3: enable usage of DAT3 pin as HW card detect

[Marcin Wojtas]

Hi Jisheng,


>>
>> >>
>> >> When using DAT3-based detection Armada 38x SDIO IP expects its internal
>> >> clock to be always on, which had to be ensured twofold:
>> >
>> > What happen if runtime suspend disables its core clk and axi clk? I guess
>> > dat3-based detection isn't compatible with runtime pm. If so, do we also
>> > need to disable runtime pm in probe function?
>>
>> Is runtime resume supposed to be triggered by card detection? Is there
>
> I think so. Take marvell berlin for example, card insert => gpio interrupt
> or => sdhci runtime resume.
>
>> a way to manually trigger runtime suspend and resume of sdhci? Anyway
>
> If runtime-pm is builtin and the host driver supports runtime-pm (sdhci-pxav3
> supports runtime-pm well), when there's no sdhc transactions, runtime suspend
> will be triggered automatically after some time (50ms?)
>
>> coreclk is not a problem, as it's not used by A38x.
>
> I checked A38x dts files, it's <&gateclk 17>. So the question is: what will
> happen if <&gateclk 17> is disabled in runtime suspend? Is the dat3-based
> CD still works? In theory, it should not work any more.
>

Actually in pxav3 driver there is one obligatory clock ("io") which
can be either named in dts on not (like in armada38x.dtsi). "coreclk"
is optional, however all this does not matter, as both are disabled in
runtime_suspend function. I think that when we disable the gate clock,
dat3 detection won't work, but I guess that card detection is not the
only thing that wakes up the mmc subsystem and make runtime_pm useful.

I will try to check how it works. If there's problem with detection I
propose, in order not to spoil the code too much and not to loose all
runtime_pm benefits, to avoid disabling/enabling clock in
runtime_suspend/resume functions on a38x working with dat3 detection.
In such case sdhci_runtime_suspend/resume would execute without
problems and we will be sure that detection will work in such
configuration.

Best regards,
Marcin

[PATCH v2 2/5] mmc: sdhci-pxav3: enable usage of DAT3 pin as HW card detect

[Marcin Wojtas]

Hi Jisheng,


>>
>> >>
>> >> When using DAT3-based detection Armada 38x SDIO IP expects its internal
>> >> clock to be always on, which had to be ensured twofold:
>> >
>> > What happen if runtime suspend disables its core clk and axi clk? I guess
>> > dat3-based detection isn't compatible with runtime pm. If so, do we also
>> > need to disable runtime pm in probe function?
>>
>> Is runtime resume supposed to be triggered by card detection? Is there
>
> I think so. Take marvell berlin for example, card insert => gpio interrupt
> or => sdhci runtime resume.
>
>> a way to manually trigger runtime suspend and resume of sdhci? Anyway
>
> If runtime-pm is builtin and the host driver supports runtime-pm (sdhci-pxav3
> supports runtime-pm well), when there's no sdhc transactions, runtime suspend
> will be triggered automatically after some time (50ms?)
>
>> coreclk is not a problem, as it's not used by A38x.
>
> I checked A38x dts files, it's <&gateclk 17>. So the question is: what will
> happen if <&gateclk 17> is disabled in runtime suspend? Is the dat3-based
> CD still works? In theory, it should not work any more.
>

Actually in pxav3 driver there is one obligatory clock ("io") which
can be either named in dts on not (like in armada38x.dtsi). "coreclk"
is optional, however all this does not matter, as both are disabled in
runtime_suspend function. I think that when we disable the gate clock,
dat3 detection won't work, but I guess that card detection is not the
only thing that wakes up the mmc subsystem and make runtime_pm useful.

I will try to check how it works. If there's problem with detection I
propose, in order not to spoil the code too much and not to loose all
runtime_pm benefits, to avoid disabling/enabling clock in
runtime_suspend/resume functions on a38x working with dat3 detection.
In such case sdhci_runtime_suspend/resume would execute without
problems and we will be sure that detection will work in such
configuration.

Best regards,
Marcin

Re: [PATCH v2 2/5] mmc: sdhci-pxav3: enable usage of DAT3 pin as HW card detect

[Jisheng Zhang]

Hi Marcin,

On Sat, 10 Oct 2015 14:13:51 +0200
Marcin Wojtas <mw@semihalf.com> wrote:

> Hi Jisheng,
> 
> 
> >>
> >> >>
> >> >> When using DAT3-based detection Armada 38x SDIO IP expects its internal
> >> >> clock to be always on, which had to be ensured twofold:
> >> >
> >> > What happen if runtime suspend disables its core clk and axi clk? I guess
> >> > dat3-based detection isn't compatible with runtime pm. If so, do we also
> >> > need to disable runtime pm in probe function?
> >>
> >> Is runtime resume supposed to be triggered by card detection? Is there
> >
> > I think so. Take marvell berlin for example, card insert => gpio interrupt
> > or => sdhci runtime resume.
> >
> >> a way to manually trigger runtime suspend and resume of sdhci? Anyway
> >
> > If runtime-pm is builtin and the host driver supports runtime-pm (sdhci-pxav3
> > supports runtime-pm well), when there's no sdhc transactions, runtime suspend
> > will be triggered automatically after some time (50ms?)
> >
> >> coreclk is not a problem, as it's not used by A38x.
> >
> > I checked A38x dts files, it's <&gateclk 17>. So the question is: what will
> > happen if <&gateclk 17> is disabled in runtime suspend? Is the dat3-based
> > CD still works? In theory, it should not work any more.
> >
> 
> Actually in pxav3 driver there is one obligatory clock ("io") which
> can be either named in dts on not (like in armada38x.dtsi). "coreclk"
> is optional, however all this does not matter, as both are disabled in

Hmm, grep the dts, I think commit 8afdc9cca27f ("mmc: sdhci-pxav3: Get optional
core clock") mainly targets for Marvell Berlin SoCs, but the two clks for sdhci
in Berlin SoCs are coreclk and axiclk, rather than ioclk and coreclk, during
which the axiclk is optional. Will cook one patch to fix this.

> runtime_suspend function. I think that when we disable the gate clock,
> dat3 detection won't work, but I guess that card detection is not the
> only thing that wakes up the mmc subsystem and make runtime_pm useful.

Card insert is not the only thing can wake up mmc, mmc initiate sdhc
transactions will also wake up mmc.

Thanks,
Jisheng

> 
> I will try to check how it works. If there's problem with detection I
> propose, in order not to spoil the code too much and not to loose all
> runtime_pm benefits, to avoid disabling/enabling clock in
> runtime_suspend/resume functions on a38x working with dat3 detection.
> In such case sdhci_runtime_suspend/resume would execute without
> problems and we will be sure that detection will work in such
> configuration.
> 
> Best regards,
> Marcin

[PATCH v2 2/5] mmc: sdhci-pxav3: enable usage of DAT3 pin as HW card detect

[Jisheng Zhang]

Hi Marcin,

On Sat, 10 Oct 2015 14:13:51 +0200
Marcin Wojtas <mw@semihalf.com> wrote:

> Hi Jisheng,
> 
> 
> >>
> >> >>
> >> >> When using DAT3-based detection Armada 38x SDIO IP expects its internal
> >> >> clock to be always on, which had to be ensured twofold:
> >> >
> >> > What happen if runtime suspend disables its core clk and axi clk? I guess
> >> > dat3-based detection isn't compatible with runtime pm. If so, do we also
> >> > need to disable runtime pm in probe function?
> >>
> >> Is runtime resume supposed to be triggered by card detection? Is there
> >
> > I think so. Take marvell berlin for example, card insert => gpio interrupt
> > or => sdhci runtime resume.
> >
> >> a way to manually trigger runtime suspend and resume of sdhci? Anyway
> >
> > If runtime-pm is builtin and the host driver supports runtime-pm (sdhci-pxav3
> > supports runtime-pm well), when there's no sdhc transactions, runtime suspend
> > will be triggered automatically after some time (50ms?)
> >
> >> coreclk is not a problem, as it's not used by A38x.
> >
> > I checked A38x dts files, it's <&gateclk 17>. So the question is: what will
> > happen if <&gateclk 17> is disabled in runtime suspend? Is the dat3-based
> > CD still works? In theory, it should not work any more.
> >
> 
> Actually in pxav3 driver there is one obligatory clock ("io") which
> can be either named in dts on not (like in armada38x.dtsi). "coreclk"
> is optional, however all this does not matter, as both are disabled in

Hmm, grep the dts, I think commit 8afdc9cca27f ("mmc: sdhci-pxav3: Get optional
core clock") mainly targets for Marvell Berlin SoCs, but the two clks for sdhci
in Berlin SoCs are coreclk and axiclk, rather than ioclk and coreclk, during
which the axiclk is optional. Will cook one patch to fix this.

> runtime_suspend function. I think that when we disable the gate clock,
> dat3 detection won't work, but I guess that card detection is not the
> only thing that wakes up the mmc subsystem and make runtime_pm useful.

Card insert is not the only thing can wake up mmc, mmc initiate sdhc
transactions will also wake up mmc.

Thanks,
Jisheng

> 
> I will try to check how it works. If there's problem with detection I
> propose, in order not to spoil the code too much and not to loose all
> runtime_pm benefits, to avoid disabling/enabling clock in
> runtime_suspend/resume functions on a38x working with dat3 detection.
> In such case sdhci_runtime_suspend/resume would execute without
> problems and we will be sure that detection will work in such
> configuration.
> 
> Best regards,
> Marcin