[PATCH v5 0/4] Add support for the Armada-370-based Seagate NAS

[PATCH v5 0/4] Add support for the Armada-370-based Seagate NAS

[Simon Guinot]

Hi,

This patch series adds support for the Seagate machines based on the
Armada-370 Marvell SoC. This includes the Personal Cloud 1 and 2-Bay
and the Seagate NAS 2 and 4-Bay.

Changes for v2:
- Rename DTS files using the products names.
- Update model and compatible properties as well.
- Add some information allowing to identify the devices in the commit
  message and in the DTS files headers.
- Remove duplicated rtc alias in armada-370-seagate-nas-xbay.dtsi.

Changes for v3:
- Use GPIO_ACTIVE_HIGH instead of 0 in gpios property (gpio-fan node).
- Fix spelling for Personal Cloud DTS files: 'personal' instead of
  'personnal'.
- Add Andrew's Acked-by.

Changes for v4:
- Introduces a DT coherency-fabric property: broken-idle.
- Use this new property to disable cpuidle support on Personal Cloud
  boards.
- Use this new property with Armada 38x SoCs as well.

Changes for v5:
- Make the broken-idle property boolean.
- Don't use the broken-idle flag for Armada 38x.

Thanks,

Simon

Simon Guinot (2):
  ARM: mvebu: add DT support for Seagate Personal Cloud
  ARM: mvebu: enable options for Seagate NAS in mvebu_v7_defconfig

Vincent Donnefort (2):
  ARM: mvebu: add broken-idle option
  ARM: mvebu: add DT support for Seagate NAS 2 and 4-Bay

 .../devicetree/bindings/arm/coherency-fabric.txt   |   5 +
 arch/arm/boot/dts/Makefile                         |   4 +
 arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts  |  36 ++++
 arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts  | 133 ++++++++++++
 arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi | 231 +++++++++++++++++++++
 .../dts/armada-370-seagate-personal-cloud-2bay.dts |  51 +++++
 .../boot/dts/armada-370-seagate-personal-cloud.dts |  37 ++++
 .../dts/armada-370-seagate-personal-cloud.dtsi     | 178 ++++++++++++++++
 arch/arm/configs/mvebu_v7_defconfig                |   9 +-
 arch/arm/mach-mvebu/pmsu.c                         |  29 ++-
 10 files changed, 709 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts
 create mode 100644 arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts
 create mode 100644 arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
 create mode 100644 arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts
 create mode 100644 arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts
 create mode 100644 arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi

-- 
2.1.4

[PATCH v5 1/4] ARM: mvebu: add broken-idle option

[Simon Guinot]

From: Vincent Donnefort <vdonnefort@gmail.com>

The broken-idle option can be activated from the coherency-fabric DT
node. This property allows to disable the idle capability, when the
hardware doesn't support it, like the Seagate Personal Cloud boards.

Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com>
---
 .../devicetree/bindings/arm/coherency-fabric.txt   |  5 ++++
 arch/arm/mach-mvebu/pmsu.c                         | 29 +++++++++++++++++++---
 2 files changed, 31 insertions(+), 3 deletions(-)

Changes for v5:
- Make the broken-idle property boolean.
- Don't use the broken-idle flag for Armada 38x.

diff --git a/Documentation/devicetree/bindings/arm/coherency-fabric.txt b/Documentation/devicetree/bindings/arm/coherency-fabric.txt
index 8dd46617c889..9b5c3f620e65 100644
--- a/Documentation/devicetree/bindings/arm/coherency-fabric.txt
+++ b/Documentation/devicetree/bindings/arm/coherency-fabric.txt
@@ -27,6 +27,11 @@ Required properties:
  * For "marvell,armada-380-coherency-fabric", only one pair is needed
    for the per-CPU fabric registers.
 
+Optional properties:
+
+- broken-idle: boolean to set when the Idle mode is not supported by the
+  hardware.
+
 Examples:
 
 coherency-fabric at d0020200 {
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index e8fdb9ceedf0..cba3fa985734 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -379,6 +379,16 @@ static struct notifier_block mvebu_v7_cpu_pm_notifier = {
 
 static struct platform_device mvebu_v7_cpuidle_device;
 
+static int broken_idle(struct device_node *np)
+{
+	if (of_property_read_bool(np, "broken-idle")) {
+		pr_warn("CPU idle is currently broken: disabling\n");
+		return 0;
+	}
+
+	return 1;
+}
+
 static __init int armada_370_cpuidle_init(void)
 {
 	struct device_node *np;
@@ -387,7 +397,9 @@ static __init int armada_370_cpuidle_init(void)
 	np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
 	if (!np)
 		return -ENODEV;
-	of_node_put(np);
+
+	if (!broken_idle(np))
+		goto end;
 
 	/*
 	 * On Armada 370, there is "a slow exit process from the deep
@@ -406,6 +418,8 @@ static __init int armada_370_cpuidle_init(void)
 	mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
 	mvebu_v7_cpuidle_device.name = "cpuidle-armada-370";
 
+end:
+	of_node_put(np);
 	return 0;
 }
 
@@ -422,6 +436,10 @@ static __init int armada_38x_cpuidle_init(void)
 				     "marvell,armada-380-coherency-fabric");
 	if (!np)
 		return -ENODEV;
+
+	if (!broken_idle(np))
+		goto end;
+
 	of_node_put(np);
 
 	np = of_find_compatible_node(NULL, NULL,
@@ -430,7 +448,6 @@ static __init int armada_38x_cpuidle_init(void)
 		return -ENODEV;
 	mpsoc_base = of_iomap(np, 0);
 	BUG_ON(!mpsoc_base);
-	of_node_put(np);
 
 	/* Set up reset mask when powering down the cpus */
 	reg = readl(mpsoc_base + MPCORE_RESET_CTL);
@@ -450,6 +467,8 @@ static __init int armada_38x_cpuidle_init(void)
 	mvebu_v7_cpuidle_device.dev.platform_data = armada_38x_cpu_suspend;
 	mvebu_v7_cpuidle_device.name = "cpuidle-armada-38x";
 
+end:
+	of_node_put(np);
 	return 0;
 }
 
@@ -460,12 +479,16 @@ static __init int armada_xp_cpuidle_init(void)
 	np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
 	if (!np)
 		return -ENODEV;
-	of_node_put(np);
+
+	if (!broken_idle(np))
+		goto end;
 
 	mvebu_cpu_resume = armada_370_xp_cpu_resume;
 	mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
 	mvebu_v7_cpuidle_device.name = "cpuidle-armada-xp";
 
+end:
+	of_node_put(np);
 	return 0;
 }
 
-- 
2.1.4

[PATCH v5 2/4] ARM: mvebu: add DT support for Seagate NAS 2 and 4-Bay

[Simon Guinot]

From: Vincent Donnefort <vdonnefort@gmail.com>

This patch adds DT support for the Seagate NAS 2 and 4-Bay.

Here are some information allowing to identify these devices:

Product name                 | Seagate NAS 2-Bay | Seagate NAS 4-Bay
Code name (board/PCB)        | Dart 2-Bay        | Dart 4-Bay
Model name (case sticker)    | SRPD20            | SRPD40
Material desc (product spec) | STCTxxxxxxx       | STCUxxxxxxx

Chipset list (common):
- SoC Marvell Armada 370 88F6707, CPU @1.2GHz
- SDRAM memory: 512MB DDR3 600MHz (16-bits bandwidth)
- NAND flash 256MB, 8-bits (Micron MT29F2G08AAB or Hinyx H27U2G8F2CTR-BC)
- 2 SATA II ports (SoC)
- 1 Ethernet Gigabit ports (PHY Marvell 88E1518)
- 2 USB3 host ports (PCIe controller ASM1042)
- GPIO fan (4 speeds)
- External I2C RTC (MCP7940NT)
- 3 push buttons (power, backup and reset)
- 2 SATA LEDs (bi-color, blue and red)
- 1 power LED (bi-color, blue and red)

Only on 4-Bay models:
- 2 extra SATA III ports (PCIe AHCI controller Marvell 88SE9170)
- 1 extra Ethernet Gigabit ports (PHY Marvell 88E1518)
- I2C GPIO expander (PCA9554A)
- 2 extra SATA LEDs (bi-color, blue and red)

Note that support for the white SATA LEDs associated with HDDs 0 and 1
is missing. A dedicated LED driver is needed.

Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
---
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts  |  36 ++++
 arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts  | 133 ++++++++++++
 arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi | 231 +++++++++++++++++++++
 4 files changed, 402 insertions(+)
 create mode 100644 arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts
 create mode 100644 arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts
 create mode 100644 arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi

Changes for v2:
- Rename DTS files using the products names.
- Update model and compatible properties as well.
- Add some information allowing to identify the devices in the commit
  message and in the DTS files headers.
- Remove duplicated rtc alias in armada-370-seagate-nas-xbay.dtsi.

Changes for v3:
- Use GPIO_ACTIVE_HIGH instead of 0 in gpios property (gpio-fan node).
- Add Andrew's Acked-by.

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 1c5f22525a8b..a0cc0b63db41 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -710,6 +710,8 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
 	armada-370-netgear-rn102.dtb \
 	armada-370-netgear-rn104.dtb \
 	armada-370-rd.dtb \
+	armada-370-seagate-nas-2bay.dtb \
+	armada-370-seagate-nas-4bay.dtb \
 	armada-370-synology-ds213j.dtb
 dtb-$(CONFIG_MACH_ARMADA_375) += \
 	armada-375-db.dtb
diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts b/arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts
new file mode 100644
index 000000000000..fef0110a8d8a
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts
@@ -0,0 +1,36 @@
+/*
+ * Device Tree file for Seagate NAS 2-Bay (Armada 370 SoC).
+ *
+ * Copyright (C) 2015 Seagate
+ *
+ * Author: Vincent Donnefort <vdonnefort@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/*
+ * Here are some information allowing to identify the device:
+ *
+ * Product name                 : Seagate NAS 2-Bay
+ * Code name (board/PCB)        : Dart 2-Bay
+ * Model name (case sticker)    : SRPD20
+ * Material desc (product spec) : STCTxxxxxxx
+ */
+
+/dts-v1/;
+#include "armada-370-seagate-nas-xbay.dtsi"
+
+/ {
+	model = "Seagate NAS 2-Bay (Dart, SRPD20)";
+	compatible = "seagate,dart-2", "marvell,armada370", "marvell,armada-370-xp";
+
+	gpio-fan {
+		gpio-fan,speed-map =
+			<   0 3
+			  950 2
+			 1400 1
+			 1800 0>;
+	};
+};
diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts b/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts
new file mode 100644
index 000000000000..ae2e1fe50ef6
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts
@@ -0,0 +1,133 @@
+/*
+ * Device Tree file for Seagate NAS 4-Bay (Armada 370 SoC).
+ *
+ * Copyright (C) 2015 Seagate
+ *
+ * Author: Vincent Donnefort <vdonnefort@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/*
+ * Here are some information allowing to identify the device:
+ *
+ * Product name                 : Seagate NAS 4-Bay
+ * Code name (board/PCB)        : Dart 4-Bay
+ * Model name (case sticker)    : SRPD40
+ * Material desc (product spec) : STCUxxxxxxx
+ */
+
+/dts-v1/;
+#include "armada-370-seagate-nas-xbay.dtsi"
+#include <dt-bindings/leds/leds-ns2.h>
+
+/ {
+	model = "Seagate NAS 4-Bay (Dart, SRPD40)";
+	compatible = "seagate,dart-4", "marvell,armada370", "marvell,armada-370-xp";
+
+	soc {
+		pcie-controller {
+			/* SATA AHCI controller 88SE9170 */
+			pcie at 1,0 {
+				status = "okay";
+			};
+		};
+
+		internal-regs {
+			mdio {
+				phy1: ethernet-phy at 1 {
+					reg = <1>;
+				};
+			};
+
+			ethernet at 74000 {
+				status = "okay";
+				pinctrl-0 = <&ge1_rgmii_pins>;
+				pinctrl-names = "default";
+				phy = <&phy1>;
+				phy-mode = "rgmii-id";
+			};
+
+			i2c at 11000 {
+				/* I2C GPIO expander (PCA9554A) */
+				pca9554: pca9554 at 21 {
+					compatible = "nxp,pca9554";
+					reg = <0x21>;
+					#gpio-cells = <2>;
+					gpio-controller;
+				};
+			};
+		};
+	};
+
+	regulators {
+		regulator at 3 {
+			compatible = "regulator-fixed";
+			reg = <3>;
+			regulator-name = "SATA2 power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&pca9554 6 GPIO_ACTIVE_HIGH>;
+		};
+		regulator at 4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "SATA3 power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&pca9554 7 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	gpio-leds {
+		red-sata2 {
+			label = "dart:red:sata2";
+			gpios = <&pca9554 0 GPIO_ACTIVE_LOW>;
+		};
+		red-sata3 {
+			label = "dart:red:sata3";
+			gpios = <&pca9554 3 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	leds-ns2 {
+		compatible = "lacie,ns2-leds";
+
+		white-sata2 {
+			label = "dart:white:sata2";
+			cmd-gpio = <&pca9554 1 GPIO_ACTIVE_HIGH>;
+			slow-gpio = <&pca9554 2 GPIO_ACTIVE_HIGH>;
+			num-modes = <4>;
+			modes-map = <NS_V2_LED_SATA 0 0
+				     NS_V2_LED_OFF  0 1
+				     NS_V2_LED_ON   1 0
+				     NS_V2_LED_ON   1 1>;
+		};
+		white-sata3 {
+			label = "dart:white:sata3";
+			cmd-gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
+			slow-gpio = <&pca9554 5 GPIO_ACTIVE_HIGH>;
+			num-modes = <4>;
+			modes-map = <NS_V2_LED_SATA 0 0
+				     NS_V2_LED_OFF  0 1
+				     NS_V2_LED_ON   1 0
+				     NS_V2_LED_ON   1 1>;
+		};
+	};
+
+	gpio-fan {
+		gpio-fan,speed-map =
+			<   0 3
+			  800 2
+			  1050 1
+			  1300 0>;
+	};
+};
diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
new file mode 100644
index 000000000000..3036e25c5992
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
@@ -0,0 +1,231 @@
+/*
+ * Device Tree common file for the Seagate NAS 2 and 4-bay (Armada 370 SoC).
+ *
+ * Copyright (C) 2015 Seagate
+ *
+ * Author: Vincent Donnefort <vdonnefort@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/*
+ * TODO: add support for the white SATA LEDs associated with HDD 0 and 1.
+ */
+
+#include "armada-370.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>; /* 512 MB */
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
+
+		pcie-controller {
+			status = "okay";
+
+			/* USB 3.0 bridge ASM1042A */
+			pcie at 2,0 {
+				status = "okay";
+			};
+		};
+
+		internal-regs {
+			serial at 12000 {
+				status = "okay";
+			};
+
+			sata at a0000 {
+				nr-ports = <2>;
+				status = "okay";
+			};
+
+			mdio {
+				pinctrl-0 = <&mdio_pins>;
+				pinctrl-names = "default";
+
+				phy0: ethernet-phy at 0 {
+					reg = <0>;
+				};
+			};
+
+			ethernet at 70000 {
+				status = "okay";
+				pinctrl-0 = <&ge0_rgmii_pins>;
+				pinctrl-names = "default";
+				phy = <&phy0>;
+				phy-mode = "rgmii-id";
+			};
+
+			i2c at 11000 {
+				status = "okay";
+				pinctrl-0 = <&i2c0_pins>;
+				pinctrl-names = "default";
+				clock-frequency = <100000>;
+
+				/* RTC - NXP 8563T (second source) */
+				rtc at 51 {
+					compatible = "nxp,pcf8563";
+					reg = <0x51>;
+					interrupts = <110>;
+				};
+				/* RTC - MCP7940NT */
+				rtc at 6f {
+					compatible = "microchip,mcp7941x";
+					reg = <0x6f>;
+					interrupts = <110>;
+				};
+			};
+
+			nand at d0000 {
+				status = "okay";
+				num-cs = <1>;
+				marvell,nand-keep-config;
+				marvell,nand-enable-arbiter;
+				nand-on-flash-bbt;
+				nand-ecc-strength = <4>;
+				nand-ecc-step-size = <512>;
+
+				partition at 0 {
+					label = "u-boot";
+					reg = <0x0 0x300000>;
+				};
+				partition at 300000 {
+					label = "device-tree";
+					reg = <0x300000 0x20000>;
+				};
+				partition at 320000 {
+					label = "linux";
+					reg = <0x320000 0x2000000>;
+				};
+				partition at 2320000 {
+					label = "rootfs";
+					reg = <0x2320000 0xdce0000>;
+				};
+			};
+		};
+
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		pinctrl-names = "default";
+
+		regulator at 1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "SATA0 power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+		};
+		regulator at 2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "SATA1 power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	gpio-fan {
+		compatible = "gpio-fan";
+		gpios = <&gpio2 0 GPIO_ACTIVE_HIGH
+			 &gpio2 1 GPIO_ACTIVE_HIGH>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		button at 1 {
+			label = "Power button";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+			debounce-interval = <100>;
+		};
+		button at 2 {
+			label = "Backup button";
+			linux,code = <KEY_OPTION>;
+			gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
+			debounce-interval = <100>;
+		};
+		button at 3 {
+			label = "Reset Button";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
+			debounce-interval = <100>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		white-power {
+			label = "dart:white:power";
+			gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "timer";
+
+		};
+		red-power {
+			label = "dart:red:power";
+			gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
+		};
+		red-sata0 {
+			label = "dart:red:sata0";
+			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+		};
+		red-sata1 {
+			label = "dart:red:sata1";
+			gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio_poweroff {
+		compatible = "gpio-poweroff";
+		gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&pinctrl {
+	pinctrl-0 = <&hdd0_led_sata_pin>, <&hdd1_led_sata_pin>;
+	pinctrl-names = "default";
+
+	hdd0_led_sata_pin: hdd0-led-sata-pin {
+		marvell,pins = "mpp48";
+		marvell,function = "sata1";
+	};
+	hdd0_led_gpio_pin: hdd0-led-gpio-pin {
+		marvell,pins = "mpp48";
+		marvell,function = "gpio";
+	};
+	hdd1_led_sata_pin: hdd1-led-sata-pin {
+		marvell,pins = "mpp57";
+		marvell,function = "sata0";
+	};
+	hdd1_led_gpio_pin: hdd1-led-gpio-pin {
+		marvell,pins = "mpp57";
+		marvell,function = "gpio";
+	};
+};
-- 
2.1.4

[PATCH v5 3/4] ARM: mvebu: add DT support for Seagate Personal Cloud

[Simon Guinot]

This patch adds DT support for the Seagate Personal Cloud 1 and 2-Bay.

Here are some information allowing to identify these devices:

Product name                 | Personal Cloud | Personal Cloud 2-Bay
Code name (board/PCB)        | Cumulus        | Cumulus Max
Model name (case sticker)    | SRN21C         | SRN22C
Material desc (product spec) | STCRxxxxxxx    | STCSxxxxxxx

Chipset list:
- SoC Marvell Armada 370 88F6707, CPU @1GHz
- SDRAM memory: 512MB DDR3 667MHz (16-bits bandwidth)
- SPI flash 1MB (Macronix MX25L8006E)
- 1 or 2 SATA internal ports
- 1 Ethernet Gigabit port (PHY Marvell 88E1518)
- 1 USB3 host port (PCIe controller ASM1042)
- 1 USB2 host port (SoC)
- 2 push buttons (power and reset)
- 1 SATA LED (bi-color, white and red)

Note that support for the white SATA LED is missing. A dedicated LED
driver is needed.

Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Acked-by: Andrew Lunn <andrew@lunn.ch>
---
 arch/arm/boot/dts/Makefile                         |   2 +
 .../dts/armada-370-seagate-personal-cloud-2bay.dts |  51 ++++++
 .../boot/dts/armada-370-seagate-personal-cloud.dts |  37 +++++
 .../dts/armada-370-seagate-personal-cloud.dtsi     | 178 +++++++++++++++++++++
 4 files changed, 268 insertions(+)
 create mode 100644 arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts
 create mode 100644 arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts
 create mode 100644 arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi

Changes for v2:
- Rename DTS files using the products names.
- Update model and compatible properties as well.
- Add some information allowing to identify the devices in the commit
  message and in the DTS files headers.

Changes for v3:
- Fix spelling for Personal Cloud DTS files: 'personal' instead of
  'personnal'.
- Add Andrew's Acked-by.

Changes for v4:
- Add "broken-idle" property in the coherency-fabric DT node.

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a0cc0b63db41..8e83da127a9c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -712,6 +712,8 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
 	armada-370-rd.dtb \
 	armada-370-seagate-nas-2bay.dtb \
 	armada-370-seagate-nas-4bay.dtb \
+	armada-370-seagate-personal-cloud.dtb \
+	armada-370-seagate-personal-cloud-2bay.dtb \
 	armada-370-synology-ds213j.dtb
 dtb-$(CONFIG_MACH_ARMADA_375) += \
 	armada-375-db.dtb
diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts b/arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts
new file mode 100644
index 000000000000..3c91f9821c89
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts
@@ -0,0 +1,51 @@
+/*
+ * Device Tree file for Seagate Personal Cloud NAS 2-Bay (Armada 370 SoC).
+ *
+ * Copyright (C) 2015 Seagate
+ *
+ * Author: Simon Guinot <simon.guinot@sequanux.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/*
+ * Here are some information allowing to identify the device:
+ *
+ * Product name                 : Seagate Personal Cloud 2-Bay
+ * Code name (board/PCB)        : Cumulus Max
+ * Model name (case sticker)    : SRN22C
+ * Material desc (product spec) : STCSxxxxxxx
+ */
+
+/dts-v1/;
+#include "armada-370-seagate-personal-cloud.dtsi"
+
+/ {
+	model = "Seagate Personal Cloud 2-Bay (Cumulus, SRN22C)";
+	compatible = "seagate,cumulus-max", "marvell,armada370", "marvell,armada-370-xp";
+
+	soc {
+		internal-regs {
+			sata at a0000 {
+				status = "okay";
+				nr-ports = <2>;
+			};
+		};
+	};
+
+	regulators {
+		regulator at 2 {
+			compatible = "regulator-fixed";
+			reg = <2>;
+			regulator-name = "SATA1 power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts
new file mode 100644
index 000000000000..aad39e97af43
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts
@@ -0,0 +1,37 @@
+/*
+ * Device Tree file for Seagate Personal Cloud NAS (Armada 370 SoC).
+ *
+ * Copyright (C) 2015 Seagate
+ *
+ * Author: Simon Guinot <simon.guinot@sequanux.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/*
+ * Here are some information allowing to identify the device:
+ *
+ * Product name                 : Seagate Personal Cloud
+ * Code name (board/PCB)        : Cumulus
+ * Model name (case sticker)    : SRN21C
+ * Material desc (product spec) : STCRxxxxxxx
+ */
+
+/dts-v1/;
+#include "armada-370-seagate-personal-cloud.dtsi"
+
+/ {
+	model = "Seagate Personal Cloud (Cumulus, SRN21C)";
+	compatible = "seagate,cumulus", "marvell,armada370", "marvell,armada-370-xp";
+
+	soc {
+		internal-regs {
+			sata at a0000 {
+				status = "okay";
+				nr-ports = <1>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
new file mode 100644
index 000000000000..1aba08e4377c
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
@@ -0,0 +1,178 @@
+/*
+ * Device Tree common file for the Seagate Personal Cloud NAS 1 and 2-Bay
+ * (Armada 370 SoC).
+ *
+ * Copyright (C) 2015 Seagate
+ *
+ * Author: Simon Guinot <simon.guinot@sequanux.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/*
+ * TODO: add support for the white SATA LED.
+ */
+
+#include "armada-370.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x20000000>; /* 512 MB */
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
+
+		pcie-controller {
+			status = "okay";
+
+			/* USB 3.0 Bridge ASM1042A */
+			pcie at 1,0 {
+				status = "okay";
+			};
+		};
+
+		internal-regs {
+			coherency-fabric at 20200 {
+				broken-idle;
+			};
+
+			serial at 12000 {
+				status = "okay";
+			};
+
+			mdio {
+				pinctrl-0 = <&mdio_pins>;
+				pinctrl-names = "default";
+
+				phy0: ethernet-phy at 0 {
+					reg = <0>;
+				};
+			};
+
+			ethernet at 74000 {
+				status = "okay";
+				pinctrl-0 = <&ge1_rgmii_pins>;
+				pinctrl-names = "default";
+				phy = <&phy0>;
+				phy-mode = "rgmii-id";
+			};
+
+			spi at 10600 {
+				status = "okay";
+				pinctrl-0 = <&spi0_pins2>;
+				pinctrl-names = "default";
+
+				spi-flash at 0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					/* MX25L8006E */
+					compatible = "mxicy,mx25l8005", "jedec,spi-nor";
+					reg = <0>; /* Chip select 0 */
+					spi-max-frequency = <50000000>;
+
+					partition at 0 {
+						label = "u-boot";
+						reg = <0x0 0x100000>;
+					};
+				};
+			};
+
+			usb at 50000 {
+				status = "okay";
+			};
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		regulator at 0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "USB Power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio1 27 GPIO_ACTIVE_LOW>;
+		};
+		regulator at 1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "SATA0 power";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			enable-active-high;
+			regulator-always-on;
+			regulator-boot-on;
+			gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		button at 1 {
+			label = "Power button";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
+			debounce-interval = <100>;
+		};
+		button at 2 {
+			label = "Reset Button";
+			linux,code = <KEY_RESTART>;
+			gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
+			debounce-interval = <100>;
+		};
+		button at 3 {
+			label = "USB VBUS error";
+			linux,code = <KEY_UNKNOWN>;
+			gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
+			debounce-interval = <100>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		red-sata0 {
+			label = "cumulus:red:sata0";
+			gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
+			default-state = "off";
+		};
+	};
+
+	gpio_poweroff {
+		compatible = "gpio-poweroff";
+		gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&pinctrl {
+	pinctrl-0 = <&sata_led_pin>;
+	pinctrl-names = "default";
+
+	sata_led_pin: sata-led-pin {
+		marvell,pins = "mpp60";
+		marvell,function = "sata0";
+	};
+	gpio_led_pin: gpio-led-pin {
+		marvell,pins = "mpp60";
+		marvell,function = "gpio";
+	};
+};
-- 
2.1.4

[PATCH v5 4/4] ARM: mvebu: enable options for Seagate NAS in mvebu_v7_defconfig

[Simon Guinot]

This patch enables the following options needed by the Seagate
Personal Cloud 1 and 2-Bay and the Seagate NAS 2 and 4-Bay:

SATA_AHCI
POWER_RESET_GPIO
RTC_DRV_DS1307
RTC_DRV_PCF8563

Additionnally this patch also enables NEW_LEDS which was missing for
some reasons.

Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Acked-by: Andrew Lunn <andrew@lunn.ch>
---
 arch/arm/configs/mvebu_v7_defconfig | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

Changes for v3:
- Add Andrew's Acked-by.

diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig
index 13fcd020e375..c6729bf0a8dd 100644
--- a/arch/arm/configs/mvebu_v7_defconfig
+++ b/arch/arm/configs/mvebu_v7_defconfig
@@ -61,6 +61,7 @@ CONFIG_MTD_SPI_NOR=y
 CONFIG_EEPROM_AT24=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
 CONFIG_AHCI_MVEBU=y
 CONFIG_SATA_MV=y
 CONFIG_NETDEVICES=y
@@ -85,6 +86,9 @@ CONFIG_SPI=y
 CONFIG_SPI_ORION=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_PCA953X=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
 CONFIG_SENSORS_GPIO_FAN=y
 CONFIG_THERMAL=y
 CONFIG_ARMADA_THERMAL=y
@@ -111,12 +115,15 @@ CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_DOVE=y
 CONFIG_MMC_SDHCI_PXAV3=y
 CONFIG_MMC_MVSDIO=y
-CONFIG_LEDS_GPIO=y
+CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_PCF8563=y
 CONFIG_RTC_DRV_S35390A=y
 CONFIG_RTC_DRV_MV=y
 CONFIG_RTC_DRV_ARMADA38X=y
-- 
2.1.4

[PATCH v5 1/4] ARM: mvebu: add broken-idle option

[Gregory CLEMENT]

Hi Simon,
 
 On mar., oct. 06 2015, Simon Guinot <simon.guinot@sequanux.org> wrote:

> From: Vincent Donnefort <vdonnefort@gmail.com>
>
> The broken-idle option can be activated from the coherency-fabric DT
> node. This property allows to disable the idle capability, when the
> hardware doesn't support it, like the Seagate Personal Cloud boards.
>
> Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com>

Applied on mvebu/config

Thanks,

Gregory
> ---
>  .../devicetree/bindings/arm/coherency-fabric.txt   |  5 ++++
>  arch/arm/mach-mvebu/pmsu.c                         | 29 +++++++++++++++++++---
>  2 files changed, 31 insertions(+), 3 deletions(-)
>
> Changes for v5:
> - Make the broken-idle property boolean.
> - Don't use the broken-idle flag for Armada 38x.
>
> diff --git a/Documentation/devicetree/bindings/arm/coherency-fabric.txt b/Documentation/devicetree/bindings/arm/coherency-fabric.txt
> index 8dd46617c889..9b5c3f620e65 100644
> --- a/Documentation/devicetree/bindings/arm/coherency-fabric.txt
> +++ b/Documentation/devicetree/bindings/arm/coherency-fabric.txt
> @@ -27,6 +27,11 @@ Required properties:
>   * For "marvell,armada-380-coherency-fabric", only one pair is needed
>     for the per-CPU fabric registers.
>  
> +Optional properties:
> +
> +- broken-idle: boolean to set when the Idle mode is not supported by the
> +  hardware.
> +
>  Examples:
>  
>  coherency-fabric at d0020200 {
> diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
> index e8fdb9ceedf0..cba3fa985734 100644
> --- a/arch/arm/mach-mvebu/pmsu.c
> +++ b/arch/arm/mach-mvebu/pmsu.c
> @@ -379,6 +379,16 @@ static struct notifier_block mvebu_v7_cpu_pm_notifier = {
>  
>  static struct platform_device mvebu_v7_cpuidle_device;
>  
> +static int broken_idle(struct device_node *np)
> +{
> +	if (of_property_read_bool(np, "broken-idle")) {
> +		pr_warn("CPU idle is currently broken: disabling\n");
> +		return 0;
> +	}
> +
> +	return 1;
> +}
> +
>  static __init int armada_370_cpuidle_init(void)
>  {
>  	struct device_node *np;
> @@ -387,7 +397,9 @@ static __init int armada_370_cpuidle_init(void)
>  	np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
>  	if (!np)
>  		return -ENODEV;
> -	of_node_put(np);
> +
> +	if (!broken_idle(np))
> +		goto end;
>  
>  	/*
>  	 * On Armada 370, there is "a slow exit process from the deep
> @@ -406,6 +418,8 @@ static __init int armada_370_cpuidle_init(void)
>  	mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
>  	mvebu_v7_cpuidle_device.name = "cpuidle-armada-370";
>  
> +end:
> +	of_node_put(np);
>  	return 0;
>  }
>  
> @@ -422,6 +436,10 @@ static __init int armada_38x_cpuidle_init(void)
>  				     "marvell,armada-380-coherency-fabric");
>  	if (!np)
>  		return -ENODEV;
> +
> +	if (!broken_idle(np))
> +		goto end;
> +
>  	of_node_put(np);
>  
>  	np = of_find_compatible_node(NULL, NULL,
> @@ -430,7 +448,6 @@ static __init int armada_38x_cpuidle_init(void)
>  		return -ENODEV;
>  	mpsoc_base = of_iomap(np, 0);
>  	BUG_ON(!mpsoc_base);
> -	of_node_put(np);
>  
>  	/* Set up reset mask when powering down the cpus */
>  	reg = readl(mpsoc_base + MPCORE_RESET_CTL);
> @@ -450,6 +467,8 @@ static __init int armada_38x_cpuidle_init(void)
>  	mvebu_v7_cpuidle_device.dev.platform_data = armada_38x_cpu_suspend;
>  	mvebu_v7_cpuidle_device.name = "cpuidle-armada-38x";
>  
> +end:
> +	of_node_put(np);
>  	return 0;
>  }
>  
> @@ -460,12 +479,16 @@ static __init int armada_xp_cpuidle_init(void)
>  	np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
>  	if (!np)
>  		return -ENODEV;
> -	of_node_put(np);
> +
> +	if (!broken_idle(np))
> +		goto end;
>  
>  	mvebu_cpu_resume = armada_370_xp_cpu_resume;
>  	mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
>  	mvebu_v7_cpuidle_device.name = "cpuidle-armada-xp";
>  
> +end:
> +	of_node_put(np);
>  	return 0;
>  }
>  
> -- 
> 2.1.4
>

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v5 2/4] ARM: mvebu: add DT support for Seagate NAS 2 and 4-Bay

[Gregory CLEMENT]

Hi Simon,
 
 On mar., oct. 06 2015, Simon Guinot <simon.guinot@sequanux.org> wrote:

> From: Vincent Donnefort <vdonnefort@gmail.com>
>
> This patch adds DT support for the Seagate NAS 2 and 4-Bay.
>
> Here are some information allowing to identify these devices:
>
> Product name                 | Seagate NAS 2-Bay | Seagate NAS 4-Bay
> Code name (board/PCB)        | Dart 2-Bay        | Dart 4-Bay
> Model name (case sticker)    | SRPD20            | SRPD40
> Material desc (product spec) | STCTxxxxxxx       | STCUxxxxxxx
>
> Chipset list (common):
> - SoC Marvell Armada 370 88F6707, CPU @1.2GHz
> - SDRAM memory: 512MB DDR3 600MHz (16-bits bandwidth)
> - NAND flash 256MB, 8-bits (Micron MT29F2G08AAB or Hinyx H27U2G8F2CTR-BC)
> - 2 SATA II ports (SoC)
> - 1 Ethernet Gigabit ports (PHY Marvell 88E1518)
> - 2 USB3 host ports (PCIe controller ASM1042)
> - GPIO fan (4 speeds)
> - External I2C RTC (MCP7940NT)
> - 3 push buttons (power, backup and reset)
> - 2 SATA LEDs (bi-color, blue and red)
> - 1 power LED (bi-color, blue and red)
>
> Only on 4-Bay models:
> - 2 extra SATA III ports (PCIe AHCI controller Marvell 88SE9170)
> - 1 extra Ethernet Gigabit ports (PHY Marvell 88E1518)
> - I2C GPIO expander (PCA9554A)
> - 2 extra SATA LEDs (bi-color, blue and red)
>
> Note that support for the white SATA LEDs associated with HDDs 0 and 1
> is missing. A dedicated LED driver is needed.
>
> Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com>
> Acked-by: Andrew Lunn <andrew@lunn.ch>

Applied on mvebu/dt

Thanks,

Gregory
> ---
>  arch/arm/boot/dts/Makefile                         |   2 +
>  arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts  |  36 ++++
>  arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts  | 133 ++++++++++++
>  arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi | 231 +++++++++++++++++++++
>  4 files changed, 402 insertions(+)
>  create mode 100644 arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts
>  create mode 100644 arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts
>  create mode 100644 arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
>
> Changes for v2:
> - Rename DTS files using the products names.
> - Update model and compatible properties as well.
> - Add some information allowing to identify the devices in the commit
>   message and in the DTS files headers.
> - Remove duplicated rtc alias in armada-370-seagate-nas-xbay.dtsi.
>
> Changes for v3:
> - Use GPIO_ACTIVE_HIGH instead of 0 in gpios property (gpio-fan node).
> - Add Andrew's Acked-by.
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 1c5f22525a8b..a0cc0b63db41 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -710,6 +710,8 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
>  	armada-370-netgear-rn102.dtb \
>  	armada-370-netgear-rn104.dtb \
>  	armada-370-rd.dtb \
> +	armada-370-seagate-nas-2bay.dtb \
> +	armada-370-seagate-nas-4bay.dtb \
>  	armada-370-synology-ds213j.dtb
>  dtb-$(CONFIG_MACH_ARMADA_375) += \
>  	armada-375-db.dtb
> diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts b/arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts
> new file mode 100644
> index 000000000000..fef0110a8d8a
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-370-seagate-nas-2bay.dts
> @@ -0,0 +1,36 @@
> +/*
> + * Device Tree file for Seagate NAS 2-Bay (Armada 370 SoC).
> + *
> + * Copyright (C) 2015 Seagate
> + *
> + * Author: Vincent Donnefort <vdonnefort@gmail.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/*
> + * Here are some information allowing to identify the device:
> + *
> + * Product name                 : Seagate NAS 2-Bay
> + * Code name (board/PCB)        : Dart 2-Bay
> + * Model name (case sticker)    : SRPD20
> + * Material desc (product spec) : STCTxxxxxxx
> + */
> +
> +/dts-v1/;
> +#include "armada-370-seagate-nas-xbay.dtsi"
> +
> +/ {
> +	model = "Seagate NAS 2-Bay (Dart, SRPD20)";
> +	compatible = "seagate,dart-2", "marvell,armada370", "marvell,armada-370-xp";
> +
> +	gpio-fan {
> +		gpio-fan,speed-map =
> +			<   0 3
> +			  950 2
> +			 1400 1
> +			 1800 0>;
> +	};
> +};
> diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts b/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts
> new file mode 100644
> index 000000000000..ae2e1fe50ef6
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-370-seagate-nas-4bay.dts
> @@ -0,0 +1,133 @@
> +/*
> + * Device Tree file for Seagate NAS 4-Bay (Armada 370 SoC).
> + *
> + * Copyright (C) 2015 Seagate
> + *
> + * Author: Vincent Donnefort <vdonnefort@gmail.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/*
> + * Here are some information allowing to identify the device:
> + *
> + * Product name                 : Seagate NAS 4-Bay
> + * Code name (board/PCB)        : Dart 4-Bay
> + * Model name (case sticker)    : SRPD40
> + * Material desc (product spec) : STCUxxxxxxx
> + */
> +
> +/dts-v1/;
> +#include "armada-370-seagate-nas-xbay.dtsi"
> +#include <dt-bindings/leds/leds-ns2.h>
> +
> +/ {
> +	model = "Seagate NAS 4-Bay (Dart, SRPD40)";
> +	compatible = "seagate,dart-4", "marvell,armada370", "marvell,armada-370-xp";
> +
> +	soc {
> +		pcie-controller {
> +			/* SATA AHCI controller 88SE9170 */
> +			pcie at 1,0 {
> +				status = "okay";
> +			};
> +		};
> +
> +		internal-regs {
> +			mdio {
> +				phy1: ethernet-phy at 1 {
> +					reg = <1>;
> +				};
> +			};
> +
> +			ethernet at 74000 {
> +				status = "okay";
> +				pinctrl-0 = <&ge1_rgmii_pins>;
> +				pinctrl-names = "default";
> +				phy = <&phy1>;
> +				phy-mode = "rgmii-id";
> +			};
> +
> +			i2c at 11000 {
> +				/* I2C GPIO expander (PCA9554A) */
> +				pca9554: pca9554 at 21 {
> +					compatible = "nxp,pca9554";
> +					reg = <0x21>;
> +					#gpio-cells = <2>;
> +					gpio-controller;
> +				};
> +			};
> +		};
> +	};
> +
> +	regulators {
> +		regulator at 3 {
> +			compatible = "regulator-fixed";
> +			reg = <3>;
> +			regulator-name = "SATA2 power";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			enable-active-high;
> +			regulator-always-on;
> +			regulator-boot-on;
> +			gpio = <&pca9554 6 GPIO_ACTIVE_HIGH>;
> +		};
> +		regulator at 4 {
> +			compatible = "regulator-fixed";
> +			reg = <4>;
> +			regulator-name = "SATA3 power";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			enable-active-high;
> +			regulator-always-on;
> +			regulator-boot-on;
> +			gpio = <&pca9554 7 GPIO_ACTIVE_HIGH>;
> +		};
> +	};
> +
> +	gpio-leds {
> +		red-sata2 {
> +			label = "dart:red:sata2";
> +			gpios = <&pca9554 0 GPIO_ACTIVE_LOW>;
> +		};
> +		red-sata3 {
> +			label = "dart:red:sata3";
> +			gpios = <&pca9554 3 GPIO_ACTIVE_LOW>;
> +		};
> +	};
> +
> +	leds-ns2 {
> +		compatible = "lacie,ns2-leds";
> +
> +		white-sata2 {
> +			label = "dart:white:sata2";
> +			cmd-gpio = <&pca9554 1 GPIO_ACTIVE_HIGH>;
> +			slow-gpio = <&pca9554 2 GPIO_ACTIVE_HIGH>;
> +			num-modes = <4>;
> +			modes-map = <NS_V2_LED_SATA 0 0
> +				     NS_V2_LED_OFF  0 1
> +				     NS_V2_LED_ON   1 0
> +				     NS_V2_LED_ON   1 1>;
> +		};
> +		white-sata3 {
> +			label = "dart:white:sata3";
> +			cmd-gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
> +			slow-gpio = <&pca9554 5 GPIO_ACTIVE_HIGH>;
> +			num-modes = <4>;
> +			modes-map = <NS_V2_LED_SATA 0 0
> +				     NS_V2_LED_OFF  0 1
> +				     NS_V2_LED_ON   1 0
> +				     NS_V2_LED_ON   1 1>;
> +		};
> +	};
> +
> +	gpio-fan {
> +		gpio-fan,speed-map =
> +			<   0 3
> +			  800 2
> +			  1050 1
> +			  1300 0>;
> +	};
> +};
> diff --git a/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
> new file mode 100644
> index 000000000000..3036e25c5992
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-370-seagate-nas-xbay.dtsi
> @@ -0,0 +1,231 @@
> +/*
> + * Device Tree common file for the Seagate NAS 2 and 4-bay (Armada 370 SoC).
> + *
> + * Copyright (C) 2015 Seagate
> + *
> + * Author: Vincent Donnefort <vdonnefort@gmail.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/*
> + * TODO: add support for the white SATA LEDs associated with HDD 0 and 1.
> + */
> +
> +#include "armada-370.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x00000000 0x20000000>; /* 512 MB */
> +	};
> +
> +	soc {
> +		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
> +			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
> +
> +		pcie-controller {
> +			status = "okay";
> +
> +			/* USB 3.0 bridge ASM1042A */
> +			pcie at 2,0 {
> +				status = "okay";
> +			};
> +		};
> +
> +		internal-regs {
> +			serial at 12000 {
> +				status = "okay";
> +			};
> +
> +			sata at a0000 {
> +				nr-ports = <2>;
> +				status = "okay";
> +			};
> +
> +			mdio {
> +				pinctrl-0 = <&mdio_pins>;
> +				pinctrl-names = "default";
> +
> +				phy0: ethernet-phy at 0 {
> +					reg = <0>;
> +				};
> +			};
> +
> +			ethernet at 70000 {
> +				status = "okay";
> +				pinctrl-0 = <&ge0_rgmii_pins>;
> +				pinctrl-names = "default";
> +				phy = <&phy0>;
> +				phy-mode = "rgmii-id";
> +			};
> +
> +			i2c at 11000 {
> +				status = "okay";
> +				pinctrl-0 = <&i2c0_pins>;
> +				pinctrl-names = "default";
> +				clock-frequency = <100000>;
> +
> +				/* RTC - NXP 8563T (second source) */
> +				rtc at 51 {
> +					compatible = "nxp,pcf8563";
> +					reg = <0x51>;
> +					interrupts = <110>;
> +				};
> +				/* RTC - MCP7940NT */
> +				rtc at 6f {
> +					compatible = "microchip,mcp7941x";
> +					reg = <0x6f>;
> +					interrupts = <110>;
> +				};
> +			};
> +
> +			nand at d0000 {
> +				status = "okay";
> +				num-cs = <1>;
> +				marvell,nand-keep-config;
> +				marvell,nand-enable-arbiter;
> +				nand-on-flash-bbt;
> +				nand-ecc-strength = <4>;
> +				nand-ecc-step-size = <512>;
> +
> +				partition at 0 {
> +					label = "u-boot";
> +					reg = <0x0 0x300000>;
> +				};
> +				partition at 300000 {
> +					label = "device-tree";
> +					reg = <0x300000 0x20000>;
> +				};
> +				partition at 320000 {
> +					label = "linux";
> +					reg = <0x320000 0x2000000>;
> +				};
> +				partition at 2320000 {
> +					label = "rootfs";
> +					reg = <0x2320000 0xdce0000>;
> +				};
> +			};
> +		};
> +
> +	};
> +
> +	regulators {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		pinctrl-names = "default";
> +
> +		regulator at 1 {
> +			compatible = "regulator-fixed";
> +			reg = <1>;
> +			regulator-name = "SATA0 power";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			enable-active-high;
> +			regulator-always-on;
> +			regulator-boot-on;
> +			gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
> +		};
> +		regulator at 2 {
> +			compatible = "regulator-fixed";
> +			reg = <2>;
> +			regulator-name = "SATA1 power";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			enable-active-high;
> +			regulator-always-on;
> +			regulator-boot-on;
> +			gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
> +		};
> +	};
> +
> +	gpio-fan {
> +		compatible = "gpio-fan";
> +		gpios = <&gpio2 0 GPIO_ACTIVE_HIGH
> +			 &gpio2 1 GPIO_ACTIVE_HIGH>;
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		button at 1 {
> +			label = "Power button";
> +			linux,code = <KEY_POWER>;
> +			gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
> +			debounce-interval = <100>;
> +		};
> +		button at 2 {
> +			label = "Backup button";
> +			linux,code = <KEY_OPTION>;
> +			gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
> +			debounce-interval = <100>;
> +		};
> +		button at 3 {
> +			label = "Reset Button";
> +			linux,code = <KEY_RESTART>;
> +			gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
> +			debounce-interval = <100>;
> +		};
> +	};
> +
> +	gpio-leds {
> +		compatible = "gpio-leds";
> +
> +		white-power {
> +			label = "dart:white:power";
> +			gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
> +			linux,default-trigger = "timer";
> +
> +		};
> +		red-power {
> +			label = "dart:red:power";
> +			gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
> +		};
> +		red-sata0 {
> +			label = "dart:red:sata0";
> +			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
> +		};
> +		red-sata1 {
> +			label = "dart:red:sata1";
> +			gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
> +		};
> +	};
> +
> +	gpio_poweroff {
> +		compatible = "gpio-poweroff";
> +		gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
> +	};
> +};
> +
> +&pinctrl {
> +	pinctrl-0 = <&hdd0_led_sata_pin>, <&hdd1_led_sata_pin>;
> +	pinctrl-names = "default";
> +
> +	hdd0_led_sata_pin: hdd0-led-sata-pin {
> +		marvell,pins = "mpp48";
> +		marvell,function = "sata1";
> +	};
> +	hdd0_led_gpio_pin: hdd0-led-gpio-pin {
> +		marvell,pins = "mpp48";
> +		marvell,function = "gpio";
> +	};
> +	hdd1_led_sata_pin: hdd1-led-sata-pin {
> +		marvell,pins = "mpp57";
> +		marvell,function = "sata0";
> +	};
> +	hdd1_led_gpio_pin: hdd1-led-gpio-pin {
> +		marvell,pins = "mpp57";
> +		marvell,function = "gpio";
> +	};
> +};
> -- 
> 2.1.4
>

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v5 3/4] ARM: mvebu: add DT support for Seagate Personal Cloud

[Gregory CLEMENT]

Hi Simon,
 
 On mar., oct. 06 2015, Simon Guinot <simon.guinot@sequanux.org> wrote:

> This patch adds DT support for the Seagate Personal Cloud 1 and 2-Bay.
>
> Here are some information allowing to identify these devices:
>
> Product name                 | Personal Cloud | Personal Cloud 2-Bay
> Code name (board/PCB)        | Cumulus        | Cumulus Max
> Model name (case sticker)    | SRN21C         | SRN22C
> Material desc (product spec) | STCRxxxxxxx    | STCSxxxxxxx
>
> Chipset list:
> - SoC Marvell Armada 370 88F6707, CPU @1GHz
> - SDRAM memory: 512MB DDR3 667MHz (16-bits bandwidth)
> - SPI flash 1MB (Macronix MX25L8006E)
> - 1 or 2 SATA internal ports
> - 1 Ethernet Gigabit port (PHY Marvell 88E1518)
> - 1 USB3 host port (PCIe controller ASM1042)
> - 1 USB2 host port (SoC)
> - 2 push buttons (power and reset)
> - 1 SATA LED (bi-color, white and red)
>
> Note that support for the white SATA LED is missing. A dedicated LED
> driver is needed.
>
> Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
> Acked-by: Andrew Lunn <andrew@lunn.ch>

Applied on mvebu/dt

Thanks,

Gregory
> ---
>  arch/arm/boot/dts/Makefile                         |   2 +
>  .../dts/armada-370-seagate-personal-cloud-2bay.dts |  51 ++++++
>  .../boot/dts/armada-370-seagate-personal-cloud.dts |  37 +++++
>  .../dts/armada-370-seagate-personal-cloud.dtsi     | 178 +++++++++++++++++++++
>  4 files changed, 268 insertions(+)
>  create mode 100644 arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts
>  create mode 100644 arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts
>  create mode 100644 arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
>
> Changes for v2:
> - Rename DTS files using the products names.
> - Update model and compatible properties as well.
> - Add some information allowing to identify the devices in the commit
>   message and in the DTS files headers.
>
> Changes for v3:
> - Fix spelling for Personal Cloud DTS files: 'personal' instead of
>   'personnal'.
> - Add Andrew's Acked-by.
>
> Changes for v4:
> - Add "broken-idle" property in the coherency-fabric DT node.
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index a0cc0b63db41..8e83da127a9c 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -712,6 +712,8 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
>  	armada-370-rd.dtb \
>  	armada-370-seagate-nas-2bay.dtb \
>  	armada-370-seagate-nas-4bay.dtb \
> +	armada-370-seagate-personal-cloud.dtb \
> +	armada-370-seagate-personal-cloud-2bay.dtb \
>  	armada-370-synology-ds213j.dtb
>  dtb-$(CONFIG_MACH_ARMADA_375) += \
>  	armada-375-db.dtb
> diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts b/arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts
> new file mode 100644
> index 000000000000..3c91f9821c89
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud-2bay.dts
> @@ -0,0 +1,51 @@
> +/*
> + * Device Tree file for Seagate Personal Cloud NAS 2-Bay (Armada 370 SoC).
> + *
> + * Copyright (C) 2015 Seagate
> + *
> + * Author: Simon Guinot <simon.guinot@sequanux.org>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/*
> + * Here are some information allowing to identify the device:
> + *
> + * Product name                 : Seagate Personal Cloud 2-Bay
> + * Code name (board/PCB)        : Cumulus Max
> + * Model name (case sticker)    : SRN22C
> + * Material desc (product spec) : STCSxxxxxxx
> + */
> +
> +/dts-v1/;
> +#include "armada-370-seagate-personal-cloud.dtsi"
> +
> +/ {
> +	model = "Seagate Personal Cloud 2-Bay (Cumulus, SRN22C)";
> +	compatible = "seagate,cumulus-max", "marvell,armada370", "marvell,armada-370-xp";
> +
> +	soc {
> +		internal-regs {
> +			sata at a0000 {
> +				status = "okay";
> +				nr-ports = <2>;
> +			};
> +		};
> +	};
> +
> +	regulators {
> +		regulator at 2 {
> +			compatible = "regulator-fixed";
> +			reg = <2>;
> +			regulator-name = "SATA1 power";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			enable-active-high;
> +			regulator-always-on;
> +			regulator-boot-on;
> +			gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts
> new file mode 100644
> index 000000000000..aad39e97af43
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dts
> @@ -0,0 +1,37 @@
> +/*
> + * Device Tree file for Seagate Personal Cloud NAS (Armada 370 SoC).
> + *
> + * Copyright (C) 2015 Seagate
> + *
> + * Author: Simon Guinot <simon.guinot@sequanux.org>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/*
> + * Here are some information allowing to identify the device:
> + *
> + * Product name                 : Seagate Personal Cloud
> + * Code name (board/PCB)        : Cumulus
> + * Model name (case sticker)    : SRN21C
> + * Material desc (product spec) : STCRxxxxxxx
> + */
> +
> +/dts-v1/;
> +#include "armada-370-seagate-personal-cloud.dtsi"
> +
> +/ {
> +	model = "Seagate Personal Cloud (Cumulus, SRN21C)";
> +	compatible = "seagate,cumulus", "marvell,armada370", "marvell,armada-370-xp";
> +
> +	soc {
> +		internal-regs {
> +			sata at a0000 {
> +				status = "okay";
> +				nr-ports = <1>;
> +			};
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
> new file mode 100644
> index 000000000000..1aba08e4377c
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi
> @@ -0,0 +1,178 @@
> +/*
> + * Device Tree common file for the Seagate Personal Cloud NAS 1 and 2-Bay
> + * (Armada 370 SoC).
> + *
> + * Copyright (C) 2015 Seagate
> + *
> + * Author: Simon Guinot <simon.guinot@sequanux.org>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/*
> + * TODO: add support for the white SATA LED.
> + */
> +
> +#include "armada-370.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x00000000 0x20000000>; /* 512 MB */
> +	};
> +
> +	soc {
> +		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
> +			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
> +
> +		pcie-controller {
> +			status = "okay";
> +
> +			/* USB 3.0 Bridge ASM1042A */
> +			pcie at 1,0 {
> +				status = "okay";
> +			};
> +		};
> +
> +		internal-regs {
> +			coherency-fabric at 20200 {
> +				broken-idle;
> +			};
> +
> +			serial at 12000 {
> +				status = "okay";
> +			};
> +
> +			mdio {
> +				pinctrl-0 = <&mdio_pins>;
> +				pinctrl-names = "default";
> +
> +				phy0: ethernet-phy at 0 {
> +					reg = <0>;
> +				};
> +			};
> +
> +			ethernet at 74000 {
> +				status = "okay";
> +				pinctrl-0 = <&ge1_rgmii_pins>;
> +				pinctrl-names = "default";
> +				phy = <&phy0>;
> +				phy-mode = "rgmii-id";
> +			};
> +
> +			spi at 10600 {
> +				status = "okay";
> +				pinctrl-0 = <&spi0_pins2>;
> +				pinctrl-names = "default";
> +
> +				spi-flash at 0 {
> +					#address-cells = <1>;
> +					#size-cells = <1>;
> +					/* MX25L8006E */
> +					compatible = "mxicy,mx25l8005", "jedec,spi-nor";
> +					reg = <0>; /* Chip select 0 */
> +					spi-max-frequency = <50000000>;
> +
> +					partition at 0 {
> +						label = "u-boot";
> +						reg = <0x0 0x100000>;
> +					};
> +				};
> +			};
> +
> +			usb at 50000 {
> +				status = "okay";
> +			};
> +		};
> +	};
> +
> +	regulators {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		regulator at 0 {
> +			compatible = "regulator-fixed";
> +			reg = <0>;
> +			regulator-name = "USB Power";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			regulator-always-on;
> +			regulator-boot-on;
> +			gpio = <&gpio1 27 GPIO_ACTIVE_LOW>;
> +		};
> +		regulator at 1 {
> +			compatible = "regulator-fixed";
> +			reg = <1>;
> +			regulator-name = "SATA0 power";
> +			regulator-min-microvolt = <5000000>;
> +			regulator-max-microvolt = <5000000>;
> +			enable-active-high;
> +			regulator-always-on;
> +			regulator-boot-on;
> +			gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>;
> +		};
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		button at 1 {
> +			label = "Power button";
> +			linux,code = <KEY_POWER>;
> +			gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>;
> +			debounce-interval = <100>;
> +		};
> +		button at 2 {
> +			label = "Reset Button";
> +			linux,code = <KEY_RESTART>;
> +			gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
> +			debounce-interval = <100>;
> +		};
> +		button at 3 {
> +			label = "USB VBUS error";
> +			linux,code = <KEY_UNKNOWN>;
> +			gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
> +			debounce-interval = <100>;
> +		};
> +	};
> +
> +	gpio-leds {
> +		compatible = "gpio-leds";
> +
> +		red-sata0 {
> +			label = "cumulus:red:sata0";
> +			gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
> +			default-state = "off";
> +		};
> +	};
> +
> +	gpio_poweroff {
> +		compatible = "gpio-poweroff";
> +		gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
> +	};
> +};
> +
> +&pinctrl {
> +	pinctrl-0 = <&sata_led_pin>;
> +	pinctrl-names = "default";
> +
> +	sata_led_pin: sata-led-pin {
> +		marvell,pins = "mpp60";
> +		marvell,function = "sata0";
> +	};
> +	gpio_led_pin: gpio-led-pin {
> +		marvell,pins = "mpp60";
> +		marvell,function = "gpio";
> +	};
> +};
> -- 
> 2.1.4
>

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v5 4/4] ARM: mvebu: enable options for Seagate NAS in mvebu_v7_defconfig

[Gregory CLEMENT]

Hi Simon,
 
 On mar., oct. 06 2015, Simon Guinot <simon.guinot@sequanux.org> wrote:

> This patch enables the following options needed by the Seagate
> Personal Cloud 1 and 2-Bay and the Seagate NAS 2 and 4-Bay:
>
> SATA_AHCI
> POWER_RESET_GPIO
> RTC_DRV_DS1307
> RTC_DRV_PCF8563
>
> Additionnally this patch also enables NEW_LEDS which was missing for
> some reasons.
>
> Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
> Acked-by: Andrew Lunn <andrew@lunn.ch>

Applied on mvebu/config

Thanks,

Gregory
> ---
>  arch/arm/configs/mvebu_v7_defconfig | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
>
> Changes for v3:
> - Add Andrew's Acked-by.
>
> diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig
> index 13fcd020e375..c6729bf0a8dd 100644
> --- a/arch/arm/configs/mvebu_v7_defconfig
> +++ b/arch/arm/configs/mvebu_v7_defconfig
> @@ -61,6 +61,7 @@ CONFIG_MTD_SPI_NOR=y
>  CONFIG_EEPROM_AT24=y
>  CONFIG_BLK_DEV_SD=y
>  CONFIG_ATA=y
> +CONFIG_SATA_AHCI=y
>  CONFIG_AHCI_MVEBU=y
>  CONFIG_SATA_MV=y
>  CONFIG_NETDEVICES=y
> @@ -85,6 +86,9 @@ CONFIG_SPI=y
>  CONFIG_SPI_ORION=y
>  CONFIG_GPIO_SYSFS=y
>  CONFIG_GPIO_PCA953X=y
> +CONFIG_POWER_SUPPLY=y
> +CONFIG_POWER_RESET=y
> +CONFIG_POWER_RESET_GPIO=y
>  CONFIG_SENSORS_GPIO_FAN=y
>  CONFIG_THERMAL=y
>  CONFIG_ARMADA_THERMAL=y
> @@ -111,12 +115,15 @@ CONFIG_MMC_SDHCI_PLTFM=y
>  CONFIG_MMC_SDHCI_DOVE=y
>  CONFIG_MMC_SDHCI_PXAV3=y
>  CONFIG_MMC_MVSDIO=y
> -CONFIG_LEDS_GPIO=y
> +CONFIG_NEW_LEDS=y
>  CONFIG_LEDS_CLASS=y
> +CONFIG_LEDS_GPIO=y
>  CONFIG_LEDS_TRIGGERS=y
>  CONFIG_LEDS_TRIGGER_TIMER=y
>  CONFIG_LEDS_TRIGGER_HEARTBEAT=y
>  CONFIG_RTC_CLASS=y
> +CONFIG_RTC_DRV_DS1307=y
> +CONFIG_RTC_DRV_PCF8563=y
>  CONFIG_RTC_DRV_S35390A=y
>  CONFIG_RTC_DRV_MV=y
>  CONFIG_RTC_DRV_ARMADA38X=y
> -- 
> 2.1.4
>

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v5 1/4] ARM: mvebu: add broken-idle option

[Gregory CLEMENT]

 On lun., oct. 12 2015, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:

> Hi Simon,
>  
>  On mar., oct. 06 2015, Simon Guinot <simon.guinot@sequanux.org> wrote:
>
>> From: Vincent Donnefort <vdonnefort@gmail.com>
>>
>> The broken-idle option can be activated from the coherency-fabric DT
>> node. This property allows to disable the idle capability, when the
>> hardware doesn't support it, like the Seagate Personal Cloud boards.
>>
>> Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com>
>
> Applied on mvebu/config
Actually on mvebu/soc

>
> Thanks,
>
> Gregory
>> ---
>>  .../devicetree/bindings/arm/coherency-fabric.txt   |  5 ++++
>>  arch/arm/mach-mvebu/pmsu.c                         | 29 +++++++++++++++++++---
>>  2 files changed, 31 insertions(+), 3 deletions(-)
>>
>> Changes for v5:
>> - Make the broken-idle property boolean.
>> - Don't use the broken-idle flag for Armada 38x.
>>
>> diff --git a/Documentation/devicetree/bindings/arm/coherency-fabric.txt b/Documentation/devicetree/bindings/arm/coherency-fabric.txt
>> index 8dd46617c889..9b5c3f620e65 100644
>> --- a/Documentation/devicetree/bindings/arm/coherency-fabric.txt
>> +++ b/Documentation/devicetree/bindings/arm/coherency-fabric.txt
>> @@ -27,6 +27,11 @@ Required properties:
>>   * For "marvell,armada-380-coherency-fabric", only one pair is needed
>>     for the per-CPU fabric registers.
>>  
>> +Optional properties:
>> +
>> +- broken-idle: boolean to set when the Idle mode is not supported by the
>> +  hardware.
>> +
>>  Examples:
>>  
>>  coherency-fabric at d0020200 {
>> diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
>> index e8fdb9ceedf0..cba3fa985734 100644
>> --- a/arch/arm/mach-mvebu/pmsu.c
>> +++ b/arch/arm/mach-mvebu/pmsu.c
>> @@ -379,6 +379,16 @@ static struct notifier_block mvebu_v7_cpu_pm_notifier = {
>>  
>>  static struct platform_device mvebu_v7_cpuidle_device;
>>  
>> +static int broken_idle(struct device_node *np)
>> +{
>> +	if (of_property_read_bool(np, "broken-idle")) {
>> +		pr_warn("CPU idle is currently broken: disabling\n");
>> +		return 0;
>> +	}
>> +
>> +	return 1;
>> +}
>> +
>>  static __init int armada_370_cpuidle_init(void)
>>  {
>>  	struct device_node *np;
>> @@ -387,7 +397,9 @@ static __init int armada_370_cpuidle_init(void)
>>  	np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
>>  	if (!np)
>>  		return -ENODEV;
>> -	of_node_put(np);
>> +
>> +	if (!broken_idle(np))
>> +		goto end;
>>  
>>  	/*
>>  	 * On Armada 370, there is "a slow exit process from the deep
>> @@ -406,6 +418,8 @@ static __init int armada_370_cpuidle_init(void)
>>  	mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
>>  	mvebu_v7_cpuidle_device.name = "cpuidle-armada-370";
>>  
>> +end:
>> +	of_node_put(np);
>>  	return 0;
>>  }
>>  
>> @@ -422,6 +436,10 @@ static __init int armada_38x_cpuidle_init(void)
>>  				     "marvell,armada-380-coherency-fabric");
>>  	if (!np)
>>  		return -ENODEV;
>> +
>> +	if (!broken_idle(np))
>> +		goto end;
>> +
>>  	of_node_put(np);
>>  
>>  	np = of_find_compatible_node(NULL, NULL,
>> @@ -430,7 +448,6 @@ static __init int armada_38x_cpuidle_init(void)
>>  		return -ENODEV;
>>  	mpsoc_base = of_iomap(np, 0);
>>  	BUG_ON(!mpsoc_base);
>> -	of_node_put(np);
>>  
>>  	/* Set up reset mask when powering down the cpus */
>>  	reg = readl(mpsoc_base + MPCORE_RESET_CTL);
>> @@ -450,6 +467,8 @@ static __init int armada_38x_cpuidle_init(void)
>>  	mvebu_v7_cpuidle_device.dev.platform_data = armada_38x_cpu_suspend;
>>  	mvebu_v7_cpuidle_device.name = "cpuidle-armada-38x";
>>  
>> +end:
>> +	of_node_put(np);
>>  	return 0;
>>  }
>>  
>> @@ -460,12 +479,16 @@ static __init int armada_xp_cpuidle_init(void)
>>  	np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
>>  	if (!np)
>>  		return -ENODEV;
>> -	of_node_put(np);
>> +
>> +	if (!broken_idle(np))
>> +		goto end;
>>  
>>  	mvebu_cpu_resume = armada_370_xp_cpu_resume;
>>  	mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
>>  	mvebu_v7_cpuidle_device.name = "cpuidle-armada-xp";
>>  
>> +end:
>> +	of_node_put(np);
>>  	return 0;
>>  }
>>  
>> -- 
>> 2.1.4
>>
>
> -- 
> Gregory Clement, Free Electrons
> Kernel, drivers, real-time and embedded Linux
> development, consulting, training and support.
> http://free-electrons.com

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v5 1/4] ARM: mvebu: add broken-idle option

[Olof Johansson]

On Tue, Oct 6, 2015 at 7:13 AM, Simon Guinot <simon.guinot@sequanux.org> wrote:
> From: Vincent Donnefort <vdonnefort@gmail.com>
>
> The broken-idle option can be activated from the coherency-fabric DT
> node. This property allows to disable the idle capability, when the
> hardware doesn't support it, like the Seagate Personal Cloud boards.
>
> Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com>
> ---
>  .../devicetree/bindings/arm/coherency-fabric.txt   |  5 ++++
>  arch/arm/mach-mvebu/pmsu.c                         | 29 +++++++++++++++++++---
>  2 files changed, 31 insertions(+), 3 deletions(-)
>
> Changes for v5:
> - Make the broken-idle property boolean.
> - Don't use the broken-idle flag for Armada 38x.
>
> diff --git a/Documentation/devicetree/bindings/arm/coherency-fabric.txt b/Documentation/devicetree/bindings/arm/coherency-fabric.txt
> index 8dd46617c889..9b5c3f620e65 100644
> --- a/Documentation/devicetree/bindings/arm/coherency-fabric.txt
> +++ b/Documentation/devicetree/bindings/arm/coherency-fabric.txt
> @@ -27,6 +27,11 @@ Required properties:
>   * For "marvell,armada-380-coherency-fabric", only one pair is needed
>     for the per-CPU fabric registers.
>
> +Optional properties:
> +
> +- broken-idle: boolean to set when the Idle mode is not supported by the
> +  hardware.
> +
>  Examples:
>
>  coherency-fabric at d0020200 {
> diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
> index e8fdb9ceedf0..cba3fa985734 100644
> --- a/arch/arm/mach-mvebu/pmsu.c
> +++ b/arch/arm/mach-mvebu/pmsu.c
> @@ -379,6 +379,16 @@ static struct notifier_block mvebu_v7_cpu_pm_notifier = {
>
>  static struct platform_device mvebu_v7_cpuidle_device;
>
> +static int broken_idle(struct device_node *np)
> +{
> +       if (of_property_read_bool(np, "broken-idle")) {
> +               pr_warn("CPU idle is currently broken: disabling\n");
> +               return 0;
> +       }
> +
> +       return 1;
> +}

This is confusing. The function is called broken_idle(), but it
returns 0 if idle is broken and 1 if it isn't.

It means these tests look odd:

> +
>  static __init int armada_370_cpuidle_init(void)
>  {
>         struct device_node *np;
> @@ -387,7 +397,9 @@ static __init int armada_370_cpuidle_init(void)
>         np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
>         if (!np)
>                 return -ENODEV;
> -       of_node_put(np);
> +
> +       if (!broken_idle(np))
> +               goto end;

So, the way I read this when I read just this code is: "If idle is NOT
broken, then don't bother set up any of the idle stuff".

Please turn this the other way around so others don't make the same
mistake when reading the code.

I know it might come across as bikesheddy and nitpicky, but
readability trumps most other things when it comes to new code. :-/



-Olof

[PATCH v5 1/4] ARM: mvebu: add broken-idle option

[Gregory CLEMENT]

Hi Simon and Vincent,
 
 On jeu., oct. 22 2015, Olof Johansson <olof@lixom.net> wrote:

>> +static int broken_idle(struct device_node *np)
>> +{
>> +       if (of_property_read_bool(np, "broken-idle")) {
>> +               pr_warn("CPU idle is currently broken: disabling\n");
>> +               return 0;
>> +       }
>> +
>> +       return 1;
>> +}
>
> This is confusing. The function is called broken_idle(), but it
> returns 0 if idle is broken and 1 if it isn't.
>
> It means these tests look odd:
>
>> +
>>  static __init int armada_370_cpuidle_init(void)
>>  {
>>         struct device_node *np;
>> @@ -387,7 +397,9 @@ static __init int armada_370_cpuidle_init(void)
>>         np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
>>         if (!np)
>>                 return -ENODEV;
>> -       of_node_put(np);
>> +
>> +       if (!broken_idle(np))
>> +               goto end;
>
> So, the way I read this when I read just this code is: "If idle is NOT
> broken, then don't bother set up any of the idle stuff".
>
> Please turn this the other way around so others don't make the same
> mistake when reading the code.
>
> I know it might come across as bikesheddy and nitpicky, but
> readability trumps most other things when it comes to new code. :-/

Could you send an updated version ? Then I will be able to make a new
pull request following it as requested by Olof. Then it will still be
part of 4.4.

Thanks,

Gregory

>
>
>
> -Olof

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v6] ARM: mvebu: add broken-idle option

[Vincent Donnefort]

changes for v6:
- broken_idle() returns 1 when broken.

Vincent Donnefort (1):
  ARM: mvebu: add broken-idle option

 .../devicetree/bindings/arm/coherency-fabric.txt   |  5 ++++
 arch/arm/mach-mvebu/pmsu.c                         | 29 +++++++++++++++++++---
 2 files changed, 31 insertions(+), 3 deletions(-)

-- 
2.1.4

[PATCH] ARM: mvebu: add broken-idle option

[Vincent Donnefort]

The broken-idle option can be activated from the coherency-fabric DT
node. This property allows to disable the idle capability, when the
hardware doesn't support it, like the Seagate Personal Cloud boards.

Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com>

diff --git a/Documentation/devicetree/bindings/arm/coherency-fabric.txt b/Documentation/devicetree/bindings/arm/coherency-fabric.txt
index 8dd4661..9b5c3f6 100644
--- a/Documentation/devicetree/bindings/arm/coherency-fabric.txt
+++ b/Documentation/devicetree/bindings/arm/coherency-fabric.txt
@@ -27,6 +27,11 @@ Required properties:
  * For "marvell,armada-380-coherency-fabric", only one pair is needed
    for the per-CPU fabric registers.
 
+Optional properties:
+
+- broken-idle: boolean to set when the Idle mode is not supported by the
+  hardware.
+
 Examples:
 
 coherency-fabric at d0020200 {
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 4f4e222..0e97b97 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -379,6 +379,16 @@ static struct notifier_block mvebu_v7_cpu_pm_notifier = {
 
 static struct platform_device mvebu_v7_cpuidle_device;
 
+static int broken_idle(struct device_node *np)
+{
+	if (of_property_read_bool(np, "broken-idle")) {
+		pr_warn("CPU idle is currently broken: disabling\n");
+		return 1;
+	}
+
+	return 0;
+}
+
 static __init int armada_370_cpuidle_init(void)
 {
 	struct device_node *np;
@@ -387,7 +397,9 @@ static __init int armada_370_cpuidle_init(void)
 	np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
 	if (!np)
 		return -ENODEV;
-	of_node_put(np);
+
+	if (broken_idle(np))
+		goto end;
 
 	/*
 	 * On Armada 370, there is "a slow exit process from the deep
@@ -406,6 +418,8 @@ static __init int armada_370_cpuidle_init(void)
 	mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
 	mvebu_v7_cpuidle_device.name = "cpuidle-armada-370";
 
+end:
+	of_node_put(np);
 	return 0;
 }
 
@@ -422,6 +436,10 @@ static __init int armada_38x_cpuidle_init(void)
 				     "marvell,armada-380-coherency-fabric");
 	if (!np)
 		return -ENODEV;
+
+	if (broken_idle(np))
+		goto end;
+
 	of_node_put(np);
 
 	np = of_find_compatible_node(NULL, NULL,
@@ -430,7 +448,6 @@ static __init int armada_38x_cpuidle_init(void)
 		return -ENODEV;
 	mpsoc_base = of_iomap(np, 0);
 	BUG_ON(!mpsoc_base);
-	of_node_put(np);
 
 	/* Set up reset mask when powering down the cpus */
 	reg = readl(mpsoc_base + MPCORE_RESET_CTL);
@@ -450,6 +467,8 @@ static __init int armada_38x_cpuidle_init(void)
 	mvebu_v7_cpuidle_device.dev.platform_data = armada_38x_cpu_suspend;
 	mvebu_v7_cpuidle_device.name = "cpuidle-armada-38x";
 
+end:
+	of_node_put(np);
 	return 0;
 }
 
@@ -460,12 +479,16 @@ static __init int armada_xp_cpuidle_init(void)
 	np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
 	if (!np)
 		return -ENODEV;
-	of_node_put(np);
+
+	if (broken_idle(np))
+		goto end;
 
 	mvebu_cpu_resume = armada_370_xp_cpu_resume;
 	mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
 	mvebu_v7_cpuidle_device.name = "cpuidle-armada-xp";
 
+end:
+	of_node_put(np);
 	return 0;
 }
 
-- 
2.1.4

[PATCH] ARM: mvebu: add broken-idle option

[Gregory CLEMENT]

Hi Vincent,
 
 On ven., oct. 23 2015, Vincent Donnefort <vdonnefort@gmail.com> wrote:

> The broken-idle option can be activated from the coherency-fabric DT
> node. This property allows to disable the idle capability, when the
> hardware doesn't support it, like the Seagate Personal Cloud boards.

Applied on mvebu/soc

Thanks,

Gregory
>
> Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com>
>
> diff --git a/Documentation/devicetree/bindings/arm/coherency-fabric.txt b/Documentation/devicetree/bindings/arm/coherency-fabric.txt
> index 8dd4661..9b5c3f6 100644
> --- a/Documentation/devicetree/bindings/arm/coherency-fabric.txt
> +++ b/Documentation/devicetree/bindings/arm/coherency-fabric.txt
> @@ -27,6 +27,11 @@ Required properties:
>   * For "marvell,armada-380-coherency-fabric", only one pair is needed
>     for the per-CPU fabric registers.
>  
> +Optional properties:
> +
> +- broken-idle: boolean to set when the Idle mode is not supported by the
> +  hardware.
> +
>  Examples:
>  
>  coherency-fabric at d0020200 {
> diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
> index 4f4e222..0e97b97 100644
> --- a/arch/arm/mach-mvebu/pmsu.c
> +++ b/arch/arm/mach-mvebu/pmsu.c
> @@ -379,6 +379,16 @@ static struct notifier_block mvebu_v7_cpu_pm_notifier = {
>  
>  static struct platform_device mvebu_v7_cpuidle_device;
>  
> +static int broken_idle(struct device_node *np)
> +{
> +	if (of_property_read_bool(np, "broken-idle")) {
> +		pr_warn("CPU idle is currently broken: disabling\n");
> +		return 1;
> +	}
> +
> +	return 0;
> +}
> +
>  static __init int armada_370_cpuidle_init(void)
>  {
>  	struct device_node *np;
> @@ -387,7 +397,9 @@ static __init int armada_370_cpuidle_init(void)
>  	np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
>  	if (!np)
>  		return -ENODEV;
> -	of_node_put(np);
> +
> +	if (broken_idle(np))
> +		goto end;
>  
>  	/*
>  	 * On Armada 370, there is "a slow exit process from the deep
> @@ -406,6 +418,8 @@ static __init int armada_370_cpuidle_init(void)
>  	mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
>  	mvebu_v7_cpuidle_device.name = "cpuidle-armada-370";
>  
> +end:
> +	of_node_put(np);
>  	return 0;
>  }
>  
> @@ -422,6 +436,10 @@ static __init int armada_38x_cpuidle_init(void)
>  				     "marvell,armada-380-coherency-fabric");
>  	if (!np)
>  		return -ENODEV;
> +
> +	if (broken_idle(np))
> +		goto end;
> +
>  	of_node_put(np);
>  
>  	np = of_find_compatible_node(NULL, NULL,
> @@ -430,7 +448,6 @@ static __init int armada_38x_cpuidle_init(void)
>  		return -ENODEV;
>  	mpsoc_base = of_iomap(np, 0);
>  	BUG_ON(!mpsoc_base);
> -	of_node_put(np);
>  
>  	/* Set up reset mask when powering down the cpus */
>  	reg = readl(mpsoc_base + MPCORE_RESET_CTL);
> @@ -450,6 +467,8 @@ static __init int armada_38x_cpuidle_init(void)
>  	mvebu_v7_cpuidle_device.dev.platform_data = armada_38x_cpu_suspend;
>  	mvebu_v7_cpuidle_device.name = "cpuidle-armada-38x";
>  
> +end:
> +	of_node_put(np);
>  	return 0;
>  }
>  
> @@ -460,12 +479,16 @@ static __init int armada_xp_cpuidle_init(void)
>  	np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
>  	if (!np)
>  		return -ENODEV;
> -	of_node_put(np);
> +
> +	if (broken_idle(np))
> +		goto end;
>  
>  	mvebu_cpu_resume = armada_370_xp_cpu_resume;
>  	mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
>  	mvebu_v7_cpuidle_device.name = "cpuidle-armada-xp";
>  
> +end:
> +	of_node_put(np);
>  	return 0;
>  }
>  
> -- 
> 2.1.4
>

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com