* [PATCH v6 01/15] eal/arm: atomic operations for ARM
2015-11-02 23:47 [PATCH v6 00/15] Support ARMv7 architecture Jan Viktorin
@ 2015-11-02 23:47 ` Jan Viktorin
2015-11-02 23:47 ` [PATCH v6 02/15] eal/arm: byte order " Jan Viktorin
` (15 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Jan Viktorin @ 2015-11-02 23:47 UTC (permalink / raw)
To: david.marchand, David Hunt, Thomas Monjalon, Jerin Jacob
Cc: Vlastimil Kosar, dev
From: Vlastimil Kosar <kosar@rehivetech.com>
This patch adds architecture specific atomic operation file
for ARM architecture. The RTE_FORCE_INTRINSICS=y is required.
Signed-off-by: Vlastimil Kosar <kosar@rehivetech.com>
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
---
v1 -> v2:
* improve rte_wmb()
* use __atomic_* or __sync_*? (may affect the required GCC version)
v4:
* checkpatch complaints about volatile keyword (but seems to be OK to me)
* checkpatch complaints about do { ... } while (0) for single statement
with asm volatile (but I didn't find a way how to write it without
the checkpatch complaints)
* checkpatch is now happy with whitespaces
v6:
* separate for 32/64 architectures
* drop the atomic implementation and require to use RTE_FORCE_INTRINSICS
---
.../common/include/arch/arm/rte_atomic.h | 38 +++++++++++
.../common/include/arch/arm/rte_atomic_32.h | 74 ++++++++++++++++++++++
2 files changed, 112 insertions(+)
create mode 100644 lib/librte_eal/common/include/arch/arm/rte_atomic.h
create mode 100644 lib/librte_eal/common/include/arch/arm/rte_atomic_32.h
diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic.h b/lib/librte_eal/common/include/arch/arm/rte_atomic.h
new file mode 100644
index 0000000..f4f5783
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic.h
@@ -0,0 +1,38 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of RehiveTech nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_ATOMIC_ARM_H_
+#define _RTE_ATOMIC_ARM_H_
+
+#include <rte_atomic_32.h>
+
+#endif /* _RTE_ATOMIC_ARM_H_ */
diff --git a/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h b/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h
new file mode 100644
index 0000000..9ae1e78
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h
@@ -0,0 +1,74 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of RehiveTech nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_ATOMIC_ARM32_H_
+#define _RTE_ATOMIC_ARM32_H_
+
+#ifndef RTE_FORCE_INTRINSICS
+# error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_atomic.h"
+
+/**
+ * General memory barrier.
+ *
+ * Guarantees that the LOAD and STORE operations generated before the
+ * barrier occur before the LOAD and STORE operations generated after.
+ */
+#define rte_mb() __sync_synchronize()
+
+/**
+ * Write memory barrier.
+ *
+ * Guarantees that the STORE operations generated before the barrier
+ * occur before the STORE operations generated after.
+ */
+#define rte_wmb() do { asm volatile ("dmb st" : : : "memory"); } while (0)
+
+/**
+ * Read memory barrier.
+ *
+ * Guarantees that the LOAD operations generated before the barrier
+ * occur before the LOAD operations generated after.
+ */
+#define rte_rmb() __sync_synchronize()
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_ATOMIC_ARM32_H_ */
--
2.6.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v6 02/15] eal/arm: byte order operations for ARM
2015-11-02 23:47 [PATCH v6 00/15] Support ARMv7 architecture Jan Viktorin
2015-11-02 23:47 ` [PATCH v6 01/15] eal/arm: atomic operations for ARM Jan Viktorin
@ 2015-11-02 23:47 ` Jan Viktorin
2015-11-02 23:47 ` [PATCH v6 03/15] eal/arm: cpu cycle " Jan Viktorin
` (14 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Jan Viktorin @ 2015-11-02 23:47 UTC (permalink / raw)
To: david.marchand, David Hunt, Thomas Monjalon, Jerin Jacob
Cc: Vlastimil Kosar, dev
From: Vlastimil Kosar <kosar@rehivetech.com>
This patch adds architecture specific byte order operations
for ARM. The architecture supports both big and little endian.
It requires RTE_FORCE_INTRINSICS=y.
Signed-off-by: Vlastimil Kosar <kosar@rehivetech.com>
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
---
v4: fix passing params to asm volatile for checkpatch
v6: disable intrinsics, however, fix the bswap16 in older GCC
---
.../common/include/arch/arm/rte_byteorder.h | 107 +++++++++++++++++++++
1 file changed, 107 insertions(+)
create mode 100644 lib/librte_eal/common/include/arch/arm/rte_byteorder.h
diff --git a/lib/librte_eal/common/include/arch/arm/rte_byteorder.h b/lib/librte_eal/common/include/arch/arm/rte_byteorder.h
new file mode 100644
index 0000000..3f2dd1f
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm/rte_byteorder.h
@@ -0,0 +1,107 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of RehiveTech nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_BYTEORDER_ARM_H_
+#define _RTE_BYTEORDER_ARM_H_
+
+#ifndef RTE_FORCE_INTRINSICS
+# error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_byteorder.h"
+
+/* fix missing __builtin_bswap16 for gcc older then 4.8 */
+#if !(__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8))
+
+static inline uint16_t rte_arch_bswap16(uint16_t _x)
+{
+ register uint16_t x = _x;
+
+ asm volatile ("rev16 %0,%1"
+ : "=r" (x)
+ : "r" (x)
+ );
+ return x;
+}
+
+#define rte_bswap16(x) ((uint16_t)(__builtin_constant_p(x) ? \
+ rte_constant_bswap16(x) : \
+ rte_arch_bswap16(x)))
+#endif
+
+/* ARM architecture is bi-endian (both big and little). */
+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
+
+#define rte_cpu_to_le_16(x) (x)
+#define rte_cpu_to_le_32(x) (x)
+#define rte_cpu_to_le_64(x) (x)
+
+#define rte_cpu_to_be_16(x) rte_bswap16(x)
+#define rte_cpu_to_be_32(x) rte_bswap32(x)
+#define rte_cpu_to_be_64(x) rte_bswap64(x)
+
+#define rte_le_to_cpu_16(x) (x)
+#define rte_le_to_cpu_32(x) (x)
+#define rte_le_to_cpu_64(x) (x)
+
+#define rte_be_to_cpu_16(x) rte_bswap16(x)
+#define rte_be_to_cpu_32(x) rte_bswap32(x)
+#define rte_be_to_cpu_64(x) rte_bswap64(x)
+
+#else /* RTE_BIG_ENDIAN */
+
+#define rte_cpu_to_le_16(x) rte_bswap16(x)
+#define rte_cpu_to_le_32(x) rte_bswap32(x)
+#define rte_cpu_to_le_64(x) rte_bswap64(x)
+
+#define rte_cpu_to_be_16(x) (x)
+#define rte_cpu_to_be_32(x) (x)
+#define rte_cpu_to_be_64(x) (x)
+
+#define rte_le_to_cpu_16(x) rte_bswap16(x)
+#define rte_le_to_cpu_32(x) rte_bswap32(x)
+#define rte_le_to_cpu_64(x) rte_bswap64(x)
+
+#define rte_be_to_cpu_16(x) (x)
+#define rte_be_to_cpu_32(x) (x)
+#define rte_be_to_cpu_64(x) (x)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_BYTEORDER_ARM_H_ */
--
2.6.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v6 03/15] eal/arm: cpu cycle operations for ARM
2015-11-02 23:47 [PATCH v6 00/15] Support ARMv7 architecture Jan Viktorin
2015-11-02 23:47 ` [PATCH v6 01/15] eal/arm: atomic operations for ARM Jan Viktorin
2015-11-02 23:47 ` [PATCH v6 02/15] eal/arm: byte order " Jan Viktorin
@ 2015-11-02 23:47 ` Jan Viktorin
2015-11-02 23:47 ` [PATCH v6 04/15] eal/arm: implement rdtsc by PMU or clock_gettime Jan Viktorin
` (13 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Jan Viktorin @ 2015-11-02 23:47 UTC (permalink / raw)
To: david.marchand, David Hunt, Thomas Monjalon, Jerin Jacob
Cc: Vlastimil Kosar, dev
From: Vlastimil Kosar <kosar@rehivetech.com>
ARM architecture doesn't have a suitable source of CPU cycles. This
patch uses clock_gettime instead. The implementation should be improved
in the future.
Signed-off-by: Vlastimil Kosar <kosar@rehivetech.com>
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
---
v5: prepare for applying ARMv8
---
.../common/include/arch/arm/rte_cycles.h | 38 ++++++++++
.../common/include/arch/arm/rte_cycles_32.h | 85 ++++++++++++++++++++++
2 files changed, 123 insertions(+)
create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cycles.h
create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cycles_32.h
diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles.h b/lib/librte_eal/common/include/arch/arm/rte_cycles.h
new file mode 100644
index 0000000..b2372fa
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm/rte_cycles.h
@@ -0,0 +1,38 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of RehiveTech nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_CYCLES_ARM_H_
+#define _RTE_CYCLES_ARM_H_
+
+#include <rte_cycles_32.h>
+
+#endif /* _RTE_CYCLES_ARM_H_ */
diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_32.h b/lib/librte_eal/common/include/arch/arm/rte_cycles_32.h
new file mode 100644
index 0000000..755cc4a
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_32.h
@@ -0,0 +1,85 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of RehiveTech nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_CYCLES_ARM32_H_
+#define _RTE_CYCLES_ARM32_H_
+
+/* ARM v7 does not have suitable source of clock signals. The only clock counter
+ available in the core is 32 bit wide. Therefore it is unsuitable as the
+ counter overlaps every few seconds and probably is not accessible by
+ userspace programs. Therefore we use clock_gettime(CLOCK_MONOTONIC_RAW) to
+ simulate counter running at 1GHz.
+*/
+
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_cycles.h"
+
+/**
+ * Read the time base register.
+ *
+ * @return
+ * The time base for this lcore.
+ */
+static inline uint64_t
+rte_rdtsc(void)
+{
+ struct timespec val;
+ uint64_t v;
+
+ while (clock_gettime(CLOCK_MONOTONIC_RAW, &val) != 0)
+ /* no body */;
+
+ v = (uint64_t) val.tv_sec * 1000000000LL;
+ v += (uint64_t) val.tv_nsec;
+ return v;
+}
+
+static inline uint64_t
+rte_rdtsc_precise(void)
+{
+ rte_mb();
+ return rte_rdtsc();
+}
+
+static inline uint64_t
+rte_get_tsc_cycles(void) { return rte_rdtsc(); }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_CYCLES_ARM32_H_ */
--
2.6.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v6 04/15] eal/arm: implement rdtsc by PMU or clock_gettime
2015-11-02 23:47 [PATCH v6 00/15] Support ARMv7 architecture Jan Viktorin
` (2 preceding siblings ...)
2015-11-02 23:47 ` [PATCH v6 03/15] eal/arm: cpu cycle " Jan Viktorin
@ 2015-11-02 23:47 ` Jan Viktorin
2015-11-02 23:47 ` [PATCH v6 05/15] eal/arm: prefetch operations for ARM Jan Viktorin
` (12 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Jan Viktorin @ 2015-11-02 23:47 UTC (permalink / raw)
To: david.marchand, David Hunt, Thomas Monjalon, Jerin Jacob; +Cc: dev
Enable to choose a preferred way to read timer based on the
configuration entry CONFIG_RTE_ARM_EAL_RDTSC_USE_PMU.
It requires a kernel module that is not included to work.
Based on the patch by David Hunt and Armuta Zende:
lib: added support for armv7 architecture
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
Signed-off-by: Amruta Zende <amruta.zende@intel.com>
Signed-off-by: David Hunt <david.hunt@intel.com>
---
.../common/include/arch/arm/rte_cycles_32.h | 38 +++++++++++++++++++++-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_cycles_32.h b/lib/librte_eal/common/include/arch/arm/rte_cycles_32.h
index 755cc4a..6c6098e 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_cycles_32.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_cycles_32.h
@@ -54,8 +54,14 @@ extern "C" {
* @return
* The time base for this lcore.
*/
+#ifndef CONFIG_RTE_ARM_EAL_RDTSC_USE_PMU
+
+/**
+ * This call is easily portable to any ARM architecture, however,
+ * it may be damn slow and inprecise for some tasks.
+ */
static inline uint64_t
-rte_rdtsc(void)
+__rte_rdtsc_syscall(void)
{
struct timespec val;
uint64_t v;
@@ -67,6 +73,36 @@ rte_rdtsc(void)
v += (uint64_t) val.tv_nsec;
return v;
}
+#define rte_rdtsc __rte_rdtsc_syscall
+
+#else
+
+/**
+ * This function requires to configure the PMCCNTR and enable
+ * userspace access to it:
+ *
+ * asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(1));
+ * asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(29));
+ * asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r"(0x8000000f));
+ *
+ * which is possible only from the priviledged mode (kernel space).
+ */
+static inline uint64_t
+__rte_rdtsc_pmccntr(void)
+{
+ unsigned tsc;
+ uint64_t final_tsc;
+
+ /* Read PMCCNTR */
+ asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r"(tsc));
+ /* 1 tick = 64 clocks */
+ final_tsc = ((uint64_t)tsc) << 6;
+
+ return (uint64_t)final_tsc;
+}
+#define rte_rdtsc __rte_rdtsc_pmccntr
+
+#endif /* RTE_ARM_EAL_RDTSC_USE_PMU */
static inline uint64_t
rte_rdtsc_precise(void)
--
2.6.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v6 05/15] eal/arm: prefetch operations for ARM
2015-11-02 23:47 [PATCH v6 00/15] Support ARMv7 architecture Jan Viktorin
` (3 preceding siblings ...)
2015-11-02 23:47 ` [PATCH v6 04/15] eal/arm: implement rdtsc by PMU or clock_gettime Jan Viktorin
@ 2015-11-02 23:47 ` Jan Viktorin
2015-11-02 23:47 ` [PATCH v6 06/15] eal/arm: spinlock operations for ARM (without HTM) Jan Viktorin
` (11 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Jan Viktorin @ 2015-11-02 23:47 UTC (permalink / raw)
To: david.marchand, David Hunt, Thomas Monjalon, Jerin Jacob
Cc: Vlastimil Kosar, dev
From: Vlastimil Kosar <kosar@rehivetech.com>
This patch adds architecture specific prefetch operations
for ARM architecture. It utilizes the pld instruction that
starts filling the appropriate cache line without blocking.
Signed-off-by: Vlastimil Kosar <kosar@rehivetech.com>
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
---
v4:
* checkpatch does not like the syntax of naming params
to asm volatile; switched to %0, %1 syntax
* checkpatch complatins about volatile (seems to be OK for me)
v5: prepare for applying ARMv8
---
.../common/include/arch/arm/rte_prefetch.h | 38 ++++++++++++++
.../common/include/arch/arm/rte_prefetch_32.h | 61 ++++++++++++++++++++++
2 files changed, 99 insertions(+)
create mode 100644 lib/librte_eal/common/include/arch/arm/rte_prefetch.h
create mode 100644 lib/librte_eal/common/include/arch/arm/rte_prefetch_32.h
diff --git a/lib/librte_eal/common/include/arch/arm/rte_prefetch.h b/lib/librte_eal/common/include/arch/arm/rte_prefetch.h
new file mode 100644
index 0000000..1f46697
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm/rte_prefetch.h
@@ -0,0 +1,38 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of RehiveTech nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_PREFETCH_ARM_H_
+#define _RTE_PREFETCH_ARM_H_
+
+#include <rte_prefetch_32.h>
+
+#endif /* _RTE_PREFETCH_ARM_H_ */
diff --git a/lib/librte_eal/common/include/arch/arm/rte_prefetch_32.h b/lib/librte_eal/common/include/arch/arm/rte_prefetch_32.h
new file mode 100644
index 0000000..b716384
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm/rte_prefetch_32.h
@@ -0,0 +1,61 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of RehiveTech nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_PREFETCH_ARM32_H_
+#define _RTE_PREFETCH_ARM32_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_prefetch.h"
+
+static inline void rte_prefetch0(const volatile void *p)
+{
+ asm volatile ("pld [%0]" : : "r" (p));
+}
+
+static inline void rte_prefetch1(const volatile void *p)
+{
+ asm volatile ("pld [%0]" : : "r" (p));
+}
+
+static inline void rte_prefetch2(const volatile void *p)
+{
+ asm volatile ("pld [%0]" : : "r" (p));
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_PREFETCH_ARM32_H_ */
--
2.6.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v6 06/15] eal/arm: spinlock operations for ARM (without HTM)
2015-11-02 23:47 [PATCH v6 00/15] Support ARMv7 architecture Jan Viktorin
` (4 preceding siblings ...)
2015-11-02 23:47 ` [PATCH v6 05/15] eal/arm: prefetch operations for ARM Jan Viktorin
@ 2015-11-02 23:47 ` Jan Viktorin
2015-11-02 23:47 ` [PATCH v6 07/15] eal/arm: vector memcpy for ARM Jan Viktorin
` (10 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Jan Viktorin @ 2015-11-02 23:47 UTC (permalink / raw)
To: david.marchand, David Hunt, Thomas Monjalon, Jerin Jacob
Cc: Vlastimil Kosar, dev
From: Vlastimil Kosar <kosar@rehivetech.com>
This patch adds spinlock operations for ARM architecture.
We do not support HTM in spinlocks on ARM. Setting of the
RTE_FORCE_INTRINSICS=y is required.
Signed-off-by: Vlastimil Kosar <kosar@rehivetech.com>
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
---
v6: use builtin intrinsics implementation
---
.../common/include/arch/arm/rte_spinlock.h | 92 ++++++++++++++++++++++
1 file changed, 92 insertions(+)
create mode 100644 lib/librte_eal/common/include/arch/arm/rte_spinlock.h
diff --git a/lib/librte_eal/common/include/arch/arm/rte_spinlock.h b/lib/librte_eal/common/include/arch/arm/rte_spinlock.h
new file mode 100644
index 0000000..396a42e
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm/rte_spinlock.h
@@ -0,0 +1,92 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of RehiveTech nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_SPINLOCK_ARM_H_
+#define _RTE_SPINLOCK_ARM_H_
+
+#ifndef RTE_FORCE_INTRINSICS
+# error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+#include "generic/rte_spinlock.h"
+
+static inline int rte_tm_supported(void)
+{
+ return 0;
+}
+
+static inline void
+rte_spinlock_lock_tm(rte_spinlock_t *sl)
+{
+ rte_spinlock_lock(sl); /* fall-back */
+}
+
+static inline int
+rte_spinlock_trylock_tm(rte_spinlock_t *sl)
+{
+ return rte_spinlock_trylock(sl);
+}
+
+static inline void
+rte_spinlock_unlock_tm(rte_spinlock_t *sl)
+{
+ rte_spinlock_unlock(sl);
+}
+
+static inline void
+rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr)
+{
+ rte_spinlock_recursive_lock(slr); /* fall-back */
+}
+
+static inline void
+rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr)
+{
+ rte_spinlock_recursive_unlock(slr);
+}
+
+static inline int
+rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr)
+{
+ return rte_spinlock_recursive_trylock(slr);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_SPINLOCK_ARM_H_ */
--
2.6.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v6 07/15] eal/arm: vector memcpy for ARM
2015-11-02 23:47 [PATCH v6 00/15] Support ARMv7 architecture Jan Viktorin
` (5 preceding siblings ...)
2015-11-02 23:47 ` [PATCH v6 06/15] eal/arm: spinlock operations for ARM (without HTM) Jan Viktorin
@ 2015-11-02 23:47 ` Jan Viktorin
2015-11-02 23:47 ` [PATCH v6 08/15] eal/arm: use vector memcpy only when NEON is enabled Jan Viktorin
` (9 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Jan Viktorin @ 2015-11-02 23:47 UTC (permalink / raw)
To: david.marchand, David Hunt, Thomas Monjalon, Jerin Jacob
Cc: Vlastimil Kosar, dev
From: Vlastimil Kosar <kosar@rehivetech.com>
The SSE based memory copy in DPDK only support x86. This patch
adds ARM NEON based memory copy functions for ARM architecture.
The implementation improves memory copy of short or well aligned
data buffers. The following measurements show improvements over
the libc memcpy on Cortex CPUs.
by X % faster
Length (B) a15 a7 a9
1 4.9 15.2 3.2
7 56.9 48.2 40.3
8 37.3 39.8 29.6
9 69.3 38.7 33.9
15 60.8 35.3 23.7
16 50.6 35.9 35.0
17 57.7 35.7 31.1
31 16.0 23.3 9.0
32 65.9 13.5 21.4
33 3.9 10.3 -3.7
63 2.0 12.9 -2.0
64 66.5 0.0 16.5
65 2.7 7.6 -35.6
127 0.1 4.5 -18.9
128 66.2 1.5 -51.4
129 -0.8 3.2 -35.8
255 -3.1 -0.9 -69.1
256 67.9 1.2 7.2
257 -3.6 -1.9 -36.9
320 67.7 1.4 0.0
384 66.8 1.4 -14.2
511 -44.9 -2.3 -41.9
512 67.3 1.4 -6.8
513 -41.7 -3.0 -36.2
1023 -82.4 -2.8 -41.2
1024 68.3 1.4 -11.6
1025 -80.1 -3.3 -38.1
1518 -47.3 -5.0 -38.3
1522 -48.3 -6.0 -37.9
1600 65.4 1.3 -27.3
2048 59.5 1.5 -10.9
3072 52.3 1.5 -12.2
4096 45.3 1.4 -12.5
5120 40.6 1.5 -14.5
6144 35.4 1.4 -13.4
7168 32.9 1.4 -13.9
8192 28.2 1.4 -15.1
Signed-off-by: Vlastimil Kosar <kosar@rehivetech.com>
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
---
v4:
* fix whitespace issues reported by checkpatch
* fix passing params to asm volatile for checkpatch
v5: prepare for applying ARMv8
---
.../common/include/arch/arm/rte_memcpy.h | 38 +++
.../common/include/arch/arm/rte_memcpy_32.h | 279 +++++++++++++++++++++
2 files changed, 317 insertions(+)
create mode 100644 lib/librte_eal/common/include/arch/arm/rte_memcpy.h
create mode 100644 lib/librte_eal/common/include/arch/arm/rte_memcpy_32.h
diff --git a/lib/librte_eal/common/include/arch/arm/rte_memcpy.h b/lib/librte_eal/common/include/arch/arm/rte_memcpy.h
new file mode 100644
index 0000000..d9f5bf1
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm/rte_memcpy.h
@@ -0,0 +1,38 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of RehiveTech nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_MEMCPY_ARM_H_
+#define _RTE_MEMCPY_ARM_H_
+
+#include <rte_memcpy_32.h>
+
+#endif /* _RTE_MEMCPY_ARM_H_ */
diff --git a/lib/librte_eal/common/include/arch/arm/rte_memcpy_32.h b/lib/librte_eal/common/include/arch/arm/rte_memcpy_32.h
new file mode 100644
index 0000000..11f8241
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm/rte_memcpy_32.h
@@ -0,0 +1,279 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of RehiveTech nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_MEMCPY_ARM32_H_
+#define _RTE_MEMCPY_ARM32_H_
+
+#include <stdint.h>
+#include <string.h>
+/* ARM NEON Intrinsics are used to copy data */
+#include <arm_neon.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_memcpy.h"
+
+static inline void
+rte_mov16(uint8_t *dst, const uint8_t *src)
+{
+ vst1q_u8(dst, vld1q_u8(src));
+}
+
+static inline void
+rte_mov32(uint8_t *dst, const uint8_t *src)
+{
+ asm volatile (
+ "vld1.8 {d0-d3}, [%0]\n\t"
+ "vst1.8 {d0-d3}, [%1]\n\t"
+ : "+r" (src), "+r" (dst)
+ : : "memory", "d0", "d1", "d2", "d3");
+}
+
+static inline void
+rte_mov48(uint8_t *dst, const uint8_t *src)
+{
+ asm volatile (
+ "vld1.8 {d0-d3}, [%0]!\n\t"
+ "vld1.8 {d4-d5}, [%0]\n\t"
+ "vst1.8 {d0-d3}, [%1]!\n\t"
+ "vst1.8 {d4-d5}, [%1]\n\t"
+ : "+r" (src), "+r" (dst)
+ :
+ : "memory", "d0", "d1", "d2", "d3", "d4", "d5");
+}
+
+static inline void
+rte_mov64(uint8_t *dst, const uint8_t *src)
+{
+ asm volatile (
+ "vld1.8 {d0-d3}, [%0]!\n\t"
+ "vld1.8 {d4-d7}, [%0]\n\t"
+ "vst1.8 {d0-d3}, [%1]!\n\t"
+ "vst1.8 {d4-d7}, [%1]\n\t"
+ : "+r" (src), "+r" (dst)
+ :
+ : "memory", "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7");
+}
+
+static inline void
+rte_mov128(uint8_t *dst, const uint8_t *src)
+{
+ asm volatile ("pld [%0, #64]" : : "r" (src));
+ asm volatile (
+ "vld1.8 {d0-d3}, [%0]!\n\t"
+ "vld1.8 {d4-d7}, [%0]!\n\t"
+ "vld1.8 {d8-d11}, [%0]!\n\t"
+ "vld1.8 {d12-d15}, [%0]\n\t"
+ "vst1.8 {d0-d3}, [%1]!\n\t"
+ "vst1.8 {d4-d7}, [%1]!\n\t"
+ "vst1.8 {d8-d11}, [%1]!\n\t"
+ "vst1.8 {d12-d15}, [%1]\n\t"
+ : "+r" (src), "+r" (dst)
+ :
+ : "memory", "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
+ "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15");
+}
+
+static inline void
+rte_mov256(uint8_t *dst, const uint8_t *src)
+{
+ asm volatile ("pld [%0, #64]" : : "r" (src));
+ asm volatile ("pld [%0, #128]" : : "r" (src));
+ asm volatile ("pld [%0, #192]" : : "r" (src));
+ asm volatile ("pld [%0, #256]" : : "r" (src));
+ asm volatile ("pld [%0, #320]" : : "r" (src));
+ asm volatile ("pld [%0, #384]" : : "r" (src));
+ asm volatile ("pld [%0, #448]" : : "r" (src));
+ asm volatile (
+ "vld1.8 {d0-d3}, [%0]!\n\t"
+ "vld1.8 {d4-d7}, [%0]!\n\t"
+ "vld1.8 {d8-d11}, [%0]!\n\t"
+ "vld1.8 {d12-d15}, [%0]!\n\t"
+ "vld1.8 {d16-d19}, [%0]!\n\t"
+ "vld1.8 {d20-d23}, [%0]!\n\t"
+ "vld1.8 {d24-d27}, [%0]!\n\t"
+ "vld1.8 {d28-d31}, [%0]\n\t"
+ "vst1.8 {d0-d3}, [%1]!\n\t"
+ "vst1.8 {d4-d7}, [%1]!\n\t"
+ "vst1.8 {d8-d11}, [%1]!\n\t"
+ "vst1.8 {d12-d15}, [%1]!\n\t"
+ "vst1.8 {d16-d19}, [%1]!\n\t"
+ "vst1.8 {d20-d23}, [%1]!\n\t"
+ "vst1.8 {d24-d27}, [%1]!\n\t"
+ "vst1.8 {d28-d31}, [%1]!\n\t"
+ : "+r" (src), "+r" (dst)
+ :
+ : "memory", "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
+ "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
+ "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
+ "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31");
+}
+
+#define rte_memcpy(dst, src, n) \
+ ({ (__builtin_constant_p(n)) ? \
+ memcpy((dst), (src), (n)) : \
+ rte_memcpy_func((dst), (src), (n)); })
+
+static inline void *
+rte_memcpy_func(void *dst, const void *src, size_t n)
+{
+ void *ret = dst;
+
+ /* We can't copy < 16 bytes using XMM registers so do it manually. */
+ if (n < 16) {
+ if (n & 0x01) {
+ *(uint8_t *)dst = *(const uint8_t *)src;
+ dst = (uint8_t *)dst + 1;
+ src = (const uint8_t *)src + 1;
+ }
+ if (n & 0x02) {
+ *(uint16_t *)dst = *(const uint16_t *)src;
+ dst = (uint16_t *)dst + 1;
+ src = (const uint16_t *)src + 1;
+ }
+ if (n & 0x04) {
+ *(uint32_t *)dst = *(const uint32_t *)src;
+ dst = (uint32_t *)dst + 1;
+ src = (const uint32_t *)src + 1;
+ }
+ if (n & 0x08) {
+ /* ARMv7 can not handle unaligned access to long long
+ * (uint64_t). Therefore two uint32_t operations are
+ * used.
+ */
+ *(uint32_t *)dst = *(const uint32_t *)src;
+ dst = (uint32_t *)dst + 1;
+ src = (const uint32_t *)src + 1;
+ *(uint32_t *)dst = *(const uint32_t *)src;
+ }
+ return ret;
+ }
+
+ /* Special fast cases for <= 128 bytes */
+ if (n <= 32) {
+ rte_mov16((uint8_t *)dst, (const uint8_t *)src);
+ rte_mov16((uint8_t *)dst - 16 + n,
+ (const uint8_t *)src - 16 + n);
+ return ret;
+ }
+
+ if (n <= 64) {
+ rte_mov32((uint8_t *)dst, (const uint8_t *)src);
+ rte_mov32((uint8_t *)dst - 32 + n,
+ (const uint8_t *)src - 32 + n);
+ return ret;
+ }
+
+ if (n <= 128) {
+ rte_mov64((uint8_t *)dst, (const uint8_t *)src);
+ rte_mov64((uint8_t *)dst - 64 + n,
+ (const uint8_t *)src - 64 + n);
+ return ret;
+ }
+
+ /*
+ * For large copies > 128 bytes. This combination of 256, 64 and 16 byte
+ * copies was found to be faster than doing 128 and 32 byte copies as
+ * well.
+ */
+ for ( ; n >= 256; n -= 256) {
+ rte_mov256((uint8_t *)dst, (const uint8_t *)src);
+ dst = (uint8_t *)dst + 256;
+ src = (const uint8_t *)src + 256;
+ }
+
+ /*
+ * We split the remaining bytes (which will be less than 256) into
+ * 64byte (2^6) chunks.
+ * Using incrementing integers in the case labels of a switch statement
+ * enourages the compiler to use a jump table. To get incrementing
+ * integers, we shift the 2 relevant bits to the LSB position to first
+ * get decrementing integers, and then subtract.
+ */
+ switch (3 - (n >> 6)) {
+ case 0x00:
+ rte_mov64((uint8_t *)dst, (const uint8_t *)src);
+ n -= 64;
+ dst = (uint8_t *)dst + 64;
+ src = (const uint8_t *)src + 64; /* fallthrough */
+ case 0x01:
+ rte_mov64((uint8_t *)dst, (const uint8_t *)src);
+ n -= 64;
+ dst = (uint8_t *)dst + 64;
+ src = (const uint8_t *)src + 64; /* fallthrough */
+ case 0x02:
+ rte_mov64((uint8_t *)dst, (const uint8_t *)src);
+ n -= 64;
+ dst = (uint8_t *)dst + 64;
+ src = (const uint8_t *)src + 64; /* fallthrough */
+ default:
+ break;
+ }
+
+ /*
+ * We split the remaining bytes (which will be less than 64) into
+ * 16byte (2^4) chunks, using the same switch structure as above.
+ */
+ switch (3 - (n >> 4)) {
+ case 0x00:
+ rte_mov16((uint8_t *)dst, (const uint8_t *)src);
+ n -= 16;
+ dst = (uint8_t *)dst + 16;
+ src = (const uint8_t *)src + 16; /* fallthrough */
+ case 0x01:
+ rte_mov16((uint8_t *)dst, (const uint8_t *)src);
+ n -= 16;
+ dst = (uint8_t *)dst + 16;
+ src = (const uint8_t *)src + 16; /* fallthrough */
+ case 0x02:
+ rte_mov16((uint8_t *)dst, (const uint8_t *)src);
+ n -= 16;
+ dst = (uint8_t *)dst + 16;
+ src = (const uint8_t *)src + 16; /* fallthrough */
+ default:
+ break;
+ }
+
+ /* Copy any remaining bytes, without going beyond end of buffers */
+ if (n != 0)
+ rte_mov16((uint8_t *)dst - 16 + n,
+ (const uint8_t *)src - 16 + n);
+ return ret;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_MEMCPY_ARM32_H_ */
--
2.6.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v6 08/15] eal/arm: use vector memcpy only when NEON is enabled
2015-11-02 23:47 [PATCH v6 00/15] Support ARMv7 architecture Jan Viktorin
` (6 preceding siblings ...)
2015-11-02 23:47 ` [PATCH v6 07/15] eal/arm: vector memcpy for ARM Jan Viktorin
@ 2015-11-02 23:47 ` Jan Viktorin
2015-11-02 23:47 ` [PATCH v6 09/15] eal/arm: cpu flag checks for ARM Jan Viktorin
` (8 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Jan Viktorin @ 2015-11-02 23:47 UTC (permalink / raw)
To: david.marchand, David Hunt, Thomas Monjalon, Jerin Jacob; +Cc: dev
The GCC can be configured to avoid using NEON extensions.
For that purpose, we provide just the memcpy implementation
of the rte_memcpy.
Based on the patch by David Hunt and Armuta Zende:
lib: added support for armv7 architecture
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
Signed-off-by: Amruta Zende <amruta.zende@intel.com>
Signed-off-by: David Hunt <david.hunt@intel.com>
---
v5: prepare for applying ARMv8
---
.../common/include/arch/arm/rte_memcpy_32.h | 59 +++++++++++++++++++++-
1 file changed, 57 insertions(+), 2 deletions(-)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_memcpy_32.h b/lib/librte_eal/common/include/arch/arm/rte_memcpy_32.h
index 11f8241..df47c0d 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_memcpy_32.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_memcpy_32.h
@@ -35,8 +35,6 @@
#include <stdint.h>
#include <string.h>
-/* ARM NEON Intrinsics are used to copy data */
-#include <arm_neon.h>
#ifdef __cplusplus
extern "C" {
@@ -44,6 +42,11 @@ extern "C" {
#include "generic/rte_memcpy.h"
+#ifdef __ARM_NEON_FP
+
+/* ARM NEON Intrinsics are used to copy data */
+#include <arm_neon.h>
+
static inline void
rte_mov16(uint8_t *dst, const uint8_t *src)
{
@@ -272,6 +275,58 @@ rte_memcpy_func(void *dst, const void *src, size_t n)
return ret;
}
+#else
+
+static inline void
+rte_mov16(uint8_t *dst, const uint8_t *src)
+{
+ memcpy(dst, src, 16);
+}
+
+static inline void
+rte_mov32(uint8_t *dst, const uint8_t *src)
+{
+ memcpy(dst, src, 32);
+}
+
+static inline void
+rte_mov48(uint8_t *dst, const uint8_t *src)
+{
+ memcpy(dst, src, 48);
+}
+
+static inline void
+rte_mov64(uint8_t *dst, const uint8_t *src)
+{
+ memcpy(dst, src, 64);
+}
+
+static inline void
+rte_mov128(uint8_t *dst, const uint8_t *src)
+{
+ memcpy(dst, src, 128);
+}
+
+static inline void
+rte_mov256(uint8_t *dst, const uint8_t *src)
+{
+ memcpy(dst, src, 256);
+}
+
+static inline void *
+rte_memcpy(void *dst, const void *src, size_t n)
+{
+ return memcpy(dst, src, n);
+}
+
+static inline void *
+rte_memcpy_func(void *dst, const void *src, size_t n)
+{
+ return memcpy(dst, src, n);
+}
+
+#endif /* __ARM_NEON_FP */
+
#ifdef __cplusplus
}
#endif
--
2.6.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v6 09/15] eal/arm: cpu flag checks for ARM
2015-11-02 23:47 [PATCH v6 00/15] Support ARMv7 architecture Jan Viktorin
` (7 preceding siblings ...)
2015-11-02 23:47 ` [PATCH v6 08/15] eal/arm: use vector memcpy only when NEON is enabled Jan Viktorin
@ 2015-11-02 23:47 ` Jan Viktorin
2015-11-02 23:47 ` [PATCH v6 10/15] eal/arm: detect arm architecture in cpu flags Jan Viktorin
` (7 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Jan Viktorin @ 2015-11-02 23:47 UTC (permalink / raw)
To: david.marchand, David Hunt, Thomas Monjalon, Jerin Jacob
Cc: Vlastimil Kosar, dev
From: Vlastimil Kosar <kosar@rehivetech.com>
This implementation is based on IBM POWER version of
rte_cpuflags. We use software emulation of HW capability
registers, because those are usually not directly accessible
from userspace on ARM.
Signed-off-by: Vlastimil Kosar <kosar@rehivetech.com>
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
---
v6: separate 32/64 architectures
---
app/test/test_cpuflags.c | 5 +
.../common/include/arch/arm/rte_cpuflags.h | 38 +++++
.../common/include/arch/arm/rte_cpuflags_32.h | 177 +++++++++++++++++++++
mk/rte.cpuflags.mk | 6 +
4 files changed, 226 insertions(+)
create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cpuflags.h
create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cpuflags_32.h
diff --git a/app/test/test_cpuflags.c b/app/test/test_cpuflags.c
index 5b92061..557458f 100644
--- a/app/test/test_cpuflags.c
+++ b/app/test/test_cpuflags.c
@@ -115,6 +115,11 @@ test_cpuflags(void)
CHECK_FOR_FLAG(RTE_CPUFLAG_ICACHE_SNOOP);
#endif
+#if defined(RTE_ARCH_ARM)
+ printf("Check for NEON:\t\t");
+ CHECK_FOR_FLAG(RTE_CPUFLAG_NEON);
+#endif
+
#if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686)
printf("Check for SSE:\t\t");
CHECK_FOR_FLAG(RTE_CPUFLAG_SSE);
diff --git a/lib/librte_eal/common/include/arch/arm/rte_cpuflags.h b/lib/librte_eal/common/include/arch/arm/rte_cpuflags.h
new file mode 100644
index 0000000..8de78d2
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm/rte_cpuflags.h
@@ -0,0 +1,38 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of RehiveTech nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_CPUFLAGS_ARM_H_
+#define _RTE_CPUFLAGS_ARM_H_
+
+#include <rte_cpuflags_32.h>
+
+#endif /* _RTE_CPUFLAGS_ARM_H_ */
diff --git a/lib/librte_eal/common/include/arch/arm/rte_cpuflags_32.h b/lib/librte_eal/common/include/arch/arm/rte_cpuflags_32.h
new file mode 100644
index 0000000..3280817
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm/rte_cpuflags_32.h
@@ -0,0 +1,177 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of RehiveTech nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_CPUFLAGS_ARM32_H_
+#define _RTE_CPUFLAGS_ARM32_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <elf.h>
+#include <fcntl.h>
+#include <assert.h>
+#include <unistd.h>
+
+#include "generic/rte_cpuflags.h"
+
+#ifndef AT_HWCAP
+#define AT_HWCAP 16
+#endif
+
+#ifndef AT_HWCAP2
+#define AT_HWCAP2 26
+#endif
+
+/* software based registers */
+enum cpu_register_t {
+ REG_HWCAP = 0,
+ REG_HWCAP2,
+};
+
+/**
+ * Enumeration of all CPU features supported
+ */
+enum rte_cpu_flag_t {
+ RTE_CPUFLAG_SWP = 0,
+ RTE_CPUFLAG_HALF,
+ RTE_CPUFLAG_THUMB,
+ RTE_CPUFLAG_A26BIT,
+ RTE_CPUFLAG_FAST_MULT,
+ RTE_CPUFLAG_FPA,
+ RTE_CPUFLAG_VFP,
+ RTE_CPUFLAG_EDSP,
+ RTE_CPUFLAG_JAVA,
+ RTE_CPUFLAG_IWMMXT,
+ RTE_CPUFLAG_CRUNCH,
+ RTE_CPUFLAG_THUMBEE,
+ RTE_CPUFLAG_NEON,
+ RTE_CPUFLAG_VFPv3,
+ RTE_CPUFLAG_VFPv3D16,
+ RTE_CPUFLAG_TLS,
+ RTE_CPUFLAG_VFPv4,
+ RTE_CPUFLAG_IDIVA,
+ RTE_CPUFLAG_IDIVT,
+ RTE_CPUFLAG_VFPD32,
+ RTE_CPUFLAG_LPAE,
+ RTE_CPUFLAG_EVTSTRM,
+ RTE_CPUFLAG_AES,
+ RTE_CPUFLAG_PMULL,
+ RTE_CPUFLAG_SHA1,
+ RTE_CPUFLAG_SHA2,
+ RTE_CPUFLAG_CRC32,
+ /* The last item */
+ RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */
+};
+
+static const struct feature_entry cpu_feature_table[] = {
+ FEAT_DEF(SWP, 0x00000001, 0, REG_HWCAP, 0)
+ FEAT_DEF(HALF, 0x00000001, 0, REG_HWCAP, 1)
+ FEAT_DEF(THUMB, 0x00000001, 0, REG_HWCAP, 2)
+ FEAT_DEF(A26BIT, 0x00000001, 0, REG_HWCAP, 3)
+ FEAT_DEF(FAST_MULT, 0x00000001, 0, REG_HWCAP, 4)
+ FEAT_DEF(FPA, 0x00000001, 0, REG_HWCAP, 5)
+ FEAT_DEF(VFP, 0x00000001, 0, REG_HWCAP, 6)
+ FEAT_DEF(EDSP, 0x00000001, 0, REG_HWCAP, 7)
+ FEAT_DEF(JAVA, 0x00000001, 0, REG_HWCAP, 8)
+ FEAT_DEF(IWMMXT, 0x00000001, 0, REG_HWCAP, 9)
+ FEAT_DEF(CRUNCH, 0x00000001, 0, REG_HWCAP, 10)
+ FEAT_DEF(THUMBEE, 0x00000001, 0, REG_HWCAP, 11)
+ FEAT_DEF(NEON, 0x00000001, 0, REG_HWCAP, 12)
+ FEAT_DEF(VFPv3, 0x00000001, 0, REG_HWCAP, 13)
+ FEAT_DEF(VFPv3D16, 0x00000001, 0, REG_HWCAP, 14)
+ FEAT_DEF(TLS, 0x00000001, 0, REG_HWCAP, 15)
+ FEAT_DEF(VFPv4, 0x00000001, 0, REG_HWCAP, 16)
+ FEAT_DEF(IDIVA, 0x00000001, 0, REG_HWCAP, 17)
+ FEAT_DEF(IDIVT, 0x00000001, 0, REG_HWCAP, 18)
+ FEAT_DEF(VFPD32, 0x00000001, 0, REG_HWCAP, 19)
+ FEAT_DEF(LPAE, 0x00000001, 0, REG_HWCAP, 20)
+ FEAT_DEF(EVTSTRM, 0x00000001, 0, REG_HWCAP, 21)
+ FEAT_DEF(AES, 0x00000001, 0, REG_HWCAP2, 0)
+ FEAT_DEF(PMULL, 0x00000001, 0, REG_HWCAP2, 1)
+ FEAT_DEF(SHA1, 0x00000001, 0, REG_HWCAP2, 2)
+ FEAT_DEF(SHA2, 0x00000001, 0, REG_HWCAP2, 3)
+ FEAT_DEF(CRC32, 0x00000001, 0, REG_HWCAP2, 4)
+};
+
+/*
+ * Read AUXV software register and get cpu features for ARM
+ */
+static inline void
+rte_cpu_get_features(__attribute__((unused)) uint32_t leaf,
+ __attribute__((unused)) uint32_t subleaf, cpuid_registers_t out)
+{
+ int auxv_fd;
+ Elf32_auxv_t auxv;
+
+ auxv_fd = open("/proc/self/auxv", O_RDONLY);
+ assert(auxv_fd);
+ while (read(auxv_fd, &auxv,
+ sizeof(Elf32_auxv_t)) == sizeof(Elf32_auxv_t)) {
+ if (auxv.a_type == AT_HWCAP)
+ out[REG_HWCAP] = auxv.a_un.a_val;
+ else if (auxv.a_type == AT_HWCAP2)
+ out[REG_HWCAP2] = auxv.a_un.a_val;
+ }
+}
+
+/*
+ * Checks if a particular flag is available on current machine.
+ */
+static inline int
+rte_cpu_get_flag_enabled(enum rte_cpu_flag_t feature)
+{
+ const struct feature_entry *feat;
+ cpuid_registers_t regs = {0};
+
+ if (feature >= RTE_CPUFLAG_NUMFLAGS)
+ /* Flag does not match anything in the feature tables */
+ return -ENOENT;
+
+ feat = &cpu_feature_table[feature];
+
+ if (!feat->leaf)
+ /* This entry in the table wasn't filled out! */
+ return -EFAULT;
+
+ /* get the cpuid leaf containing the desired feature */
+ rte_cpu_get_features(feat->leaf, feat->subleaf, regs);
+
+ /* check if the feature is enabled */
+ return (regs[feat->reg] >> feat->bit) & 1;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_CPUFLAGS_ARM32_H_ */
diff --git a/mk/rte.cpuflags.mk b/mk/rte.cpuflags.mk
index f595cd0..bec7bdd 100644
--- a/mk/rte.cpuflags.mk
+++ b/mk/rte.cpuflags.mk
@@ -106,6 +106,12 @@ ifneq ($(filter $(AUTO_CPUFLAGS),__builtin_vsx_xvnmaddadp),)
CPUFLAGS += VSX
endif
+# ARM flags
+ifneq ($(filter $(AUTO_CPUFLAGS),__ARM_NEON_FP),)
+CPUFLAGS += NEON
+endif
+
+
MACHINE_CFLAGS += $(addprefix -DRTE_MACHINE_CPUFLAG_,$(CPUFLAGS))
# To strip whitespace
--
2.6.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v6 10/15] eal/arm: detect arm architecture in cpu flags
2015-11-02 23:47 [PATCH v6 00/15] Support ARMv7 architecture Jan Viktorin
` (8 preceding siblings ...)
2015-11-02 23:47 ` [PATCH v6 09/15] eal/arm: cpu flag checks for ARM Jan Viktorin
@ 2015-11-02 23:47 ` Jan Viktorin
2015-11-02 23:47 ` [PATCH v6 11/15] eal/arm: rwlock support for ARM Jan Viktorin
` (6 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Jan Viktorin @ 2015-11-02 23:47 UTC (permalink / raw)
To: david.marchand, David Hunt, Thomas Monjalon, Jerin Jacob; +Cc: dev
Based on the patch by David Hunt and Armuta Zende:
lib: added support for armv7 architecture
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
Signed-off-by: Amruta Zende <amruta.zende@intel.com>
Signed-off-by: David Hunt <david.hunt@intel.com>
---
v2 -> v3: fixed forgotten include of string.h
v4: checkpatch reports few characters over 80 for checking aarch64
v6: drop checking of "aarch32/64" (invalid for armv7),
check for "v7l" string instead
---
lib/librte_eal/common/include/arch/arm/rte_cpuflags_32.h | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/lib/librte_eal/common/include/arch/arm/rte_cpuflags_32.h b/lib/librte_eal/common/include/arch/arm/rte_cpuflags_32.h
index 3280817..2106c41 100644
--- a/lib/librte_eal/common/include/arch/arm/rte_cpuflags_32.h
+++ b/lib/librte_eal/common/include/arch/arm/rte_cpuflags_32.h
@@ -41,6 +41,7 @@ extern "C" {
#include <fcntl.h>
#include <assert.h>
#include <unistd.h>
+#include <string.h>
#include "generic/rte_cpuflags.h"
@@ -52,10 +53,15 @@ extern "C" {
#define AT_HWCAP2 26
#endif
+#ifndef AT_PLATFORM
+#define AT_PLATFORM 15
+#endif
+
/* software based registers */
enum cpu_register_t {
REG_HWCAP = 0,
REG_HWCAP2,
+ REG_PLATFORM,
};
/**
@@ -89,6 +95,7 @@ enum rte_cpu_flag_t {
RTE_CPUFLAG_SHA1,
RTE_CPUFLAG_SHA2,
RTE_CPUFLAG_CRC32,
+ RTE_CPUFLAG_V7L,
/* The last item */
RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */
};
@@ -121,6 +128,7 @@ static const struct feature_entry cpu_feature_table[] = {
FEAT_DEF(SHA1, 0x00000001, 0, REG_HWCAP2, 2)
FEAT_DEF(SHA2, 0x00000001, 0, REG_HWCAP2, 3)
FEAT_DEF(CRC32, 0x00000001, 0, REG_HWCAP2, 4)
+ FEAT_DEF(V7L, 0x00000001, 0, REG_PLATFORM, 0)
};
/*
@@ -141,6 +149,10 @@ rte_cpu_get_features(__attribute__((unused)) uint32_t leaf,
out[REG_HWCAP] = auxv.a_un.a_val;
else if (auxv.a_type == AT_HWCAP2)
out[REG_HWCAP2] = auxv.a_un.a_val;
+ else if (auxv.a_type == AT_PLATFORM) {
+ if (!strcmp((const char *)auxv.a_un.a_val, "v7l"))
+ out[REG_PLATFORM] = 0x0001;
+ }
}
}
--
2.6.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v6 11/15] eal/arm: rwlock support for ARM
2015-11-02 23:47 [PATCH v6 00/15] Support ARMv7 architecture Jan Viktorin
` (9 preceding siblings ...)
2015-11-02 23:47 ` [PATCH v6 10/15] eal/arm: detect arm architecture in cpu flags Jan Viktorin
@ 2015-11-02 23:47 ` Jan Viktorin
2015-11-02 23:47 ` [PATCH v6 12/15] eal/arm: add very incomplete rte_vect Jan Viktorin
` (5 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Jan Viktorin @ 2015-11-02 23:47 UTC (permalink / raw)
To: david.marchand, David Hunt, Thomas Monjalon, Jerin Jacob; +Cc: dev
Just a copy from PPC.
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
---
.../common/include/arch/arm/rte_rwlock.h | 40 ++++++++++++++++++++++
1 file changed, 40 insertions(+)
create mode 100644 lib/librte_eal/common/include/arch/arm/rte_rwlock.h
diff --git a/lib/librte_eal/common/include/arch/arm/rte_rwlock.h b/lib/librte_eal/common/include/arch/arm/rte_rwlock.h
new file mode 100644
index 0000000..664bec8
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm/rte_rwlock.h
@@ -0,0 +1,40 @@
+/* copied from ppc_64 */
+
+#ifndef _RTE_RWLOCK_ARM_H_
+#define _RTE_RWLOCK_ARM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_rwlock.h"
+
+static inline void
+rte_rwlock_read_lock_tm(rte_rwlock_t *rwl)
+{
+ rte_rwlock_read_lock(rwl);
+}
+
+static inline void
+rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl)
+{
+ rte_rwlock_read_unlock(rwl);
+}
+
+static inline void
+rte_rwlock_write_lock_tm(rte_rwlock_t *rwl)
+{
+ rte_rwlock_write_lock(rwl);
+}
+
+static inline void
+rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl)
+{
+ rte_rwlock_write_unlock(rwl);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_RWLOCK_ARM_H_ */
--
2.6.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v6 12/15] eal/arm: add very incomplete rte_vect
2015-11-02 23:47 [PATCH v6 00/15] Support ARMv7 architecture Jan Viktorin
` (10 preceding siblings ...)
2015-11-02 23:47 ` [PATCH v6 11/15] eal/arm: rwlock support for ARM Jan Viktorin
@ 2015-11-02 23:47 ` Jan Viktorin
2015-11-02 23:47 ` [PATCH v6 13/15] gcc/arm: avoid alignment errors to break build Jan Viktorin
` (4 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Jan Viktorin @ 2015-11-02 23:47 UTC (permalink / raw)
To: david.marchand, David Hunt, Thomas Monjalon, Jerin Jacob; +Cc: dev
This patch does not map x86 SIMD operations to the ARM ones.
It just fills the necessary gap between the platforms to enable
compilation of libraries LPM (includes rte_vect.h, lpm_test needs
those SIMD functions) and ACL (includes rte_vect.h).
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
---
v4: checkpatch reports warning for the new typedef
---
lib/librte_eal/common/include/arch/arm/rte_vect.h | 84 +++++++++++++++++++++++
1 file changed, 84 insertions(+)
create mode 100644 lib/librte_eal/common/include/arch/arm/rte_vect.h
diff --git a/lib/librte_eal/common/include/arch/arm/rte_vect.h b/lib/librte_eal/common/include/arch/arm/rte_vect.h
new file mode 100644
index 0000000..7d5de97
--- /dev/null
+++ b/lib/librte_eal/common/include/arch/arm/rte_vect.h
@@ -0,0 +1,84 @@
+/*-
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of RehiveTech nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_VECT_ARM_H_
+#define _RTE_VECT_ARM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define XMM_SIZE 16
+#define XMM_MASK (XMM_MASK - 1)
+
+typedef struct {
+ union uint128 {
+ uint8_t uint8[16];
+ uint32_t uint32[4];
+ } val;
+} __m128i;
+
+static inline __m128i
+_mm_set_epi32(uint32_t v0, uint32_t v1, uint32_t v2, uint32_t v3)
+{
+ __m128i res;
+
+ res.val.uint32[0] = v0;
+ res.val.uint32[1] = v1;
+ res.val.uint32[2] = v2;
+ res.val.uint32[3] = v3;
+ return res;
+}
+
+static inline __m128i
+_mm_loadu_si128(__m128i *v)
+{
+ __m128i res;
+
+ res = *v;
+ return res;
+}
+
+static inline __m128i
+_mm_load_si128(__m128i *v)
+{
+ __m128i res;
+
+ res = *v;
+ return res;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--
2.6.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v6 13/15] gcc/arm: avoid alignment errors to break build
2015-11-02 23:47 [PATCH v6 00/15] Support ARMv7 architecture Jan Viktorin
` (11 preceding siblings ...)
2015-11-02 23:47 ` [PATCH v6 12/15] eal/arm: add very incomplete rte_vect Jan Viktorin
@ 2015-11-02 23:47 ` Jan Viktorin
2015-11-02 23:47 ` [PATCH v6 14/15] mk: Introduce ARMv7 architecture Jan Viktorin
` (3 subsequent siblings)
16 siblings, 0 replies; 26+ messages in thread
From: Jan Viktorin @ 2015-11-02 23:47 UTC (permalink / raw)
To: david.marchand, David Hunt, Thomas Monjalon, Jerin Jacob
Cc: dev, Vlastimil Kosar
There several issues with alignment when compiling for ARMv7.
They are not considered to be fatal (ARMv7 supports unaligned
access of 32b words), so we just leave them as warnings. They
should be solved later, however.
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
Signed-off-by: Vlastimil Kosar <kosar@rehivetech.com>
---
v4: restrict -Wno-error to the cast-align only
---
mk/toolchain/gcc/rte.vars.mk | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/mk/toolchain/gcc/rte.vars.mk b/mk/toolchain/gcc/rte.vars.mk
index 0f51c66..c2c5255 100644
--- a/mk/toolchain/gcc/rte.vars.mk
+++ b/mk/toolchain/gcc/rte.vars.mk
@@ -77,6 +77,12 @@ WERROR_FLAGS += -Wcast-align -Wnested-externs -Wcast-qual
WERROR_FLAGS += -Wformat-nonliteral -Wformat-security
WERROR_FLAGS += -Wundef -Wwrite-strings
+# There are many issues reported for ARMv7 architecture
+# which are not necessarily fatal. Report as warnings.
+ifeq ($(CONFIG_RTE_ARCH_ARMv7),y)
+WERROR_FLAGS += -Wno-error=cast-align
+endif
+
# process cpu flags
include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.toolchain-compat.mk
--
2.6.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH v6 14/15] mk: Introduce ARMv7 architecture
2015-11-02 23:47 [PATCH v6 00/15] Support ARMv7 architecture Jan Viktorin
` (12 preceding siblings ...)
2015-11-02 23:47 ` [PATCH v6 13/15] gcc/arm: avoid alignment errors to break build Jan Viktorin
@ 2015-11-02 23:47 ` Jan Viktorin
2015-11-03 10:16 ` Hunt, David
2015-11-02 23:47 ` [PATCH v6 15/15] maintainers: claim responsibility for ARMv7 Jan Viktorin
` (2 subsequent siblings)
16 siblings, 1 reply; 26+ messages in thread
From: Jan Viktorin @ 2015-11-02 23:47 UTC (permalink / raw)
To: david.marchand, David Hunt, Thomas Monjalon, Jerin Jacob
Cc: Vlastimil Kosar, dev
From: Vlastimil Kosar <kosar@rehivetech.com>
Make DPDK run on ARMv7-A architecture. This patch assumes
ARM Cortex-A9. However, it is known to be working on Cortex-A7
and Cortex-A15.
Signed-off-by: Vlastimil Kosar <kosar@rehivetech.com>
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
---
v2:
* the -mtune parameter of GCC is configurable now
* the -mfpu=neon can be turned off
v3: XMM_SIZE is defined in rte_vect.h in a following patch
v4:
* update release notes for 2.2
* get rid of CONFIG_RTE_BITMAP_OPTIMIZATIONS=0 setting
* rename arm defconfig: "armv7-a" -> "arvm7a"
* disable pipeline and table modules unless lpm is fixed
---
config/defconfig_arm-armv7a-linuxapp-gcc | 76 ++++++++++++++++++++++++++++++++
doc/guides/rel_notes/release_2_2.rst | 5 +++
mk/arch/arm/rte.vars.mk | 39 ++++++++++++++++
mk/machine/armv7-a/rte.vars.mk | 67 ++++++++++++++++++++++++++++
4 files changed, 187 insertions(+)
create mode 100644 config/defconfig_arm-armv7a-linuxapp-gcc
create mode 100644 mk/arch/arm/rte.vars.mk
create mode 100644 mk/machine/armv7-a/rte.vars.mk
diff --git a/config/defconfig_arm-armv7a-linuxapp-gcc b/config/defconfig_arm-armv7a-linuxapp-gcc
new file mode 100644
index 0000000..82143af
--- /dev/null
+++ b/config/defconfig_arm-armv7a-linuxapp-gcc
@@ -0,0 +1,76 @@
+# BSD LICENSE
+#
+# Copyright (C) 2015 RehiveTech. All right reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# * Neither the name of RehiveTech nor the names of its
+# contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include "common_linuxapp"
+
+CONFIG_RTE_MACHINE="armv7-a"
+
+CONFIG_RTE_ARCH="arm"
+CONFIG_RTE_ARCH_ARM=y
+CONFIG_RTE_ARCH_ARMv7=y
+CONFIG_RTE_ARCH_ARM_TUNE="cortex-a9"
+CONFIG_RTE_ARCH_ARM_NEON=y
+
+CONFIG_RTE_FORCE_INTRINSICS=y
+
+CONFIG_RTE_TOOLCHAIN="gcc"
+CONFIG_RTE_TOOLCHAIN_GCC=y
+
+# ARM doesn't have support for vmware TSC map
+CONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=n
+
+# KNI is not supported on 32-bit
+CONFIG_RTE_LIBRTE_KNI=n
+
+# PCI is usually not used on ARM
+CONFIG_RTE_EAL_IGB_UIO=n
+
+# fails to compile on ARM
+CONFIG_RTE_LIBRTE_ACL=n
+CONFIG_RTE_LIBRTE_LPM=n
+CONFIG_RTE_LIBRTE_TABLE=n
+CONFIG_RTE_LIBRTE_PIPELINE=n
+
+# cannot use those on ARM
+CONFIG_RTE_KNI_KMOD=n
+CONFIG_RTE_LIBRTE_EM_PMD=n
+CONFIG_RTE_LIBRTE_IGB_PMD=n
+CONFIG_RTE_LIBRTE_CXGBE_PMD=n
+CONFIG_RTE_LIBRTE_E1000_PMD=n
+CONFIG_RTE_LIBRTE_ENIC_PMD=n
+CONFIG_RTE_LIBRTE_FM10K_PMD=n
+CONFIG_RTE_LIBRTE_I40E_PMD=n
+CONFIG_RTE_LIBRTE_IXGBE_PMD=n
+CONFIG_RTE_LIBRTE_MLX4_PMD=n
+CONFIG_RTE_LIBRTE_MPIPE_PMD=n
+CONFIG_RTE_LIBRTE_VIRTIO_PMD=n
+CONFIG_RTE_LIBRTE_VMXNET3_PMD=n
+CONFIG_RTE_LIBRTE_PMD_XENVIRT=n
+CONFIG_RTE_LIBRTE_PMD_BNX2X=n
diff --git a/doc/guides/rel_notes/release_2_2.rst b/doc/guides/rel_notes/release_2_2.rst
index be6f827..43a3a3c 100644
--- a/doc/guides/rel_notes/release_2_2.rst
+++ b/doc/guides/rel_notes/release_2_2.rst
@@ -23,6 +23,11 @@ New Features
* **Added vhost-user multiple queue support.**
+* **Introduce ARMv7 architecture**
+
+ It is now possible to build DPDK for the ARMv7 platform and test with
+ virtual PMD drivers.
+
Resolved Issues
---------------
diff --git a/mk/arch/arm/rte.vars.mk b/mk/arch/arm/rte.vars.mk
new file mode 100644
index 0000000..df0c043
--- /dev/null
+++ b/mk/arch/arm/rte.vars.mk
@@ -0,0 +1,39 @@
+# BSD LICENSE
+#
+# Copyright (C) 2015 RehiveTech. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# * Neither the name of RehiveTech nor the names of its
+# contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+ARCH ?= arm
+CROSS ?=
+
+CPU_CFLAGS ?= -marm -DRTE_CACHE_LINE_SIZE=64 -munaligned-access
+CPU_LDFLAGS ?=
+CPU_ASFLAGS ?= -felf
+
+export ARCH CROSS CPU_CFLAGS CPU_LDFLAGS CPU_ASFLAGS
diff --git a/mk/machine/armv7-a/rte.vars.mk b/mk/machine/armv7-a/rte.vars.mk
new file mode 100644
index 0000000..48d3979
--- /dev/null
+++ b/mk/machine/armv7-a/rte.vars.mk
@@ -0,0 +1,67 @@
+# BSD LICENSE
+#
+# Copyright (C) 2015 RehiveTech. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# * Neither the name of RehiveTech nor the names of its
+# contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#
+# machine:
+#
+# - can define ARCH variable (overridden by cmdline value)
+# - can define CROSS variable (overridden by cmdline value)
+# - define MACHINE_CFLAGS variable (overridden by cmdline value)
+# - define MACHINE_LDFLAGS variable (overridden by cmdline value)
+# - define MACHINE_ASFLAGS variable (overridden by cmdline value)
+# - can define CPU_CFLAGS variable (overridden by cmdline value) that
+# overrides the one defined in arch.
+# - can define CPU_LDFLAGS variable (overridden by cmdline value) that
+# overrides the one defined in arch.
+# - can define CPU_ASFLAGS variable (overridden by cmdline value) that
+# overrides the one defined in arch.
+# - may override any previously defined variable
+#
+
+# ARCH =
+# CROSS =
+# MACHINE_CFLAGS =
+# MACHINE_LDFLAGS =
+# MACHINE_ASFLAGS =
+# CPU_CFLAGS =
+# CPU_LDFLAGS =
+# CPU_ASFLAGS =
+
+CPU_CFLAGS += -mfloat-abi=softfp
+
+MACHINE_CFLAGS += -march=armv7-a
+
+ifdef CONFIG_RTE_ARCH_ARM_TUNE
+MACHINE_CFLAGS += -mtune=$(CONFIG_RTE_ARCH_ARM_TUNE)
+endif
+
+ifeq ($(CONFIG_RTE_ARCH_ARM_NEON),y)
+MACHINE_CFLAGS += -mfpu=neon
+endif
--
2.6.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH v6 14/15] mk: Introduce ARMv7 architecture
2015-11-02 23:47 ` [PATCH v6 14/15] mk: Introduce ARMv7 architecture Jan Viktorin
@ 2015-11-03 10:16 ` Hunt, David
2015-11-03 10:24 ` Bruce Richardson
2015-11-03 10:27 ` Jan Viktorin
0 siblings, 2 replies; 26+ messages in thread
From: Hunt, David @ 2015-11-03 10:16 UTC (permalink / raw)
To: Jan Viktorin, david.marchand, Thomas Monjalon, Jerin Jacob
Cc: Vlastimil Kosar, dev
On 02/11/2015 23:47, Jan Viktorin wrote:
--snip--
> diff --git a/doc/guides/rel_notes/release_2_2.rst b/doc/guides/rel_notes/release_2_2.rst
> index be6f827..43a3a3c 100644
> --- a/doc/guides/rel_notes/release_2_2.rst
> +++ b/doc/guides/rel_notes/release_2_2.rst
> @@ -23,6 +23,11 @@ New Features
>
> * **Added vhost-user multiple queue support.**
Jan,
There's a small issue here. To apply cleanly on the latest head, this
line needs to be
* **Added port hotplug support to xenvirt.**
Rgds,
Dave.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v6 14/15] mk: Introduce ARMv7 architecture
2015-11-03 10:16 ` Hunt, David
@ 2015-11-03 10:24 ` Bruce Richardson
2015-11-03 11:18 ` Thomas Monjalon
2015-11-03 10:27 ` Jan Viktorin
1 sibling, 1 reply; 26+ messages in thread
From: Bruce Richardson @ 2015-11-03 10:24 UTC (permalink / raw)
To: Hunt, David; +Cc: Vlastimil Kosar, dev
On Tue, Nov 03, 2015 at 10:16:23AM +0000, Hunt, David wrote:
> On 02/11/2015 23:47, Jan Viktorin wrote:
> --snip--
> >diff --git a/doc/guides/rel_notes/release_2_2.rst b/doc/guides/rel_notes/release_2_2.rst
> >index be6f827..43a3a3c 100644
> >--- a/doc/guides/rel_notes/release_2_2.rst
> >+++ b/doc/guides/rel_notes/release_2_2.rst
> >@@ -23,6 +23,11 @@ New Features
> >
> > * **Added vhost-user multiple queue support.**
>
> Jan,
> There's a small issue here. To apply cleanly on the latest head, this line
> needs to be
> * **Added port hotplug support to xenvirt.**
>
> Rgds,
> Dave.
The release notes "New Feature" section is always one that causes conflicts on
apply of patches. I think Thomas is ok to handle that on apply, or else we'd all
be constantly rebasing.
For 2.3 we maybe need to come up with a new way to modify this to make applying
patches easier. For example, can the new features section just be pulled from
a set of individual single-bullet-point files inside a directory? Then each new
feature just drops its addition in a new file and there are no conflicts. Can
rst be used to pull into a doc a directory: e.g. "new_features/*.rst"?
/Bruce
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v6 14/15] mk: Introduce ARMv7 architecture
2015-11-03 10:24 ` Bruce Richardson
@ 2015-11-03 11:18 ` Thomas Monjalon
0 siblings, 0 replies; 26+ messages in thread
From: Thomas Monjalon @ 2015-11-03 11:18 UTC (permalink / raw)
To: Bruce Richardson; +Cc: Vlastimil Kosar, dev
2015-11-03 10:24, Bruce Richardson:
> The release notes "New Feature" section is always one that causes conflicts on
> apply of patches. I think Thomas is ok to handle that on apply, or else we'd all
> be constantly rebasing.
Yes, it is a common conflict managed when applying.
> For 2.3 we maybe need to come up with a new way to modify this to make applying
> patches easier. For example, can the new features section just be pulled from
> a set of individual single-bullet-point files inside a directory? Then each new
> feature just drops its addition in a new file and there are no conflicts. Can
> rst be used to pull into a doc a directory: e.g. "new_features/*.rst"?
Good idea.
But we should try to have some automatic sorting in the list.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v6 14/15] mk: Introduce ARMv7 architecture
2015-11-03 10:16 ` Hunt, David
2015-11-03 10:24 ` Bruce Richardson
@ 2015-11-03 10:27 ` Jan Viktorin
2015-11-03 11:08 ` Hunt, David
1 sibling, 1 reply; 26+ messages in thread
From: Jan Viktorin @ 2015-11-03 10:27 UTC (permalink / raw)
To: Hunt, David; +Cc: Vlastimil Kosar, dev
On Tue, 3 Nov 2015 10:16:23 +0000
"Hunt, David" <david.hunt@intel.com> wrote:
> On 02/11/2015 23:47, Jan Viktorin wrote:
> --snip--
> > diff --git a/doc/guides/rel_notes/release_2_2.rst b/doc/guides/rel_notes/release_2_2.rst
> > index be6f827..43a3a3c 100644
> > --- a/doc/guides/rel_notes/release_2_2.rst
> > +++ b/doc/guides/rel_notes/release_2_2.rst
> > @@ -23,6 +23,11 @@ New Features
> >
> > * **Added vhost-user multiple queue support.**
>
> Jan,
> There's a small issue here. To apply cleanly on the latest head, this
> line needs to be
> * **Added port hotplug support to xenvirt.**
Yes, the original v6 patchset was rebased on 82fb70207 (as stated in
the cover letter). I've force pushed an update (as resubmitting all the
series just due to this trivial conflict seems to be meaningless to me):
You can pull the changes from 647d1eaf758b97311ab3692770acac72144eea87:
https://github.com/RehiveTech/dpdk.git arm-support-v6
since commit :
i40evf: support AQ based RSS config (2015-11-03 11:13:32 +0100)
up to 46dcc0857d7a5c760e6ec991906619351618f290:
maintainers: claim responsibility for ARMv7 (2015-11-03 11:18:56 +0100)
>
> Rgds,
> Dave.
--
Jan Viktorin E-mail: Viktorin@RehiveTech.com
System Architect Web: www.RehiveTech.com
RehiveTech
Brno, Czech Republic
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v6 14/15] mk: Introduce ARMv7 architecture
2015-11-03 10:27 ` Jan Viktorin
@ 2015-11-03 11:08 ` Hunt, David
0 siblings, 0 replies; 26+ messages in thread
From: Hunt, David @ 2015-11-03 11:08 UTC (permalink / raw)
To: Jan Viktorin; +Cc: Vlastimil Kosar, dev
On 03/11/2015 10:27, Jan Viktorin wrote:
> On Tue, 3 Nov 2015 10:16:23 +0000
> "Hunt, David" <david.hunt@intel.com> wrote:
>
>> On 02/11/2015 23:47, Jan Viktorin wrote:
>> --snip--
>>> diff --git a/doc/guides/rel_notes/release_2_2.rst b/doc/guides/rel_notes/release_2_2.rst
>>> index be6f827..43a3a3c 100644
>>> --- a/doc/guides/rel_notes/release_2_2.rst
>>> +++ b/doc/guides/rel_notes/release_2_2.rst
>>> @@ -23,6 +23,11 @@ New Features
>>>
>>> * **Added vhost-user multiple queue support.**
>>
>> Jan,
>> There's a small issue here. To apply cleanly on the latest head, this
>> line needs to be
>> * **Added port hotplug support to xenvirt.**
>
> Yes, the original v6 patchset was rebased on 82fb70207 (as stated in
> the cover letter). I've force pushed an update (as resubmitting all the
> series just due to this trivial conflict seems to be meaningless to me):
Agreed, just noting for the future :)
Dave
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v6 15/15] maintainers: claim responsibility for ARMv7
2015-11-02 23:47 [PATCH v6 00/15] Support ARMv7 architecture Jan Viktorin
` (13 preceding siblings ...)
2015-11-02 23:47 ` [PATCH v6 14/15] mk: Introduce ARMv7 architecture Jan Viktorin
@ 2015-11-02 23:47 ` Jan Viktorin
2015-11-03 4:49 ` [PATCH v6 00/15] Support ARMv7 architecture Jerin Jacob
2015-11-16 21:33 ` David Marchand
16 siblings, 0 replies; 26+ messages in thread
From: Jan Viktorin @ 2015-11-02 23:47 UTC (permalink / raw)
To: david.marchand, David Hunt, Thomas Monjalon, Jerin Jacob; +Cc: dev
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
---
MAINTAINERS | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 080a8e8..a8933eb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -124,6 +124,10 @@ IBM POWER
M: Chao Zhu <chaozhu@linux.vnet.ibm.com>
F: lib/librte_eal/common/include/arch/ppc_64/
+ARM v7
+M: Jan Viktorin <viktorin@rehivetech.com>
+F: lib/librte_eal/common/include/arch/arm/
+
Intel x86
M: Bruce Richardson <bruce.richardson@intel.com>
M: Konstantin Ananyev <konstantin.ananyev@intel.com>
--
2.6.2
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH v6 00/15] Support ARMv7 architecture
2015-11-02 23:47 [PATCH v6 00/15] Support ARMv7 architecture Jan Viktorin
` (14 preceding siblings ...)
2015-11-02 23:47 ` [PATCH v6 15/15] maintainers: claim responsibility for ARMv7 Jan Viktorin
@ 2015-11-03 4:49 ` Jerin Jacob
2015-11-03 11:33 ` Hunt, David
2015-11-16 21:33 ` David Marchand
16 siblings, 1 reply; 26+ messages in thread
From: Jerin Jacob @ 2015-11-03 4:49 UTC (permalink / raw)
To: Jan Viktorin; +Cc: dev
On Tue, Nov 03, 2015 at 12:47:13AM +0100, Jan Viktorin wrote:
> Hello DPDK community,
>
> ARMv7 again, changes:
>
> * removed unnecessary code in the #ifndef RTE_FORCE_INTRINSICS .. #endif (atomic, spinlock, byteorder)
> * more splitting of headers to have 32/64 bit variants (atomic, cpuflags)
> * fixed cpuflags AT_PLATFORM
Thanks Jan, Dave .
I will rework on the arm64 support based on this version.
>
> Other details in the individual commits as usual.
>
> ---
>
> You can pull the changes from
>
> https://github.com/RehiveTech/dpdk.git arm-support-v6
>
> since commit 82fb702077f67585d64a07de0080e5cb6a924a72:
>
> ixgbe: support new flow director modes for X550 (2015-10-29 00:06:01 +0100)
>
> up to 9d686e4bd972dea2f9baef0a419a57a1c037d26e:
>
> maintainers: claim responsibility for ARMv7 (2015-11-02 23:34:14 +0100)
>
> ---
>
> Jan Viktorin (7):
> eal/arm: implement rdtsc by PMU or clock_gettime
> eal/arm: use vector memcpy only when NEON is enabled
> eal/arm: detect arm architecture in cpu flags
> eal/arm: rwlock support for ARM
> eal/arm: add very incomplete rte_vect
> gcc/arm: avoid alignment errors to break build
> maintainers: claim responsibility for ARMv7
>
> Vlastimil Kosar (8):
> eal/arm: atomic operations for ARM
> eal/arm: byte order operations for ARM
> eal/arm: cpu cycle operations for ARM
> eal/arm: prefetch operations for ARM
> eal/arm: spinlock operations for ARM (without HTM)
> eal/arm: vector memcpy for ARM
> eal/arm: cpu flag checks for ARM
> mk: Introduce ARMv7 architecture
>
> MAINTAINERS | 4 +
> app/test/test_cpuflags.c | 5 +
> config/defconfig_arm-armv7a-linuxapp-gcc | 76 +++++
> doc/guides/rel_notes/release_2_2.rst | 5 +
> .../common/include/arch/arm/rte_atomic.h | 38 +++
> .../common/include/arch/arm/rte_atomic_32.h | 74 +++++
> .../common/include/arch/arm/rte_byteorder.h | 107 +++++++
> .../common/include/arch/arm/rte_cpuflags.h | 38 +++
> .../common/include/arch/arm/rte_cpuflags_32.h | 189 ++++++++++++
> .../common/include/arch/arm/rte_cycles.h | 38 +++
> .../common/include/arch/arm/rte_cycles_32.h | 121 ++++++++
> .../common/include/arch/arm/rte_memcpy.h | 38 +++
> .../common/include/arch/arm/rte_memcpy_32.h | 334 +++++++++++++++++++++
> .../common/include/arch/arm/rte_prefetch.h | 38 +++
> .../common/include/arch/arm/rte_prefetch_32.h | 61 ++++
> .../common/include/arch/arm/rte_rwlock.h | 40 +++
> .../common/include/arch/arm/rte_spinlock.h | 92 ++++++
> lib/librte_eal/common/include/arch/arm/rte_vect.h | 84 ++++++
> mk/arch/arm/rte.vars.mk | 39 +++
> mk/machine/armv7-a/rte.vars.mk | 67 +++++
> mk/rte.cpuflags.mk | 6 +
> mk/toolchain/gcc/rte.vars.mk | 6 +
> 22 files changed, 1500 insertions(+)
> create mode 100644 config/defconfig_arm-armv7a-linuxapp-gcc
> create mode 100644 lib/librte_eal/common/include/arch/arm/rte_atomic.h
> create mode 100644 lib/librte_eal/common/include/arch/arm/rte_atomic_32.h
> create mode 100644 lib/librte_eal/common/include/arch/arm/rte_byteorder.h
> create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cpuflags.h
> create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cpuflags_32.h
> create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cycles.h
> create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cycles_32.h
> create mode 100644 lib/librte_eal/common/include/arch/arm/rte_memcpy.h
> create mode 100644 lib/librte_eal/common/include/arch/arm/rte_memcpy_32.h
> create mode 100644 lib/librte_eal/common/include/arch/arm/rte_prefetch.h
> create mode 100644 lib/librte_eal/common/include/arch/arm/rte_prefetch_32.h
> create mode 100644 lib/librte_eal/common/include/arch/arm/rte_rwlock.h
> create mode 100644 lib/librte_eal/common/include/arch/arm/rte_spinlock.h
> create mode 100644 lib/librte_eal/common/include/arch/arm/rte_vect.h
> create mode 100644 mk/arch/arm/rte.vars.mk
> create mode 100644 mk/machine/armv7-a/rte.vars.mk
>
> --
> 2.6.2
>
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH v6 00/15] Support ARMv7 architecture
2015-11-03 4:49 ` [PATCH v6 00/15] Support ARMv7 architecture Jerin Jacob
@ 2015-11-03 11:33 ` Hunt, David
2015-11-03 12:32 ` Jacob, Jerin
0 siblings, 1 reply; 26+ messages in thread
From: Hunt, David @ 2015-11-03 11:33 UTC (permalink / raw)
To: Jerin Jacob, Jan Viktorin; +Cc: dev
On 03/11/2015 04:49, Jerin Jacob wrote:
> On Tue, Nov 03, 2015 at 12:47:13AM +0100, Jan Viktorin wrote:
>> Hello DPDK community,
>>
>> ARMv7 again, changes:
>>
>> * removed unnecessary code in the #ifndef RTE_FORCE_INTRINSICS .. #endif (atomic, spinlock, byteorder)
>> * more splitting of headers to have 32/64 bit variants (atomic, cpuflags)
>> * fixed cpuflags AT_PLATFORM
>
> Thanks Jan, Dave .
> I will rework on the arm64 support based on this version.
Jerin,
I've got an updated ARMv8 patchset almost ready based on Jan's latest
patchset (v6). Will I post it to the list? I suspect that your patchset
will be the preferred option for acceptance into DPDK, but there may be
one or two snippets of code worth merging together for the final patchset.
Rgds,
Dave.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v6 00/15] Support ARMv7 architecture
2015-11-03 11:33 ` Hunt, David
@ 2015-11-03 12:32 ` Jacob, Jerin
0 siblings, 0 replies; 26+ messages in thread
From: Jacob, Jerin @ 2015-11-03 12:32 UTC (permalink / raw)
To: Hunt, David, Jan Viktorin; +Cc: dev
I will be posting the new version with in a hour.
Thanks,
Jerin
________________________________________
From: Hunt, David <david.hunt@intel.com>
Sent: Tuesday, November 3, 2015 5:03 PM
To: Jacob, Jerin; Jan Viktorin
Cc: david.marchand@6wind.com; Thomas Monjalon; dev@dpdk.org
Subject: Re: [PATCH v6 00/15] Support ARMv7 architecture
On 03/11/2015 04:49, Jerin Jacob wrote:
> On Tue, Nov 03, 2015 at 12:47:13AM +0100, Jan Viktorin wrote:
>> Hello DPDK community,
>>
>> ARMv7 again, changes:
>>
>> * removed unnecessary code in the #ifndef RTE_FORCE_INTRINSICS .. #endif (atomic, spinlock, byteorder)
>> * more splitting of headers to have 32/64 bit variants (atomic, cpuflags)
>> * fixed cpuflags AT_PLATFORM
>
> Thanks Jan, Dave .
> I will rework on the arm64 support based on this version.
Jerin,
I've got an updated ARMv8 patchset almost ready based on Jan's latest
patchset (v6). Will I post it to the list? I suspect that your patchset
will be the preferred option for acceptance into DPDK, but there may be
one or two snippets of code worth merging together for the final patchset.
Rgds,
Dave.
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v6 00/15] Support ARMv7 architecture
2015-11-02 23:47 [PATCH v6 00/15] Support ARMv7 architecture Jan Viktorin
` (15 preceding siblings ...)
2015-11-03 4:49 ` [PATCH v6 00/15] Support ARMv7 architecture Jerin Jacob
@ 2015-11-16 21:33 ` David Marchand
2015-11-18 21:45 ` Thomas Monjalon
16 siblings, 1 reply; 26+ messages in thread
From: David Marchand @ 2015-11-16 21:33 UTC (permalink / raw)
To: Jan Viktorin; +Cc: dev
Hello,
On Tue, Nov 3, 2015 at 12:47 AM, Jan Viktorin <viktorin@rehivetech.com>
wrote:
> Hello DPDK community,
>
> ARMv7 again, changes:
>
> * removed unnecessary code in the #ifndef RTE_FORCE_INTRINSICS .. #endif
> (atomic, spinlock, byteorder)
> * more splitting of headers to have 32/64 bit variants (atomic, cpuflags)
> * fixed cpuflags AT_PLATFORM
>
> Other details in the individual commits as usual.
>
> ---
> [snip]
> ---
>
> Jan Viktorin (7):
> eal/arm: implement rdtsc by PMU or clock_gettime
> eal/arm: use vector memcpy only when NEON is enabled
> eal/arm: detect arm architecture in cpu flags
> eal/arm: rwlock support for ARM
> eal/arm: add very incomplete rte_vect
> gcc/arm: avoid alignment errors to break build
> maintainers: claim responsibility for ARMv7
>
> Vlastimil Kosar (8):
> eal/arm: atomic operations for ARM
> eal/arm: byte order operations for ARM
> eal/arm: cpu cycle operations for ARM
> eal/arm: prefetch operations for ARM
> eal/arm: spinlock operations for ARM (without HTM)
> eal/arm: vector memcpy for ARM
> eal/arm: cpu flag checks for ARM
> mk: Introduce ARMv7 architecture
>
>
Looks good to me.
Acked-by: David Marchand <david.marchand@6wind.com>
Thanks Jan.
--
David Marchand
^ permalink raw reply [flat|nested] 26+ messages in thread* Re: [PATCH v6 00/15] Support ARMv7 architecture
2015-11-16 21:33 ` David Marchand
@ 2015-11-18 21:45 ` Thomas Monjalon
0 siblings, 0 replies; 26+ messages in thread
From: Thomas Monjalon @ 2015-11-18 21:45 UTC (permalink / raw)
To: Jan Viktorin; +Cc: dev
> > Jan Viktorin (7):
> > eal/arm: implement rdtsc by PMU or clock_gettime
> > eal/arm: use vector memcpy only when NEON is enabled
> > eal/arm: detect arm architecture in cpu flags
> > eal/arm: rwlock support for ARM
> > eal/arm: add very incomplete rte_vect
> > gcc/arm: avoid alignment errors to break build
> > maintainers: claim responsibility for ARMv7
> >
> > Vlastimil Kosar (8):
> > eal/arm: atomic operations for ARM
> > eal/arm: byte order operations for ARM
> > eal/arm: cpu cycle operations for ARM
> > eal/arm: prefetch operations for ARM
> > eal/arm: spinlock operations for ARM (without HTM)
> > eal/arm: vector memcpy for ARM
> > eal/arm: cpu flag checks for ARM
> > mk: Introduce ARMv7 architecture
> >
> >
> Looks good to me.
> Acked-by: David Marchand <david.marchand@6wind.com>
>
> Thanks Jan.
Applied, thanks
The rte_vect patch is squashed/removed because Jerin's patch replace it.
^ permalink raw reply [flat|nested] 26+ messages in thread