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From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>,
	Mika Kuoppala <mika.kuoppala@intel.com>
Subject: [PATCH 07/10] drm/i915/gen9: simplify DC toggling code
Date: Wed,  4 Nov 2015 19:24:16 +0200	[thread overview]
Message-ID: <1446657859-9598-8-git-send-email-imre.deak@intel.com> (raw)
In-Reply-To: <1446657859-9598-1-git-send-email-imre.deak@intel.com>

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h         |  1 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 66 ++++++++++++++-------------------
 2 files changed, 29 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c103f8d..e6d88f5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7491,6 +7491,7 @@ enum skl_disp_power_wells {
 
 /* GEN9 DC */
 #define DC_STATE_EN			0x45504
+#define  DC_STATE_DISABLE		0
 #define  DC_STATE_EN_UPTO_DC5		(1<<0)
 #define  DC_STATE_EN_DC9		(1<<3)
 #define  DC_STATE_EN_UPTO_DC6		(2<<0)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b9a0493..f5fb003 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -401,32 +401,43 @@ static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 	  */
 }
 
+static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
+{
+	uint32_t val;
+	uint32_t mask;
+
+	mask = DC_STATE_EN_UPTO_DC5;
+	if (IS_BROXTON(dev_priv))
+		mask |= DC_STATE_EN_DC9;
+	else
+		mask |= DC_STATE_EN_UPTO_DC6;
+
+	WARN_ON_ONCE(state & ~mask);
+
+	val = I915_READ(DC_STATE_EN);
+	DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", val & mask, state);
+	val &= ~mask;
+	val |= state;
+	I915_WRITE(DC_STATE_EN, val);
+	POSTING_READ(DC_STATE_EN);
+}
+
 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 {
-	uint32_t val;
-
 	assert_can_enable_dc9(dev_priv);
 
 	DRM_DEBUG_KMS("Enabling DC9\n");
 
-	val = I915_READ(DC_STATE_EN);
-	val |= DC_STATE_EN_DC9;
-	I915_WRITE(DC_STATE_EN, val);
-	POSTING_READ(DC_STATE_EN);
+	gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 }
 
 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 {
-	uint32_t val;
-
 	assert_can_disable_dc9(dev_priv);
 
 	DRM_DEBUG_KMS("Disabling DC9\n");
 
-	val = I915_READ(DC_STATE_EN);
-	val &= ~DC_STATE_EN_DC9;
-	I915_WRITE(DC_STATE_EN, val);
-	POSTING_READ(DC_STATE_EN);
+	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 }
 
 static void gen9_set_dc_state_debugmask_memory_up(
@@ -487,33 +498,22 @@ static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
 
 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 {
-	uint32_t val;
-
 	assert_can_enable_dc5(dev_priv);
 
 	DRM_DEBUG_KMS("Enabling DC5\n");
 
 	gen9_set_dc_state_debugmask_memory_up(dev_priv);
 
-	val = I915_READ(DC_STATE_EN);
-	val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
-	val |= DC_STATE_EN_UPTO_DC5;
-	I915_WRITE(DC_STATE_EN, val);
-	POSTING_READ(DC_STATE_EN);
+	gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 }
 
 static void gen9_disable_dc5(struct drm_i915_private *dev_priv)
 {
-	uint32_t val;
-
 	assert_can_disable_dc5(dev_priv);
 
 	DRM_DEBUG_KMS("Disabling DC5\n");
 
-	val = I915_READ(DC_STATE_EN);
-	val &= ~DC_STATE_EN_UPTO_DC5;
-	I915_WRITE(DC_STATE_EN, val);
-	POSTING_READ(DC_STATE_EN);
+	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 }
 
 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
@@ -545,33 +545,23 @@ static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
 
 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 {
-	uint32_t val;
-
 	assert_can_enable_dc6(dev_priv);
 
 	DRM_DEBUG_KMS("Enabling DC6\n");
 
 	gen9_set_dc_state_debugmask_memory_up(dev_priv);
 
-	val = I915_READ(DC_STATE_EN);
-	val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK;
-	val |= DC_STATE_EN_UPTO_DC6;
-	I915_WRITE(DC_STATE_EN, val);
-	POSTING_READ(DC_STATE_EN);
+	gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
+
 }
 
 void skl_disable_dc6(struct drm_i915_private *dev_priv)
 {
-	uint32_t val;
-
 	assert_can_disable_dc6(dev_priv);
 
 	DRM_DEBUG_KMS("Disabling DC6\n");
 
-	val = I915_READ(DC_STATE_EN);
-	val &= ~DC_STATE_EN_UPTO_DC6;
-	I915_WRITE(DC_STATE_EN, val);
-	POSTING_READ(DC_STATE_EN);
+	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 }
 
 static void skl_set_power_well(struct drm_i915_private *dev_priv,
-- 
2.1.4

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  parent reply	other threads:[~2015-11-04 17:24 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-04 17:24 [PATCH 00/10] drm/i915/skl: fix display core init/uninit sequence Imre Deak
2015-11-04 17:24 ` [PATCH 01/10] drm/i915: fix the power well ID for always on wells Imre Deak
2015-11-12 13:34   ` Patrik Jakobsson
2015-11-12 13:39   ` Ville Syrjälä
2015-11-12 13:57     ` Imre Deak
2015-11-04 17:24 ` [PATCH 02/10] drm/i915: fix lookup_power_well for power wells without any domain Imre Deak
2015-11-12 13:36   ` Patrik Jakobsson
2015-11-04 17:24 ` [PATCH 03/10] drm/i915: Make turning on/off PW1 and Misc I/O part of the init/fini sequences Imre Deak
2015-11-12 13:49   ` Patrik Jakobsson
2015-11-17 19:19   ` Imre Deak
2015-11-04 17:24 ` [PATCH 04/10] drm/i915: rename intel_power_domains_resume to *_sync_hw Imre Deak
2015-11-12 13:53   ` Patrik Jakobsson
2015-11-04 17:24 ` [PATCH 05/10] drm/i915/skl: init/uninit display core as part of the HW power domain state Imre Deak
2015-11-13  9:02   ` Patrik Jakobsson
2015-11-17 15:33   ` [PATCH v2 " Imre Deak
2015-11-04 17:24 ` [PATCH 06/10] drm/i915/skl: don't toggle PW1 and MISC power wells on-demand Imre Deak
2015-11-13  9:31   ` Patrik Jakobsson
2015-11-04 17:24 ` Imre Deak [this message]
2015-11-13  9:48   ` [PATCH 07/10] drm/i915/gen9: simplify DC toggling code Patrik Jakobsson
2015-11-04 17:24 ` [PATCH 08/10] drm/i915/skl: disable DC states before display core init/uninit Imre Deak
2015-11-13  9:52   ` Patrik Jakobsson
2015-11-04 17:24 ` [PATCH 09/10] drm/i915/skl: make sure LCPLL is disabled when uniniting CDCLK Imre Deak
2015-11-13 10:11   ` Patrik Jakobsson
2015-11-04 17:24 ` [PATCH 10/10] drm/i915/skl: remove redundant DDI/IRQ reinitialization during PW1 enabling Imre Deak
2015-11-13 11:00   ` Patrik Jakobsson
2015-11-17 19:34 ` [PATCH 00/10] drm/i915/skl: fix display core init/uninit sequence Imre Deak

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