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From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>,
	Mika Kuoppala <mika.kuoppala@intel.com>
Subject: [PATCH 08/10] drm/i915/skl: disable DC states before display core init/uninit
Date: Wed,  4 Nov 2015 19:24:17 +0200	[thread overview]
Message-ID: <1446657859-9598-9-git-send-email-imre.deak@intel.com> (raw)
In-Reply-To: <1446657859-9598-1-git-send-email-imre.deak@intel.com>

We need to disable the DC states during display core init to sanitize
the HW state we inherit from the BIOS. We need to disable it during
display core uninit too, since the power well framework will leave it
enabled (since we get to the display core uninit step with all power
domains disabled already).

Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index f5fb003..3d500e1d 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1900,6 +1900,8 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 	uint32_t val;
 
+	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
 	/* enable PCH reset handshake */
 	val = I915_READ(HSW_NDE_RSTWRN_OPT);
 	I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
@@ -1921,6 +1923,8 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
 {
 	struct i915_power_domains *power_domains = &dev_priv->power_domains;
 
+	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
 	skl_uninit_cdclk(dev_priv);
 
 	/* The spec doesn't call for removing the reset handshake flag */
-- 
2.1.4

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  parent reply	other threads:[~2015-11-04 17:24 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-11-04 17:24 [PATCH 00/10] drm/i915/skl: fix display core init/uninit sequence Imre Deak
2015-11-04 17:24 ` [PATCH 01/10] drm/i915: fix the power well ID for always on wells Imre Deak
2015-11-12 13:34   ` Patrik Jakobsson
2015-11-12 13:39   ` Ville Syrjälä
2015-11-12 13:57     ` Imre Deak
2015-11-04 17:24 ` [PATCH 02/10] drm/i915: fix lookup_power_well for power wells without any domain Imre Deak
2015-11-12 13:36   ` Patrik Jakobsson
2015-11-04 17:24 ` [PATCH 03/10] drm/i915: Make turning on/off PW1 and Misc I/O part of the init/fini sequences Imre Deak
2015-11-12 13:49   ` Patrik Jakobsson
2015-11-17 19:19   ` Imre Deak
2015-11-04 17:24 ` [PATCH 04/10] drm/i915: rename intel_power_domains_resume to *_sync_hw Imre Deak
2015-11-12 13:53   ` Patrik Jakobsson
2015-11-04 17:24 ` [PATCH 05/10] drm/i915/skl: init/uninit display core as part of the HW power domain state Imre Deak
2015-11-13  9:02   ` Patrik Jakobsson
2015-11-17 15:33   ` [PATCH v2 " Imre Deak
2015-11-04 17:24 ` [PATCH 06/10] drm/i915/skl: don't toggle PW1 and MISC power wells on-demand Imre Deak
2015-11-13  9:31   ` Patrik Jakobsson
2015-11-04 17:24 ` [PATCH 07/10] drm/i915/gen9: simplify DC toggling code Imre Deak
2015-11-13  9:48   ` Patrik Jakobsson
2015-11-04 17:24 ` Imre Deak [this message]
2015-11-13  9:52   ` [PATCH 08/10] drm/i915/skl: disable DC states before display core init/uninit Patrik Jakobsson
2015-11-04 17:24 ` [PATCH 09/10] drm/i915/skl: make sure LCPLL is disabled when uniniting CDCLK Imre Deak
2015-11-13 10:11   ` Patrik Jakobsson
2015-11-04 17:24 ` [PATCH 10/10] drm/i915/skl: remove redundant DDI/IRQ reinitialization during PW1 enabling Imre Deak
2015-11-13 11:00   ` Patrik Jakobsson
2015-11-17 19:34 ` [PATCH 00/10] drm/i915/skl: fix display core init/uninit sequence Imre Deak

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