[PATCH v2 0/3] Support more sample rates, let the rates normal work

[PATCH v2 0/3] Support more sample rates, let the rates normal work

[Caesar Wang]

That's seem the moment rockchip-codec driver other than 44100 and 48000
do not work.
Says the (max98090, rt5640).

----
As the chromeos reported
issue:(https://chromium.googlesource.com/chromiumos/third_party/kernel/+/v3.14)

For detail:
        In that bug we want to add 32000 to
        sound/soc/rockchip/rockchip_max98090.c rk_aif1_hw_params.
        However that does not work.

        Previously, in
        https://chromium-review.googlesource.com/#/c/268398/ , rate
        8000, 1600, 96000 were added.
        However, those rates do not work. I got the same audio as 48000
        when I run

        aplay -D hw:0,0
        /usr/local/autotest/cros/audio/fix_440_16_half.raw --rate 8000
        -f S16_LE -c2
        aplay -D hw:0,0
        /usr/local/autotest/cros/audio/fix_440_16_half.raw --rate 16000
        -f S16_LE -c2
        aplay -D hw:0,0
        /usr/local/autotest/cros/audio/fix_440_16_half.raw --rate 96000
        -f S16_LE -c2

        They all sound identical to
        aplay -D hw:0,0
        /usr/local/autotest/cros/audio/fix_440_16_half.raw --rate 48000
        -f S16_LE -c2

        Also, recording using
        aplay -D hw:0,0 /usr/local/test.raw --rate 96000 -f S16_LE -c2
        and examine the output we see it was recording using 48000.

        Okay, let's add this series patchs to fix this issue.

        arecord -D hw:0 -f S16_LE -c 2 --rate [8000-96000] -d 5 foobar.wav
        and
            aplay -D hw:0 foobar.wav
Tested on veyron devices.


Changes in v2:
- move the set clock divider into rockchip i2s.
- add the 64000 sample rates for max98090.
- add the 64000 sample rate for rt5645.

Caesar Wang (3):
  ASoC: rockchip: i2s: change bclk and lrck according to sample rates
  ASoC: rockchip-max98090: Allow more sample rates
  ASoC: rockchip-rt5645: Allow more sample rates

 sound/soc/rockchip/rockchip_i2s.c      | 23 +++++++++++++++++++++++
 sound/soc/rockchip/rockchip_max98090.c |  6 ++++++
 sound/soc/rockchip/rockchip_rt5645.c   |  6 ++++++
 3 files changed, 35 insertions(+)

-- 
1.9.1

[PATCH v2 0/3] Support more sample rates, let the rates normal work

[Caesar Wang]

That's seem the moment rockchip-codec driver other than 44100 and 48000
do not work.
Says the (max98090, rt5640).

----
As the chromeos reported
issue:(https://chromium.googlesource.com/chromiumos/third_party/kernel/+/v3.14)

For detail:
        In that bug we want to add 32000 to
        sound/soc/rockchip/rockchip_max98090.c rk_aif1_hw_params.
        However that does not work.

        Previously, in
        https://chromium-review.googlesource.com/#/c/268398/ , rate
        8000, 1600, 96000 were added.
        However, those rates do not work. I got the same audio as 48000
        when I run

        aplay -D hw:0,0
        /usr/local/autotest/cros/audio/fix_440_16_half.raw --rate 8000
        -f S16_LE -c2
        aplay -D hw:0,0
        /usr/local/autotest/cros/audio/fix_440_16_half.raw --rate 16000
        -f S16_LE -c2
        aplay -D hw:0,0
        /usr/local/autotest/cros/audio/fix_440_16_half.raw --rate 96000
        -f S16_LE -c2

        They all sound identical to
        aplay -D hw:0,0
        /usr/local/autotest/cros/audio/fix_440_16_half.raw --rate 48000
        -f S16_LE -c2

        Also, recording using
        aplay -D hw:0,0 /usr/local/test.raw --rate 96000 -f S16_LE -c2
        and examine the output we see it was recording using 48000.

        Okay, let's add this series patchs to fix this issue.

        arecord -D hw:0 -f S16_LE -c 2 --rate [8000-96000] -d 5 foobar.wav
        and
            aplay -D hw:0 foobar.wav
Tested on veyron devices.


Changes in v2:
- move the set clock divider into rockchip i2s.
- add the 64000 sample rates for max98090.
- add the 64000 sample rate for rt5645.

Caesar Wang (3):
  ASoC: rockchip: i2s: change bclk and lrck according to sample rates
  ASoC: rockchip-max98090: Allow more sample rates
  ASoC: rockchip-rt5645: Allow more sample rates

 sound/soc/rockchip/rockchip_i2s.c      | 23 +++++++++++++++++++++++
 sound/soc/rockchip/rockchip_max98090.c |  6 ++++++
 sound/soc/rockchip/rockchip_rt5645.c   |  6 ++++++
 3 files changed, 35 insertions(+)

-- 
1.9.1

[PATCH v2 1/3] ASoC: rockchip: i2s: change bclk and lrck according to sample rates

[Caesar Wang]

This patch sets the dividers autonomously.

when i2s works on master mode, and sample rates changed. We need to change
bclk and lrck at the same time for cpu internal side.

As the input source clock to the module is MCLK_I2S,
and by the divider of the module, the clock generator generates
SCLK and LRCK to transmitter and receiver.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>

---

Changes in v2:
- move the set clock divider into rockchip i2s.

 sound/soc/rockchip/rockchip_i2s.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c
index b936102..b349935 100644
--- a/sound/soc/rockchip/rockchip_i2s.c
+++ b/sound/soc/rockchip/rockchip_i2s.c
@@ -41,6 +41,7 @@ struct rk_i2s_dev {
 */
 	bool tx_start;
 	bool rx_start;
+	bool is_master_mode;
 };
 
 static int i2s_runtime_suspend(struct device *dev)
@@ -174,9 +175,11 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
 	case SND_SOC_DAIFMT_CBS_CFS:
 		/* Set source clock in Master mode */
 		val = I2S_CKR_MSS_MASTER;
+		i2s->is_master_mode = true;
 		break;
 	case SND_SOC_DAIFMT_CBM_CFM:
 		val = I2S_CKR_MSS_SLAVE;
+		i2s->is_master_mode = false;
 		break;
 	default:
 		return -EINVAL;
@@ -227,6 +230,26 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
 {
 	struct rk_i2s_dev *i2s = to_info(dai);
 	unsigned int val = 0;
+	unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
+
+	if (i2s->is_master_mode) {
+		mclk_rate = clk_get_rate(i2s->mclk);
+		bclk_rate = 2 * 32 * params_rate(params);
+		if (bclk_rate && mclk_rate % bclk_rate)
+			return -EINVAL;
+
+		div_bclk = mclk_rate / bclk_rate;
+		div_lrck = bclk_rate / params_rate(params);
+		regmap_update_bits(i2s->regmap, I2S_CKR,
+				   I2S_CKR_MDIV_MASK,
+				   I2S_CKR_MDIV(div_bclk));
+
+		regmap_update_bits(i2s->regmap, I2S_CKR,
+				   I2S_CKR_TSD_MASK |
+				   I2S_CKR_RSD_MASK,
+				   I2S_CKR_TSD(div_lrck) |
+				   I2S_CKR_RSD(div_lrck));
+	}
 
 	switch (params_format(params)) {
 	case SNDRV_PCM_FORMAT_S8:
-- 
1.9.1

[PATCH v2 1/3] ASoC: rockchip: i2s: change bclk and lrck according to sample rates

[Caesar Wang]

This patch sets the dividers autonomously.

when i2s works on master mode, and sample rates changed. We need to change
bclk and lrck at the same time for cpu internal side.

As the input source clock to the module is MCLK_I2S,
and by the divider of the module, the clock generator generates
SCLK and LRCK to transmitter and receiver.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>

---

Changes in v2:
- move the set clock divider into rockchip i2s.

 sound/soc/rockchip/rockchip_i2s.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c
index b936102..b349935 100644
--- a/sound/soc/rockchip/rockchip_i2s.c
+++ b/sound/soc/rockchip/rockchip_i2s.c
@@ -41,6 +41,7 @@ struct rk_i2s_dev {
 */
 	bool tx_start;
 	bool rx_start;
+	bool is_master_mode;
 };
 
 static int i2s_runtime_suspend(struct device *dev)
@@ -174,9 +175,11 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
 	case SND_SOC_DAIFMT_CBS_CFS:
 		/* Set source clock in Master mode */
 		val = I2S_CKR_MSS_MASTER;
+		i2s->is_master_mode = true;
 		break;
 	case SND_SOC_DAIFMT_CBM_CFM:
 		val = I2S_CKR_MSS_SLAVE;
+		i2s->is_master_mode = false;
 		break;
 	default:
 		return -EINVAL;
@@ -227,6 +230,26 @@ static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
 {
 	struct rk_i2s_dev *i2s = to_info(dai);
 	unsigned int val = 0;
+	unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
+
+	if (i2s->is_master_mode) {
+		mclk_rate = clk_get_rate(i2s->mclk);
+		bclk_rate = 2 * 32 * params_rate(params);
+		if (bclk_rate && mclk_rate % bclk_rate)
+			return -EINVAL;
+
+		div_bclk = mclk_rate / bclk_rate;
+		div_lrck = bclk_rate / params_rate(params);
+		regmap_update_bits(i2s->regmap, I2S_CKR,
+				   I2S_CKR_MDIV_MASK,
+				   I2S_CKR_MDIV(div_bclk));
+
+		regmap_update_bits(i2s->regmap, I2S_CKR,
+				   I2S_CKR_TSD_MASK |
+				   I2S_CKR_RSD_MASK,
+				   I2S_CKR_TSD(div_lrck) |
+				   I2S_CKR_RSD(div_lrck));
+	}
 
 	switch (params_format(params)) {
 	case SNDRV_PCM_FORMAT_S8:
-- 
1.9.1

[PATCH v2 2/3] ASoC: rockchip-max98090: Allow more sample rates

[Caesar Wang]

The MAX98090 audio codec support sample rates from 8 to 96 kHz
as the dai claim.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>

---

Changes in v2:
- add the 64000 sample rates for max98090.

 sound/soc/rockchip/rockchip_max98090.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/sound/soc/rockchip/rockchip_max98090.c b/sound/soc/rockchip/rockchip_max98090.c
index 26567b1..5436102 100644
--- a/sound/soc/rockchip/rockchip_max98090.c
+++ b/sound/soc/rockchip/rockchip_max98090.c
@@ -80,11 +80,17 @@ static int rk_aif1_hw_params(struct snd_pcm_substream *substream,
 	switch (params_rate(params)) {
 	case 8000:
 	case 16000:
+	case 24000:
+	case 32000:
 	case 48000:
+	case 64000:
 	case 96000:
 		mclk = 12288000;
 		break;
+	case 11025:
+	case 22050:
 	case 44100:
+	case 88200:
 		mclk = 11289600;
 		break;
 	default:
-- 
1.9.1

[PATCH v2 2/3] ASoC: rockchip-max98090: Allow more sample rates

[Caesar Wang]

The MAX98090 audio codec support sample rates from 8 to 96 kHz
as the dai claim.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>

---

Changes in v2:
- add the 64000 sample rates for max98090.

 sound/soc/rockchip/rockchip_max98090.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/sound/soc/rockchip/rockchip_max98090.c b/sound/soc/rockchip/rockchip_max98090.c
index 26567b1..5436102 100644
--- a/sound/soc/rockchip/rockchip_max98090.c
+++ b/sound/soc/rockchip/rockchip_max98090.c
@@ -80,11 +80,17 @@ static int rk_aif1_hw_params(struct snd_pcm_substream *substream,
 	switch (params_rate(params)) {
 	case 8000:
 	case 16000:
+	case 24000:
+	case 32000:
 	case 48000:
+	case 64000:
 	case 96000:
 		mclk = 12288000;
 		break;
+	case 11025:
+	case 22050:
 	case 44100:
+	case 88200:
 		mclk = 11289600;
 		break;
 	default:
-- 
1.9.1

[PATCH v2 3/3] ASoC: rockchip-rt5645: Allow more sample rates

[Caesar Wang]

The RT5645 audio codec support sample rates from 8 to 96 kHz
as the dai claim.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>

---

Changes in v2:
- add the 64000 sample rate for rt5645.

 sound/soc/rockchip/rockchip_rt5645.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/sound/soc/rockchip/rockchip_rt5645.c b/sound/soc/rockchip/rockchip_rt5645.c
index 68c62e4..440a802 100644
--- a/sound/soc/rockchip/rockchip_rt5645.c
+++ b/sound/soc/rockchip/rockchip_rt5645.c
@@ -79,11 +79,17 @@ static int rk_aif1_hw_params(struct snd_pcm_substream *substream,
 	switch (params_rate(params)) {
 	case 8000:
 	case 16000:
+	case 24000:
+	case 32000:
 	case 48000:
+	case 64000:
 	case 96000:
 		mclk = 12288000;
 		break;
+	case 11025:
+	case 22050:
 	case 44100:
+	case 88200:
 		mclk = 11289600;
 		break;
 	default:
-- 
1.9.1

[PATCH v2 3/3] ASoC: rockchip-rt5645: Allow more sample rates

[Caesar Wang]

The RT5645 audio codec support sample rates from 8 to 96 kHz
as the dai claim.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>

---

Changes in v2:
- add the 64000 sample rate for rt5645.

 sound/soc/rockchip/rockchip_rt5645.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/sound/soc/rockchip/rockchip_rt5645.c b/sound/soc/rockchip/rockchip_rt5645.c
index 68c62e4..440a802 100644
--- a/sound/soc/rockchip/rockchip_rt5645.c
+++ b/sound/soc/rockchip/rockchip_rt5645.c
@@ -79,11 +79,17 @@ static int rk_aif1_hw_params(struct snd_pcm_substream *substream,
 	switch (params_rate(params)) {
 	case 8000:
 	case 16000:
+	case 24000:
+	case 32000:
 	case 48000:
+	case 64000:
 	case 96000:
 		mclk = 12288000;
 		break;
+	case 11025:
+	case 22050:
 	case 44100:
+	case 88200:
 		mclk = 11289600;
 		break;
 	default:
-- 
1.9.1

Applied "ASoC: rockchip-rt5645: Allow more sample rates" to the asoc tree

[Mark Brown]

The patch

   ASoC: rockchip-rt5645: Allow more sample rates

has been applied to the asoc tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From 8916bdb49800558b36fd0baaf36470234b91fa96 Mon Sep 17 00:00:00 2001
From: Caesar Wang <wxt@rock-chips.com>
Date: Fri, 6 Nov 2015 19:38:16 +0800
Subject: [PATCH] ASoC: rockchip-rt5645: Allow more sample rates

The RT5645 audio codec support sample rates from 8 to 96 kHz
as the dai claim.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/rockchip/rockchip_rt5645.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/sound/soc/rockchip/rockchip_rt5645.c b/sound/soc/rockchip/rockchip_rt5645.c
index 68c62e4..440a802 100644
--- a/sound/soc/rockchip/rockchip_rt5645.c
+++ b/sound/soc/rockchip/rockchip_rt5645.c
@@ -79,11 +79,17 @@ static int rk_aif1_hw_params(struct snd_pcm_substream *substream,
 	switch (params_rate(params)) {
 	case 8000:
 	case 16000:
+	case 24000:
+	case 32000:
 	case 48000:
+	case 64000:
 	case 96000:
 		mclk = 12288000;
 		break;
+	case 11025:
+	case 22050:
 	case 44100:
+	case 88200:
 		mclk = 11289600;
 		break;
 	default:
-- 
2.6.1

Applied "ASoC: rockchip-max98090: Allow more sample rates" to the asoc tree

[Mark Brown]

The patch

   ASoC: rockchip-max98090: Allow more sample rates

has been applied to the asoc tree at

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

>From dfc15c9e42819c5bb7586751b3d03534362287aa Mon Sep 17 00:00:00 2001
From: Caesar Wang <wxt@rock-chips.com>
Date: Fri, 6 Nov 2015 19:38:15 +0800
Subject: [PATCH] ASoC: rockchip-max98090: Allow more sample rates

The MAX98090 audio codec support sample rates from 8 to 96 kHz
as the dai claim.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
 sound/soc/rockchip/rockchip_max98090.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/sound/soc/rockchip/rockchip_max98090.c b/sound/soc/rockchip/rockchip_max98090.c
index 26567b1..5436102 100644
--- a/sound/soc/rockchip/rockchip_max98090.c
+++ b/sound/soc/rockchip/rockchip_max98090.c
@@ -80,11 +80,17 @@ static int rk_aif1_hw_params(struct snd_pcm_substream *substream,
 	switch (params_rate(params)) {
 	case 8000:
 	case 16000:
+	case 24000:
+	case 32000:
 	case 48000:
+	case 64000:
 	case 96000:
 		mclk = 12288000;
 		break;
+	case 11025:
+	case 22050:
 	case 44100:
+	case 88200:
 		mclk = 11289600;
 		break;
 	default:
-- 
2.6.1