From: John Garry <john.garry@huawei.com> To: <JBottomley@odin.com>, <robh+dt@kernel.org>, <pawel.moll@arm.com>, <mark.rutland@arm.com>, <ijc+devicetree@hellion.org.uk>, <galak@codeaurora.org>, <arnd@arndb.de> Cc: <linux-scsi@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>, <linuxarm@huawei.com>, <john.garry2@mail.dcu.ie>, <hare@suse.de>, <xuwei5@hisilicon.com>, <zhangfei.gao@linaro.org>, <john.garry@huawei.com> Subject: [PATCH v4 02/32] devicetree: bindings: scsi: HiSi SAS Date: Mon, 16 Nov 2015 21:05:48 +0800 [thread overview] Message-ID: <1447679178-220222-3-git-send-email-john.garry@huawei.com> (raw) In-Reply-To: <1447679178-220222-1-git-send-email-john.garry@huawei.com> Add devicetree bindings for HiSilicon SAS driver. Signed-off-by: John Garry <john.garry@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> --- .../devicetree/bindings/scsi/hisilicon-sas.txt | 69 ++++++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/scsi/hisilicon-sas.txt diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt new file mode 100644 index 0000000..f67e761 --- /dev/null +++ b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt @@ -0,0 +1,69 @@ +* HiSilicon SAS controller + +The HiSilicon SAS controller supports SAS/SATA. + +Main node required properties: + - compatible : value should be as follows: + (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset + - sas-addr : array of 8 bytes for host SAS address + - reg : Address and length of the SAS register + - hisilicon,sas-syscon: phandle of syscon used for sas control + - ctrl-reset-reg : offset to controller reset register in ctrl reg + - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg + - ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg + - queue-count : number of delivery and completion queues in the controller + - phy-count : number of phys accessible by the controller + - interrupts : Interrupts for phys, completion queues, and fatal + sources; the interrupts are ordered in 3 groups, as follows: + - Phy interrupts + - Completion queue interrupts + - Fatal interrupts + Phy interrupts : Each phy has 3 interrupt sources: + - broadcast + - phyup + - abnormal + The phy interrupts are ordered into groups of 3 per phy + (broadcast, phyup, and abnormal) in increasing order. + Completion queue interrupts : each completion queue has 1 + interrupt source. + The interrupts are ordered in increasing order. + Fatal interrupts : the fatal interrupts are ordered as follows: + - ECC + - AXI bus + +Example: + sas0: sas@c1000000 { + compatible = "hisilicon,hip05-sas-v1"; + sas-addr = [50 01 88 20 16 00 00 0a]; + reg = <0x0 0xc1000000 0x0 0x10000>; + hisilicon,sas-syscon = <&pcie_sas>; + ctrl-reset-reg = <0xa60>; + ctrl-reset-sts-reg = <0x5a30>; + ctrl-clock-ena-reg = <0x338>; + queue-count = <32>; + phy-count = <8>; + dma-coherent; + interrupt-parent = <&mbigen_dsa>; + interrupts = <259 4>,<263 4>,<264 4>,/* phy0 */ + <269 4>,<273 4>,<274 4>,/* phy1 */ + <279 4>,<283 4>,<284 4>,/* phy2 */ + <289 4>,<293 4>,<294 4>,/* phy3 */ + <299 4>,<303 4>,<304 4>,/* phy4 */ + <309 4>,<313 4>,<314 4>,/* phy5 */ + <319 4>,<323 4>,<324 4>,/* phy6 */ + <329 4>,<333 4>,<334 4>,/* phy7 */ + <336 1>,<337 1>,<338 1>,/* cq0-2 */ + <339 1>,<340 1>,<341 1>,/* cq3-5 */ + <342 1>,<343 1>,<344 1>,/* cq6-8 */ + <345 1>,<346 1>,<347 1>,/* cq9-11 */ + <348 1>,<349 1>,<350 1>,/* cq12-14 */ + <351 1>,<352 1>,<353 1>,/* cq15-17 */ + <354 1>,<355 1>,<356 1>,/* cq18-20 */ + <357 1>,<358 1>,<359 1>,/* cq21-23 */ + <360 1>,<361 1>,<362 1>,/* cq24-26 */ + <363 1>,<364 1>,<365 1>,/* cq27-29 */ + <366 1>,<367 1>/* cq30-31 */ + <376 4>,/* fatal ecc */ + <381 4>;/* fatal axi */ + status = "disabled"; + }; -- 1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> To: JBottomley-wo1vFcy6AUs@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, arnd-r2nGTMty4D4@public.gmane.org Cc: linux-scsi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linuxarm-hv44wF8Li93QT0dZR+AlfA@public.gmane.org, john.garry2-s/0ZXS5h9803lw97EnAbAg@public.gmane.org, hare-l3A5Bk7waGM@public.gmane.org, xuwei5-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org, zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org Subject: [PATCH v4 02/32] devicetree: bindings: scsi: HiSi SAS Date: Mon, 16 Nov 2015 21:05:48 +0800 [thread overview] Message-ID: <1447679178-220222-3-git-send-email-john.garry@huawei.com> (raw) In-Reply-To: <1447679178-220222-1-git-send-email-john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> Add devicetree bindings for HiSilicon SAS driver. Signed-off-by: John Garry <john.garry-hv44wF8Li93QT0dZR+AlfA@public.gmane.org> Signed-off-by: Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> --- .../devicetree/bindings/scsi/hisilicon-sas.txt | 69 ++++++++++++++++++++++ 1 file changed, 69 insertions(+) create mode 100644 Documentation/devicetree/bindings/scsi/hisilicon-sas.txt diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt new file mode 100644 index 0000000..f67e761 --- /dev/null +++ b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt @@ -0,0 +1,69 @@ +* HiSilicon SAS controller + +The HiSilicon SAS controller supports SAS/SATA. + +Main node required properties: + - compatible : value should be as follows: + (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset + - sas-addr : array of 8 bytes for host SAS address + - reg : Address and length of the SAS register + - hisilicon,sas-syscon: phandle of syscon used for sas control + - ctrl-reset-reg : offset to controller reset register in ctrl reg + - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg + - ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg + - queue-count : number of delivery and completion queues in the controller + - phy-count : number of phys accessible by the controller + - interrupts : Interrupts for phys, completion queues, and fatal + sources; the interrupts are ordered in 3 groups, as follows: + - Phy interrupts + - Completion queue interrupts + - Fatal interrupts + Phy interrupts : Each phy has 3 interrupt sources: + - broadcast + - phyup + - abnormal + The phy interrupts are ordered into groups of 3 per phy + (broadcast, phyup, and abnormal) in increasing order. + Completion queue interrupts : each completion queue has 1 + interrupt source. + The interrupts are ordered in increasing order. + Fatal interrupts : the fatal interrupts are ordered as follows: + - ECC + - AXI bus + +Example: + sas0: sas@c1000000 { + compatible = "hisilicon,hip05-sas-v1"; + sas-addr = [50 01 88 20 16 00 00 0a]; + reg = <0x0 0xc1000000 0x0 0x10000>; + hisilicon,sas-syscon = <&pcie_sas>; + ctrl-reset-reg = <0xa60>; + ctrl-reset-sts-reg = <0x5a30>; + ctrl-clock-ena-reg = <0x338>; + queue-count = <32>; + phy-count = <8>; + dma-coherent; + interrupt-parent = <&mbigen_dsa>; + interrupts = <259 4>,<263 4>,<264 4>,/* phy0 */ + <269 4>,<273 4>,<274 4>,/* phy1 */ + <279 4>,<283 4>,<284 4>,/* phy2 */ + <289 4>,<293 4>,<294 4>,/* phy3 */ + <299 4>,<303 4>,<304 4>,/* phy4 */ + <309 4>,<313 4>,<314 4>,/* phy5 */ + <319 4>,<323 4>,<324 4>,/* phy6 */ + <329 4>,<333 4>,<334 4>,/* phy7 */ + <336 1>,<337 1>,<338 1>,/* cq0-2 */ + <339 1>,<340 1>,<341 1>,/* cq3-5 */ + <342 1>,<343 1>,<344 1>,/* cq6-8 */ + <345 1>,<346 1>,<347 1>,/* cq9-11 */ + <348 1>,<349 1>,<350 1>,/* cq12-14 */ + <351 1>,<352 1>,<353 1>,/* cq15-17 */ + <354 1>,<355 1>,<356 1>,/* cq18-20 */ + <357 1>,<358 1>,<359 1>,/* cq21-23 */ + <360 1>,<361 1>,<362 1>,/* cq24-26 */ + <363 1>,<364 1>,<365 1>,/* cq27-29 */ + <366 1>,<367 1>/* cq30-31 */ + <376 4>,/* fatal ecc */ + <381 4>;/* fatal axi */ + status = "disabled"; + }; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
next prev parent reply other threads:[~2015-11-16 13:28 UTC|newest] Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-11-16 13:05 [PATCH v4 00/32] HiSilicon SAS driver John Garry 2015-11-16 13:05 ` John Garry 2015-11-16 13:05 ` [PATCH v4 01/32] [SCSI] sas: centralise ssp frame information units John Garry 2015-11-16 13:05 ` John Garry 2015-11-16 13:05 ` John Garry [this message] 2015-11-16 13:05 ` [PATCH v4 02/32] devicetree: bindings: scsi: HiSi SAS John Garry 2015-11-16 13:56 ` Rob Herring 2015-11-16 13:05 ` [PATCH v4 03/32] scsi: hisi_sas: add initial bare main driver John Garry 2015-11-16 13:05 ` John Garry 2015-11-16 17:35 ` kbuild test robot 2015-11-16 17:35 ` kbuild test robot 2015-11-17 16:24 ` John Garry 2015-11-16 13:05 ` [PATCH v4 04/32] scsi: hisi_sas: add scsi host registration John Garry 2015-11-16 13:05 ` John Garry 2015-11-16 13:05 ` [PATCH v4 05/32] scsi: hisi_sas: scan device tree John Garry 2015-11-16 13:05 ` John Garry 2015-11-16 21:10 ` kbuild test robot 2015-11-16 21:10 ` kbuild test robot 2015-11-16 13:05 ` [PATCH v4 06/32] scsi: hisi_sas: add HW DMA structures John Garry 2015-11-16 13:05 ` John Garry 2015-11-16 13:05 ` [PATCH v4 07/32] scsi: hisi_sas: allocate memories and create pools John Garry 2015-11-16 13:05 ` John Garry 2015-11-16 13:05 ` [PATCH v4 08/32] scsi: hisi_sas: add hisi_sas_remove John Garry 2015-11-16 13:05 ` John Garry 2015-11-16 13:05 ` [PATCH v4 09/32] scsi: hisi_sas: add slot init code John Garry 2015-11-16 13:05 ` John Garry 2015-11-16 13:05 ` [PATCH v4 10/32] scsi: hisi_sas: add cq structure initialization John Garry 2015-11-16 13:05 ` John Garry 2015-11-16 13:05 ` [PATCH v4 11/32] scsi: hisi_sas: add phy SAS ADDR initialization John Garry 2015-11-16 13:05 ` John Garry 2015-11-16 13:05 ` [PATCH v4 12/32] scsi: hisi_sas: set dev DMA mask John Garry 2015-11-16 13:05 ` John Garry 2015-11-16 13:05 ` [PATCH v4 13/32] scsi: hisi_sas: add hisi_hba workqueue John Garry 2015-11-16 13:05 ` John Garry 2015-11-16 13:06 ` [PATCH v4 14/32] scsi: hisi_sas: add hisi sas device type John Garry 2015-11-16 13:06 ` John Garry 2015-11-16 13:06 ` [PATCH v4 15/32] scsi: hisi_sas: add phy and port init John Garry 2015-11-16 13:06 ` John Garry 2015-11-16 13:06 ` [PATCH v4 16/32] scsi: hisi_sas: add timer and spinlock init John Garry 2015-11-16 13:06 ` John Garry 2015-11-16 13:06 ` [PATCH v4 17/32] scsi: hisi_sas: add v1 hw module init John Garry 2015-11-16 13:06 ` John Garry 2015-11-16 13:06 ` [PATCH v4 18/32] scsi: hisi_sas: add v1 hardware register definitions John Garry 2015-11-16 13:06 ` John Garry 2015-11-16 13:06 ` [PATCH v4 19/32] scsi: hisi_sas: add v1 HW initialisation code John Garry 2015-11-16 13:06 ` John Garry 2015-11-16 13:06 ` [PATCH v4 20/32] scsi: hisi_sas: add v1 hw interrupt init John Garry 2015-11-16 13:06 ` John Garry 2015-11-16 13:06 ` [PATCH v4 21/32] scsi: hisi_sas: add path from phyup irq to SAS framework John Garry 2015-11-16 13:06 ` John Garry 2015-11-16 13:06 ` [PATCH v4 22/32] scsi: hisi_sas: add ssp command function John Garry 2015-11-16 13:06 ` John Garry 2015-11-16 13:06 ` [PATCH v4 23/32] scsi: hisi_sas: add cq interrupt handler John Garry 2015-11-16 13:06 ` John Garry 2015-11-16 13:06 ` [PATCH v4 24/32] scsi: hisi_sas: add dev_found and dev_gone John Garry 2015-11-16 13:06 ` John Garry 2015-11-16 13:06 ` [PATCH v4 25/32] scsi: hisi_sas: add abnormal irq handler John Garry 2015-11-16 13:06 ` John Garry 2015-11-16 13:06 ` [PATCH v4 26/32] scsi: hisi_sas: add bcast interrupt handler John Garry 2015-11-16 13:06 ` John Garry 2015-11-16 13:06 ` [PATCH v4 27/32] scsi: hisi_sas: add smp protocol support John Garry 2015-11-16 13:06 ` John Garry 2015-11-16 13:06 ` [PATCH v4 28/32] scsi: hisi_sas: add scan finished and start John Garry 2015-11-16 13:06 ` John Garry 2015-11-16 13:06 ` [PATCH v4 29/32] scsi: hisi_sas: add tmf methods John Garry 2015-11-16 13:06 ` John Garry 2015-11-16 13:06 ` [PATCH v4 30/32] scsi: hisi_sas: add control phy handler John Garry 2015-11-16 13:06 ` John Garry 2015-11-16 13:06 ` [PATCH v4 31/32] scsi: hisi_sas: add fatal irq handler John Garry 2015-11-16 13:06 ` John Garry 2015-11-16 13:06 ` [PATCH v4 32/32] MAINTAINERS: add maintainer for HiSi SAS driver John Garry 2015-11-16 13:06 ` John Garry
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