From: Andy Gross <agross@codeaurora.org> To: linux-arm-msm@vger.kernel.org Cc: Felipe Balbi <balbi@ti.com>, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org, Greg KH <gregkh@linuxfoundation.org>, devicetree@vger.kernel.org, Kishon Vijay Abraham I <kishon@ti.com>, Andy Gross <agross@codeaurora.org> Subject: [PATCH 4/4] Documentation: usb: dwc3: qcom: Add TCSR mux usage Date: Fri, 20 Nov 2015 02:35:09 -0600 [thread overview] Message-ID: <1448008509-8913-5-git-send-email-agross@codeaurora.org> (raw) In-Reply-To: <1448008509-8913-1-git-send-email-agross@codeaurora.org> This patch adds documentation for the optional syscon-tcsr property in the Qualcomm DWC3 node. The syscon-tcsr specifies the register and bit used to configure the TCSR USB phy mux register. Signed-off-by: Andy Gross <agross@codeaurora.org> --- Documentation/devicetree/bindings/usb/qcom,dwc3.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt index ca164e7..dfa222d 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt @@ -8,6 +8,10 @@ Required properties: "core" Master/Core clock, have to be >= 125 MHz for SS operation and >= 60MHz for HS operation +Optional properties: +- syscon-tcsr Specifies TCSR handle, register offset, and bit position for + configuring the phy mux setting. + Optional clocks: "iface" System bus AXI clock. Not present on all platforms "sleep" Sleep clock, used when USB3 core goes into low @@ -22,6 +26,11 @@ Documentation/devicetree/bindings/phy/qcom,dwc3-usb-phy.txt Example device nodes: + tcsr: syscon@1a400000 { + compatible = "qcom,tcsr-ipq8064", "syscon"; + reg = <0x1a400000 0x100>; + }; + hs_phy: phy@100f8800 { compatible = "qcom,dwc3-hs-usb-phy"; reg = <0x100f8800 0x30>; @@ -51,6 +60,8 @@ Example device nodes: ranges; + syscon-tcsr = <&tcsr 0xb0 0x1>; + status = "ok"; dwc3@10000000 { -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
WARNING: multiple messages have this Message-ID (diff)
From: agross@codeaurora.org (Andy Gross) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/4] Documentation: usb: dwc3: qcom: Add TCSR mux usage Date: Fri, 20 Nov 2015 02:35:09 -0600 [thread overview] Message-ID: <1448008509-8913-5-git-send-email-agross@codeaurora.org> (raw) In-Reply-To: <1448008509-8913-1-git-send-email-agross@codeaurora.org> This patch adds documentation for the optional syscon-tcsr property in the Qualcomm DWC3 node. The syscon-tcsr specifies the register and bit used to configure the TCSR USB phy mux register. Signed-off-by: Andy Gross <agross@codeaurora.org> --- Documentation/devicetree/bindings/usb/qcom,dwc3.txt | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt index ca164e7..dfa222d 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt @@ -8,6 +8,10 @@ Required properties: "core" Master/Core clock, have to be >= 125 MHz for SS operation and >= 60MHz for HS operation +Optional properties: +- syscon-tcsr Specifies TCSR handle, register offset, and bit position for + configuring the phy mux setting. + Optional clocks: "iface" System bus AXI clock. Not present on all platforms "sleep" Sleep clock, used when USB3 core goes into low @@ -22,6 +26,11 @@ Documentation/devicetree/bindings/phy/qcom,dwc3-usb-phy.txt Example device nodes: + tcsr: syscon at 1a400000 { + compatible = "qcom,tcsr-ipq8064", "syscon"; + reg = <0x1a400000 0x100>; + }; + hs_phy: phy at 100f8800 { compatible = "qcom,dwc3-hs-usb-phy"; reg = <0x100f8800 0x30>; @@ -51,6 +60,8 @@ Example device nodes: ranges; + syscon-tcsr = <&tcsr 0xb0 0x1>; + status = "ok"; dwc3 at 10000000 { -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2015-11-20 8:35 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-11-20 8:35 [PATCH 0/4] Add QCOM DWC3 Phy support Andy Gross 2015-11-20 8:35 ` Andy Gross 2015-11-20 8:35 ` Andy Gross 2015-11-20 8:35 ` [PATCH 1/4] phy: Add Qualcomm DWC3 HS/SS PHY driver Andy Gross 2015-11-20 8:35 ` Andy Gross 2015-11-20 8:35 ` Andy Gross 2015-11-20 8:35 ` [PATCH 2/4] usb: dwc3: qcom: Configure TCSR phy mux register Andy Gross 2015-11-20 8:35 ` Andy Gross 2015-11-20 8:35 ` Andy Gross [not found] ` <1448008509-8913-3-git-send-email-agross-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2015-11-20 15:06 ` Felipe Balbi 2015-11-20 15:06 ` Felipe Balbi 2015-11-20 15:06 ` Felipe Balbi 2015-11-20 15:54 ` Andy Gross 2015-11-20 15:54 ` Andy Gross 2015-11-20 8:35 ` [PATCH 3/4] ARM: dts: qcom: Add DWC3 USB support on IPQ8064 Andy Gross 2015-11-20 8:35 ` Andy Gross 2015-11-20 8:35 ` Andy Gross [this message] 2015-11-20 8:35 ` [PATCH 4/4] Documentation: usb: dwc3: qcom: Add TCSR mux usage Andy Gross [not found] ` <1448008509-8913-5-git-send-email-agross-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> 2015-11-20 14:33 ` Rob Herring 2015-11-20 14:33 ` Rob Herring 2015-11-20 14:33 ` Rob Herring 2015-11-20 15:08 ` Felipe Balbi 2015-11-20 15:08 ` Felipe Balbi 2015-11-20 15:08 ` Felipe Balbi 2015-11-20 15:56 ` Andy Gross 2015-11-20 15:56 ` Andy Gross
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