* [PATCH 01/12] drm/i915: Convert i915_semaphores_is_enabled over to drm_i915_private
@ 2015-11-20 12:43 Chris Wilson
2015-11-20 12:43 ` [PATCH 02/12] drm/i915: Use the new rq->i915 field where appropriate Chris Wilson
` (11 more replies)
0 siblings, 12 replies; 41+ messages in thread
From: Chris Wilson @ 2015-11-20 12:43 UTC (permalink / raw)
To: intel-gfx
We only need our private device struct for checking semapahore status,
and to reduce churn later convert the parameter over now.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_dma.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 8 ++++----
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 20 ++++++++++----------
8 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8890b115a2c0..359436162f3d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2859,7 +2859,7 @@ static int i915_semaphore_status(struct seq_file *m, void *unused)
int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
int i, j, ret;
- if (!i915_semaphore_is_enabled(dev)) {
+ if (!i915_semaphore_is_enabled(dev_priv)) {
seq_puts(m, "Semaphores are disabled\n");
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index cd79ef114b8e..d41bf214fc84 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -127,7 +127,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = 1;
break;
case I915_PARAM_HAS_SEMAPHORES:
- value = i915_semaphore_is_enabled(dev);
+ value = i915_semaphore_is_enabled(dev_priv);
break;
case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
value = 1;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 1d887459e37f..10c4cc2cece9 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -512,9 +512,9 @@ void intel_detect_pch(struct drm_device *dev)
pci_dev_put(pch);
}
-bool i915_semaphore_is_enabled(struct drm_device *dev)
+bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv)
{
- if (INTEL_INFO(dev)->gen < 6)
+ if (INTEL_INFO(dev_priv)->gen < 6)
return false;
if (i915.semaphores >= 0)
@@ -525,12 +525,12 @@ bool i915_semaphore_is_enabled(struct drm_device *dev)
return false;
/* Until we get further testing... */
- if (IS_GEN8(dev))
+ if (IS_GEN8(dev_priv))
return false;
#ifdef CONFIG_INTEL_IOMMU
/* Enable semaphores on SNB when IO remapping is off */
- if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
+ if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped)
return false;
#endif
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 343a0a723d2c..fadf2ceb1f72 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3311,7 +3311,7 @@ extern void intel_detect_pch(struct drm_device *dev);
extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
extern int intel_enable_rc6(const struct drm_device *dev);
-extern bool i915_semaphore_is_enabled(struct drm_device *dev);
+extern bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv);
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
struct drm_file *file);
int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 69d8d5fc750b..e6ac049a4698 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3150,7 +3150,7 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
if (i915_gem_request_completed(from_req, true))
return 0;
- if (!i915_semaphore_is_enabled(obj->base.dev)) {
+ if (!i915_semaphore_is_enabled(to_i915(obj->base.dev))) {
struct drm_i915_private *i915 = to_i915(obj->base.dev);
ret = __i915_wait_request(from_req,
atomic_read(&i915->gpu_error.reset_counter),
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index f2f1e913f17a..55d2985c1dbb 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -483,7 +483,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
u32 flags = hw_flags | MI_MM_SPACE_GTT;
const int num_rings =
/* Use an extended w/a on ivb+ if signalling from other rings */
- i915_semaphore_is_enabled(ring->dev) ?
+ i915_semaphore_is_enabled(to_i915(ring->dev)) ?
hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 :
0;
int len, i, ret;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 0d0a7b1a6b4b..d8e035e126d7 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -816,7 +816,7 @@ static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
struct intel_engine_cs *to;
int i;
- if (!i915_semaphore_is_enabled(dev_priv->dev))
+ if (!i915_semaphore_is_enabled(dev_priv))
return;
if (!error->semaphore_obj)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 0eaaab92dea0..8d8ba717a022 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2594,7 +2594,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
ring->mmio_base = RENDER_RING_BASE;
if (INTEL_INFO(dev)->gen >= 8) {
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
obj = i915_gem_alloc_object(dev, 4096);
if (obj == NULL) {
DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
@@ -2619,7 +2619,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
WARN_ON(!dev_priv->semaphore_obj);
ring->semaphore.sync_to = gen8_ring_sync;
ring->semaphore.signal = gen8_rcs_signal;
@@ -2635,7 +2635,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
ring->get_seqno = gen6_ring_get_seqno;
ring->set_seqno = ring_set_seqno;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
ring->semaphore.sync_to = gen6_ring_sync;
ring->semaphore.signal = gen6_signal;
/*
@@ -2756,7 +2756,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
ring->irq_put = gen8_ring_put_irq;
ring->dispatch_execbuffer =
gen8_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
ring->semaphore.sync_to = gen8_ring_sync;
ring->semaphore.signal = gen8_xcs_signal;
GEN8_RING_SEMAPHORE_INIT;
@@ -2767,7 +2767,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
ring->irq_put = gen6_ring_put_irq;
ring->dispatch_execbuffer =
gen6_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
ring->semaphore.sync_to = gen6_ring_sync;
ring->semaphore.signal = gen6_signal;
ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
@@ -2827,7 +2827,7 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
ring->irq_put = gen8_ring_put_irq;
ring->dispatch_execbuffer =
gen8_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
ring->semaphore.sync_to = gen8_ring_sync;
ring->semaphore.signal = gen8_xcs_signal;
GEN8_RING_SEMAPHORE_INIT;
@@ -2857,7 +2857,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
ring->irq_get = gen8_ring_get_irq;
ring->irq_put = gen8_ring_put_irq;
ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
ring->semaphore.sync_to = gen8_ring_sync;
ring->semaphore.signal = gen8_xcs_signal;
GEN8_RING_SEMAPHORE_INIT;
@@ -2867,7 +2867,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
ring->irq_get = gen6_ring_get_irq;
ring->irq_put = gen6_ring_put_irq;
ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
ring->semaphore.signal = gen6_signal;
ring->semaphore.sync_to = gen6_ring_sync;
/*
@@ -2915,7 +2915,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
ring->irq_get = gen8_ring_get_irq;
ring->irq_put = gen8_ring_put_irq;
ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
ring->semaphore.sync_to = gen8_ring_sync;
ring->semaphore.signal = gen8_xcs_signal;
GEN8_RING_SEMAPHORE_INIT;
@@ -2925,7 +2925,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
ring->irq_get = hsw_vebox_get_irq;
ring->irq_put = hsw_vebox_put_irq;
ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
- if (i915_semaphore_is_enabled(dev)) {
+ if (i915_semaphore_is_enabled(dev_priv)) {
ring->semaphore.sync_to = gen6_ring_sync;
ring->semaphore.signal = gen6_signal;
ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
--
2.6.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 02/12] drm/i915: Use the new rq->i915 field where appropriate
2015-11-20 12:43 [PATCH 01/12] drm/i915: Convert i915_semaphores_is_enabled over to drm_i915_private Chris Wilson
@ 2015-11-20 12:43 ` Chris Wilson
2015-11-24 13:57 ` Daniel Vetter
2015-11-20 12:43 ` [PATCH 03/12] drm/i915: Unify intel_logical_ring_emit and intel_ring_emit Chris Wilson
` (10 subsequent siblings)
11 siblings, 1 reply; 41+ messages in thread
From: Chris Wilson @ 2015-11-20 12:43 UTC (permalink / raw)
To: intel-gfx
In a few frequent cases, having a direct pointer to the drm_i915_private
from the request is very useful.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem.c | 22 +++++++-----------
drivers/gpu/drm/i915/i915_gem_context.c | 23 +++++++++----------
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 +--
drivers/gpu/drm/i915/intel_lrc.c | 8 +++----
drivers/gpu/drm/i915/intel_pm.c | 3 +--
drivers/gpu/drm/i915/intel_ringbuffer.c | 36 +++++++++++++-----------------
6 files changed, 39 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e6ac049a4698..5c3d11d020f0 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1221,8 +1221,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
struct intel_rps_client *rps)
{
struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
- struct drm_device *dev = ring->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = req->i915;
const bool irq_test_in_progress =
ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
@@ -1336,7 +1335,6 @@ out:
int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
struct drm_file *file)
{
- struct drm_i915_private *dev_private;
struct drm_i915_file_private *file_priv;
WARN_ON(!req || !file || req->file_priv);
@@ -1347,7 +1345,6 @@ int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
if (req->file_priv)
return -EINVAL;
- dev_private = req->ring->dev->dev_private;
file_priv = file->driver_priv;
spin_lock(&file_priv->mm.lock);
@@ -1425,18 +1422,16 @@ __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
int
i915_wait_request(struct drm_i915_gem_request *req)
{
- struct drm_device *dev;
struct drm_i915_private *dev_priv;
bool interruptible;
int ret;
BUG_ON(req == NULL);
- dev = req->ring->dev;
- dev_priv = dev->dev_private;
+ dev_priv = req->i915;
interruptible = dev_priv->mm.interruptible;
- BUG_ON(!mutex_is_locked(&dev->struct_mutex));
+ BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
if (ret)
@@ -2568,7 +2563,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
return;
ring = request->ring;
- dev_priv = ring->dev->dev_private;
+ dev_priv = request->i915;
ringbuf = request->ringbuf;
/*
@@ -3150,8 +3145,8 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
if (i915_gem_request_completed(from_req, true))
return 0;
- if (!i915_semaphore_is_enabled(to_i915(obj->base.dev))) {
- struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ if (!i915_semaphore_is_enabled(from_req->i915)) {
+ struct drm_i915_private *i915 = from_req->i915;
ret = __i915_wait_request(from_req,
atomic_read(&i915->gpu_error.reset_counter),
i915->mm.interruptible,
@@ -4648,13 +4643,12 @@ err:
int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
{
struct intel_engine_cs *ring = req->ring;
- struct drm_device *dev = ring->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = req->i915;
u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
int i, ret;
- if (!HAS_L3_DPF(dev) || !remap_info)
+ if (!HAS_L3_DPF(dev_priv) || !remap_info)
return 0;
ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 55d2985c1dbb..82a9f7197d32 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -483,8 +483,8 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
u32 flags = hw_flags | MI_MM_SPACE_GTT;
const int num_rings =
/* Use an extended w/a on ivb+ if signalling from other rings */
- i915_semaphore_is_enabled(to_i915(ring->dev)) ?
- hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 :
+ i915_semaphore_is_enabled(req->i915) ?
+ hweight32(INTEL_INFO(req->i915)->ring_mask) - 1 :
0;
int len, i, ret;
@@ -493,21 +493,21 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
* explicitly, so we rely on the value at ring init, stored in
* itlb_before_ctx_switch.
*/
- if (IS_GEN6(ring->dev)) {
+ if (IS_GEN6(req->i915)) {
ret = ring->flush(req, I915_GEM_GPU_DOMAINS, 0);
if (ret)
return ret;
}
/* These flags are for resource streamer on HSW+ */
- if (IS_HASWELL(ring->dev) || INTEL_INFO(ring->dev)->gen >= 8)
+ if (IS_HASWELL(req->i915) || INTEL_INFO(req->i915)->gen >= 8)
flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
- else if (INTEL_INFO(ring->dev)->gen < 8)
+ else if (INTEL_INFO(req->i915)->gen < 8)
flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
len = 4;
- if (INTEL_INFO(ring->dev)->gen >= 7)
+ if (INTEL_INFO(req->i915)->gen >= 7)
len += 2 + (num_rings ? 4*num_rings + 2 : 0);
ret = intel_ring_begin(req, len);
@@ -515,13 +515,13 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
return ret;
/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
- if (INTEL_INFO(ring->dev)->gen >= 7) {
+ if (INTEL_INFO(req->i915)->gen >= 7) {
intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
if (num_rings) {
struct intel_engine_cs *signaller;
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
- for_each_ring(signaller, to_i915(ring->dev), i) {
+ for_each_ring(signaller, req->i915, i) {
if (signaller == ring)
continue;
@@ -541,12 +541,12 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
*/
intel_ring_emit(ring, MI_NOOP);
- if (INTEL_INFO(ring->dev)->gen >= 7) {
+ if (INTEL_INFO(req->i915)->gen >= 7) {
if (num_rings) {
struct intel_engine_cs *signaller;
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
- for_each_ring(signaller, to_i915(ring->dev), i) {
+ for_each_ring(signaller, req->i915, i) {
if (signaller == ring)
continue;
@@ -785,10 +785,9 @@ unpin_out:
int i915_switch_context(struct drm_i915_gem_request *req)
{
struct intel_engine_cs *ring = req->ring;
- struct drm_i915_private *dev_priv = ring->dev->dev_private;
WARN_ON(i915.enable_execlists);
- WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
+ WARN_ON(!mutex_is_locked(&req->i915->dev->struct_mutex));
if (req->ctx->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */
if (req->ctx != ring->last_context) {
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 7ac4685e0d3e..e8164b644e0e 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1066,7 +1066,6 @@ void
i915_gem_execbuffer_move_to_active(struct list_head *vmas,
struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
struct i915_vma *vma;
list_for_each_entry(vma, vmas, exec_list) {
@@ -1093,7 +1092,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
i915_gem_request_assign(&obj->last_fenced_req, req);
if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
- struct drm_i915_private *dev_priv = to_i915(ring->dev);
+ struct drm_i915_private *dev_priv = req->i915;
list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
&dev_priv->mm.fence_list);
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 10020505be75..cfa77a59b352 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -307,8 +307,7 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
{
struct intel_engine_cs *ring = rq0->ring;
- struct drm_device *dev = ring->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = rq0->i915;
uint64_t desc[2];
if (rq1) {
@@ -787,7 +786,7 @@ int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
int ret;
WARN_ON(req == NULL);
- dev_priv = req->ring->dev->dev_private;
+ dev_priv = req->i915;
ret = i915_gem_check_wedge(&dev_priv->gpu_error,
dev_priv->mm.interruptible);
@@ -1027,8 +1026,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
int ret, i;
struct intel_engine_cs *ring = req->ring;
struct intel_ringbuffer *ringbuf = req->ringbuf;
- struct drm_device *dev = ring->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = req->i915;
struct i915_workarounds *w = &dev_priv->workarounds;
if (WARN_ON_ONCE(w->count == 0))
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index aef9eb1c6c33..3d54f76ad176 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7410,8 +7410,7 @@ static void __intel_rps_boost_work(struct work_struct *work)
struct drm_i915_gem_request *req = boost->req;
if (!i915_gem_request_completed(req, true))
- intel_rps_boost(to_i915(req->ring->dev), NULL,
- req->emitted_jiffies);
+ intel_rps_boost(req->i915, NULL, req->emitted_jiffies);
i915_gem_request_unreference__unlocked(req);
kfree(boost);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8d8ba717a022..9fbe730aae47 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -123,7 +123,6 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
u32 flush_domains)
{
struct intel_engine_cs *ring = req->ring;
- struct drm_device *dev = ring->dev;
u32 cmd;
int ret;
@@ -162,7 +161,7 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
cmd |= MI_EXE_FLUSH;
if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
- (IS_G4X(dev) || IS_GEN5(dev)))
+ (IS_G4X(req->i915) || IS_GEN5(req->i915)))
cmd |= MI_INVALIDATE_ISP;
ret = intel_ring_begin(req, 2);
@@ -715,8 +714,7 @@ static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
{
int ret, i;
struct intel_engine_cs *ring = req->ring;
- struct drm_device *dev = ring->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = req->i915;
struct i915_workarounds *w = &dev_priv->workarounds;
if (WARN_ON_ONCE(w->count == 0))
@@ -1187,12 +1185,11 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
{
#define MBOX_UPDATE_DWORDS 8
struct intel_engine_cs *signaller = signaller_req->ring;
- struct drm_device *dev = signaller->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *waiter;
int i, ret, num_rings;
- num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
+ num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
#undef MBOX_UPDATE_DWORDS
@@ -1228,12 +1225,11 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
{
#define MBOX_UPDATE_DWORDS 6
struct intel_engine_cs *signaller = signaller_req->ring;
- struct drm_device *dev = signaller->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *waiter;
int i, ret, num_rings;
- num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
+ num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
#undef MBOX_UPDATE_DWORDS
@@ -1266,13 +1262,12 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
unsigned int num_dwords)
{
struct intel_engine_cs *signaller = signaller_req->ring;
- struct drm_device *dev = signaller->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *useless;
int i, ret, num_rings;
#define MBOX_UPDATE_DWORDS 3
- num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
+ num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
#undef MBOX_UPDATE_DWORDS
@@ -1349,7 +1344,7 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
u32 seqno)
{
struct intel_engine_cs *waiter = waiter_req->ring;
- struct drm_i915_private *dev_priv = waiter->dev->dev_private;
+ struct drm_i915_private *dev_priv = waiter_req->i915;
int ret;
ret = intel_ring_begin(waiter_req, 4);
@@ -2201,8 +2196,8 @@ int intel_ring_idle(struct intel_engine_cs *ring)
/* Make sure we do not trigger any retires */
return __i915_wait_request(req,
- atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
- to_i915(ring->dev)->mm.interruptible,
+ atomic_read(&req->i915->gpu_error.reset_counter),
+ req->i915->mm.interruptible,
NULL, NULL);
}
@@ -2330,7 +2325,7 @@ int intel_ring_begin(struct drm_i915_gem_request *req,
WARN_ON(req == NULL);
ring = req->ring;
- dev_priv = ring->dev->dev_private;
+ dev_priv = req->i915;
ret = i915_gem_check_wedge(&dev_priv->gpu_error,
dev_priv->mm.interruptible);
@@ -2467,7 +2462,7 @@ gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
unsigned dispatch_flags)
{
struct intel_engine_cs *ring = req->ring;
- bool ppgtt = USES_PPGTT(ring->dev) &&
+ bool ppgtt = USES_PPGTT(req->i915) &&
!(dispatch_flags & I915_DISPATCH_SECURE);
int ret;
@@ -2541,7 +2536,6 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate, u32 flush)
{
struct intel_engine_cs *ring = req->ring;
- struct drm_device *dev = ring->dev;
uint32_t cmd;
int ret;
@@ -2550,7 +2544,7 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
return ret;
cmd = MI_FLUSH_DW;
- if (INTEL_INFO(dev)->gen >= 8)
+ if (INTEL_INFO(req->i915)->gen >= 8)
cmd += 1;
/* We always require a command barrier so that subsequent
@@ -2570,7 +2564,7 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
cmd |= MI_INVALIDATE_TLB;
intel_ring_emit(ring, cmd);
intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
- if (INTEL_INFO(dev)->gen >= 8) {
+ if (INTEL_INFO(req->i915)->gen >= 8) {
intel_ring_emit(ring, 0); /* upper addr */
intel_ring_emit(ring, 0); /* value */
} else {
--
2.6.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 03/12] drm/i915: Unify intel_logical_ring_emit and intel_ring_emit
2015-11-20 12:43 [PATCH 01/12] drm/i915: Convert i915_semaphores_is_enabled over to drm_i915_private Chris Wilson
2015-11-20 12:43 ` [PATCH 02/12] drm/i915: Use the new rq->i915 field where appropriate Chris Wilson
@ 2015-11-20 12:43 ` Chris Wilson
2015-11-24 14:33 ` Daniel Vetter
2015-11-20 12:43 ` [PATCH 04/12] drm/i915: Unify intel_ring_begin() Chris Wilson
` (9 subsequent siblings)
11 siblings, 1 reply; 41+ messages in thread
From: Chris Wilson @ 2015-11-20 12:43 UTC (permalink / raw)
To: intel-gfx
Both perform the same actions with more or less indirection, so just
unify the code.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
drivers/gpu/drm/i915/i915_gem_context.c | 8 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 34 ++++-----
drivers/gpu/drm/i915/i915_gem_gtt.c | 26 +++----
drivers/gpu/drm/i915/intel_display.c | 26 +++----
drivers/gpu/drm/i915/intel_lrc.c | 118 ++++++++++++++---------------
drivers/gpu/drm/i915/intel_lrc.h | 21 -----
drivers/gpu/drm/i915/intel_mocs.c | 30 ++++----
drivers/gpu/drm/i915/intel_overlay.c | 42 +++++-----
drivers/gpu/drm/i915/intel_ringbuffer.c | 107 +++++++++++++-------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 15 +---
11 files changed, 195 insertions(+), 234 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5c3d11d020f0..c60105e36263 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4642,7 +4642,7 @@ err:
int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
struct drm_i915_private *dev_priv = req->i915;
u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 82a9f7197d32..c3adc121aab4 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -479,7 +479,7 @@ i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
static inline int
mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
u32 flags = hw_flags | MI_MM_SPACE_GTT;
const int num_rings =
/* Use an extended w/a on ivb+ if signalling from other rings */
@@ -494,7 +494,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
* itlb_before_ctx_switch.
*/
if (IS_GEN6(req->i915)) {
- ret = ring->flush(req, I915_GEM_GPU_DOMAINS, 0);
+ ret = req->ring->flush(req, I915_GEM_GPU_DOMAINS, 0);
if (ret)
return ret;
}
@@ -522,7 +522,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
for_each_ring(signaller, req->i915, i) {
- if (signaller == ring)
+ if (signaller == req->ring)
continue;
intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
@@ -547,7 +547,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
for_each_ring(signaller, req->i915, i) {
- if (signaller == ring)
+ if (signaller == req->ring)
continue;
intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index e8164b644e0e..5f1b9b7df051 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1113,14 +1113,12 @@ i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
}
static int
-i915_reset_gen7_sol_offsets(struct drm_device *dev,
- struct drm_i915_gem_request *req)
+i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *ring = req->ring;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret, i;
- if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) {
+ if (!IS_GEN7(req->i915) || req->ring->id != RCS) {
DRM_DEBUG("sol reset is gen7/rcs only\n");
return -EINVAL;
}
@@ -1198,9 +1196,8 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
struct drm_i915_gem_execbuffer2 *args,
struct list_head *vmas)
{
- struct drm_device *dev = params->dev;
- struct intel_engine_cs *ring = params->ring;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_ringbuffer *ring = params->request->ringbuf;
+ struct drm_i915_private *dev_priv = params->request->i915;
u64 exec_start, exec_len;
int instp_mode;
u32 instp_mask;
@@ -1214,34 +1211,31 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
if (ret)
return ret;
- WARN(params->ctx->ppgtt && params->ctx->ppgtt->pd_dirty_rings & (1<<ring->id),
- "%s didn't clear reload\n", ring->name);
-
instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
instp_mask = I915_EXEC_CONSTANTS_MASK;
switch (instp_mode) {
case I915_EXEC_CONSTANTS_REL_GENERAL:
case I915_EXEC_CONSTANTS_ABSOLUTE:
case I915_EXEC_CONSTANTS_REL_SURFACE:
- if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
+ if (instp_mode != 0 && params->ring->id != RCS) {
DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
return -EINVAL;
}
if (instp_mode != dev_priv->relative_constants_mode) {
- if (INTEL_INFO(dev)->gen < 4) {
+ if (INTEL_INFO(dev_priv)->gen < 4) {
DRM_DEBUG("no rel constants on pre-gen4\n");
return -EINVAL;
}
- if (INTEL_INFO(dev)->gen > 5 &&
+ if (INTEL_INFO(dev_priv)->gen > 5 &&
instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
return -EINVAL;
}
/* The HW changed the meaning on this bit on gen6 */
- if (INTEL_INFO(dev)->gen >= 6)
+ if (INTEL_INFO(dev_priv)->gen >= 6)
instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
}
break;
@@ -1250,7 +1244,7 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
return -EINVAL;
}
- if (ring == &dev_priv->ring[RCS] &&
+ if (params->ring->id == RCS &&
instp_mode != dev_priv->relative_constants_mode) {
ret = intel_ring_begin(params->request, 4);
if (ret)
@@ -1266,7 +1260,7 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
}
if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
- ret = i915_reset_gen7_sol_offsets(dev, params->request);
+ ret = i915_reset_gen7_sol_offsets(params->request);
if (ret)
return ret;
}
@@ -1275,9 +1269,9 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
exec_start = params->batch_obj_vm_offset +
params->args_batch_start_offset;
- ret = ring->dispatch_execbuffer(params->request,
- exec_start, exec_len,
- params->dispatch_flags);
+ ret = params->ring->dispatch_execbuffer(params->request,
+ exec_start, exec_len,
+ params->dispatch_flags);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 7820e8983136..4608884adfc8 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -651,7 +651,7 @@ static int gen8_write_pdp(struct drm_i915_gem_request *req,
unsigned entry,
dma_addr_t addr)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
BUG_ON(entry >= 4);
@@ -661,10 +661,10 @@ static int gen8_write_pdp(struct drm_i915_gem_request *req,
return ret;
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
- intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
+ intel_ring_emit(ring, GEN8_RING_PDP_UDW(req->ring, entry));
intel_ring_emit(ring, upper_32_bits(addr));
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
- intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
+ intel_ring_emit(ring, GEN8_RING_PDP_LDW(req->ring, entry));
intel_ring_emit(ring, lower_32_bits(addr));
intel_ring_advance(ring);
@@ -1588,11 +1588,11 @@ static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
/* NB: TLBs must be flushed and invalidated before a switch */
- ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
+ ret = req->ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
if (ret)
return ret;
@@ -1601,9 +1601,9 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
return ret;
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
- intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
+ intel_ring_emit(ring, RING_PP_DIR_DCLV(req->ring));
intel_ring_emit(ring, PP_DIR_DCLV_2G);
- intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
+ intel_ring_emit(ring, RING_PP_DIR_BASE(req->ring));
intel_ring_emit(ring, get_pd_offset(ppgtt));
intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
@@ -1625,11 +1625,11 @@ static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
/* NB: TLBs must be flushed and invalidated before a switch */
- ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
+ ret = req->ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
if (ret)
return ret;
@@ -1638,16 +1638,16 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
return ret;
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
- intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
+ intel_ring_emit(ring, RING_PP_DIR_DCLV(req->ring));
intel_ring_emit(ring, PP_DIR_DCLV_2G);
- intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
+ intel_ring_emit(ring, RING_PP_DIR_BASE(req->ring));
intel_ring_emit(ring, get_pd_offset(ppgtt));
intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
/* XXX: RCS is the only one to auto invalidate the TLBs? */
- if (ring->id != RCS) {
- ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
+ if (req->ring->id != RCS) {
+ ret = req->ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
if (ret)
return ret;
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6bd204980b70..f6dae2cfd9c9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10824,7 +10824,7 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
u32 flip_mask;
int ret;
@@ -10859,7 +10859,7 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
u32 flip_mask;
int ret;
@@ -10891,8 +10891,8 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_engine_cs *ring = req->ring;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_ringbuffer *ring = req->ringbuf;
+ struct drm_i915_private *dev_priv = req->i915;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t pf, pipesrc;
int ret;
@@ -10930,8 +10930,8 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_engine_cs *ring = req->ring;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_ringbuffer *ring = req->ringbuf;
+ struct drm_i915_private *dev_priv = req->i915;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t pf, pipesrc;
int ret;
@@ -10966,7 +10966,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t plane_bit = 0;
int len, ret;
@@ -10987,14 +10987,14 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
}
len = 4;
- if (ring->id == RCS) {
+ if (req->ring->id == RCS) {
len += 6;
/*
* On Gen 8, SRM is now taking an extra dword to accommodate
* 48bits addresses, and we need a NOOP for the batch size to
* stay even.
*/
- if (IS_GEN8(dev))
+ if (IS_GEN8(req->i915))
len += 2;
}
@@ -11025,21 +11025,21 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
* for the RCS also doesn't appear to drop events. Setting the DERRMR
* to zero does lead to lockups within MI_DISPLAY_FLIP.
*/
- if (ring->id == RCS) {
+ if (req->ring->id == RCS) {
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
intel_ring_emit(ring, DERRMR);
intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
DERRMR_PIPEB_PRI_FLIP_DONE |
DERRMR_PIPEC_PRI_FLIP_DONE));
- if (IS_GEN8(dev))
+ if (IS_GEN8(req->i915))
intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
MI_SRM_LRM_GLOBAL_GTT);
else
intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
MI_SRM_LRM_GLOBAL_GTT);
intel_ring_emit(ring, DERRMR);
- intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
- if (IS_GEN8(dev)) {
+ intel_ring_emit(ring, req->ring->scratch.gtt_offset + 256);
+ if (IS_GEN8(req->i915)) {
intel_ring_emit(ring, 0);
intel_ring_emit(ring, MI_NOOP);
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index cfa77a59b352..0db23c474045 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -700,11 +700,9 @@ static int logical_ring_wait_for_space(struct drm_i915_gem_request *req,
static void
intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
{
- struct intel_engine_cs *ring = request->ring;
-
- intel_logical_ring_advance(request->ringbuf);
+ intel_ring_advance(request->ringbuf);
- if (intel_ring_stopped(ring))
+ if (intel_ring_stopped(request->ring))
return;
execlists_context_queue(request);
@@ -887,11 +885,11 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
if (ret)
return ret;
- intel_logical_ring_emit(ringbuf, MI_NOOP);
- intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
- intel_logical_ring_emit(ringbuf, INSTPM);
- intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
- intel_logical_ring_advance(ringbuf);
+ intel_ring_emit(ringbuf, MI_NOOP);
+ intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
+ intel_ring_emit(ringbuf, INSTPM);
+ intel_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
+ intel_ring_advance(ringbuf);
dev_priv->relative_constants_mode = instp_mode;
}
@@ -1041,14 +1039,14 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
if (ret)
return ret;
- intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
+ intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
for (i = 0; i < w->count; i++) {
- intel_logical_ring_emit(ringbuf, w->reg[i].addr);
- intel_logical_ring_emit(ringbuf, w->reg[i].value);
+ intel_ring_emit(ringbuf, w->reg[i].addr);
+ intel_ring_emit(ringbuf, w->reg[i].value);
}
- intel_logical_ring_emit(ringbuf, MI_NOOP);
+ intel_ring_emit(ringbuf, MI_NOOP);
- intel_logical_ring_advance(ringbuf);
+ intel_ring_advance(ringbuf);
ring->gpu_caches_dirty = true;
ret = logical_ring_flush_all_caches(req);
@@ -1478,18 +1476,18 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
if (ret)
return ret;
- intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
+ intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
- intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i));
- intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
- intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i));
- intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
+ intel_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i));
+ intel_ring_emit(ringbuf, upper_32_bits(pd_daddr));
+ intel_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i));
+ intel_ring_emit(ringbuf, lower_32_bits(pd_daddr));
}
- intel_logical_ring_emit(ringbuf, MI_NOOP);
- intel_logical_ring_advance(ringbuf);
+ intel_ring_emit(ringbuf, MI_NOOP);
+ intel_ring_advance(ringbuf);
return 0;
}
@@ -1523,14 +1521,14 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
return ret;
/* FIXME(BDW): Address space and security selectors. */
- intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
- (ppgtt<<8) |
- (dispatch_flags & I915_DISPATCH_RS ?
- MI_BATCH_RESOURCE_STREAMER : 0));
- intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
- intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
- intel_logical_ring_emit(ringbuf, MI_NOOP);
- intel_logical_ring_advance(ringbuf);
+ intel_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
+ (ppgtt<<8) |
+ (dispatch_flags & I915_DISPATCH_RS ?
+ MI_BATCH_RESOURCE_STREAMER : 0));
+ intel_ring_emit(ringbuf, lower_32_bits(offset));
+ intel_ring_emit(ringbuf, upper_32_bits(offset));
+ intel_ring_emit(ringbuf, MI_NOOP);
+ intel_ring_advance(ringbuf);
return 0;
}
@@ -1598,13 +1596,13 @@ static int gen8_emit_flush(struct drm_i915_gem_request *request,
cmd |= MI_INVALIDATE_BSD;
}
- intel_logical_ring_emit(ringbuf, cmd);
- intel_logical_ring_emit(ringbuf,
- I915_GEM_HWS_SCRATCH_ADDR |
- MI_FLUSH_DW_USE_GTT);
- intel_logical_ring_emit(ringbuf, 0); /* upper addr */
- intel_logical_ring_emit(ringbuf, 0); /* value */
- intel_logical_ring_advance(ringbuf);
+ intel_ring_emit(ringbuf, cmd);
+ intel_ring_emit(ringbuf,
+ I915_GEM_HWS_SCRATCH_ADDR |
+ MI_FLUSH_DW_USE_GTT);
+ intel_ring_emit(ringbuf, 0); /* upper addr */
+ intel_ring_emit(ringbuf, 0); /* value */
+ intel_ring_advance(ringbuf);
return 0;
}
@@ -1651,21 +1649,21 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
return ret;
if (vf_flush_wa) {
- intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, 0);
+ intel_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
+ intel_ring_emit(ringbuf, 0);
+ intel_ring_emit(ringbuf, 0);
+ intel_ring_emit(ringbuf, 0);
+ intel_ring_emit(ringbuf, 0);
+ intel_ring_emit(ringbuf, 0);
}
- intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
- intel_logical_ring_emit(ringbuf, flags);
- intel_logical_ring_emit(ringbuf, scratch_addr);
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_advance(ringbuf);
+ intel_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
+ intel_ring_emit(ringbuf, flags);
+ intel_ring_emit(ringbuf, scratch_addr);
+ intel_ring_emit(ringbuf, 0);
+ intel_ring_emit(ringbuf, 0);
+ intel_ring_emit(ringbuf, 0);
+ intel_ring_advance(ringbuf);
return 0;
}
@@ -1699,23 +1697,23 @@ static int gen8_emit_request(struct drm_i915_gem_request *request)
cmd = MI_STORE_DWORD_IMM_GEN4;
cmd |= MI_GLOBAL_GTT;
- intel_logical_ring_emit(ringbuf, cmd);
- intel_logical_ring_emit(ringbuf,
- (ring->status_page.gfx_addr +
- (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
- intel_logical_ring_emit(ringbuf, 0);
- intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
- intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
- intel_logical_ring_emit(ringbuf, MI_NOOP);
+ intel_ring_emit(ringbuf, cmd);
+ intel_ring_emit(ringbuf,
+ (ring->status_page.gfx_addr +
+ (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
+ intel_ring_emit(ringbuf, 0);
+ intel_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
+ intel_ring_emit(ringbuf, MI_USER_INTERRUPT);
+ intel_ring_emit(ringbuf, MI_NOOP);
intel_logical_ring_advance_and_submit(request);
/*
* Here we add two extra NOOPs as padding to avoid
* lite restore of a context with HEAD==TAIL.
*/
- intel_logical_ring_emit(ringbuf, MI_NOOP);
- intel_logical_ring_emit(ringbuf, MI_NOOP);
- intel_logical_ring_advance(ringbuf);
+ intel_ring_emit(ringbuf, MI_NOOP);
+ intel_ring_emit(ringbuf, MI_NOOP);
+ intel_ring_advance(ringbuf);
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 8b56fb934763..861668919e5a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -45,27 +45,6 @@ int intel_logical_rings_init(struct drm_device *dev);
int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords);
int logical_ring_flush_all_caches(struct drm_i915_gem_request *req);
-/**
- * intel_logical_ring_advance() - advance the ringbuffer tail
- * @ringbuf: Ringbuffer to advance.
- *
- * The tail is only updated in our logical ringbuffer struct.
- */
-static inline void intel_logical_ring_advance(struct intel_ringbuffer *ringbuf)
-{
- intel_ringbuffer_advance(ringbuf);
-}
-
-/**
- * intel_logical_ring_emit() - write a DWORD to the ringbuffer.
- * @ringbuf: Ringbuffer to write to.
- * @data: DWORD to write.
- */
-static inline void intel_logical_ring_emit(struct intel_ringbuffer *ringbuf,
- u32 data)
-{
- intel_ringbuffer_emit(ringbuf, data);
-}
/* Logical Ring Contexts */
void intel_lr_context_free(struct intel_context *ctx);
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 6d3c6c0a5c62..399a131a94b6 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -187,13 +187,11 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
return ret;
}
- intel_logical_ring_emit(ringbuf,
- MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
+ intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
for (index = 0; index < table->size; index++) {
- intel_logical_ring_emit(ringbuf, reg_base + index * 4);
- intel_logical_ring_emit(ringbuf,
- table->table[index].control_value);
+ intel_ring_emit(ringbuf, reg_base + index * 4);
+ intel_ring_emit(ringbuf, table->table[index].control_value);
}
/*
@@ -205,12 +203,12 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
* that value to all the used entries.
*/
for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
- intel_logical_ring_emit(ringbuf, reg_base + index * 4);
- intel_logical_ring_emit(ringbuf, table->table[0].control_value);
+ intel_ring_emit(ringbuf, reg_base + index * 4);
+ intel_ring_emit(ringbuf, table->table[0].control_value);
}
- intel_logical_ring_emit(ringbuf, MI_NOOP);
- intel_logical_ring_advance(ringbuf);
+ intel_ring_emit(ringbuf, MI_NOOP);
+ intel_ring_advance(ringbuf);
return 0;
}
@@ -246,15 +244,15 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
return ret;
}
- intel_logical_ring_emit(ringbuf,
+ intel_ring_emit(ringbuf,
MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2));
for (i = 0, count = 0; i < table->size / 2; i++, count += 2) {
value = (table->table[count].l3cc_value & 0xffff) |
((table->table[count + 1].l3cc_value & 0xffff) << 16);
- intel_logical_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);
- intel_logical_ring_emit(ringbuf, value);
+ intel_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);
+ intel_ring_emit(ringbuf, value);
}
if (table->size & 0x01) {
@@ -270,14 +268,14 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
* they are reserved by the hardware.
*/
for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
- intel_logical_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);
- intel_logical_ring_emit(ringbuf, value);
+ intel_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);
+ intel_ring_emit(ringbuf, value);
value = filler;
}
- intel_logical_ring_emit(ringbuf, MI_NOOP);
- intel_logical_ring_advance(ringbuf);
+ intel_ring_emit(ringbuf, MI_NOOP);
+ intel_ring_advance(ringbuf);
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 444542696a2c..5e9c7c15a84b 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -252,11 +252,11 @@ static int intel_overlay_on(struct intel_overlay *overlay)
overlay->active = true;
- intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
- intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE);
- intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
- intel_ring_emit(ring, MI_NOOP);
- intel_ring_advance(ring);
+ intel_ring_emit(req->ringbuf, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
+ intel_ring_emit(req->ringbuf, overlay->flip_addr | OFC_UPDATE);
+ intel_ring_emit(req->ringbuf, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
+ intel_ring_emit(req->ringbuf, MI_NOOP);
+ intel_ring_advance(req->ringbuf);
return intel_overlay_do_wait_request(overlay, req, NULL);
}
@@ -293,9 +293,9 @@ static int intel_overlay_continue(struct intel_overlay *overlay,
return ret;
}
- intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
- intel_ring_emit(ring, flip_addr);
- intel_ring_advance(ring);
+ intel_ring_emit(req->ringbuf, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
+ intel_ring_emit(req->ringbuf, flip_addr);
+ intel_ring_advance(req->ringbuf);
WARN_ON(overlay->last_flip_req);
i915_gem_request_assign(&overlay->last_flip_req, req);
@@ -360,22 +360,22 @@ static int intel_overlay_off(struct intel_overlay *overlay)
}
/* wait for overlay to go idle */
- intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
- intel_ring_emit(ring, flip_addr);
- intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
+ intel_ring_emit(req->ringbuf, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
+ intel_ring_emit(req->ringbuf, flip_addr);
+ intel_ring_emit(req->ringbuf, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
/* turn overlay off */
if (IS_I830(dev)) {
/* Workaround: Don't disable the overlay fully, since otherwise
* it dies on the next OVERLAY_ON cmd. */
- intel_ring_emit(ring, MI_NOOP);
- intel_ring_emit(ring, MI_NOOP);
- intel_ring_emit(ring, MI_NOOP);
+ intel_ring_emit(req->ringbuf, MI_NOOP);
+ intel_ring_emit(req->ringbuf, MI_NOOP);
+ intel_ring_emit(req->ringbuf, MI_NOOP);
} else {
- intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
- intel_ring_emit(ring, flip_addr);
- intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
+ intel_ring_emit(req->ringbuf, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
+ intel_ring_emit(req->ringbuf, flip_addr);
+ intel_ring_emit(req->ringbuf, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
}
- intel_ring_advance(ring);
+ intel_ring_advance(req->ringbuf);
return intel_overlay_do_wait_request(overlay, req, intel_overlay_off_tail);
}
@@ -433,9 +433,9 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
return ret;
}
- intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
- intel_ring_emit(ring, MI_NOOP);
- intel_ring_advance(ring);
+ intel_ring_emit(req->ringbuf, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
+ intel_ring_emit(req->ringbuf, MI_NOOP);
+ intel_ring_advance(req->ringbuf);
ret = intel_overlay_do_wait_request(overlay, req,
intel_overlay_release_old_vid_tail);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 9fbe730aae47..b3de8b1fde2f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -95,7 +95,7 @@ gen2_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains,
u32 flush_domains)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
u32 cmd;
int ret;
@@ -122,7 +122,7 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains,
u32 flush_domains)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
u32 cmd;
int ret;
@@ -215,8 +215,8 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
static int
intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *ring = req->ring;
- u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
+ struct intel_ringbuffer *ring = req->ringbuf;
+ u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
int ret;
ret = intel_ring_begin(req, 6);
@@ -251,9 +251,9 @@ static int
gen6_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains, u32 flush_domains)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
u32 flags = 0;
- u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
+ u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
int ret;
/* Force SNB workarounds for PIPE_CONTROL flushes */
@@ -303,7 +303,7 @@ gen6_render_ring_flush(struct drm_i915_gem_request *req,
static int
gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
ret = intel_ring_begin(req, 4);
@@ -324,9 +324,9 @@ static int
gen7_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains, u32 flush_domains)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
u32 flags = 0;
- u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
+ u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
int ret;
/*
@@ -387,7 +387,7 @@ static int
gen8_emit_pipe_control(struct drm_i915_gem_request *req,
u32 flags, u32 scratch_addr)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
ret = intel_ring_begin(req, 6);
@@ -712,15 +712,15 @@ err:
static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
{
- int ret, i;
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
struct drm_i915_private *dev_priv = req->i915;
struct i915_workarounds *w = &dev_priv->workarounds;
+ int ret, i;
if (WARN_ON_ONCE(w->count == 0))
return 0;
- ring->gpu_caches_dirty = true;
+ req->ring->gpu_caches_dirty = true;
ret = intel_ring_flush_all_caches(req);
if (ret)
return ret;
@@ -738,7 +738,7 @@ static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
intel_ring_advance(ring);
- ring->gpu_caches_dirty = true;
+ req->ring->gpu_caches_dirty = true;
ret = intel_ring_flush_all_caches(req);
if (ret)
return ret;
@@ -1184,7 +1184,7 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
unsigned int num_dwords)
{
#define MBOX_UPDATE_DWORDS 8
- struct intel_engine_cs *signaller = signaller_req->ring;
+ struct intel_ringbuffer *signaller = signaller_req->ringbuf;
struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *waiter;
int i, ret, num_rings;
@@ -1199,7 +1199,7 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
for_each_ring(waiter, dev_priv, i) {
u32 seqno;
- u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
+ u64 gtt_offset = signaller_req->ring->semaphore.signal_ggtt[i];
if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
continue;
@@ -1224,7 +1224,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
unsigned int num_dwords)
{
#define MBOX_UPDATE_DWORDS 6
- struct intel_engine_cs *signaller = signaller_req->ring;
+ struct intel_ringbuffer *signaller = signaller_req->ringbuf;
struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *waiter;
int i, ret, num_rings;
@@ -1239,7 +1239,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
for_each_ring(waiter, dev_priv, i) {
u32 seqno;
- u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
+ u64 gtt_offset = signaller_req->ring->semaphore.signal_ggtt[i];
if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
continue;
@@ -1261,7 +1261,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
static int gen6_signal(struct drm_i915_gem_request *signaller_req,
unsigned int num_dwords)
{
- struct intel_engine_cs *signaller = signaller_req->ring;
+ struct intel_ringbuffer *signaller = signaller_req->ringbuf;
struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *useless;
int i, ret, num_rings;
@@ -1276,7 +1276,7 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
return ret;
for_each_ring(useless, dev_priv, i) {
- u32 mbox_reg = signaller->semaphore.mbox.signal[i];
+ u32 mbox_reg = signaller_req->ring->semaphore.mbox.signal[i];
if (mbox_reg != GEN6_NOSYNC) {
u32 seqno = i915_gem_request_get_seqno(signaller_req);
intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
@@ -1303,11 +1303,11 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
static int
gen6_add_request(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
- if (ring->semaphore.signal)
- ret = ring->semaphore.signal(req, 4);
+ if (req->ring->semaphore.signal)
+ ret = req->ring->semaphore.signal(req, 4);
else
ret = intel_ring_begin(req, 4);
@@ -1318,15 +1318,14 @@ gen6_add_request(struct drm_i915_gem_request *req)
intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
intel_ring_emit(ring, i915_gem_request_get_seqno(req));
intel_ring_emit(ring, MI_USER_INTERRUPT);
- __intel_ring_advance(ring);
+ __intel_ring_advance(req->ring);
return 0;
}
-static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
+static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv,
u32 seqno)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
return dev_priv->last_seqno < seqno;
}
@@ -1343,7 +1342,7 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
struct intel_engine_cs *signaller,
u32 seqno)
{
- struct intel_engine_cs *waiter = waiter_req->ring;
+ struct intel_ringbuffer *waiter = waiter_req->ringbuf;
struct drm_i915_private *dev_priv = waiter_req->i915;
int ret;
@@ -1357,9 +1356,11 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
MI_SEMAPHORE_SAD_GTE_SDD);
intel_ring_emit(waiter, seqno);
intel_ring_emit(waiter,
- lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
+ lower_32_bits(GEN8_WAIT_OFFSET(waiter_req->ring,
+ signaller->id)));
intel_ring_emit(waiter,
- upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
+ upper_32_bits(GEN8_WAIT_OFFSET(waiter_req->ring,
+ signaller->id)));
intel_ring_advance(waiter);
return 0;
}
@@ -1369,11 +1370,11 @@ gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
struct intel_engine_cs *signaller,
u32 seqno)
{
- struct intel_engine_cs *waiter = waiter_req->ring;
+ struct intel_ringbuffer *waiter = waiter_req->ringbuf;
u32 dw1 = MI_SEMAPHORE_MBOX |
MI_SEMAPHORE_COMPARE |
MI_SEMAPHORE_REGISTER;
- u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
+ u32 wait_mbox = signaller->semaphore.mbox.wait[waiter_req->ring->id];
int ret;
/* Throughout all of the GEM code, seqno passed implies our current
@@ -1389,7 +1390,7 @@ gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
return ret;
/* If seqno wrap happened, omit the wait with no-ops */
- if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
+ if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) {
intel_ring_emit(waiter, dw1 | wait_mbox);
intel_ring_emit(waiter, seqno);
intel_ring_emit(waiter, 0);
@@ -1417,8 +1418,8 @@ do { \
static int
pc_render_add_request(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *ring = req->ring;
- u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
+ struct intel_ringbuffer *ring = req->ringbuf;
+ u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
int ret;
/* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
@@ -1436,7 +1437,7 @@ pc_render_add_request(struct drm_i915_gem_request *req)
intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
PIPE_CONTROL_WRITE_FLUSH |
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
- intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
+ intel_ring_emit(ring, req->ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
intel_ring_emit(ring, i915_gem_request_get_seqno(req));
intel_ring_emit(ring, 0);
PIPE_CONTROL_FLUSH(ring, scratch_addr);
@@ -1455,10 +1456,10 @@ pc_render_add_request(struct drm_i915_gem_request *req)
PIPE_CONTROL_WRITE_FLUSH |
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_NOTIFY);
- intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
+ intel_ring_emit(ring, req->ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
intel_ring_emit(ring, i915_gem_request_get_seqno(req));
intel_ring_emit(ring, 0);
- __intel_ring_advance(ring);
+ __intel_ring_advance(req->ring);
return 0;
}
@@ -1611,7 +1612,7 @@ bsd_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains,
u32 flush_domains)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
ret = intel_ring_begin(req, 2);
@@ -1627,7 +1628,7 @@ bsd_ring_flush(struct drm_i915_gem_request *req,
static int
i9xx_add_request(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
ret = intel_ring_begin(req, 4);
@@ -1638,7 +1639,7 @@ i9xx_add_request(struct drm_i915_gem_request *req)
intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
intel_ring_emit(ring, i915_gem_request_get_seqno(req));
intel_ring_emit(ring, MI_USER_INTERRUPT);
- __intel_ring_advance(ring);
+ __intel_ring_advance(req->ring);
return 0;
}
@@ -1772,7 +1773,7 @@ i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 length,
unsigned dispatch_flags)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
ret = intel_ring_begin(req, 2);
@@ -1799,8 +1800,8 @@ i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_engine_cs *ring = req->ring;
- u32 cs_offset = ring->scratch.gtt_offset;
+ struct intel_ringbuffer *ring = req->ringbuf;
+ u32 cs_offset = req->ring->scratch.gtt_offset;
int ret;
ret = intel_ring_begin(req, 6);
@@ -1862,7 +1863,7 @@ i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
ret = intel_ring_begin(req, 2);
@@ -2343,8 +2344,8 @@ int intel_ring_begin(struct drm_i915_gem_request *req,
/* Align the ring tail to a cacheline boundary */
int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *ring = req->ring;
- int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
+ struct intel_ringbuffer *ring = req->ringbuf;
+ int num_dwords = (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
int ret;
if (num_dwords == 0)
@@ -2415,7 +2416,7 @@ static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate, u32 flush)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
uint32_t cmd;
int ret;
@@ -2424,7 +2425,7 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
return ret;
cmd = MI_FLUSH_DW;
- if (INTEL_INFO(ring->dev)->gen >= 8)
+ if (INTEL_INFO(req->i915)->gen >= 8)
cmd += 1;
/* We always require a command barrier so that subsequent
@@ -2445,7 +2446,7 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
intel_ring_emit(ring, cmd);
intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
- if (INTEL_INFO(ring->dev)->gen >= 8) {
+ if (INTEL_INFO(req->i915)->gen >= 8) {
intel_ring_emit(ring, 0); /* upper addr */
intel_ring_emit(ring, 0); /* value */
} else {
@@ -2461,7 +2462,7 @@ gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
bool ppgtt = USES_PPGTT(req->i915) &&
!(dispatch_flags & I915_DISPATCH_SECURE);
int ret;
@@ -2487,7 +2488,7 @@ hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
ret = intel_ring_begin(req, 2);
@@ -2512,7 +2513,7 @@ gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
int ret;
ret = intel_ring_begin(req, 2);
@@ -2535,7 +2536,7 @@ gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
static int gen6_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate, u32 flush)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_ringbuffer *ring = req->ringbuf;
uint32_t cmd;
int ret;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 10f80df5f121..212b402818f9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -427,25 +427,16 @@ int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);
int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n);
int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
-static inline void intel_ringbuffer_emit(struct intel_ringbuffer *rb,
- u32 data)
+static inline void intel_ring_emit(struct intel_ringbuffer *rb,
+ u32 data)
{
*(uint32_t *)(rb->virtual_start + rb->tail) = data;
rb->tail += 4;
}
-static inline void intel_ringbuffer_advance(struct intel_ringbuffer *rb)
+static inline void intel_ring_advance(struct intel_ringbuffer *rb)
{
rb->tail &= rb->size - 1;
}
-static inline void intel_ring_emit(struct intel_engine_cs *ring,
- u32 data)
-{
- intel_ringbuffer_emit(ring->buffer, data);
-}
-static inline void intel_ring_advance(struct intel_engine_cs *ring)
-{
- intel_ringbuffer_advance(ring->buffer);
-}
int __intel_ring_space(int head, int tail, int size);
void intel_ring_update_space(struct intel_ringbuffer *ringbuf);
int intel_ring_space(struct intel_ringbuffer *ringbuf);
--
2.6.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 04/12] drm/i915: Unify intel_ring_begin()
2015-11-20 12:43 [PATCH 01/12] drm/i915: Convert i915_semaphores_is_enabled over to drm_i915_private Chris Wilson
2015-11-20 12:43 ` [PATCH 02/12] drm/i915: Use the new rq->i915 field where appropriate Chris Wilson
2015-11-20 12:43 ` [PATCH 03/12] drm/i915: Unify intel_logical_ring_emit and intel_ring_emit Chris Wilson
@ 2015-11-20 12:43 ` Chris Wilson
2015-11-24 14:38 ` Daniel Vetter
2015-11-20 12:43 ` [PATCH 05/12] drm/i915: Remove the identical implementations of request space reservation Chris Wilson
` (8 subsequent siblings)
11 siblings, 1 reply; 41+ messages in thread
From: Chris Wilson @ 2015-11-20 12:43 UTC (permalink / raw)
To: intel-gfx
Combine the near identical implementations of intel_logical_ring_begin()
and intel_ring_begin() - the only difference is that the logical wait
has to check for a matching ring (which is assumed by legacy).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_lrc.c | 149 ++------------------------------
drivers/gpu/drm/i915/intel_lrc.h | 1 -
drivers/gpu/drm/i915/intel_mocs.c | 12 +--
drivers/gpu/drm/i915/intel_ringbuffer.c | 115 ++++++++++++------------
4 files changed, 71 insertions(+), 206 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0db23c474045..02f798e4c726 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -646,48 +646,6 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request
return 0;
}
-static int logical_ring_wait_for_space(struct drm_i915_gem_request *req,
- int bytes)
-{
- struct intel_ringbuffer *ringbuf = req->ringbuf;
- struct intel_engine_cs *ring = req->ring;
- struct drm_i915_gem_request *target;
- unsigned space;
- int ret;
-
- if (intel_ring_space(ringbuf) >= bytes)
- return 0;
-
- /* The whole point of reserving space is to not wait! */
- WARN_ON(ringbuf->reserved_in_use);
-
- list_for_each_entry(target, &ring->request_list, list) {
- /*
- * The request queue is per-engine, so can contain requests
- * from multiple ringbuffers. Here, we must ignore any that
- * aren't from the ringbuffer we're considering.
- */
- if (target->ringbuf != ringbuf)
- continue;
-
- /* Would completion of this request free enough space? */
- space = __intel_ring_space(target->postfix, ringbuf->tail,
- ringbuf->size);
- if (space >= bytes)
- break;
- }
-
- if (WARN_ON(&target->list == &ring->request_list))
- return -ENOSPC;
-
- ret = i915_wait_request(target);
- if (ret)
- return ret;
-
- ringbuf->space = space;
- return 0;
-}
-
/*
* intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
* @request: Request to advance the logical ringbuffer of.
@@ -708,97 +666,6 @@ intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
execlists_context_queue(request);
}
-static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
-{
- int rem = ringbuf->size - ringbuf->tail;
- memset(ringbuf->virtual_start + ringbuf->tail, 0, rem);
-
- ringbuf->tail = 0;
- intel_ring_update_space(ringbuf);
-}
-
-static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes)
-{
- struct intel_ringbuffer *ringbuf = req->ringbuf;
- int remain_usable = ringbuf->effective_size - ringbuf->tail;
- int remain_actual = ringbuf->size - ringbuf->tail;
- int ret, total_bytes, wait_bytes = 0;
- bool need_wrap = false;
-
- if (ringbuf->reserved_in_use)
- total_bytes = bytes;
- else
- total_bytes = bytes + ringbuf->reserved_size;
-
- if (unlikely(bytes > remain_usable)) {
- /*
- * Not enough space for the basic request. So need to flush
- * out the remainder and then wait for base + reserved.
- */
- wait_bytes = remain_actual + total_bytes;
- need_wrap = true;
- } else {
- if (unlikely(total_bytes > remain_usable)) {
- /*
- * The base request will fit but the reserved space
- * falls off the end. So only need to to wait for the
- * reserved size after flushing out the remainder.
- */
- wait_bytes = remain_actual + ringbuf->reserved_size;
- need_wrap = true;
- } else if (total_bytes > ringbuf->space) {
- /* No wrapping required, just waiting. */
- wait_bytes = total_bytes;
- }
- }
-
- if (wait_bytes) {
- ret = logical_ring_wait_for_space(req, wait_bytes);
- if (unlikely(ret))
- return ret;
-
- if (need_wrap)
- __wrap_ring_buffer(ringbuf);
- }
-
- return 0;
-}
-
-/**
- * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
- *
- * @request: The request to start some new work for
- * @ctx: Logical ring context whose ringbuffer is being prepared.
- * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
- *
- * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
- * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
- * and also preallocates a request (every workload submission is still mediated through
- * requests, same as it did with legacy ringbuffer submission).
- *
- * Return: non-zero if the ringbuffer is not ready to be written to.
- */
-int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
-{
- struct drm_i915_private *dev_priv;
- int ret;
-
- WARN_ON(req == NULL);
- dev_priv = req->i915;
-
- ret = i915_gem_check_wedge(&dev_priv->gpu_error,
- dev_priv->mm.interruptible);
- if (ret)
- return ret;
-
- ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t));
- if (ret)
- return ret;
-
- req->ringbuf->space -= num_dwords * sizeof(uint32_t);
- return 0;
-}
-
int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
{
/*
@@ -811,7 +678,7 @@ int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
*/
intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
- return intel_logical_ring_begin(request, 0);
+ return intel_ring_begin(request, 0);
}
/**
@@ -881,7 +748,7 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
if (ring == &dev_priv->ring[RCS] &&
instp_mode != dev_priv->relative_constants_mode) {
- ret = intel_logical_ring_begin(params->request, 4);
+ ret = intel_ring_begin(params->request, 4);
if (ret)
return ret;
@@ -1035,7 +902,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
if (ret)
return ret;
- ret = intel_logical_ring_begin(req, w->count * 2 + 2);
+ ret = intel_ring_begin(req, w->count * 2 + 2);
if (ret)
return ret;
@@ -1472,7 +1339,7 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
int i, ret;
- ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2);
+ ret = intel_ring_begin(req, num_lri_cmds * 2 + 2);
if (ret)
return ret;
@@ -1516,7 +1383,7 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring);
}
- ret = intel_logical_ring_begin(req, 4);
+ ret = intel_ring_begin(req, 4);
if (ret)
return ret;
@@ -1577,7 +1444,7 @@ static int gen8_emit_flush(struct drm_i915_gem_request *request,
uint32_t cmd;
int ret;
- ret = intel_logical_ring_begin(request, 4);
+ ret = intel_ring_begin(request, 4);
if (ret)
return ret;
@@ -1644,7 +1511,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
- ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6);
+ ret = intel_ring_begin(request, vf_flush_wa ? 12 : 6);
if (ret)
return ret;
@@ -1690,7 +1557,7 @@ static int gen8_emit_request(struct drm_i915_gem_request *request)
* used as a workaround for not being allowed to do lite
* restore with HEAD==TAIL (WaIdleLiteRestore).
*/
- ret = intel_logical_ring_begin(request, 8);
+ ret = intel_ring_begin(request, 8);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 861668919e5a..5402eca78a07 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -42,7 +42,6 @@ int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
void intel_logical_ring_stop(struct intel_engine_cs *ring);
void intel_logical_ring_cleanup(struct intel_engine_cs *ring);
int intel_logical_rings_init(struct drm_device *dev);
-int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords);
int logical_ring_flush_all_caches(struct drm_i915_gem_request *req);
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 399a131a94b6..ac0a982bbf55 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -181,11 +181,9 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
return -ENODEV;
- ret = intel_logical_ring_begin(req, 2 + 2 * GEN9_NUM_MOCS_ENTRIES);
- if (ret) {
- DRM_DEBUG("intel_logical_ring_begin failed %d\n", ret);
+ ret = intel_ring_begin(req, 2 + 2 * GEN9_NUM_MOCS_ENTRIES);
+ if (ret)
return ret;
- }
intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
@@ -238,11 +236,9 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
return -ENODEV;
- ret = intel_logical_ring_begin(req, 2 + GEN9_NUM_MOCS_ENTRIES);
- if (ret) {
- DRM_DEBUG("intel_logical_ring_begin failed %d\n", ret);
+ ret = intel_ring_begin(req, 2 + GEN9_NUM_MOCS_ENTRIES);
+ if (ret)
return ret;
- }
intel_ring_emit(ringbuf,
MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2));
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b3de8b1fde2f..fbee790ddaf0 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2143,46 +2143,6 @@ void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
ring->buffer = NULL;
}
-static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
-{
- struct intel_ringbuffer *ringbuf = ring->buffer;
- struct drm_i915_gem_request *request;
- unsigned space;
- int ret;
-
- if (intel_ring_space(ringbuf) >= n)
- return 0;
-
- /* The whole point of reserving space is to not wait! */
- WARN_ON(ringbuf->reserved_in_use);
-
- list_for_each_entry(request, &ring->request_list, list) {
- space = __intel_ring_space(request->postfix, ringbuf->tail,
- ringbuf->size);
- if (space >= n)
- break;
- }
-
- if (WARN_ON(&request->list == &ring->request_list))
- return -ENOSPC;
-
- ret = i915_wait_request(request);
- if (ret)
- return ret;
-
- ringbuf->space = space;
- return 0;
-}
-
-static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
-{
- int rem = ringbuf->size - ringbuf->tail;
- memset(ringbuf->virtual_start + ringbuf->tail, 0, rem);
-
- ringbuf->tail = 0;
- intel_ring_update_space(ringbuf);
-}
-
int intel_ring_idle(struct intel_engine_cs *ring)
{
struct drm_i915_gem_request *req;
@@ -2270,9 +2230,59 @@ void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
ringbuf->reserved_in_use = false;
}
-static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
+static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
{
- struct intel_ringbuffer *ringbuf = ring->buffer;
+ struct intel_ringbuffer *ringbuf = req->ringbuf;
+ struct intel_engine_cs *ring = req->ring;
+ struct drm_i915_gem_request *target;
+ unsigned space;
+ int ret;
+
+ if (intel_ring_space(ringbuf) >= bytes)
+ return 0;
+
+ /* The whole point of reserving space is to not wait! */
+ WARN_ON(ringbuf->reserved_in_use);
+
+ list_for_each_entry(target, &ring->request_list, list) {
+ /*
+ * The request queue is per-engine, so can contain requests
+ * from multiple ringbuffers. Here, we must ignore any that
+ * aren't from the ringbuffer we're considering.
+ */
+ if (target->ringbuf != ringbuf)
+ continue;
+
+ /* Would completion of this request free enough space? */
+ space = __intel_ring_space(target->postfix, ringbuf->tail,
+ ringbuf->size);
+ if (space >= bytes)
+ break;
+ }
+
+ if (WARN_ON(&target->list == &ring->request_list))
+ return -ENOSPC;
+
+ ret = i915_wait_request(target);
+ if (ret)
+ return ret;
+
+ ringbuf->space = space;
+ return 0;
+}
+
+static void ring_wrap(struct intel_ringbuffer *ringbuf)
+{
+ int rem = ringbuf->size - ringbuf->tail;
+ memset(ringbuf->virtual_start + ringbuf->tail, 0, rem);
+
+ ringbuf->tail = 0;
+ intel_ring_update_space(ringbuf);
+}
+
+static int ring_prepare(struct drm_i915_gem_request *req, int bytes)
+{
+ struct intel_ringbuffer *ringbuf = req->ringbuf;
int remain_usable = ringbuf->effective_size - ringbuf->tail;
int remain_actual = ringbuf->size - ringbuf->tail;
int ret, total_bytes, wait_bytes = 0;
@@ -2306,38 +2316,31 @@ static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
}
if (wait_bytes) {
- ret = ring_wait_for_space(ring, wait_bytes);
+ ret = wait_for_space(req, wait_bytes);
if (unlikely(ret))
return ret;
if (need_wrap)
- __wrap_ring_buffer(ringbuf);
+ ring_wrap(ringbuf);
}
return 0;
}
-int intel_ring_begin(struct drm_i915_gem_request *req,
- int num_dwords)
+int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
{
- struct intel_engine_cs *ring;
- struct drm_i915_private *dev_priv;
int ret;
- WARN_ON(req == NULL);
- ring = req->ring;
- dev_priv = req->i915;
-
- ret = i915_gem_check_wedge(&dev_priv->gpu_error,
- dev_priv->mm.interruptible);
+ ret = i915_gem_check_wedge(&req->i915->gpu_error,
+ req->i915->mm.interruptible);
if (ret)
return ret;
- ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
+ ret = ring_prepare(req, num_dwords * sizeof(uint32_t));
if (ret)
return ret;
- ring->buffer->space -= num_dwords * sizeof(uint32_t);
+ req->ringbuf->space -= num_dwords * sizeof(uint32_t);
return 0;
}
--
2.6.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 05/12] drm/i915: Remove the identical implementations of request space reservation
2015-11-20 12:43 [PATCH 01/12] drm/i915: Convert i915_semaphores_is_enabled over to drm_i915_private Chris Wilson
` (2 preceding siblings ...)
2015-11-20 12:43 ` [PATCH 04/12] drm/i915: Unify intel_ring_begin() Chris Wilson
@ 2015-11-20 12:43 ` Chris Wilson
2015-11-24 14:42 ` Daniel Vetter
2015-11-20 12:43 ` [PATCH 06/12] drm/i915: Rename request->ring to request->engine Chris Wilson
` (7 subsequent siblings)
11 siblings, 1 reply; 41+ messages in thread
From: Chris Wilson @ 2015-11-20 12:43 UTC (permalink / raw)
To: intel-gfx
Now that we share intel_ring_begin(), reserving space for the tail of
the request is identical between legacy/execlists and so the tautology
can be removed.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_gem.c | 7 +++----
drivers/gpu/drm/i915/intel_lrc.c | 15 ---------------
drivers/gpu/drm/i915/intel_lrc.h | 1 -
drivers/gpu/drm/i915/intel_ringbuffer.c | 15 ---------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 3 ---
5 files changed, 3 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c60105e36263..030fc9d14385 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2743,10 +2743,9 @@ int i915_gem_request_alloc(struct intel_engine_cs *ring,
* to be redone if the request is not actually submitted straight
* away, e.g. because a GPU scheduler has deferred it.
*/
- if (i915.enable_execlists)
- ret = intel_logical_ring_reserve_space(req);
- else
- ret = intel_ring_reserve_space(req);
+ intel_ring_reserved_space_reserve(req->ringbuf,
+ MIN_SPACE_FOR_ADD_REQUEST);
+ ret = intel_ring_begin(req, 0);
if (ret) {
/*
* At this point, the request is fully allocated even if not
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 02f798e4c726..2458804c521d 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -666,21 +666,6 @@ intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
execlists_context_queue(request);
}
-int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
-{
- /*
- * The first call merely notes the reserve request and is common for
- * all back ends. The subsequent localised _begin() call actually
- * ensures that the reservation is available. Without the begin, if
- * the request creator immediately submitted the request without
- * adding any commands to it then there might not actually be
- * sufficient room for the submission commands.
- */
- intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
-
- return intel_ring_begin(request, 0);
-}
-
/**
* execlists_submission() - submit a batchbuffer for execution, Execlists style
* @dev: DRM device.
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 5402eca78a07..9981e989fcaf 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -38,7 +38,6 @@
/* Logical Rings */
int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
-int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
void intel_logical_ring_stop(struct intel_engine_cs *ring);
void intel_logical_ring_cleanup(struct intel_engine_cs *ring);
int intel_logical_rings_init(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index fbee790ddaf0..9821c2a8074a 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2168,21 +2168,6 @@ int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
return 0;
}
-int intel_ring_reserve_space(struct drm_i915_gem_request *request)
-{
- /*
- * The first call merely notes the reserve request and is common for
- * all back ends. The subsequent localised _begin() call actually
- * ensures that the reservation is available. Without the begin, if
- * the request creator immediately submitted the request without
- * adding any commands to it then there might not actually be
- * sufficient room for the submission commands.
- */
- intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
-
- return intel_ring_begin(request, 0);
-}
-
void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
{
WARN_ON(ringbuf->reserved_size);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 212b402818f9..368d9b0454ed 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -487,7 +487,4 @@ void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf);
/* Finish with the reserved space - for use by i915_add_request() only. */
void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf);
-/* Legacy ringbuffer specific portion of reservation code: */
-int intel_ring_reserve_space(struct drm_i915_gem_request *request);
-
#endif /* _INTEL_RINGBUFFER_H_ */
--
2.6.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 06/12] drm/i915: Rename request->ring to request->engine
2015-11-20 12:43 [PATCH 01/12] drm/i915: Convert i915_semaphores_is_enabled over to drm_i915_private Chris Wilson
` (3 preceding siblings ...)
2015-11-20 12:43 ` [PATCH 05/12] drm/i915: Remove the identical implementations of request space reservation Chris Wilson
@ 2015-11-20 12:43 ` Chris Wilson
2015-11-24 14:48 ` Daniel Vetter
2015-11-20 12:43 ` [PATCH 07/12] drm/i915: Rename request->ringbuf to request->ring Chris Wilson
` (6 subsequent siblings)
11 siblings, 1 reply; 41+ messages in thread
From: Chris Wilson @ 2015-11-20 12:43 UTC (permalink / raw)
To: intel-gfx
In order to disambiguate between the pointer to the intel_engine_cs
(called ring) and the intel_ringbuffer (called ringbuf), rename
s/ring/engine/.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 11 ++-
drivers/gpu/drm/i915/i915_drv.h | 12 +--
drivers/gpu/drm/i915/i915_gem.c | 76 ++++++++--------
drivers/gpu/drm/i915/i915_gem_context.c | 63 ++++++-------
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 49 +++++-----
drivers/gpu/drm/i915/i915_gem_render_state.c | 18 ++--
drivers/gpu/drm/i915/i915_gpu_error.c | 3 +-
drivers/gpu/drm/i915/i915_trace.h | 34 +++----
drivers/gpu/drm/i915/intel_display.c | 12 +--
drivers/gpu/drm/i915/intel_lrc.c | 128 +++++++++++++--------------
drivers/gpu/drm/i915/intel_mocs.c | 10 +--
drivers/gpu/drm/i915/intel_ringbuffer.c | 66 +++++++-------
13 files changed, 239 insertions(+), 251 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 359436162f3d..56375c36b381 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -190,8 +190,7 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
seq_printf(m, " (%s mappable)", s);
}
if (obj->last_write_req != NULL)
- seq_printf(m, " (%s)",
- i915_gem_request_get_ring(obj->last_write_req)->name);
+ seq_printf(m, " (%s)", obj->last_write_req->engine->name);
if (obj->frontbuffer_bits)
seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
}
@@ -594,14 +593,14 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data)
pipe, plane);
}
if (work->flip_queued_req) {
- struct intel_engine_cs *ring =
- i915_gem_request_get_ring(work->flip_queued_req);
+ struct intel_engine_cs *engine =
+ work->flip_queued_req->engine;
seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
- ring->name,
+ engine->name,
i915_gem_request_get_seqno(work->flip_queued_req),
dev_priv->next_seqno,
- ring->get_seqno(ring, true),
+ engine->get_seqno(engine, true),
i915_gem_request_completed(work->flip_queued_req, true));
} else
seq_printf(m, "Flip not associated with any ring\n");
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fadf2ceb1f72..9ce8b3fcb3a0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2156,7 +2156,7 @@ struct drm_i915_gem_request {
/** On Which ring this request was generated */
struct drm_i915_private *i915;
- struct intel_engine_cs *ring;
+ struct intel_engine_cs *engine;
/** GEM sequence number associated with this request. */
uint32_t seqno;
@@ -2240,9 +2240,9 @@ i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
}
static inline struct intel_engine_cs *
-i915_gem_request_get_ring(struct drm_i915_gem_request *req)
+i915_gem_request_get_engine(struct drm_i915_gem_request *req)
{
- return req ? req->ring : NULL;
+ return req ? req->engine : NULL;
}
static inline struct drm_i915_gem_request *
@@ -2256,7 +2256,7 @@ i915_gem_request_reference(struct drm_i915_gem_request *req)
static inline void
i915_gem_request_unreference(struct drm_i915_gem_request *req)
{
- WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
+ WARN_ON(!mutex_is_locked(&req->i915->dev->struct_mutex));
kref_put(&req->ref, i915_gem_request_free);
}
@@ -2268,7 +2268,7 @@ i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
if (!req)
return;
- dev = req->ring->dev;
+ dev = req->i915->dev;
if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
mutex_unlock(&dev->struct_mutex);
}
@@ -2877,7 +2877,7 @@ static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
BUG_ON(req == NULL);
- seqno = req->ring->get_seqno(req->ring, lazy_coherency);
+ seqno = req->engine->get_seqno(req->engine, lazy_coherency);
return i915_seqno_passed(seqno, req->seqno);
}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 030fc9d14385..5a1b51a27fe3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1174,7 +1174,7 @@ static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
u64 timeout;
unsigned cpu;
- if (i915_gem_request_get_ring(req)->irq_refcount)
+ if (req->engine->irq_refcount)
return -EBUSY;
timeout = local_clock_us(&cpu) + 2;
@@ -1220,10 +1220,10 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
s64 *timeout,
struct intel_rps_client *rps)
{
- struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
+ struct intel_engine_cs *engine = req->engine;
struct drm_i915_private *dev_priv = req->i915;
const bool irq_test_in_progress =
- ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
+ ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(engine);
int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
DEFINE_WAIT(wait);
unsigned long timeout_expire;
@@ -1252,7 +1252,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
if (ret == 0)
goto out;
- if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) {
+ if (!irq_test_in_progress && WARN_ON(!engine->irq_get(engine))) {
ret = -ENODEV;
goto out;
}
@@ -1260,7 +1260,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
for (;;) {
struct timer_list timer;
- prepare_to_wait(&ring->irq_queue, &wait, state);
+ prepare_to_wait(&engine->irq_queue, &wait, state);
/* We need to check whether any gpu reset happened in between
* the caller grabbing the seqno and now ... */
@@ -1289,11 +1289,11 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
}
timer.function = NULL;
- if (timeout || missed_irq(dev_priv, ring)) {
+ if (timeout || missed_irq(dev_priv, engine)) {
unsigned long expire;
setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
- expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
+ expire = missed_irq(dev_priv, engine) ? jiffies + 1 : timeout_expire;
mod_timer(&timer, expire);
}
@@ -1305,9 +1305,9 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
}
}
if (!irq_test_in_progress)
- ring->irq_put(ring);
+ engine->irq_put(engine);
- finish_wait(&ring->irq_queue, &wait);
+ finish_wait(&engine->irq_queue, &wait);
out:
now = ktime_get_raw_ns();
@@ -1397,7 +1397,7 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request)
static void
__i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *engine = req->ring;
+ struct intel_engine_cs *engine = req->engine;
struct drm_i915_gem_request *tmp;
lockdep_assert_held(&engine->dev->struct_mutex);
@@ -1466,7 +1466,7 @@ i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
if (ret)
return ret;
- i = obj->last_write_req->ring->id;
+ i = obj->last_write_req->engine->id;
if (obj->last_read_req[i] == obj->last_write_req)
i915_gem_object_retire__read(obj, i);
else
@@ -1493,7 +1493,7 @@ static void
i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
struct drm_i915_gem_request *req)
{
- int ring = req->ring->id;
+ int ring = req->engine->id;
if (obj->last_read_req[ring] == req)
i915_gem_object_retire__read(obj, ring);
@@ -2415,17 +2415,15 @@ void i915_vma_move_to_active(struct i915_vma *vma,
struct drm_i915_gem_request *req)
{
struct drm_i915_gem_object *obj = vma->obj;
- struct intel_engine_cs *ring;
-
- ring = i915_gem_request_get_ring(req);
+ struct intel_engine_cs *engine = req->engine;;
/* Add a reference if we're newly entering the active list. */
if (obj->active == 0)
drm_gem_object_reference(&obj->base);
- obj->active |= intel_ring_flag(ring);
+ obj->active |= intel_ring_flag(engine);
- list_move_tail(&obj->ring_list[ring->id], &ring->active_list);
- i915_gem_request_assign(&obj->last_read_req[ring->id], req);
+ list_move_tail(&obj->ring_list[engine->id], &engine->active_list);
+ i915_gem_request_assign(&obj->last_read_req[engine->id], req);
list_move_tail(&vma->mm_list, &vma->vm->active_list);
}
@@ -2434,7 +2432,7 @@ static void
i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
{
RQ_BUG_ON(obj->last_write_req == NULL);
- RQ_BUG_ON(!(obj->active & intel_ring_flag(obj->last_write_req->ring)));
+ RQ_BUG_ON(!(obj->active & intel_ring_flag(obj->last_write_req->engine)));
i915_gem_request_assign(&obj->last_write_req, NULL);
intel_fb_obj_flush(obj, true, ORIGIN_CS);
@@ -2451,7 +2449,7 @@ i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
list_del_init(&obj->ring_list[ring]);
i915_gem_request_assign(&obj->last_read_req[ring], NULL);
- if (obj->last_write_req && obj->last_write_req->ring->id == ring)
+ if (obj->last_write_req && obj->last_write_req->engine->id == ring)
i915_gem_object_retire__write(obj);
obj->active &= ~(1 << ring);
@@ -2553,7 +2551,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
struct drm_i915_gem_object *obj,
bool flush_caches)
{
- struct intel_engine_cs *ring;
+ struct intel_engine_cs *engine;
struct drm_i915_private *dev_priv;
struct intel_ringbuffer *ringbuf;
u32 request_start;
@@ -2562,7 +2560,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
if (WARN_ON(request == NULL))
return;
- ring = request->ring;
+ engine = request->engine;
dev_priv = request->i915;
ringbuf = request->ringbuf;
@@ -2598,9 +2596,9 @@ void __i915_add_request(struct drm_i915_gem_request *request,
request->postfix = intel_ring_get_tail(ringbuf);
if (i915.enable_execlists)
- ret = ring->emit_request(request);
+ ret = engine->emit_request(request);
else {
- ret = ring->add_request(request);
+ ret = engine->add_request(request);
request->tail = intel_ring_get_tail(ringbuf);
}
@@ -2618,12 +2616,12 @@ void __i915_add_request(struct drm_i915_gem_request *request,
request->batch_obj = obj;
request->emitted_jiffies = jiffies;
- ring->last_submitted_seqno = request->seqno;
- list_add_tail(&request->list, &ring->request_list);
+ engine->last_submitted_seqno = request->seqno;
+ list_add_tail(&request->list, &engine->request_list);
trace_i915_gem_request_add(request);
- i915_queue_hangcheck(ring->dev);
+ i915_queue_hangcheck(engine->dev);
queue_delayed_work(dev_priv->wq,
&dev_priv->mm.retire_work,
@@ -2690,7 +2688,7 @@ void i915_gem_request_free(struct kref *req_ref)
if (ctx) {
if (i915.enable_execlists) {
- if (ctx != req->ring->default_context)
+ if (ctx != req->engine->default_context)
intel_lr_context_unpin(req);
}
@@ -2700,11 +2698,11 @@ void i915_gem_request_free(struct kref *req_ref)
kmem_cache_free(req->i915->requests, req);
}
-int i915_gem_request_alloc(struct intel_engine_cs *ring,
+int i915_gem_request_alloc(struct intel_engine_cs *engine,
struct intel_context *ctx,
struct drm_i915_gem_request **req_out)
{
- struct drm_i915_private *dev_priv = to_i915(ring->dev);
+ struct drm_i915_private *dev_priv = to_i915(engine->dev);
struct drm_i915_gem_request *req;
int ret;
@@ -2717,13 +2715,13 @@ int i915_gem_request_alloc(struct intel_engine_cs *ring,
if (req == NULL)
return -ENOMEM;
- ret = i915_gem_get_seqno(ring->dev, &req->seqno);
+ ret = i915_gem_get_seqno(engine->dev, &req->seqno);
if (ret)
goto err;
kref_init(&req->ref);
req->i915 = dev_priv;
- req->ring = ring;
+ req->engine = engine;
req->ctx = ctx;
i915_gem_context_reference(req->ctx);
@@ -3137,7 +3135,7 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
struct intel_engine_cs *from;
int ret;
- from = i915_gem_request_get_ring(from_req);
+ from = from_req->engine;
if (to == from)
return 0;
@@ -4308,7 +4306,7 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
BUILD_BUG_ON(I915_NUM_RINGS > 16);
args->busy = obj->active << 16;
if (obj->last_write_req)
- args->busy |= obj->last_write_req->ring->id;
+ args->busy |= obj->last_write_req->engine->id;
unref:
drm_gem_object_unreference(&obj->base);
@@ -4641,7 +4639,6 @@ err:
int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
{
- struct intel_ringbuffer *ring = req->ringbuf;
struct drm_i915_private *dev_priv = req->i915;
u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
@@ -4660,12 +4657,11 @@ int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
* at initialization time.
*/
for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
- intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
- intel_ring_emit(ring, reg_base + i);
- intel_ring_emit(ring, remap_info[i/4]);
+ intel_ring_emit(req->ringbuf, MI_LOAD_REGISTER_IMM(1));
+ intel_ring_emit(req->ringbuf, reg_base + i);
+ intel_ring_emit(req->ringbuf, remap_info[i/4]);
}
-
- intel_ring_advance(ring);
+ intel_ring_advance(req->ringbuf);
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index c3adc121aab4..047c2f94bd22 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -410,14 +410,14 @@ void i915_gem_context_fini(struct drm_device *dev)
int i915_gem_context_enable(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_engine_cs *engine = req->engine;
int ret;
if (i915.enable_execlists) {
- if (ring->init_context == NULL)
+ if (engine->init_context == NULL)
return 0;
- ret = ring->init_context(req);
+ ret = engine->init_context(req);
} else
ret = i915_switch_context(req);
@@ -494,7 +494,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
* itlb_before_ctx_switch.
*/
if (IS_GEN6(req->i915)) {
- ret = req->ring->flush(req, I915_GEM_GPU_DOMAINS, 0);
+ ret = req->engine->flush(req, I915_GEM_GPU_DOMAINS, 0);
if (ret)
return ret;
}
@@ -522,7 +522,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
for_each_ring(signaller, req->i915, i) {
- if (signaller == req->ring)
+ if (signaller == req->engine)
continue;
intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
@@ -547,7 +547,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
for_each_ring(signaller, req->i915, i) {
- if (signaller == req->ring)
+ if (signaller == req->engine)
continue;
intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
@@ -618,19 +618,19 @@ needs_pd_load_post(struct intel_engine_cs *ring, struct intel_context *to,
static int do_switch(struct drm_i915_gem_request *req)
{
struct intel_context *to = req->ctx;
- struct intel_engine_cs *ring = req->ring;
- struct intel_context *from = ring->last_context;
+ struct intel_engine_cs *engine = req->engine;
+ struct intel_context *from = engine->last_context;
u32 hw_flags = 0;
bool uninitialized = false;
int ret, i;
- if (should_skip_switch(ring, from, to))
+ if (should_skip_switch(engine, from, to))
return 0;
/* Trying to pin first makes error handling easier. */
- if (ring->id == RCS) {
+ if (engine->id == RCS) {
ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state,
- get_context_alignment(ring->dev), 0);
+ get_context_alignment(engine->dev), 0);
if (ret)
return ret;
}
@@ -640,23 +640,23 @@ static int do_switch(struct drm_i915_gem_request *req)
* evict_everything - as a last ditch gtt defrag effort that also
* switches to the default context. Hence we need to reload from here.
*/
- from = ring->last_context;
+ from = engine->last_context;
- if (needs_pd_load_pre(ring, to)) {
+ if (needs_pd_load_pre(engine, to)) {
/* Older GENs and non render rings still want the load first,
* "PP_DCLV followed by PP_DIR_BASE register through Load
* Register Immediate commands in Ring Buffer before submitting
* a context."*/
- trace_switch_mm(ring, to);
+ trace_switch_mm(engine, to);
ret = to->ppgtt->switch_mm(to->ppgtt, req);
if (ret)
goto unpin_out;
/* Doing a PD load always reloads the page dirs */
- to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring);
+ to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(engine);
}
- if (ring->id != RCS) {
+ if (engine->id != RCS) {
if (from)
i915_gem_context_unreference(from);
goto done;
@@ -681,14 +681,14 @@ static int do_switch(struct drm_i915_gem_request *req)
* space. This means we must enforce that a page table load
* occur when this occurs. */
} else if (to->ppgtt &&
- (intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) {
+ (intel_ring_flag(engine) & to->ppgtt->pd_dirty_rings)) {
hw_flags |= MI_FORCE_RESTORE;
- to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring);
+ to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(engine);
}
/* We should never emit switch_mm more than once */
- WARN_ON(needs_pd_load_pre(ring, to) &&
- needs_pd_load_post(ring, to, hw_flags));
+ WARN_ON(needs_pd_load_pre(engine, to) &&
+ needs_pd_load_post(engine, to, hw_flags));
ret = mi_set_context(req, hw_flags);
if (ret)
@@ -697,8 +697,8 @@ static int do_switch(struct drm_i915_gem_request *req)
/* GEN8 does *not* require an explicit reload if the PDPs have been
* setup, and we do not wish to move them.
*/
- if (needs_pd_load_post(ring, to, hw_flags)) {
- trace_switch_mm(ring, to);
+ if (needs_pd_load_post(engine, to, hw_flags)) {
+ trace_switch_mm(engine, to);
ret = to->ppgtt->switch_mm(to->ppgtt, req);
/* The hardware context switch is emitted, but we haven't
* actually changed the state - so it's probably safe to bail
@@ -751,11 +751,11 @@ static int do_switch(struct drm_i915_gem_request *req)
done:
i915_gem_context_reference(to);
- ring->last_context = to;
+ engine->last_context = to;
if (uninitialized) {
- if (ring->init_context) {
- ret = ring->init_context(req);
+ if (engine->init_context) {
+ ret = engine->init_context(req);
if (ret)
DRM_ERROR("ring init context: %d\n", ret);
}
@@ -764,7 +764,7 @@ done:
return 0;
unpin_out:
- if (ring->id == RCS)
+ if (engine->id == RCS)
i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state);
return ret;
}
@@ -784,17 +784,18 @@ unpin_out:
*/
int i915_switch_context(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *ring = req->ring;
WARN_ON(i915.enable_execlists);
WARN_ON(!mutex_is_locked(&req->i915->dev->struct_mutex));
if (req->ctx->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */
- if (req->ctx != ring->last_context) {
+ struct intel_engine_cs *engine = req->engine;
+
+ if (req->ctx != engine->last_context) {
i915_gem_context_reference(req->ctx);
- if (ring->last_context)
- i915_gem_context_unreference(ring->last_context);
- ring->last_context = req->ctx;
+ if (engine->last_context)
+ i915_gem_context_unreference(engine->last_context);
+ engine->last_context = req->ctx;
}
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 5f1b9b7df051..32c2d08bdd4c 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -922,7 +922,7 @@ static int
i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
struct list_head *vmas)
{
- const unsigned other_rings = ~intel_ring_flag(req->ring);
+ const unsigned other_rings = ~intel_ring_flag(req->engine);
struct i915_vma *vma;
uint32_t flush_domains = 0;
bool flush_chipset = false;
@@ -932,7 +932,7 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
struct drm_i915_gem_object *obj = vma->obj;
if (obj->active & other_rings) {
- ret = i915_gem_object_sync(obj, req->ring, &req);
+ ret = i915_gem_object_sync(obj, req->engine, &req);
if (ret)
return ret;
}
@@ -944,7 +944,7 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
}
if (flush_chipset)
- i915_gem_chipset_flush(req->ring->dev);
+ i915_gem_chipset_flush(req->engine->dev);
if (flush_domains & I915_GEM_DOMAIN_GTT)
wmb();
@@ -1118,7 +1118,7 @@ i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
struct intel_ringbuffer *ring = req->ringbuf;
int ret, i;
- if (!IS_GEN7(req->i915) || req->ring->id != RCS) {
+ if (!IS_GEN7(req->i915) || req->engine->id != RCS) {
DRM_DEBUG("sol reset is gen7/rcs only\n");
return -EINVAL;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4608884adfc8..c222456961fb 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -661,10 +661,10 @@ static int gen8_write_pdp(struct drm_i915_gem_request *req,
return ret;
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
- intel_ring_emit(ring, GEN8_RING_PDP_UDW(req->ring, entry));
+ intel_ring_emit(ring, GEN8_RING_PDP_UDW(req->engine, entry));
intel_ring_emit(ring, upper_32_bits(addr));
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
- intel_ring_emit(ring, GEN8_RING_PDP_LDW(req->ring, entry));
+ intel_ring_emit(ring, GEN8_RING_PDP_LDW(req->engine, entry));
intel_ring_emit(ring, lower_32_bits(addr));
intel_ring_advance(ring);
@@ -1592,7 +1592,9 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
int ret;
/* NB: TLBs must be flushed and invalidated before a switch */
- ret = req->ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
+ ret = req->engine->flush(req,
+ I915_GEM_GPU_DOMAINS,
+ I915_GEM_GPU_DOMAINS);
if (ret)
return ret;
@@ -1601,9 +1603,9 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
return ret;
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
- intel_ring_emit(ring, RING_PP_DIR_DCLV(req->ring));
+ intel_ring_emit(ring, RING_PP_DIR_DCLV(req->engine));
intel_ring_emit(ring, PP_DIR_DCLV_2G);
- intel_ring_emit(ring, RING_PP_DIR_BASE(req->ring));
+ intel_ring_emit(ring, RING_PP_DIR_BASE(req->engine));
intel_ring_emit(ring, get_pd_offset(ppgtt));
intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
@@ -1614,11 +1616,10 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *ring = req->ring;
- struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
+ struct drm_i915_private *dev_priv = req->i915;
- I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
- I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
+ I915_WRITE(RING_PP_DIR_DCLV(req->engine), PP_DIR_DCLV_2G);
+ I915_WRITE(RING_PP_DIR_BASE(req->engine), get_pd_offset(ppgtt));
return 0;
}
@@ -1629,7 +1630,9 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
int ret;
/* NB: TLBs must be flushed and invalidated before a switch */
- ret = req->ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
+ ret = req->engine->flush(req,
+ I915_GEM_GPU_DOMAINS,
+ I915_GEM_GPU_DOMAINS);
if (ret)
return ret;
@@ -1638,16 +1641,18 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
return ret;
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
- intel_ring_emit(ring, RING_PP_DIR_DCLV(req->ring));
+ intel_ring_emit(ring, RING_PP_DIR_DCLV(req->engine));
intel_ring_emit(ring, PP_DIR_DCLV_2G);
- intel_ring_emit(ring, RING_PP_DIR_BASE(req->ring));
+ intel_ring_emit(ring, RING_PP_DIR_BASE(req->engine));
intel_ring_emit(ring, get_pd_offset(ppgtt));
intel_ring_emit(ring, MI_NOOP);
intel_ring_advance(ring);
/* XXX: RCS is the only one to auto invalidate the TLBs? */
- if (req->ring->id != RCS) {
- ret = req->ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
+ if (req->engine->id != RCS) {
+ ret = req->engine->flush(req,
+ I915_GEM_GPU_DOMAINS,
+ I915_GEM_GPU_DOMAINS);
if (ret)
return ret;
}
@@ -1658,15 +1663,12 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *ring = req->ring;
- struct drm_device *dev = ppgtt->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
-
+ struct drm_i915_private *dev_priv = req->i915;
- I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
- I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
+ I915_WRITE(RING_PP_DIR_DCLV(req->engine), PP_DIR_DCLV_2G);
+ I915_WRITE(RING_PP_DIR_BASE(req->engine), get_pd_offset(ppgtt));
- POSTING_READ(RING_PP_DIR_DCLV(ring));
+ POSTING_READ(RING_PP_DIR_DCLV(req->engine));
return 0;
}
@@ -2101,8 +2103,7 @@ int i915_ppgtt_init_hw(struct drm_device *dev)
int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
{
- struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
- struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
+ struct i915_hw_ppgtt *ppgtt = req->i915->mm.aliasing_ppgtt;
int ret;
if (i915.enable_execlists)
@@ -2115,7 +2116,7 @@ int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
if (ret)
return ret;
- ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring);
+ ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->engine);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index 5026a6267a88..f11e8685b1af 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -198,25 +198,25 @@ int i915_gem_render_state_init(struct drm_i915_gem_request *req)
struct render_state so;
int ret;
- ret = i915_gem_render_state_prepare(req->ring, &so);
+ ret = i915_gem_render_state_prepare(req->engine, &so);
if (ret)
return ret;
if (so.rodata == NULL)
return 0;
- ret = req->ring->dispatch_execbuffer(req, so.ggtt_offset,
- so.rodata->batch_items * 4,
- I915_DISPATCH_SECURE);
+ ret = req->engine->dispatch_execbuffer(req, so.ggtt_offset,
+ so.rodata->batch_items * 4,
+ I915_DISPATCH_SECURE);
if (ret)
goto out;
if (so.aux_batch_size > 8) {
- ret = req->ring->dispatch_execbuffer(req,
- (so.ggtt_offset +
- so.aux_batch_offset),
- so.aux_batch_size,
- I915_DISPATCH_SECURE);
+ ret = req->engine->dispatch_execbuffer(req,
+ (so.ggtt_offset +
+ so.aux_batch_offset),
+ so.aux_batch_size,
+ I915_DISPATCH_SECURE);
if (ret)
goto out;
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index d8e035e126d7..974e3481e449 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -709,8 +709,7 @@ static void capture_bo(struct drm_i915_error_buffer *err,
err->dirty = obj->dirty;
err->purgeable = obj->madv != I915_MADV_WILLNEED;
err->userptr = obj->userptr.mm != NULL;
- err->ring = obj->last_write_req ?
- i915_gem_request_get_ring(obj->last_write_req)->id : -1;
+ err->ring = obj->last_write_req ? obj->last_write_req->engine->id : -1;
err->cache_level = obj->cache_level;
}
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index ad64d6ba13a2..533b6a87fd1d 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -498,7 +498,7 @@ TRACE_EVENT(i915_gem_ring_sync_to,
TP_fast_assign(
__entry->dev = from->dev->primary->index;
__entry->sync_from = from->id;
- __entry->sync_to = to_req->ring->id;
+ __entry->sync_to = to_req->engine->id;
__entry->seqno = i915_gem_request_get_seqno(req);
),
@@ -520,13 +520,11 @@ TRACE_EVENT(i915_gem_ring_dispatch,
),
TP_fast_assign(
- struct intel_engine_cs *ring =
- i915_gem_request_get_ring(req);
- __entry->dev = ring->dev->primary->index;
- __entry->ring = ring->id;
- __entry->seqno = i915_gem_request_get_seqno(req);
+ __entry->dev = req->i915->dev->primary->index;
+ __entry->ring = req->engine->id;
+ __entry->seqno = req->seqno;
__entry->flags = flags;
- i915_trace_irq_get(ring, req);
+ i915_trace_irq_get(req->engine, req);
),
TP_printk("dev=%u, ring=%u, seqno=%u, flags=%x",
@@ -545,8 +543,8 @@ TRACE_EVENT(i915_gem_ring_flush,
),
TP_fast_assign(
- __entry->dev = req->ring->dev->primary->index;
- __entry->ring = req->ring->id;
+ __entry->dev = req->engine->dev->primary->index;
+ __entry->ring = req->engine->id;
__entry->invalidate = invalidate;
__entry->flush = flush;
),
@@ -567,11 +565,9 @@ DECLARE_EVENT_CLASS(i915_gem_request,
),
TP_fast_assign(
- struct intel_engine_cs *ring =
- i915_gem_request_get_ring(req);
- __entry->dev = ring->dev->primary->index;
- __entry->ring = ring->id;
- __entry->seqno = i915_gem_request_get_seqno(req);
+ __entry->dev = req->i915->dev->primary->index;
+ __entry->ring = req->engine->id;
+ __entry->seqno = req->seqno;
),
TP_printk("dev=%u, ring=%u, seqno=%u",
@@ -631,13 +627,11 @@ TRACE_EVENT(i915_gem_request_wait_begin,
* less desirable.
*/
TP_fast_assign(
- struct intel_engine_cs *ring =
- i915_gem_request_get_ring(req);
- __entry->dev = ring->dev->primary->index;
- __entry->ring = ring->id;
- __entry->seqno = i915_gem_request_get_seqno(req);
+ __entry->dev = req->i915->dev->primary->index;
+ __entry->ring = req->engine->id;
+ __entry->seqno = req->seqno;
__entry->blocking =
- mutex_is_locked(&ring->dev->struct_mutex);
+ mutex_is_locked(&req->i915->dev->struct_mutex);
),
TP_printk("dev=%u, ring=%u, seqno=%u, blocking=%s",
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f6dae2cfd9c9..2447f1a36fb0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10987,7 +10987,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
}
len = 4;
- if (req->ring->id == RCS) {
+ if (req->engine->id == RCS) {
len += 6;
/*
* On Gen 8, SRM is now taking an extra dword to accommodate
@@ -11025,7 +11025,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
* for the RCS also doesn't appear to drop events. Setting the DERRMR
* to zero does lead to lockups within MI_DISPLAY_FLIP.
*/
- if (req->ring->id == RCS) {
+ if (req->engine->id == RCS) {
intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
intel_ring_emit(ring, DERRMR);
intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
@@ -11038,7 +11038,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
MI_SRM_LRM_GLOBAL_GTT);
intel_ring_emit(ring, DERRMR);
- intel_ring_emit(ring, req->ring->scratch.gtt_offset + 256);
+ intel_ring_emit(ring, req->engine->scratch.gtt_offset + 256);
if (IS_GEN8(req->i915)) {
intel_ring_emit(ring, 0);
intel_ring_emit(ring, MI_NOOP);
@@ -11078,7 +11078,7 @@ static bool use_mmio_flip(struct intel_engine_cs *ring,
else if (i915.enable_execlists)
return true;
else
- return ring != i915_gem_request_get_ring(obj->last_write_req);
+ return ring != i915_gem_request_get_engine(obj->last_write_req);
}
static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
@@ -11395,7 +11395,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
ring = &dev_priv->ring[BCS];
} else if (INTEL_INFO(dev)->gen >= 7) {
- ring = i915_gem_request_get_ring(obj->last_write_req);
+ ring = i915_gem_request_get_engine(obj->last_write_req);
if (ring == NULL || ring->id != RCS)
ring = &dev_priv->ring[BCS];
} else {
@@ -11411,7 +11411,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
*/
ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
crtc->primary->state,
- mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
+ mmio_flip ? i915_gem_request_get_engine(obj->last_write_req) : ring, &request);
if (ret)
goto cleanup_pending;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 2458804c521d..1502e53d2ad6 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -272,17 +272,16 @@ u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_request *rq)
{
- struct intel_engine_cs *ring = rq->ring;
- struct drm_device *dev = ring->dev;
- struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
- uint64_t desc;
+ int ring = rq->engine->id;
+ struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring].state;
uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
+ uint64_t desc;
WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
desc = GEN8_CTX_VALID;
- desc |= GEN8_CTX_ADDRESSING_MODE(dev) << GEN8_CTX_ADDRESSING_MODE_SHIFT;
- if (IS_GEN8(ctx_obj->base.dev))
+ desc |= GEN8_CTX_ADDRESSING_MODE(rq->i915) << GEN8_CTX_ADDRESSING_MODE_SHIFT;
+ if (IS_GEN8(rq->i915))
desc |= GEN8_CTX_L3LLC_COHERENT;
desc |= GEN8_CTX_PRIVILEGE;
desc |= lrca;
@@ -293,10 +292,10 @@ static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_request *rq)
/* desc |= GEN8_CTX_FORCE_RESTORE; */
/* WaEnableForceRestoreInCtxtDescForVCS:skl */
- if (IS_GEN9(dev) &&
- INTEL_REVID(dev) <= SKL_REVID_B0 &&
- (ring->id == BCS || ring->id == VCS ||
- ring->id == VECS || ring->id == VCS2))
+ if (IS_GEN9(rq->i915) &&
+ INTEL_REVID(rq->i915) <= SKL_REVID_B0 &&
+ (ring == BCS || ring == VCS ||
+ ring == VECS || ring == VCS2))
desc |= GEN8_CTX_FORCE_RESTORE;
return desc;
@@ -306,7 +305,7 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
struct drm_i915_gem_request *rq1)
{
- struct intel_engine_cs *ring = rq0->ring;
+ struct intel_engine_cs *engine = rq0->engine;
struct drm_i915_private *dev_priv = rq0->i915;
uint64_t desc[2];
@@ -323,24 +322,23 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
/* You must always write both descriptors in the order below. */
spin_lock(&dev_priv->uncore.lock);
intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
- I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[1]));
- I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[1]));
+ I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[1]));
+ I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[1]));
- I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[0]));
+ I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[0]));
/* The context is automatically loaded after the following */
- I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[0]));
+ I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[0]));
/* ELSP is a wo register, use another nearby reg for posting */
- POSTING_READ_FW(RING_EXECLIST_STATUS(ring));
+ POSTING_READ_FW(RING_EXECLIST_STATUS(engine));
intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
spin_unlock(&dev_priv->uncore.lock);
}
static int execlists_update_context(struct drm_i915_gem_request *rq)
{
- struct intel_engine_cs *ring = rq->ring;
struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
- struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
+ struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[rq->engine->id].state;
struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
struct page *page;
uint32_t *reg_state;
@@ -355,7 +353,7 @@ static int execlists_update_context(struct drm_i915_gem_request *rq)
reg_state[CTX_RING_TAIL+1] = rq->tail;
reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);
- if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
+ if (ppgtt && !USES_FULL_48BIT_PPGTT(rq->i915)) {
/* True 32b PPGTT with dynamic page allocation: update PDP
* registers and point the unallocated PDPs to scratch page.
* PML4 is allocated during ppgtt init, so this is not needed
@@ -538,27 +536,27 @@ void intel_lrc_irq_handler(struct intel_engine_cs *ring)
static int execlists_context_queue(struct drm_i915_gem_request *request)
{
- struct intel_engine_cs *ring = request->ring;
+ struct intel_engine_cs *engine = request->engine;
struct drm_i915_gem_request *cursor;
int num_elements = 0;
- if (request->ctx != ring->default_context)
+ if (request->ctx != engine->default_context)
intel_lr_context_pin(request);
i915_gem_request_reference(request);
request->tail = request->ringbuf->tail;
- spin_lock_irq(&ring->execlist_lock);
+ spin_lock_irq(&engine->execlist_lock);
- list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
+ list_for_each_entry(cursor, &engine->execlist_queue, execlist_link)
if (++num_elements > 2)
break;
if (num_elements > 2) {
struct drm_i915_gem_request *tail_req;
- tail_req = list_last_entry(&ring->execlist_queue,
+ tail_req = list_last_entry(&engine->execlist_queue,
struct drm_i915_gem_request,
execlist_link);
@@ -567,41 +565,41 @@ static int execlists_context_queue(struct drm_i915_gem_request *request)
"More than 2 already-submitted reqs queued\n");
list_del(&tail_req->execlist_link);
list_add_tail(&tail_req->execlist_link,
- &ring->execlist_retired_req_list);
+ &engine->execlist_retired_req_list);
}
}
- list_add_tail(&request->execlist_link, &ring->execlist_queue);
+ list_add_tail(&request->execlist_link, &engine->execlist_queue);
if (num_elements == 0)
- execlists_context_unqueue(ring);
+ execlists_context_unqueue(engine);
- spin_unlock_irq(&ring->execlist_lock);
+ spin_unlock_irq(&engine->execlist_lock);
return 0;
}
static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_engine_cs *engine = req->engine;
uint32_t flush_domains;
int ret;
flush_domains = 0;
- if (ring->gpu_caches_dirty)
+ if (engine->gpu_caches_dirty)
flush_domains = I915_GEM_GPU_DOMAINS;
- ret = ring->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
+ ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
if (ret)
return ret;
- ring->gpu_caches_dirty = false;
+ engine->gpu_caches_dirty = false;
return 0;
}
static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
struct list_head *vmas)
{
- const unsigned other_rings = ~intel_ring_flag(req->ring);
+ const unsigned other_rings = ~intel_ring_flag(req->engine);
struct i915_vma *vma;
uint32_t flush_domains = 0;
bool flush_chipset = false;
@@ -611,7 +609,7 @@ static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
struct drm_i915_gem_object *obj = vma->obj;
if (obj->active & other_rings) {
- ret = i915_gem_object_sync(obj, req->ring, &req);
+ ret = i915_gem_object_sync(obj, req->engine, &req);
if (ret)
return ret;
}
@@ -635,9 +633,9 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request
{
int ret;
- request->ringbuf = request->ctx->engine[request->ring->id].ringbuf;
+ request->ringbuf = request->ctx->engine[request->engine->id].ringbuf;
- if (request->ctx != request->ring->default_context) {
+ if (request->ctx != request->engine->default_context) {
ret = intel_lr_context_pin(request);
if (ret)
return ret;
@@ -660,7 +658,7 @@ intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
{
intel_ring_advance(request->ringbuf);
- if (intel_ring_stopped(request->ring))
+ if (intel_ring_stopped(request->engine))
return;
execlists_context_queue(request);
@@ -811,35 +809,35 @@ void intel_logical_ring_stop(struct intel_engine_cs *ring)
int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_engine_cs *engine = req->engine;
int ret;
- if (!ring->gpu_caches_dirty)
+ if (!engine->gpu_caches_dirty)
return 0;
- ret = ring->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
+ ret = engine->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
if (ret)
return ret;
- ring->gpu_caches_dirty = false;
+ engine->gpu_caches_dirty = false;
return 0;
}
static int intel_lr_context_pin(struct drm_i915_gem_request *rq)
{
- struct intel_engine_cs *ring = rq->ring;
- struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
+ int engine = rq->engine->id;
+ struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[engine].state;
struct intel_ringbuffer *ringbuf = rq->ringbuf;
int ret = 0;
- WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
- if (rq->ctx->engine[ring->id].pin_count++ == 0) {
+ WARN_ON(!mutex_is_locked(&rq->i915->dev->struct_mutex));
+ if (rq->ctx->engine[engine].pin_count++ == 0) {
ret = i915_gem_obj_ggtt_pin(ctx_obj,
GEN8_LR_CONTEXT_ALIGN, 0);
if (ret)
goto reset_pin_count;
- ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
+ ret = intel_pin_and_map_ringbuffer_obj(rq->i915->dev, ringbuf);
if (ret)
goto unpin_ctx_obj;
@@ -851,20 +849,20 @@ static int intel_lr_context_pin(struct drm_i915_gem_request *rq)
unpin_ctx_obj:
i915_gem_object_ggtt_unpin(ctx_obj);
reset_pin_count:
- rq->ctx->engine[ring->id].pin_count = 0;
+ rq->ctx->engine[engine].pin_count = 0;
return ret;
}
void intel_lr_context_unpin(struct drm_i915_gem_request *rq)
{
- struct intel_engine_cs *ring = rq->ring;
- struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
+ int engine = rq->engine->id;
+ struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[engine].state;
struct intel_ringbuffer *ringbuf = rq->ringbuf;
if (ctx_obj) {
- WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
- if (--rq->ctx->engine[ring->id].pin_count == 0) {
+ WARN_ON(!mutex_is_locked(&rq->i915->dev->struct_mutex));
+ if (--rq->ctx->engine[engine].pin_count == 0) {
intel_unpin_ringbuffer_obj(ringbuf);
i915_gem_object_ggtt_unpin(ctx_obj);
}
@@ -874,7 +872,7 @@ void intel_lr_context_unpin(struct drm_i915_gem_request *rq)
static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
{
int ret, i;
- struct intel_engine_cs *ring = req->ring;
+ struct intel_engine_cs *engine = req->engine;
struct intel_ringbuffer *ringbuf = req->ringbuf;
struct drm_i915_private *dev_priv = req->i915;
struct i915_workarounds *w = &dev_priv->workarounds;
@@ -882,7 +880,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
if (WARN_ON_ONCE(w->count == 0))
return 0;
- ring->gpu_caches_dirty = true;
+ engine->gpu_caches_dirty = true;
ret = logical_ring_flush_all_caches(req);
if (ret)
return ret;
@@ -900,7 +898,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
intel_ring_advance(ringbuf);
- ring->gpu_caches_dirty = true;
+ engine->gpu_caches_dirty = true;
ret = logical_ring_flush_all_caches(req);
if (ret)
return ret;
@@ -1319,7 +1317,7 @@ static int gen9_init_render_ring(struct intel_engine_cs *ring)
static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
{
struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
- struct intel_engine_cs *ring = req->ring;
+ struct intel_engine_cs *engine = req->engine;
struct intel_ringbuffer *ringbuf = req->ringbuf;
const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
int i, ret;
@@ -1332,9 +1330,9 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
- intel_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i));
+ intel_ring_emit(ringbuf, GEN8_RING_PDP_UDW(engine, i));
intel_ring_emit(ringbuf, upper_32_bits(pd_daddr));
- intel_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i));
+ intel_ring_emit(ringbuf, GEN8_RING_PDP_LDW(engine, i));
intel_ring_emit(ringbuf, lower_32_bits(pd_daddr));
}
@@ -1358,14 +1356,14 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
* not idle). PML4 is allocated during ppgtt init so this is
* not needed in 48-bit.*/
if (req->ctx->ppgtt &&
- (intel_ring_flag(req->ring) & req->ctx->ppgtt->pd_dirty_rings)) {
+ (intel_ring_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
if (!USES_FULL_48BIT_PPGTT(req->i915)) {
ret = intel_logical_ring_emit_pdps(req);
if (ret)
return ret;
}
- req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring);
+ req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->engine);
}
ret = intel_ring_begin(req, 4);
@@ -1575,21 +1573,21 @@ static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
struct render_state so;
int ret;
- ret = i915_gem_render_state_prepare(req->ring, &so);
+ ret = i915_gem_render_state_prepare(req->engine, &so);
if (ret)
return ret;
if (so.rodata == NULL)
return 0;
- ret = req->ring->emit_bb_start(req, so.ggtt_offset,
- I915_DISPATCH_SECURE);
+ ret = req->engine->emit_bb_start(req, so.ggtt_offset,
+ I915_DISPATCH_SECURE);
if (ret)
goto out;
- ret = req->ring->emit_bb_start(req,
- (so.ggtt_offset + so.aux_batch_offset),
- I915_DISPATCH_SECURE);
+ ret = req->engine->emit_bb_start(req,
+ (so.ggtt_offset + so.aux_batch_offset),
+ I915_DISPATCH_SECURE);
if (ret)
goto out;
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index ac0a982bbf55..d79c9c0bbffb 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -138,21 +138,21 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
*
* Return: true if there are applicable MOCS settings for the device.
*/
-static bool get_mocs_settings(struct drm_device *dev,
+static bool get_mocs_settings(struct drm_i915_private *dev_priv,
struct drm_i915_mocs_table *table)
{
bool result = false;
- if (IS_SKYLAKE(dev)) {
+ if (IS_SKYLAKE(dev_priv)) {
table->size = ARRAY_SIZE(skylake_mocs_table);
table->table = skylake_mocs_table;
result = true;
- } else if (IS_BROXTON(dev)) {
+ } else if (IS_BROXTON(dev_priv)) {
table->size = ARRAY_SIZE(broxton_mocs_table);
table->table = broxton_mocs_table;
result = true;
} else {
- WARN_ONCE(INTEL_INFO(dev)->gen >= 9,
+ WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
"Platform that should have a MOCS table does not.\n");
}
@@ -297,7 +297,7 @@ int intel_rcs_context_init_mocs(struct drm_i915_gem_request *req)
struct drm_i915_mocs_table t;
int ret;
- if (get_mocs_settings(req->ring->dev, &t)) {
+ if (get_mocs_settings(req->i915, &t)) {
/* Program the control registers */
ret = emit_mocs_control_table(req, &t, GEN9_GFX_MOCS_0);
if (ret)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 9821c2a8074a..cc060588a287 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -216,7 +216,7 @@ static int
intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
{
struct intel_ringbuffer *ring = req->ringbuf;
- u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
+ u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
int ret;
ret = intel_ring_begin(req, 6);
@@ -253,7 +253,7 @@ gen6_render_ring_flush(struct drm_i915_gem_request *req,
{
struct intel_ringbuffer *ring = req->ringbuf;
u32 flags = 0;
- u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
+ u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
int ret;
/* Force SNB workarounds for PIPE_CONTROL flushes */
@@ -326,7 +326,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
{
struct intel_ringbuffer *ring = req->ringbuf;
u32 flags = 0;
- u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
+ u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
int ret;
/*
@@ -410,7 +410,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains, u32 flush_domains)
{
u32 flags = 0;
- u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
+ u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
int ret;
flags |= PIPE_CONTROL_CS_STALL;
@@ -720,7 +720,7 @@ static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
if (WARN_ON_ONCE(w->count == 0))
return 0;
- req->ring->gpu_caches_dirty = true;
+ req->engine->gpu_caches_dirty = true;
ret = intel_ring_flush_all_caches(req);
if (ret)
return ret;
@@ -738,7 +738,7 @@ static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
intel_ring_advance(ring);
- req->ring->gpu_caches_dirty = true;
+ req->engine->gpu_caches_dirty = true;
ret = intel_ring_flush_all_caches(req);
if (ret)
return ret;
@@ -1199,7 +1199,7 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
for_each_ring(waiter, dev_priv, i) {
u32 seqno;
- u64 gtt_offset = signaller_req->ring->semaphore.signal_ggtt[i];
+ u64 gtt_offset = signaller_req->engine->semaphore.signal_ggtt[i];
if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
continue;
@@ -1239,7 +1239,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
for_each_ring(waiter, dev_priv, i) {
u32 seqno;
- u64 gtt_offset = signaller_req->ring->semaphore.signal_ggtt[i];
+ u64 gtt_offset = signaller_req->engine->semaphore.signal_ggtt[i];
if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
continue;
@@ -1276,7 +1276,7 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
return ret;
for_each_ring(useless, dev_priv, i) {
- u32 mbox_reg = signaller_req->ring->semaphore.mbox.signal[i];
+ u32 mbox_reg = signaller_req->engine->semaphore.mbox.signal[i];
if (mbox_reg != GEN6_NOSYNC) {
u32 seqno = i915_gem_request_get_seqno(signaller_req);
intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
@@ -1306,8 +1306,8 @@ gen6_add_request(struct drm_i915_gem_request *req)
struct intel_ringbuffer *ring = req->ringbuf;
int ret;
- if (req->ring->semaphore.signal)
- ret = req->ring->semaphore.signal(req, 4);
+ if (req->engine->semaphore.signal)
+ ret = req->engine->semaphore.signal(req, 4);
else
ret = intel_ring_begin(req, 4);
@@ -1318,7 +1318,7 @@ gen6_add_request(struct drm_i915_gem_request *req)
intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
intel_ring_emit(ring, i915_gem_request_get_seqno(req));
intel_ring_emit(ring, MI_USER_INTERRUPT);
- __intel_ring_advance(req->ring);
+ __intel_ring_advance(req->engine);
return 0;
}
@@ -1356,10 +1356,10 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
MI_SEMAPHORE_SAD_GTE_SDD);
intel_ring_emit(waiter, seqno);
intel_ring_emit(waiter,
- lower_32_bits(GEN8_WAIT_OFFSET(waiter_req->ring,
+ lower_32_bits(GEN8_WAIT_OFFSET(waiter_req->engine,
signaller->id)));
intel_ring_emit(waiter,
- upper_32_bits(GEN8_WAIT_OFFSET(waiter_req->ring,
+ upper_32_bits(GEN8_WAIT_OFFSET(waiter_req->engine,
signaller->id)));
intel_ring_advance(waiter);
return 0;
@@ -1374,7 +1374,7 @@ gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
u32 dw1 = MI_SEMAPHORE_MBOX |
MI_SEMAPHORE_COMPARE |
MI_SEMAPHORE_REGISTER;
- u32 wait_mbox = signaller->semaphore.mbox.wait[waiter_req->ring->id];
+ u32 wait_mbox = signaller->semaphore.mbox.wait[waiter_req->engine->id];
int ret;
/* Throughout all of the GEM code, seqno passed implies our current
@@ -1419,7 +1419,7 @@ static int
pc_render_add_request(struct drm_i915_gem_request *req)
{
struct intel_ringbuffer *ring = req->ringbuf;
- u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
+ u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
int ret;
/* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
@@ -1437,7 +1437,7 @@ pc_render_add_request(struct drm_i915_gem_request *req)
intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
PIPE_CONTROL_WRITE_FLUSH |
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
- intel_ring_emit(ring, req->ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
+ intel_ring_emit(ring, req->engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
intel_ring_emit(ring, i915_gem_request_get_seqno(req));
intel_ring_emit(ring, 0);
PIPE_CONTROL_FLUSH(ring, scratch_addr);
@@ -1456,10 +1456,10 @@ pc_render_add_request(struct drm_i915_gem_request *req)
PIPE_CONTROL_WRITE_FLUSH |
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_NOTIFY);
- intel_ring_emit(ring, req->ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
+ intel_ring_emit(ring, req->engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
intel_ring_emit(ring, i915_gem_request_get_seqno(req));
intel_ring_emit(ring, 0);
- __intel_ring_advance(req->ring);
+ __intel_ring_advance(req->engine);
return 0;
}
@@ -1639,7 +1639,7 @@ i9xx_add_request(struct drm_i915_gem_request *req)
intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
intel_ring_emit(ring, i915_gem_request_get_seqno(req));
intel_ring_emit(ring, MI_USER_INTERRUPT);
- __intel_ring_advance(req->ring);
+ __intel_ring_advance(req->engine);
return 0;
}
@@ -1801,7 +1801,7 @@ i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
unsigned dispatch_flags)
{
struct intel_ringbuffer *ring = req->ringbuf;
- u32 cs_offset = req->ring->scratch.gtt_offset;
+ u32 cs_offset = req->engine->scratch.gtt_offset;
int ret;
ret = intel_ring_begin(req, 6);
@@ -2164,7 +2164,7 @@ int intel_ring_idle(struct intel_engine_cs *ring)
int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
{
- request->ringbuf = request->ring->buffer;
+ request->ringbuf = request->engine->buffer;
return 0;
}
@@ -2218,7 +2218,7 @@ void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
{
struct intel_ringbuffer *ringbuf = req->ringbuf;
- struct intel_engine_cs *ring = req->ring;
+ struct intel_engine_cs *engine = req->engine;
struct drm_i915_gem_request *target;
unsigned space;
int ret;
@@ -2229,7 +2229,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
/* The whole point of reserving space is to not wait! */
WARN_ON(ringbuf->reserved_in_use);
- list_for_each_entry(target, &ring->request_list, list) {
+ list_for_each_entry(target, &engine->request_list, list) {
/*
* The request queue is per-engine, so can contain requests
* from multiple ringbuffers. Here, we must ignore any that
@@ -2245,7 +2245,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
break;
}
- if (WARN_ON(&target->list == &ring->request_list))
+ if (WARN_ON(&target->list == &engine->request_list))
return -ENOSPC;
ret = i915_wait_request(target);
@@ -2931,40 +2931,40 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
int
intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_engine_cs *engine = req->engine;
int ret;
- if (!ring->gpu_caches_dirty)
+ if (!engine->gpu_caches_dirty)
return 0;
- ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
+ ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
if (ret)
return ret;
trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
- ring->gpu_caches_dirty = false;
+ engine->gpu_caches_dirty = false;
return 0;
}
int
intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *ring = req->ring;
+ struct intel_engine_cs *engine = req->engine;
uint32_t flush_domains;
int ret;
flush_domains = 0;
- if (ring->gpu_caches_dirty)
+ if (engine->gpu_caches_dirty)
flush_domains = I915_GEM_GPU_DOMAINS;
- ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
+ ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
if (ret)
return ret;
trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
- ring->gpu_caches_dirty = false;
+ engine->gpu_caches_dirty = false;
return 0;
}
--
2.6.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 07/12] drm/i915: Rename request->ringbuf to request->ring
2015-11-20 12:43 [PATCH 01/12] drm/i915: Convert i915_semaphores_is_enabled over to drm_i915_private Chris Wilson
` (4 preceding siblings ...)
2015-11-20 12:43 ` [PATCH 06/12] drm/i915: Rename request->ring to request->engine Chris Wilson
@ 2015-11-20 12:43 ` Chris Wilson
2015-11-24 14:51 ` Daniel Vetter
2015-11-24 15:08 ` Tvrtko Ursulin
2015-11-20 12:43 ` [PATCH 08/12] drm/i915: Rename backpointer from intel_ringbuffer to intel_engine_cs Chris Wilson
` (5 subsequent siblings)
11 siblings, 2 replies; 41+ messages in thread
From: Chris Wilson @ 2015-11-20 12:43 UTC (permalink / raw)
To: intel-gfx
Now that we have disambuigated ring and engine, we can use the clearer
and more consistent name for the intel_ringbuffer pointer in the
request.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_gem.c | 28 +++---
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +-
drivers/gpu/drm/i915/intel_display.c | 10 +-
drivers/gpu/drm/i915/intel_lrc.c | 149 ++++++++++++++---------------
drivers/gpu/drm/i915/intel_mocs.c | 32 +++----
drivers/gpu/drm/i915/intel_overlay.c | 42 ++++----
drivers/gpu/drm/i915/intel_ringbuffer.c | 86 ++++++++---------
10 files changed, 178 insertions(+), 183 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9ce8b3fcb3a0..b7eaa2deb437 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2185,7 +2185,7 @@ struct drm_i915_gem_request {
* context.
*/
struct intel_context *ctx;
- struct intel_ringbuffer *ringbuf;
+ struct intel_ringbuffer *ring;
/** Batch buffer related to this request if any (used for
error state dump only) */
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 5a1b51a27fe3..d6706dd4117c 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1386,7 +1386,7 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request)
* Note this requires that we are always called in request
* completion order.
*/
- request->ringbuf->last_retired_head = request->postfix;
+ request->ring->last_retired_head = request->postfix;
list_del_init(&request->list);
i915_gem_request_remove_from_client(request);
@@ -2553,7 +2553,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
{
struct intel_engine_cs *engine;
struct drm_i915_private *dev_priv;
- struct intel_ringbuffer *ringbuf;
+ struct intel_ringbuffer *ring;
u32 request_start;
int ret;
@@ -2562,16 +2562,16 @@ void __i915_add_request(struct drm_i915_gem_request *request,
engine = request->engine;
dev_priv = request->i915;
- ringbuf = request->ringbuf;
+ ring = request->ring;
/*
* To ensure that this call will not fail, space for its emissions
* should already have been reserved in the ring buffer. Let the ring
* know that it is time to use that space up.
*/
- intel_ring_reserved_space_use(ringbuf);
+ intel_ring_reserved_space_use(ring);
- request_start = intel_ring_get_tail(ringbuf);
+ request_start = intel_ring_get_tail(ring);
/*
* Emit any outstanding flushes - execbuf can fail to emit the flush
* after having emitted the batchbuffer command. Hence we need to fix
@@ -2593,14 +2593,14 @@ void __i915_add_request(struct drm_i915_gem_request *request,
* GPU processing the request, we never over-estimate the
* position of the head.
*/
- request->postfix = intel_ring_get_tail(ringbuf);
+ request->postfix = intel_ring_get_tail(ring);
if (i915.enable_execlists)
ret = engine->emit_request(request);
else {
ret = engine->add_request(request);
- request->tail = intel_ring_get_tail(ringbuf);
+ request->tail = intel_ring_get_tail(ring);
}
/* Not allowed to fail! */
WARN(ret, "emit|add_request failed: %d!\n", ret);
@@ -2629,7 +2629,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
intel_mark_busy(dev_priv->dev);
/* Sanity check that the reserved size was large enough. */
- intel_ring_reserved_space_end(ringbuf);
+ intel_ring_reserved_space_end(ring);
}
static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
@@ -2741,7 +2741,7 @@ int i915_gem_request_alloc(struct intel_engine_cs *engine,
* to be redone if the request is not actually submitted straight
* away, e.g. because a GPU scheduler has deferred it.
*/
- intel_ring_reserved_space_reserve(req->ringbuf,
+ intel_ring_reserved_space_reserve(req->ring,
MIN_SPACE_FOR_ADD_REQUEST);
ret = intel_ring_begin(req, 0);
if (ret) {
@@ -2764,7 +2764,7 @@ err:
void i915_gem_request_cancel(struct drm_i915_gem_request *req)
{
- intel_ring_reserved_space_cancel(req->ringbuf);
+ intel_ring_reserved_space_cancel(req->ring);
i915_gem_request_unreference(req);
}
@@ -4657,11 +4657,11 @@ int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
* at initialization time.
*/
for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
- intel_ring_emit(req->ringbuf, MI_LOAD_REGISTER_IMM(1));
- intel_ring_emit(req->ringbuf, reg_base + i);
- intel_ring_emit(req->ringbuf, remap_info[i/4]);
+ intel_ring_emit(req->ring, MI_LOAD_REGISTER_IMM(1));
+ intel_ring_emit(req->ring, reg_base + i);
+ intel_ring_emit(req->ring, remap_info[i/4]);
}
- intel_ring_advance(req->ringbuf);
+ intel_ring_advance(req->ring);
return ret;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 047c2f94bd22..5d0516930b16 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -479,7 +479,7 @@ i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
static inline int
mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
u32 flags = hw_flags | MI_MM_SPACE_GTT;
const int num_rings =
/* Use an extended w/a on ivb+ if signalling from other rings */
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 32c2d08bdd4c..afa930dab632 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1115,7 +1115,7 @@ i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
static int
i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret, i;
if (!IS_GEN7(req->i915) || req->engine->id != RCS) {
@@ -1196,7 +1196,7 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
struct drm_i915_gem_execbuffer2 *args,
struct list_head *vmas)
{
- struct intel_ringbuffer *ring = params->request->ringbuf;
+ struct intel_ringbuffer *ring = params->request->ring;
struct drm_i915_private *dev_priv = params->request->i915;
u64 exec_start, exec_len;
int instp_mode;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c222456961fb..b1ee6f89e70b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -651,7 +651,7 @@ static int gen8_write_pdp(struct drm_i915_gem_request *req,
unsigned entry,
dma_addr_t addr)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
BUG_ON(entry >= 4);
@@ -1588,7 +1588,7 @@ static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
/* NB: TLBs must be flushed and invalidated before a switch */
@@ -1626,7 +1626,7 @@ static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
/* NB: TLBs must be flushed and invalidated before a switch */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2447f1a36fb0..cdd6074257af 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10824,7 +10824,7 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
u32 flip_mask;
int ret;
@@ -10859,7 +10859,7 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
u32 flip_mask;
int ret;
@@ -10891,7 +10891,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct drm_i915_private *dev_priv = req->i915;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t pf, pipesrc;
@@ -10930,7 +10930,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct drm_i915_private *dev_priv = req->i915;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t pf, pipesrc;
@@ -10966,7 +10966,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
struct drm_i915_gem_request *req,
uint32_t flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
uint32_t plane_bit = 0;
int len, ret;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 1502e53d2ad6..5c37922c3cde 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -339,7 +339,7 @@ static int execlists_update_context(struct drm_i915_gem_request *rq)
{
struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[rq->engine->id].state;
- struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
+ struct drm_i915_gem_object *rb_obj = rq->ring->obj;
struct page *page;
uint32_t *reg_state;
@@ -545,7 +545,7 @@ static int execlists_context_queue(struct drm_i915_gem_request *request)
i915_gem_request_reference(request);
- request->tail = request->ringbuf->tail;
+ request->tail = request->ring->tail;
spin_lock_irq(&engine->execlist_lock);
@@ -633,7 +633,7 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request
{
int ret;
- request->ringbuf = request->ctx->engine[request->engine->id].ringbuf;
+ request->ring = request->ctx->engine[request->engine->id].ringbuf;
if (request->ctx != request->engine->default_context) {
ret = intel_lr_context_pin(request);
@@ -656,7 +656,7 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request
static void
intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
{
- intel_ring_advance(request->ringbuf);
+ intel_ring_advance(request->ring);
if (intel_ring_stopped(request->engine))
return;
@@ -686,9 +686,9 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
struct list_head *vmas)
{
struct drm_device *dev = params->dev;
- struct intel_engine_cs *ring = params->ring;
+ struct intel_engine_cs *engine = params->ring;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf;
+ struct intel_ringbuffer *ring = params->request->ring;
u64 exec_start;
int instp_mode;
u32 instp_mask;
@@ -700,7 +700,7 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
case I915_EXEC_CONSTANTS_REL_GENERAL:
case I915_EXEC_CONSTANTS_ABSOLUTE:
case I915_EXEC_CONSTANTS_REL_SURFACE:
- if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
+ if (instp_mode != 0 && engine->id != RCS) {
DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
return -EINVAL;
}
@@ -729,17 +729,17 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
if (ret)
return ret;
- if (ring == &dev_priv->ring[RCS] &&
+ if (engine->id == RCS &&
instp_mode != dev_priv->relative_constants_mode) {
ret = intel_ring_begin(params->request, 4);
if (ret)
return ret;
- intel_ring_emit(ringbuf, MI_NOOP);
- intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
- intel_ring_emit(ringbuf, INSTPM);
- intel_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
- intel_ring_advance(ringbuf);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
+ intel_ring_emit(ring, INSTPM);
+ intel_ring_emit(ring, instp_mask << 16 | instp_mode);
+ intel_ring_advance(ring);
dev_priv->relative_constants_mode = instp_mode;
}
@@ -747,7 +747,7 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
exec_start = params->batch_obj_vm_offset +
args->batch_start_offset;
- ret = ring->emit_bb_start(params->request, exec_start, params->dispatch_flags);
+ ret = engine->emit_bb_start(params->request, exec_start, params->dispatch_flags);
if (ret)
return ret;
@@ -827,7 +827,7 @@ static int intel_lr_context_pin(struct drm_i915_gem_request *rq)
{
int engine = rq->engine->id;
struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[engine].state;
- struct intel_ringbuffer *ringbuf = rq->ringbuf;
+ struct intel_ringbuffer *ring = rq->ring;
int ret = 0;
WARN_ON(!mutex_is_locked(&rq->i915->dev->struct_mutex));
@@ -837,7 +837,7 @@ static int intel_lr_context_pin(struct drm_i915_gem_request *rq)
if (ret)
goto reset_pin_count;
- ret = intel_pin_and_map_ringbuffer_obj(rq->i915->dev, ringbuf);
+ ret = intel_pin_and_map_ringbuffer_obj(rq->i915->dev, ring);
if (ret)
goto unpin_ctx_obj;
@@ -858,12 +858,12 @@ void intel_lr_context_unpin(struct drm_i915_gem_request *rq)
{
int engine = rq->engine->id;
struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[engine].state;
- struct intel_ringbuffer *ringbuf = rq->ringbuf;
+ struct intel_ringbuffer *ring = rq->ring;
if (ctx_obj) {
WARN_ON(!mutex_is_locked(&rq->i915->dev->struct_mutex));
if (--rq->ctx->engine[engine].pin_count == 0) {
- intel_unpin_ringbuffer_obj(ringbuf);
+ intel_unpin_ringbuffer_obj(ring);
i915_gem_object_ggtt_unpin(ctx_obj);
}
}
@@ -873,7 +873,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
{
int ret, i;
struct intel_engine_cs *engine = req->engine;
- struct intel_ringbuffer *ringbuf = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct drm_i915_private *dev_priv = req->i915;
struct i915_workarounds *w = &dev_priv->workarounds;
@@ -889,14 +889,14 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
if (ret)
return ret;
- intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
for (i = 0; i < w->count; i++) {
- intel_ring_emit(ringbuf, w->reg[i].addr);
- intel_ring_emit(ringbuf, w->reg[i].value);
+ intel_ring_emit(ring, w->reg[i].addr);
+ intel_ring_emit(ring, w->reg[i].value);
}
- intel_ring_emit(ringbuf, MI_NOOP);
+ intel_ring_emit(ring, MI_NOOP);
- intel_ring_advance(ringbuf);
+ intel_ring_advance(ring);
engine->gpu_caches_dirty = true;
ret = logical_ring_flush_all_caches(req);
@@ -1318,7 +1318,7 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
{
struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
struct intel_engine_cs *engine = req->engine;
- struct intel_ringbuffer *ringbuf = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
int i, ret;
@@ -1326,18 +1326,18 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
if (ret)
return ret;
- intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_lri_cmds));
for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
- intel_ring_emit(ringbuf, GEN8_RING_PDP_UDW(engine, i));
- intel_ring_emit(ringbuf, upper_32_bits(pd_daddr));
- intel_ring_emit(ringbuf, GEN8_RING_PDP_LDW(engine, i));
- intel_ring_emit(ringbuf, lower_32_bits(pd_daddr));
+ intel_ring_emit(ring, GEN8_RING_PDP_UDW(engine, i));
+ intel_ring_emit(ring, upper_32_bits(pd_daddr));
+ intel_ring_emit(ring, GEN8_RING_PDP_LDW(engine, i));
+ intel_ring_emit(ring, lower_32_bits(pd_daddr));
}
- intel_ring_emit(ringbuf, MI_NOOP);
- intel_ring_advance(ringbuf);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
return 0;
}
@@ -1345,7 +1345,7 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
u64 offset, unsigned dispatch_flags)
{
- struct intel_ringbuffer *ringbuf = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
int ret;
@@ -1371,14 +1371,14 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
return ret;
/* FIXME(BDW): Address space and security selectors. */
- intel_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
+ intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 |
(ppgtt<<8) |
(dispatch_flags & I915_DISPATCH_RS ?
MI_BATCH_RESOURCE_STREAMER : 0));
- intel_ring_emit(ringbuf, lower_32_bits(offset));
- intel_ring_emit(ringbuf, upper_32_bits(offset));
- intel_ring_emit(ringbuf, MI_NOOP);
- intel_ring_advance(ringbuf);
+ intel_ring_emit(ring, lower_32_bits(offset));
+ intel_ring_emit(ring, upper_32_bits(offset));
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
return 0;
}
@@ -1420,10 +1420,7 @@ static int gen8_emit_flush(struct drm_i915_gem_request *request,
u32 invalidate_domains,
u32 unused)
{
- struct intel_ringbuffer *ringbuf = request->ringbuf;
- struct intel_engine_cs *ring = ringbuf->ring;
- struct drm_device *dev = ring->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_ringbuffer *ring = request->ring;
uint32_t cmd;
int ret;
@@ -1442,17 +1439,17 @@ static int gen8_emit_flush(struct drm_i915_gem_request *request,
if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
cmd |= MI_INVALIDATE_TLB;
- if (ring == &dev_priv->ring[VCS])
+ if (request->engine->id == VCS)
cmd |= MI_INVALIDATE_BSD;
}
- intel_ring_emit(ringbuf, cmd);
- intel_ring_emit(ringbuf,
+ intel_ring_emit(ring, cmd);
+ intel_ring_emit(ring,
I915_GEM_HWS_SCRATCH_ADDR |
MI_FLUSH_DW_USE_GTT);
- intel_ring_emit(ringbuf, 0); /* upper addr */
- intel_ring_emit(ringbuf, 0); /* value */
- intel_ring_advance(ringbuf);
+ intel_ring_emit(ring, 0); /* upper addr */
+ intel_ring_emit(ring, 0); /* value */
+ intel_ring_advance(ring);
return 0;
}
@@ -1461,9 +1458,8 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
u32 invalidate_domains,
u32 flush_domains)
{
- struct intel_ringbuffer *ringbuf = request->ringbuf;
- struct intel_engine_cs *ring = ringbuf->ring;
- u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
+ struct intel_ringbuffer *ring = request->ring;
+ u32 scratch_addr = request->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
bool vf_flush_wa;
u32 flags = 0;
int ret;
@@ -1491,7 +1487,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
* On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
* control.
*/
- vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
+ vf_flush_wa = INTEL_INFO(request->i915)->gen >= 9 &&
flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
ret = intel_ring_begin(request, vf_flush_wa ? 12 : 6);
@@ -1499,21 +1495,21 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
return ret;
if (vf_flush_wa) {
- intel_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
- intel_ring_emit(ringbuf, 0);
- intel_ring_emit(ringbuf, 0);
- intel_ring_emit(ringbuf, 0);
- intel_ring_emit(ringbuf, 0);
- intel_ring_emit(ringbuf, 0);
+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
}
- intel_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
- intel_ring_emit(ringbuf, flags);
- intel_ring_emit(ringbuf, scratch_addr);
- intel_ring_emit(ringbuf, 0);
- intel_ring_emit(ringbuf, 0);
- intel_ring_emit(ringbuf, 0);
- intel_ring_advance(ringbuf);
+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
+ intel_ring_emit(ring, flags);
+ intel_ring_emit(ring, scratch_addr);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, 0);
+ intel_ring_advance(ring);
return 0;
}
@@ -1530,8 +1526,7 @@ static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
static int gen8_emit_request(struct drm_i915_gem_request *request)
{
- struct intel_ringbuffer *ringbuf = request->ringbuf;
- struct intel_engine_cs *ring = ringbuf->ring;
+ struct intel_ringbuffer *ring = request->ring;
u32 cmd;
int ret;
@@ -1547,23 +1542,23 @@ static int gen8_emit_request(struct drm_i915_gem_request *request)
cmd = MI_STORE_DWORD_IMM_GEN4;
cmd |= MI_GLOBAL_GTT;
- intel_ring_emit(ringbuf, cmd);
- intel_ring_emit(ringbuf,
- (ring->status_page.gfx_addr +
+ intel_ring_emit(ring, cmd);
+ intel_ring_emit(ring,
+ (request->engine->status_page.gfx_addr +
(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
- intel_ring_emit(ringbuf, 0);
- intel_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
- intel_ring_emit(ringbuf, MI_USER_INTERRUPT);
- intel_ring_emit(ringbuf, MI_NOOP);
+ intel_ring_emit(ring, 0);
+ intel_ring_emit(ring, i915_gem_request_get_seqno(request));
+ intel_ring_emit(ring, MI_USER_INTERRUPT);
+ intel_ring_emit(ring, MI_NOOP);
intel_logical_ring_advance_and_submit(request);
/*
* Here we add two extra NOOPs as padding to avoid
* lite restore of a context with HEAD==TAIL.
*/
- intel_ring_emit(ringbuf, MI_NOOP);
- intel_ring_emit(ringbuf, MI_NOOP);
- intel_ring_advance(ringbuf);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index d79c9c0bbffb..3a1bd5f7af55 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -174,7 +174,7 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
const struct drm_i915_mocs_table *table,
u32 reg_base)
{
- struct intel_ringbuffer *ringbuf = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
unsigned int index;
int ret;
@@ -185,11 +185,11 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
if (ret)
return ret;
- intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
+ intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
for (index = 0; index < table->size; index++) {
- intel_ring_emit(ringbuf, reg_base + index * 4);
- intel_ring_emit(ringbuf, table->table[index].control_value);
+ intel_ring_emit(ring, reg_base + index * 4);
+ intel_ring_emit(ring, table->table[index].control_value);
}
/*
@@ -201,12 +201,12 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
* that value to all the used entries.
*/
for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
- intel_ring_emit(ringbuf, reg_base + index * 4);
- intel_ring_emit(ringbuf, table->table[0].control_value);
+ intel_ring_emit(ring, reg_base + index * 4);
+ intel_ring_emit(ring, table->table[0].control_value);
}
- intel_ring_emit(ringbuf, MI_NOOP);
- intel_ring_advance(ringbuf);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
return 0;
}
@@ -225,7 +225,7 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
const struct drm_i915_mocs_table *table)
{
- struct intel_ringbuffer *ringbuf = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
unsigned int count;
unsigned int i;
u32 value;
@@ -240,15 +240,15 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
if (ret)
return ret;
- intel_ring_emit(ringbuf,
+ intel_ring_emit(ring,
MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2));
for (i = 0, count = 0; i < table->size / 2; i++, count += 2) {
value = (table->table[count].l3cc_value & 0xffff) |
((table->table[count + 1].l3cc_value & 0xffff) << 16);
- intel_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);
- intel_ring_emit(ringbuf, value);
+ intel_ring_emit(ring, GEN9_LNCFCMOCS0 + i * 4);
+ intel_ring_emit(ring, value);
}
if (table->size & 0x01) {
@@ -264,14 +264,14 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
* they are reserved by the hardware.
*/
for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
- intel_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);
- intel_ring_emit(ringbuf, value);
+ intel_ring_emit(ring, GEN9_LNCFCMOCS0 + i * 4);
+ intel_ring_emit(ring, value);
value = filler;
}
- intel_ring_emit(ringbuf, MI_NOOP);
- intel_ring_advance(ringbuf);
+ intel_ring_emit(ring, MI_NOOP);
+ intel_ring_advance(ring);
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index 5e9c7c15a84b..451c59b8f526 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -252,11 +252,11 @@ static int intel_overlay_on(struct intel_overlay *overlay)
overlay->active = true;
- intel_ring_emit(req->ringbuf, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
- intel_ring_emit(req->ringbuf, overlay->flip_addr | OFC_UPDATE);
- intel_ring_emit(req->ringbuf, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
- intel_ring_emit(req->ringbuf, MI_NOOP);
- intel_ring_advance(req->ringbuf);
+ intel_ring_emit(req->ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
+ intel_ring_emit(req->ring, overlay->flip_addr | OFC_UPDATE);
+ intel_ring_emit(req->ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
+ intel_ring_emit(req->ring, MI_NOOP);
+ intel_ring_advance(req->ring);
return intel_overlay_do_wait_request(overlay, req, NULL);
}
@@ -293,9 +293,9 @@ static int intel_overlay_continue(struct intel_overlay *overlay,
return ret;
}
- intel_ring_emit(req->ringbuf, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
- intel_ring_emit(req->ringbuf, flip_addr);
- intel_ring_advance(req->ringbuf);
+ intel_ring_emit(req->ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
+ intel_ring_emit(req->ring, flip_addr);
+ intel_ring_advance(req->ring);
WARN_ON(overlay->last_flip_req);
i915_gem_request_assign(&overlay->last_flip_req, req);
@@ -360,22 +360,22 @@ static int intel_overlay_off(struct intel_overlay *overlay)
}
/* wait for overlay to go idle */
- intel_ring_emit(req->ringbuf, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
- intel_ring_emit(req->ringbuf, flip_addr);
- intel_ring_emit(req->ringbuf, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
+ intel_ring_emit(req->ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
+ intel_ring_emit(req->ring, flip_addr);
+ intel_ring_emit(req->ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
/* turn overlay off */
if (IS_I830(dev)) {
/* Workaround: Don't disable the overlay fully, since otherwise
* it dies on the next OVERLAY_ON cmd. */
- intel_ring_emit(req->ringbuf, MI_NOOP);
- intel_ring_emit(req->ringbuf, MI_NOOP);
- intel_ring_emit(req->ringbuf, MI_NOOP);
+ intel_ring_emit(req->ring, MI_NOOP);
+ intel_ring_emit(req->ring, MI_NOOP);
+ intel_ring_emit(req->ring, MI_NOOP);
} else {
- intel_ring_emit(req->ringbuf, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
- intel_ring_emit(req->ringbuf, flip_addr);
- intel_ring_emit(req->ringbuf, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
+ intel_ring_emit(req->ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
+ intel_ring_emit(req->ring, flip_addr);
+ intel_ring_emit(req->ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
}
- intel_ring_advance(req->ringbuf);
+ intel_ring_advance(req->ring);
return intel_overlay_do_wait_request(overlay, req, intel_overlay_off_tail);
}
@@ -433,9 +433,9 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
return ret;
}
- intel_ring_emit(req->ringbuf, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
- intel_ring_emit(req->ringbuf, MI_NOOP);
- intel_ring_advance(req->ringbuf);
+ intel_ring_emit(req->ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
+ intel_ring_emit(req->ring, MI_NOOP);
+ intel_ring_advance(req->ring);
ret = intel_overlay_do_wait_request(overlay, req,
intel_overlay_release_old_vid_tail);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index cc060588a287..c4610c727c49 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -95,7 +95,7 @@ gen2_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains,
u32 flush_domains)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
u32 cmd;
int ret;
@@ -122,7 +122,7 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains,
u32 flush_domains)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
u32 cmd;
int ret;
@@ -215,7 +215,7 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
static int
intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
int ret;
@@ -251,7 +251,7 @@ static int
gen6_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains, u32 flush_domains)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
u32 flags = 0;
u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
int ret;
@@ -303,7 +303,7 @@ gen6_render_ring_flush(struct drm_i915_gem_request *req,
static int
gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 4);
@@ -324,7 +324,7 @@ static int
gen7_render_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains, u32 flush_domains)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
u32 flags = 0;
u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
int ret;
@@ -387,7 +387,7 @@ static int
gen8_emit_pipe_control(struct drm_i915_gem_request *req,
u32 flags, u32 scratch_addr)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 6);
@@ -712,7 +712,7 @@ err:
static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct drm_i915_private *dev_priv = req->i915;
struct i915_workarounds *w = &dev_priv->workarounds;
int ret, i;
@@ -1184,7 +1184,7 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
unsigned int num_dwords)
{
#define MBOX_UPDATE_DWORDS 8
- struct intel_ringbuffer *signaller = signaller_req->ringbuf;
+ struct intel_ringbuffer *signaller = signaller_req->ring;
struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *waiter;
int i, ret, num_rings;
@@ -1224,7 +1224,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
unsigned int num_dwords)
{
#define MBOX_UPDATE_DWORDS 6
- struct intel_ringbuffer *signaller = signaller_req->ringbuf;
+ struct intel_ringbuffer *signaller = signaller_req->ring;
struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *waiter;
int i, ret, num_rings;
@@ -1261,7 +1261,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
static int gen6_signal(struct drm_i915_gem_request *signaller_req,
unsigned int num_dwords)
{
- struct intel_ringbuffer *signaller = signaller_req->ringbuf;
+ struct intel_ringbuffer *signaller = signaller_req->ring;
struct drm_i915_private *dev_priv = signaller_req->i915;
struct intel_engine_cs *useless;
int i, ret, num_rings;
@@ -1303,7 +1303,7 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
static int
gen6_add_request(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
if (req->engine->semaphore.signal)
@@ -1342,7 +1342,7 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
struct intel_engine_cs *signaller,
u32 seqno)
{
- struct intel_ringbuffer *waiter = waiter_req->ringbuf;
+ struct intel_ringbuffer *waiter = waiter_req->ring;
struct drm_i915_private *dev_priv = waiter_req->i915;
int ret;
@@ -1370,7 +1370,7 @@ gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
struct intel_engine_cs *signaller,
u32 seqno)
{
- struct intel_ringbuffer *waiter = waiter_req->ringbuf;
+ struct intel_ringbuffer *waiter = waiter_req->ring;
u32 dw1 = MI_SEMAPHORE_MBOX |
MI_SEMAPHORE_COMPARE |
MI_SEMAPHORE_REGISTER;
@@ -1418,7 +1418,7 @@ do { \
static int
pc_render_add_request(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
int ret;
@@ -1612,7 +1612,7 @@ bsd_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate_domains,
u32 flush_domains)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 2);
@@ -1628,7 +1628,7 @@ bsd_ring_flush(struct drm_i915_gem_request *req,
static int
i9xx_add_request(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 4);
@@ -1773,7 +1773,7 @@ i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 length,
unsigned dispatch_flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 2);
@@ -1800,7 +1800,7 @@ i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
u32 cs_offset = req->engine->scratch.gtt_offset;
int ret;
@@ -1863,7 +1863,7 @@ i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 2);
@@ -2164,7 +2164,7 @@ int intel_ring_idle(struct intel_engine_cs *ring)
int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
{
- request->ringbuf = request->engine->buffer;
+ request->ring = request->engine->buffer;
return 0;
}
@@ -2217,17 +2217,17 @@ void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
{
- struct intel_ringbuffer *ringbuf = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
struct intel_engine_cs *engine = req->engine;
struct drm_i915_gem_request *target;
unsigned space;
int ret;
- if (intel_ring_space(ringbuf) >= bytes)
+ if (intel_ring_space(ring) >= bytes)
return 0;
/* The whole point of reserving space is to not wait! */
- WARN_ON(ringbuf->reserved_in_use);
+ WARN_ON(ring->reserved_in_use);
list_for_each_entry(target, &engine->request_list, list) {
/*
@@ -2235,12 +2235,12 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
* from multiple ringbuffers. Here, we must ignore any that
* aren't from the ringbuffer we're considering.
*/
- if (target->ringbuf != ringbuf)
+ if (target->ring != ring)
continue;
/* Would completion of this request free enough space? */
- space = __intel_ring_space(target->postfix, ringbuf->tail,
- ringbuf->size);
+ space = __intel_ring_space(target->postfix, ring->tail,
+ ring->size);
if (space >= bytes)
break;
}
@@ -2252,7 +2252,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
if (ret)
return ret;
- ringbuf->space = space;
+ ring->space = space;
return 0;
}
@@ -2267,16 +2267,16 @@ static void ring_wrap(struct intel_ringbuffer *ringbuf)
static int ring_prepare(struct drm_i915_gem_request *req, int bytes)
{
- struct intel_ringbuffer *ringbuf = req->ringbuf;
- int remain_usable = ringbuf->effective_size - ringbuf->tail;
- int remain_actual = ringbuf->size - ringbuf->tail;
+ struct intel_ringbuffer *ring = req->ring;
+ int remain_usable = ring->effective_size - ring->tail;
+ int remain_actual = ring->size - ring->tail;
int ret, total_bytes, wait_bytes = 0;
bool need_wrap = false;
- if (ringbuf->reserved_in_use)
+ if (ring->reserved_in_use)
total_bytes = bytes;
else
- total_bytes = bytes + ringbuf->reserved_size;
+ total_bytes = bytes + ring->reserved_size;
if (unlikely(bytes > remain_usable)) {
/*
@@ -2292,9 +2292,9 @@ static int ring_prepare(struct drm_i915_gem_request *req, int bytes)
* falls off the end. So only need to to wait for the
* reserved size after flushing out the remainder.
*/
- wait_bytes = remain_actual + ringbuf->reserved_size;
+ wait_bytes = remain_actual + ring->reserved_size;
need_wrap = true;
- } else if (total_bytes > ringbuf->space) {
+ } else if (total_bytes > ring->space) {
/* No wrapping required, just waiting. */
wait_bytes = total_bytes;
}
@@ -2306,7 +2306,7 @@ static int ring_prepare(struct drm_i915_gem_request *req, int bytes)
return ret;
if (need_wrap)
- ring_wrap(ringbuf);
+ ring_wrap(ring);
}
return 0;
@@ -2325,14 +2325,14 @@ int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
if (ret)
return ret;
- req->ringbuf->space -= num_dwords * sizeof(uint32_t);
+ req->ring->space -= num_dwords * sizeof(uint32_t);
return 0;
}
/* Align the ring tail to a cacheline boundary */
int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int num_dwords = (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
int ret;
@@ -2404,7 +2404,7 @@ static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate, u32 flush)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
uint32_t cmd;
int ret;
@@ -2450,7 +2450,7 @@ gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
bool ppgtt = USES_PPGTT(req->i915) &&
!(dispatch_flags & I915_DISPATCH_SECURE);
int ret;
@@ -2476,7 +2476,7 @@ hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 2);
@@ -2501,7 +2501,7 @@ gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
u64 offset, u32 len,
unsigned dispatch_flags)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
int ret;
ret = intel_ring_begin(req, 2);
@@ -2524,7 +2524,7 @@ gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
static int gen6_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate, u32 flush)
{
- struct intel_ringbuffer *ring = req->ringbuf;
+ struct intel_ringbuffer *ring = req->ring;
uint32_t cmd;
int ret;
--
2.6.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 08/12] drm/i915: Rename backpointer from intel_ringbuffer to intel_engine_cs
2015-11-20 12:43 [PATCH 01/12] drm/i915: Convert i915_semaphores_is_enabled over to drm_i915_private Chris Wilson
` (5 preceding siblings ...)
2015-11-20 12:43 ` [PATCH 07/12] drm/i915: Rename request->ringbuf to request->ring Chris Wilson
@ 2015-11-20 12:43 ` Chris Wilson
2015-11-24 14:58 ` Daniel Vetter
2015-11-20 12:43 ` [PATCH 09/12] drm/i915: Rename intel_context[engine].ringbuf Chris Wilson
` (4 subsequent siblings)
11 siblings, 1 reply; 41+ messages in thread
From: Chris Wilson @ 2015-11-20 12:43 UTC (permalink / raw)
To: intel-gfx
Having ringbuf->ring point to an engine is confusing, so rename it once
again to ring->engine.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_lrc.c | 46 ++++++++++++++++-----------------
drivers/gpu/drm/i915/intel_ringbuffer.c | 36 +++++++++++++-------------
drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
3 files changed, 42 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 5c37922c3cde..346f5889738e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2089,13 +2089,13 @@ void intel_lr_context_free(struct intel_context *ctx)
if (ctx_obj) {
struct intel_ringbuffer *ringbuf =
ctx->engine[i].ringbuf;
- struct intel_engine_cs *ring = ringbuf->ring;
+ struct intel_engine_cs *engine = ringbuf->engine;
- if (ctx == ring->default_context) {
+ if (ctx == engine->default_context) {
intel_unpin_ringbuffer_obj(ringbuf);
i915_gem_object_ggtt_unpin(ctx_obj);
}
- WARN_ON(ctx->engine[ring->id].pin_count);
+ WARN_ON(ctx->engine[engine->id].pin_count);
intel_destroy_ringbuffer_obj(ringbuf);
kfree(ringbuf);
drm_gem_object_unreference(&ctx_obj->base);
@@ -2158,19 +2158,19 @@ static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
* Return: non-zero on error.
*/
int intel_lr_context_deferred_create(struct intel_context *ctx,
- struct intel_engine_cs *ring)
+ struct intel_engine_cs *engine)
{
- const bool is_global_default_ctx = (ctx == ring->default_context);
- struct drm_device *dev = ring->dev;
+ const bool is_global_default_ctx = (ctx == engine->default_context);
+ struct drm_device *dev = engine->dev;
struct drm_i915_gem_object *ctx_obj;
uint32_t context_size;
struct intel_ringbuffer *ringbuf;
int ret;
WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
- WARN_ON(ctx->engine[ring->id].state);
+ WARN_ON(ctx->engine[engine->id].state);
- context_size = round_up(get_lr_context_size(ring), 4096);
+ context_size = round_up(get_lr_context_size(engine), 4096);
ctx_obj = i915_gem_alloc_object(dev, context_size);
if (!ctx_obj) {
@@ -2191,12 +2191,12 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
if (!ringbuf) {
DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
- ring->name);
+ engine->name);
ret = -ENOMEM;
goto error_unpin_ctx;
}
- ringbuf->ring = ring;
+ ringbuf->engine = engine;
ringbuf->size = 32 * PAGE_SIZE;
ringbuf->effective_size = ringbuf->size;
@@ -2210,7 +2210,7 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
if (ret) {
DRM_DEBUG_DRIVER(
"Failed to allocate ringbuffer obj %s: %d\n",
- ring->name, ret);
+ engine->name, ret);
goto error_free_rbuf;
}
@@ -2219,38 +2219,38 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
if (ret) {
DRM_ERROR(
"Failed to pin and map ringbuffer %s: %d\n",
- ring->name, ret);
+ engine->name, ret);
goto error_destroy_rbuf;
}
}
}
- ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
+ ret = populate_lr_context(ctx, ctx_obj, engine, ringbuf);
if (ret) {
DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
goto error;
}
- ctx->engine[ring->id].ringbuf = ringbuf;
- ctx->engine[ring->id].state = ctx_obj;
+ ctx->engine[engine->id].ringbuf = ringbuf;
+ ctx->engine[engine->id].state = ctx_obj;
- if (ctx == ring->default_context)
- lrc_setup_hardware_status_page(ring, ctx_obj);
- else if (ring->id == RCS && !ctx->rcs_initialized) {
- if (ring->init_context) {
+ if (ctx == engine->default_context)
+ lrc_setup_hardware_status_page(engine, ctx_obj);
+ else if (engine->id == RCS && !ctx->rcs_initialized) {
+ if (engine->init_context) {
struct drm_i915_gem_request *req;
- ret = i915_gem_request_alloc(ring, ctx, &req);
+ ret = i915_gem_request_alloc(engine, ctx, &req);
if (ret)
return ret;
- ret = ring->init_context(req);
+ ret = engine->init_context(req);
if (ret) {
DRM_ERROR("ring init context: %d\n", ret);
i915_gem_request_cancel(req);
- ctx->engine[ring->id].ringbuf = NULL;
- ctx->engine[ring->id].state = NULL;
+ ctx->engine[engine->id].ringbuf = NULL;
+ ctx->engine[engine->id].state = NULL;
goto error;
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index c4610c727c49..1d43a24b6268 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2043,36 +2043,36 @@ int intel_alloc_ringbuffer_obj(struct drm_device *dev,
}
static int intel_init_ring_buffer(struct drm_device *dev,
- struct intel_engine_cs *ring)
+ struct intel_engine_cs *engine)
{
struct intel_ringbuffer *ringbuf;
int ret;
- WARN_ON(ring->buffer);
+ WARN_ON(engine->buffer);
ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
if (!ringbuf)
return -ENOMEM;
- ring->buffer = ringbuf;
+ engine->buffer = ringbuf;
- ring->dev = dev;
- INIT_LIST_HEAD(&ring->active_list);
- INIT_LIST_HEAD(&ring->request_list);
- INIT_LIST_HEAD(&ring->execlist_queue);
- i915_gem_batch_pool_init(dev, &ring->batch_pool);
+ engine->dev = dev;
+ INIT_LIST_HEAD(&engine->active_list);
+ INIT_LIST_HEAD(&engine->request_list);
+ INIT_LIST_HEAD(&engine->execlist_queue);
+ i915_gem_batch_pool_init(dev, &engine->batch_pool);
ringbuf->size = 32 * PAGE_SIZE;
- ringbuf->ring = ring;
- memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
+ ringbuf->engine = engine;
+ memset(engine->semaphore.sync_seqno, 0, sizeof(engine->semaphore.sync_seqno));
- init_waitqueue_head(&ring->irq_queue);
+ init_waitqueue_head(&engine->irq_queue);
if (I915_NEED_GFX_HWS(dev)) {
- ret = init_status_page(ring);
+ ret = init_status_page(engine);
if (ret)
goto error;
} else {
- BUG_ON(ring->id != RCS);
- ret = init_phys_status_page(ring);
+ BUG_ON(engine->id != RCS);
+ ret = init_phys_status_page(engine);
if (ret)
goto error;
}
@@ -2082,14 +2082,14 @@ static int intel_init_ring_buffer(struct drm_device *dev,
ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
if (ret) {
DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
- ring->name, ret);
+ engine->name, ret);
goto error;
}
ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
if (ret) {
DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
- ring->name, ret);
+ engine->name, ret);
intel_destroy_ringbuffer_obj(ringbuf);
goto error;
}
@@ -2102,7 +2102,7 @@ static int intel_init_ring_buffer(struct drm_device *dev,
if (IS_I830(dev) || IS_845G(dev))
ringbuf->effective_size -= 2 * CACHELINE_BYTES;
- ret = i915_cmd_parser_init_ring(ring);
+ ret = i915_cmd_parser_init_ring(engine);
if (ret)
goto error;
@@ -2110,7 +2110,7 @@ static int intel_init_ring_buffer(struct drm_device *dev,
error:
kfree(ringbuf);
- ring->buffer = NULL;
+ engine->buffer = NULL;
return ret;
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 368d9b0454ed..6a9056e3ac46 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -99,7 +99,7 @@ struct intel_ringbuffer {
struct drm_i915_gem_object *obj;
void *virtual_start;
- struct intel_engine_cs *ring;
+ struct intel_engine_cs *engine;
u32 head;
u32 tail;
--
2.6.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 09/12] drm/i915: Rename intel_context[engine].ringbuf
2015-11-20 12:43 [PATCH 01/12] drm/i915: Convert i915_semaphores_is_enabled over to drm_i915_private Chris Wilson
` (6 preceding siblings ...)
2015-11-20 12:43 ` [PATCH 08/12] drm/i915: Rename backpointer from intel_ringbuffer to intel_engine_cs Chris Wilson
@ 2015-11-20 12:43 ` Chris Wilson
2015-11-24 14:59 ` Daniel Vetter
2015-11-24 15:09 ` Tvrtko Ursulin
2015-11-20 12:43 ` [PATCH 10/12] drm/i915: Reduce the pointer dance of i915_is_ggtt() Chris Wilson
` (3 subsequent siblings)
11 siblings, 2 replies; 41+ messages in thread
From: Chris Wilson @ 2015-11-20 12:43 UTC (permalink / raw)
To: intel-gfx
Perform s/ringbuf/ring/ on the context struct for consistency with the
ring/engine split.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
drivers/gpu/drm/i915/intel_lrc.c | 85 ++++++++++++++++-----------------
drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++---
5 files changed, 52 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 56375c36b381..630717fec688 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1950,7 +1950,7 @@ static int i915_context_status(struct seq_file *m, void *unused)
struct drm_i915_gem_object *ctx_obj =
ctx->engine[i].state;
struct intel_ringbuffer *ringbuf =
- ctx->engine[i].ringbuf;
+ ctx->engine[i].ring;
seq_printf(m, "%s: ", ring->name);
if (ctx_obj)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b7eaa2deb437..d8bd58cbb727 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -882,9 +882,9 @@ struct intel_context {
/* Execlists */
bool rcs_initialized;
- struct {
+ struct intel_context_engine {
struct drm_i915_gem_object *state;
- struct intel_ringbuffer *ringbuf;
+ struct intel_ringbuffer *ring;
int pin_count;
} engine[I915_NUM_RINGS];
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 974e3481e449..8b37f72bd91f 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1040,9 +1040,9 @@ static void i915_gem_record_rings(struct drm_device *dev,
* executed).
*/
if (request)
- rbuf = request->ctx->engine[ring->id].ringbuf;
+ rbuf = request->ctx->engine[ring->id].ring;
else
- rbuf = ring->default_context->engine[ring->id].ringbuf;
+ rbuf = ring->default_context->engine[ring->id].ring;
} else
rbuf = ring->buffer;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 346f5889738e..222ae8383f48 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -381,24 +381,24 @@ static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
execlists_elsp_write(rq0, rq1);
}
-static void execlists_context_unqueue(struct intel_engine_cs *ring)
+static void execlists_context_unqueue(struct intel_engine_cs *engine)
{
struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
- assert_spin_locked(&ring->execlist_lock);
+ assert_spin_locked(&engine->execlist_lock);
/*
* If irqs are not active generate a warning as batches that finish
* without the irqs may get lost and a GPU Hang may occur.
*/
- WARN_ON(!intel_irqs_enabled(ring->dev->dev_private));
+ WARN_ON(!intel_irqs_enabled(engine->dev->dev_private));
- if (list_empty(&ring->execlist_queue))
+ if (list_empty(&engine->execlist_queue))
return;
/* Try to read in pairs */
- list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
+ list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue,
execlist_link) {
if (!req0) {
req0 = cursor;
@@ -408,7 +408,7 @@ static void execlists_context_unqueue(struct intel_engine_cs *ring)
cursor->elsp_submitted = req0->elsp_submitted;
list_del(&req0->execlist_link);
list_add_tail(&req0->execlist_link,
- &ring->execlist_retired_req_list);
+ &engine->execlist_retired_req_list);
req0 = cursor;
} else {
req1 = cursor;
@@ -416,7 +416,7 @@ static void execlists_context_unqueue(struct intel_engine_cs *ring)
}
}
- if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
+ if (IS_GEN8(engine->dev) || IS_GEN9(engine->dev)) {
/*
* WaIdleLiteRestore: make sure we never cause a lite
* restore with HEAD==TAIL
@@ -428,11 +428,11 @@ static void execlists_context_unqueue(struct intel_engine_cs *ring)
* for where we prepare the padding after the end of the
* request.
*/
- struct intel_ringbuffer *ringbuf;
+ struct intel_ringbuffer *ring;
- ringbuf = req0->ctx->engine[ring->id].ringbuf;
+ ring = req0->ctx->engine[engine->id].ring;
req0->tail += 8;
- req0->tail &= ringbuf->size - 1;
+ req0->tail &= ring->size - 1;
}
}
@@ -633,7 +633,7 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request
{
int ret;
- request->ring = request->ctx->engine[request->engine->id].ringbuf;
+ request->ring = request->ctx->engine[request->engine->id].ring;
if (request->ctx != request->engine->default_context) {
ret = intel_lr_context_pin(request);
@@ -2087,17 +2087,16 @@ void intel_lr_context_free(struct intel_context *ctx)
struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
if (ctx_obj) {
- struct intel_ringbuffer *ringbuf =
- ctx->engine[i].ringbuf;
- struct intel_engine_cs *engine = ringbuf->engine;
+ struct intel_ringbuffer *ring = ctx->engine[i].ring;
+ struct intel_engine_cs *engine = ring->engine;
if (ctx == engine->default_context) {
- intel_unpin_ringbuffer_obj(ringbuf);
+ intel_unpin_ringbuffer_obj(ring);
i915_gem_object_ggtt_unpin(ctx_obj);
}
WARN_ON(ctx->engine[engine->id].pin_count);
- intel_destroy_ringbuffer_obj(ringbuf);
- kfree(ringbuf);
+ intel_destroy_ringbuffer_obj(ring);
+ kfree(ring);
drm_gem_object_unreference(&ctx_obj->base);
}
}
@@ -2164,7 +2163,7 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
struct drm_device *dev = engine->dev;
struct drm_i915_gem_object *ctx_obj;
uint32_t context_size;
- struct intel_ringbuffer *ringbuf;
+ struct intel_ringbuffer *ring;
int ret;
WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
@@ -2188,25 +2187,25 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
}
}
- ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
- if (!ringbuf) {
+ ring = kzalloc(sizeof(*ring), GFP_KERNEL);
+ if (!ring) {
DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
engine->name);
ret = -ENOMEM;
goto error_unpin_ctx;
}
- ringbuf->engine = engine;
+ ring->engine = engine;
- ringbuf->size = 32 * PAGE_SIZE;
- ringbuf->effective_size = ringbuf->size;
- ringbuf->head = 0;
- ringbuf->tail = 0;
- ringbuf->last_retired_head = -1;
- intel_ring_update_space(ringbuf);
+ ring->size = 32 * PAGE_SIZE;
+ ring->effective_size = ring->size;
+ ring->head = 0;
+ ring->tail = 0;
+ ring->last_retired_head = -1;
+ intel_ring_update_space(ring);
- if (ringbuf->obj == NULL) {
- ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
+ if (ring->obj == NULL) {
+ ret = intel_alloc_ringbuffer_obj(dev, ring);
if (ret) {
DRM_DEBUG_DRIVER(
"Failed to allocate ringbuffer obj %s: %d\n",
@@ -2215,7 +2214,7 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
}
if (is_global_default_ctx) {
- ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
+ ret = intel_pin_and_map_ringbuffer_obj(dev, ring);
if (ret) {
DRM_ERROR(
"Failed to pin and map ringbuffer %s: %d\n",
@@ -2226,13 +2225,13 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
}
- ret = populate_lr_context(ctx, ctx_obj, engine, ringbuf);
+ ret = populate_lr_context(ctx, ctx_obj, engine, ring);
if (ret) {
DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
goto error;
}
- ctx->engine[engine->id].ringbuf = ringbuf;
+ ctx->engine[engine->id].ring = ring;
ctx->engine[engine->id].state = ctx_obj;
if (ctx == engine->default_context)
@@ -2249,7 +2248,7 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
if (ret) {
DRM_ERROR("ring init context: %d\n", ret);
i915_gem_request_cancel(req);
- ctx->engine[engine->id].ringbuf = NULL;
+ ctx->engine[engine->id].ring = NULL;
ctx->engine[engine->id].state = NULL;
goto error;
}
@@ -2264,11 +2263,11 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
error:
if (is_global_default_ctx)
- intel_unpin_ringbuffer_obj(ringbuf);
+ intel_unpin_ringbuffer_obj(ring);
error_destroy_rbuf:
- intel_destroy_ringbuffer_obj(ringbuf);
+ intel_destroy_ringbuffer_obj(ring);
error_free_rbuf:
- kfree(ringbuf);
+ kfree(ring);
error_unpin_ctx:
if (is_global_default_ctx)
i915_gem_object_ggtt_unpin(ctx_obj);
@@ -2280,14 +2279,12 @@ void intel_lr_context_reset(struct drm_device *dev,
struct intel_context *ctx)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_engine_cs *ring;
+ struct intel_engine_cs *unused;
int i;
- for_each_ring(ring, dev_priv, i) {
- struct drm_i915_gem_object *ctx_obj =
- ctx->engine[ring->id].state;
- struct intel_ringbuffer *ringbuf =
- ctx->engine[ring->id].ringbuf;
+ for_each_ring(unused, dev_priv, i) {
+ struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
+ struct intel_ringbuffer *ring = ctx->engine[i].ring;
uint32_t *reg_state;
struct page *page;
@@ -2306,7 +2303,7 @@ void intel_lr_context_reset(struct drm_device *dev,
kunmap_atomic(reg_state);
- ringbuf->head = 0;
- ringbuf->tail = 0;
+ ring->head = 0;
+ ring->tail = 0;
}
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1d43a24b6268..f6b7e209cc3c 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -34,20 +34,20 @@
#include "intel_drv.h"
bool
-intel_ring_initialized(struct intel_engine_cs *ring)
+intel_ring_initialized(struct intel_engine_cs *engine)
{
- struct drm_device *dev = ring->dev;
+ struct drm_device *dev = engine->dev;
if (!dev)
return false;
if (i915.enable_execlists) {
- struct intel_context *dctx = ring->default_context;
- struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
+ struct intel_context *dctx = engine->default_context;
+ struct intel_ringbuffer *ring = dctx->engine[engine->id].ring;
- return ringbuf->obj;
+ return ring->obj;
} else
- return ring->buffer && ring->buffer->obj;
+ return engine->buffer && engine->buffer->obj;
}
int __intel_ring_space(int head, int tail, int size)
--
2.6.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 10/12] drm/i915: Reduce the pointer dance of i915_is_ggtt()
2015-11-20 12:43 [PATCH 01/12] drm/i915: Convert i915_semaphores_is_enabled over to drm_i915_private Chris Wilson
` (7 preceding siblings ...)
2015-11-20 12:43 ` [PATCH 09/12] drm/i915: Rename intel_context[engine].ringbuf Chris Wilson
@ 2015-11-20 12:43 ` Chris Wilson
2015-11-24 15:08 ` Daniel Vetter
2015-11-20 12:43 ` [PATCH 11/12] drm/i915: Remove request retirement before each batch Chris Wilson
` (2 subsequent siblings)
11 siblings, 1 reply; 41+ messages in thread
From: Chris Wilson @ 2015-11-20 12:43 UTC (permalink / raw)
To: intel-gfx
The multiple levels of indirect do nothing but hinder the compiler and
the pointer chasing turns to be quite painful but painless to fix.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 14 ++++++-------
drivers/gpu/drm/i915/i915_drv.h | 9 +--------
drivers/gpu/drm/i915/i915_gem.c | 32 +++++++++++++-----------------
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 5 ++---
drivers/gpu/drm/i915/i915_gem_gtt.c | 21 +++++++++-----------
drivers/gpu/drm/i915/i915_gem_gtt.h | 3 +++
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/i915_trace.h | 27 ++++++++-----------------
8 files changed, 44 insertions(+), 69 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 630717fec688..d83f35c8df34 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -123,8 +123,7 @@ static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
struct i915_vma *vma;
list_for_each_entry(vma, &obj->vma_list, vma_link) {
- if (i915_is_ggtt(vma->vm) &&
- drm_mm_node_allocated(&vma->node))
+ if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
size += vma->node.size;
}
@@ -171,12 +170,11 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
seq_printf(m, " (fence: %d)", obj->fence_reg);
list_for_each_entry(vma, &obj->vma_list, vma_link) {
seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
- i915_is_ggtt(vma->vm) ? "g" : "pp",
+ vma->is_ggtt ? "g" : "pp",
vma->node.start, vma->node.size);
- if (i915_is_ggtt(vma->vm))
- seq_printf(m, ", type: %u)", vma->ggtt_view.type);
- else
- seq_puts(m, ")");
+ if (vma->is_ggtt)
+ seq_printf(m, ", type: %u", vma->ggtt_view.type);
+ seq_puts(m, ")");
}
if (obj->stolen)
seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
@@ -348,7 +346,7 @@ static int per_file_stats(int id, void *ptr, void *data)
if (!drm_mm_node_allocated(&vma->node))
continue;
- if (i915_is_ggtt(vma->vm)) {
+ if (vma->is_ggtt) {
stats->global += obj->base.size;
continue;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d8bd58cbb727..e86e1188deb0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3023,18 +3023,11 @@ bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
/* Some GGTT VM helpers */
#define i915_obj_to_ggtt(obj) \
(&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
-static inline bool i915_is_ggtt(struct i915_address_space *vm)
-{
- struct i915_address_space *ggtt =
- &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
- return vm == ggtt;
-}
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
- WARN_ON(i915_is_ggtt(vm));
-
+ WARN_ON(vm->is_ggtt);
return container_of(vm, struct i915_hw_ppgtt, base);
}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d6706dd4117c..390cb9c15bad 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3300,8 +3300,7 @@ int i915_vma_unbind(struct i915_vma *vma)
* cause memory corruption through use-after-free.
*/
- if (i915_is_ggtt(vma->vm) &&
- vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
+ if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
i915_gem_object_finish_gtt(obj);
/* release the fence reg _after_ flushing */
@@ -3316,7 +3315,7 @@ int i915_vma_unbind(struct i915_vma *vma)
vma->bound = 0;
list_del_init(&vma->mm_list);
- if (i915_is_ggtt(vma->vm)) {
+ if (vma->is_ggtt) {
if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
obj->map_and_fenceable = false;
} else if (vma->ggtt_view.pages) {
@@ -3427,7 +3426,7 @@ i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
struct i915_vma *vma;
int ret;
- if (i915_is_ggtt(vm)) {
+ if (vm->is_ggtt) {
u32 fence_size, fence_alignment, unfenced_alignment;
u64 view_size;
@@ -4177,13 +4176,13 @@ i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
return -ENODEV;
- if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
+ if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !vm->is_ggtt))
return -EINVAL;
if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
return -EINVAL;
- if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
+ if (WARN_ON(vm->is_ggtt != !!ggtt_view))
return -EINVAL;
vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
@@ -4245,7 +4244,7 @@ i915_gem_object_pin(struct drm_i915_gem_object *obj,
uint64_t flags)
{
return i915_gem_object_do_pin(obj, vm,
- i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
+ vm->is_ggtt ? &i915_ggtt_view_normal : NULL,
size, alignment, flags);
}
@@ -4550,7 +4549,7 @@ struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
{
struct i915_vma *vma;
list_for_each_entry(vma, &obj->vma_list, vma_link) {
- if (i915_is_ggtt(vma->vm) &&
+ if (vma->is_ggtt &&
vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
continue;
if (vma->vm == vm)
@@ -4577,17 +4576,14 @@ struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
void i915_gem_vma_destroy(struct i915_vma *vma)
{
- struct i915_address_space *vm = NULL;
WARN_ON(vma->node.allocated);
/* Keep the vma as a placeholder in the execbuffer reservation lists */
if (!list_empty(&vma->exec_list))
return;
- vm = vma->vm;
-
- if (!i915_is_ggtt(vm))
- i915_ppgtt_put(i915_vm_to_ppgtt(vm));
+ if (!vma->is_ggtt)
+ i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm));
list_del(&vma->vma_link);
@@ -4984,7 +4980,7 @@ init_ring_lists(struct intel_engine_cs *ring)
void i915_init_vm(struct drm_i915_private *dev_priv,
struct i915_address_space *vm)
{
- if (!i915_is_ggtt(vm))
+ if (!vm->is_ggtt)
drm_mm_init(&vm->mm, vm->start, vm->total);
vm->dev = dev_priv->dev;
INIT_LIST_HEAD(&vm->active_list);
@@ -5148,7 +5144,7 @@ u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
list_for_each_entry(vma, &o->vma_list, vma_link) {
- if (i915_is_ggtt(vma->vm) &&
+ if (vma->is_ggtt &&
vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
continue;
if (vma->vm == vm)
@@ -5156,7 +5152,7 @@ u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
}
WARN(1, "%s vma for this object not found.\n",
- i915_is_ggtt(vm) ? "global" : "ppgtt");
+ vm->is_ggtt ? "global" : "ppgtt");
return -1;
}
@@ -5181,7 +5177,7 @@ bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
struct i915_vma *vma;
list_for_each_entry(vma, &o->vma_list, vma_link) {
- if (i915_is_ggtt(vma->vm) &&
+ if (vma->is_ggtt &&
vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
continue;
if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
@@ -5228,7 +5224,7 @@ unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
BUG_ON(list_empty(&o->vma_list));
list_for_each_entry(vma, &o->vma_list, vma_link) {
- if (i915_is_ggtt(vma->vm) &&
+ if (vma->is_ggtt &&
vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
continue;
if (vma->vm == vm)
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index afa930dab632..46907f5da4f2 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -652,7 +652,7 @@ need_reloc_mappable(struct i915_vma *vma)
if (entry->relocation_count == 0)
return false;
- if (!i915_is_ggtt(vma->vm))
+ if (!vma->is_ggtt)
return false;
/* See also use_cpu_reloc() */
@@ -671,8 +671,7 @@ eb_vma_misplaced(struct i915_vma *vma)
struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
struct drm_i915_gem_object *obj = vma->obj;
- WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP &&
- !i915_is_ggtt(vma->vm));
+ WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && !vma->is_ggtt);
if (entry->alignment &&
vma->node.start & (entry->alignment - 1))
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index b1ee6f89e70b..8bb1102608fd 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2456,7 +2456,6 @@ static int ggtt_bind_vma(struct i915_vma *vma,
if (obj->gt_ro)
pte_flags |= PTE_READ_ONLY;
-
if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
vma->vm->insert_entries(vma->vm, pages,
vma->node.start,
@@ -3027,6 +3026,7 @@ int i915_gem_gtt_init(struct drm_device *dev)
}
gtt->base.dev = dev;
+ gtt->base.is_ggtt = true;
ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size,
>t->mappable_base, >t->mappable_end);
@@ -3105,7 +3105,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
container_of(vm, struct i915_hw_ppgtt,
base);
- if (i915_is_ggtt(vm))
+ if (vm->is_ggtt)
ppgtt = dev_priv->mm.aliasing_ppgtt;
gen6_write_page_range(dev_priv, &ppgtt->pd,
@@ -3123,7 +3123,7 @@ __i915_gem_vma_create(struct drm_i915_gem_object *obj,
{
struct i915_vma *vma;
- if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
+ if (WARN_ON(vm->is_ggtt != !!ggtt_view))
return ERR_PTR(-EINVAL);
vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
@@ -3135,13 +3135,14 @@ __i915_gem_vma_create(struct drm_i915_gem_object *obj,
INIT_LIST_HEAD(&vma->exec_list);
vma->vm = vm;
vma->obj = obj;
+ vma->is_ggtt = vm->is_ggtt;
- if (i915_is_ggtt(vm))
+ if (vm->is_ggtt)
vma->ggtt_view = *ggtt_view;
+ else
+ i915_ppgtt_get(i915_vm_to_ppgtt(vm));
list_add_tail(&vma->vma_link, &obj->vma_list);
- if (!i915_is_ggtt(vm))
- i915_ppgtt_get(i915_vm_to_ppgtt(vm));
return vma;
}
@@ -3155,7 +3156,7 @@ i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
vma = i915_gem_obj_to_vma(obj, vm);
if (!vma)
vma = __i915_gem_vma_create(obj, vm,
- i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
+ vm->is_ggtt ? &i915_ggtt_view_normal : NULL);
return vma;
}
@@ -3381,13 +3382,9 @@ int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
return 0;
if (vma->bound == 0 && vma->vm->allocate_va_range) {
- trace_i915_va_alloc(vma->vm,
- vma->node.start,
- vma->node.size,
- VM_TO_TRACE_NAME(vma->vm));
-
/* XXX: i915_vma_pin() will fix this +- hack */
vma->pin_count++;
+ trace_i915_va_alloc(vma);
ret = vma->vm->allocate_va_range(vma->vm,
vma->node.start,
vma->node.size);
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 82750073d5b3..9b506ec6b90c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -183,6 +183,7 @@ struct i915_vma {
#define GLOBAL_BIND (1<<0)
#define LOCAL_BIND (1<<1)
unsigned int bound : 4;
+ unsigned is_ggtt : 1;
/**
* Support different GGTT views into the same object.
@@ -275,6 +276,8 @@ struct i915_address_space {
u64 start; /* Start offset always 0 for dri2 */
u64 total; /* size addr space maps (ex. 2GB for ggtt) */
+ bool is_ggtt;
+
struct i915_page_scratch *scratch_page;
struct i915_page_table *scratch_pt;
struct i915_page_directory *scratch_pd;
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 8b37f72bd91f..8afc49600835 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -612,7 +612,7 @@ i915_error_object_create(struct drm_i915_private *dev_priv,
dst->gtt_offset = -1;
reloc_offset = dst->gtt_offset;
- if (i915_is_ggtt(vm))
+ if (vm->is_ggtt)
vma = i915_gem_obj_to_ggtt(src);
use_ggtt = (src->cache_level == I915_CACHE_NONE &&
vma && (vma->bound & GLOBAL_BIND) &&
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index 533b6a87fd1d..58ef4e0ccea1 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -175,35 +175,24 @@ TRACE_EVENT(i915_vma_unbind,
__entry->obj, __entry->offset, __entry->size, __entry->vm)
);
-#define VM_TO_TRACE_NAME(vm) \
- (i915_is_ggtt(vm) ? "G" : \
- "P")
-
-DECLARE_EVENT_CLASS(i915_va,
- TP_PROTO(struct i915_address_space *vm, u64 start, u64 length, const char *name),
- TP_ARGS(vm, start, length, name),
+TRACE_EVENT(i915_va_alloc,
+ TP_PROTO(struct i915_vma *vma),
+ TP_ARGS(vma),
TP_STRUCT__entry(
__field(struct i915_address_space *, vm)
__field(u64, start)
__field(u64, end)
- __string(name, name)
),
TP_fast_assign(
- __entry->vm = vm;
- __entry->start = start;
- __entry->end = start + length - 1;
- __assign_str(name, name);
+ __entry->vm = vma->vm;
+ __entry->start = vma->node.start;
+ __entry->end = vma->node.start + vma->node.size - 1;
),
- TP_printk("vm=%p (%s), 0x%llx-0x%llx",
- __entry->vm, __get_str(name), __entry->start, __entry->end)
-);
-
-DEFINE_EVENT(i915_va, i915_va_alloc,
- TP_PROTO(struct i915_address_space *vm, u64 start, u64 length, const char *name),
- TP_ARGS(vm, start, length, name)
+ TP_printk("vm=%p (%c), 0x%llx-0x%llx",
+ __entry->vm, __entry->vm->is_ggtt ? 'G' : 'P', __entry->start, __entry->end)
);
DECLARE_EVENT_CLASS(i915_px_entry,
--
2.6.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 11/12] drm/i915: Remove request retirement before each batch
2015-11-20 12:43 [PATCH 01/12] drm/i915: Convert i915_semaphores_is_enabled over to drm_i915_private Chris Wilson
` (8 preceding siblings ...)
2015-11-20 12:43 ` [PATCH 10/12] drm/i915: Reduce the pointer dance of i915_is_ggtt() Chris Wilson
@ 2015-11-20 12:43 ` Chris Wilson
2015-11-20 12:43 ` [PATCH 12/12] drm/i915: Cache the reset_counter for the request Chris Wilson
2015-11-24 13:52 ` [PATCH 01/12] drm/i915: Convert i915_semaphores_is_enabled over to drm_i915_private Daniel Vetter
11 siblings, 0 replies; 41+ messages in thread
From: Chris Wilson @ 2015-11-20 12:43 UTC (permalink / raw)
To: intel-gfx
This reimplements the denial-of-service protection against igt from
commit 227f782e4667fc622810bce8be8ccdeee45f89c2
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date: Thu May 15 10:41:42 2014 +0100
drm/i915: Retire requests before creating a new one
and transfers the stall from before each batch into a new close handler.
The issue is that the stall is increasing latency between batches which
is detrimental in some cases (especially coupled with execlists) to
keeping the GPU well fed. Also we make the observation that retiring
requests can of itself free objects (and requests) and therefore makes
a good first step when shrinking. However, we do wish to do a retire
before forcing an allocation of a new batch pool object (prior to an
execbuffer), but we make the optimisation that we only need to do so if
the oldest available batch pool object is active.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/i915_gem.c | 17 ++++++++++++++++-
drivers/gpu/drm/i915/i915_gem_batch_pool.c | 25 +++++++++++++++++--------
drivers/gpu/drm/i915/i915_gem_batch_pool.h | 7 +++++--
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 --
drivers/gpu/drm/i915/i915_gem_shrinker.c | 2 ++
drivers/gpu/drm/i915/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 28 ++++++++++++++--------------
9 files changed, 58 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 10c4cc2cece9..ffd99d27fac7 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1663,6 +1663,7 @@ static struct drm_driver driver = {
.debugfs_init = i915_debugfs_init,
.debugfs_cleanup = i915_debugfs_cleanup,
#endif
+ .gem_close_object = i915_gem_close_object,
.gem_free_object = i915_gem_free_object,
.gem_vm_ops = &i915_gem_vm_ops,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e86e1188deb0..3fe933e4e664 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2767,6 +2767,8 @@ struct drm_i915_gem_object *i915_gem_object_create_from_data(
struct drm_device *dev, const void *data, size_t size);
void i915_init_vm(struct drm_i915_private *dev_priv,
struct i915_address_space *vm);
+void i915_gem_close_object(struct drm_gem_object *obj,
+ struct drm_file *file);
void i915_gem_free_object(struct drm_gem_object *obj);
void i915_gem_vma_destroy(struct i915_vma *vma);
@@ -2889,7 +2891,6 @@ struct drm_i915_gem_request *
i915_gem_find_active_request(struct intel_engine_cs *ring);
bool i915_gem_retire_requests(struct drm_device *dev);
-void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
bool interruptible);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 390cb9c15bad..d3609e111647 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2261,6 +2261,10 @@ i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
for (i = 0; i < page_count; i++) {
page = shmem_read_mapping_page_gfp(mapping, i, gfp);
if (IS_ERR(page)) {
+ i915_gem_retire_requests(dev_priv->dev);
+ page = shmem_read_mapping_page_gfp(mapping, i, gfp);
+ }
+ if (IS_ERR(page)) {
i915_gem_shrink(dev_priv,
page_count,
I915_SHRINK_BOUND |
@@ -2880,7 +2884,7 @@ void i915_gem_reset(struct drm_device *dev)
/**
* This function clears the request list as sequence numbers are passed.
*/
-void
+static void
i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
{
WARN_ON(i915_verify_lists(ring->dev));
@@ -3037,6 +3041,17 @@ retire:
return 0;
}
+void i915_gem_close_object(struct drm_gem_object *gem,
+ struct drm_file *file)
+{
+ struct drm_i915_gem_object *obj = to_intel_bo(gem);
+
+ if (obj->active && mutex_trylock(&obj->base.dev->struct_mutex)) {
+ (void)i915_gem_object_flush_active(obj);
+ mutex_unlock(&obj->base.dev->struct_mutex);
+ }
+}
+
/**
* i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
* @DRM_IOCTL_ARGS: standard ioctl arguments
diff --git a/drivers/gpu/drm/i915/i915_gem_batch_pool.c b/drivers/gpu/drm/i915/i915_gem_batch_pool.c
index 7bf2f3f2968e..b8ec7131e064 100644
--- a/drivers/gpu/drm/i915/i915_gem_batch_pool.c
+++ b/drivers/gpu/drm/i915/i915_gem_batch_pool.c
@@ -41,15 +41,15 @@
/**
* i915_gem_batch_pool_init() - initialize a batch buffer pool
- * @dev: the drm device
+ * @engine: the associated request submission engine
* @pool: the batch buffer pool
*/
-void i915_gem_batch_pool_init(struct drm_device *dev,
+void i915_gem_batch_pool_init(struct intel_engine_cs *engine,
struct i915_gem_batch_pool *pool)
{
int n;
- pool->dev = dev;
+ pool->engine = engine;
for (n = 0; n < ARRAY_SIZE(pool->cache_list); n++)
INIT_LIST_HEAD(&pool->cache_list[n]);
@@ -65,7 +65,7 @@ void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool)
{
int n;
- WARN_ON(!mutex_is_locked(&pool->dev->struct_mutex));
+ lockdep_assert_held(&pool->engine->dev->struct_mutex);
for (n = 0; n < ARRAY_SIZE(pool->cache_list); n++) {
while (!list_empty(&pool->cache_list[n])) {
@@ -102,7 +102,7 @@ i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool,
struct list_head *list;
int n;
- WARN_ON(!mutex_is_locked(&pool->dev->struct_mutex));
+ lockdep_assert_held(&pool->engine->dev->struct_mutex);
/* Compute a power-of-two bucket, but throw everything greater than
* 16KiB into the same bucket: i.e. the the buckets hold objects of
@@ -115,8 +115,17 @@ i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool,
list_for_each_entry_safe(tmp, next, list, batch_pool_link) {
/* The batches are strictly LRU ordered */
- if (tmp->active)
- break;
+ if (tmp->active) {
+ struct drm_i915_gem_request *rq;
+
+ /* XXX To be simplified later! */
+ rq = tmp->last_read_req[pool->engine->id];
+ if (!i915_gem_request_completed(rq, true))
+ break;
+
+ BUG_ON(tmp->active & ~intel_ring_flag(pool->engine));
+ BUG_ON(tmp->last_write_req);
+ }
/* While we're looping, do some clean up */
if (tmp->madv == __I915_MADV_PURGED) {
@@ -134,7 +143,7 @@ i915_gem_batch_pool_get(struct i915_gem_batch_pool *pool,
if (obj == NULL) {
int ret;
- obj = i915_gem_alloc_object(pool->dev, size);
+ obj = i915_gem_alloc_object(pool->engine->dev, size);
if (obj == NULL)
return ERR_PTR(-ENOMEM);
diff --git a/drivers/gpu/drm/i915/i915_gem_batch_pool.h b/drivers/gpu/drm/i915/i915_gem_batch_pool.h
index 848e90703eed..7fd4df0a29fe 100644
--- a/drivers/gpu/drm/i915/i915_gem_batch_pool.h
+++ b/drivers/gpu/drm/i915/i915_gem_batch_pool.h
@@ -27,13 +27,16 @@
#include "i915_drv.h"
+struct drm_device;
+struct intel_engine_cs;
+
struct i915_gem_batch_pool {
- struct drm_device *dev;
+ struct intel_engine_cs *engine;
struct list_head cache_list[4];
};
/* i915_gem_batch_pool.c */
-void i915_gem_batch_pool_init(struct drm_device *dev,
+void i915_gem_batch_pool_init(struct intel_engine_cs *engine,
struct i915_gem_batch_pool *pool);
void i915_gem_batch_pool_fini(struct i915_gem_batch_pool *pool);
struct drm_i915_gem_object*
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 46907f5da4f2..43856bdbb330 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -712,8 +712,6 @@ i915_gem_execbuffer_reserve(struct intel_engine_cs *ring,
bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
int retry;
- i915_gem_retire_requests_ring(ring);
-
vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
INIT_LIST_HEAD(&ordered_vmas);
diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index b2ccb7346899..0c7d654195a3 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -216,6 +216,8 @@ i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
if (!i915_gem_shrinker_lock(dev, &unlock))
return 0;
+ i915_gem_retire_requests(dev);
+
count = 0;
list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
if (obj->pages_pin_count == 0)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 222ae8383f48..61aa6dd294c2 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1654,7 +1654,7 @@ static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *rin
ring->dev = dev;
INIT_LIST_HEAD(&ring->active_list);
INIT_LIST_HEAD(&ring->request_list);
- i915_gem_batch_pool_init(dev, &ring->batch_pool);
+ i915_gem_batch_pool_init(ring, &ring->batch_pool);
init_waitqueue_head(&ring->irq_queue);
INIT_LIST_HEAD(&ring->execlist_queue);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index f6b7e209cc3c..f33db3495e35 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2045,23 +2045,23 @@ int intel_alloc_ringbuffer_obj(struct drm_device *dev,
static int intel_init_ring_buffer(struct drm_device *dev,
struct intel_engine_cs *engine)
{
- struct intel_ringbuffer *ringbuf;
+ struct intel_ringbuffer *ring;
int ret;
WARN_ON(engine->buffer);
- ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
- if (!ringbuf)
+ ring = kzalloc(sizeof(*ring), GFP_KERNEL);
+ if (!ring)
return -ENOMEM;
- engine->buffer = ringbuf;
+ engine->buffer = ring;
engine->dev = dev;
INIT_LIST_HEAD(&engine->active_list);
INIT_LIST_HEAD(&engine->request_list);
INIT_LIST_HEAD(&engine->execlist_queue);
- i915_gem_batch_pool_init(dev, &engine->batch_pool);
- ringbuf->size = 32 * PAGE_SIZE;
- ringbuf->engine = engine;
+ i915_gem_batch_pool_init(engine, &engine->batch_pool);
+ ring->size = 32 * PAGE_SIZE;
+ ring->engine = engine;
memset(engine->semaphore.sync_seqno, 0, sizeof(engine->semaphore.sync_seqno));
init_waitqueue_head(&engine->irq_queue);
@@ -2077,20 +2077,20 @@ static int intel_init_ring_buffer(struct drm_device *dev,
goto error;
}
- WARN_ON(ringbuf->obj);
+ WARN_ON(ring->obj);
- ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
+ ret = intel_alloc_ringbuffer_obj(dev, ring);
if (ret) {
DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
engine->name, ret);
goto error;
}
- ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
+ ret = intel_pin_and_map_ringbuffer_obj(dev, ring);
if (ret) {
DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
engine->name, ret);
- intel_destroy_ringbuffer_obj(ringbuf);
+ intel_destroy_ringbuffer_obj(ring);
goto error;
}
@@ -2098,9 +2098,9 @@ static int intel_init_ring_buffer(struct drm_device *dev,
* the TAIL pointer points to within the last 2 cachelines
* of the buffer.
*/
- ringbuf->effective_size = ringbuf->size;
+ ring->effective_size = ring->size;
if (IS_I830(dev) || IS_845G(dev))
- ringbuf->effective_size -= 2 * CACHELINE_BYTES;
+ ring->effective_size -= 2 * CACHELINE_BYTES;
ret = i915_cmd_parser_init_ring(engine);
if (ret)
@@ -2109,7 +2109,7 @@ static int intel_init_ring_buffer(struct drm_device *dev,
return 0;
error:
- kfree(ringbuf);
+ kfree(ring);
engine->buffer = NULL;
return ret;
}
--
2.6.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [PATCH 12/12] drm/i915: Cache the reset_counter for the request
2015-11-20 12:43 [PATCH 01/12] drm/i915: Convert i915_semaphores_is_enabled over to drm_i915_private Chris Wilson
` (9 preceding siblings ...)
2015-11-20 12:43 ` [PATCH 11/12] drm/i915: Remove request retirement before each batch Chris Wilson
@ 2015-11-20 12:43 ` Chris Wilson
2015-11-24 16:43 ` Daniel Vetter
2015-11-24 13:52 ` [PATCH 01/12] drm/i915: Convert i915_semaphores_is_enabled over to drm_i915_private Daniel Vetter
11 siblings, 1 reply; 41+ messages in thread
From: Chris Wilson @ 2015-11-20 12:43 UTC (permalink / raw)
To: intel-gfx
Instead of querying the reset counter before every access to the ring,
query it the first time we touch the ring, and do a final compare when
submitting the request. For correctness, we need to then sanitize how
the reset_counter is incremented to prevent broken submission and
waiting across resets, in the process fixing the persistent -EIO we
still see today on failed waits.
v2: Rebase
v3: Now with added testcase
Testcase: igt/gem_eio
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 32 +++++++-----
drivers/gpu/drm/i915/i915_drv.h | 39 ++++++++++----
drivers/gpu/drm/i915/i915_gem.c | 90 +++++++++++++++------------------
drivers/gpu/drm/i915/i915_irq.c | 21 +-------
drivers/gpu/drm/i915/intel_display.c | 10 ++--
drivers/gpu/drm/i915/intel_ringbuffer.c | 17 ++++---
7 files changed, 104 insertions(+), 107 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d83f35c8df34..107711ec956f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4415,7 +4415,7 @@ i915_wedged_get(void *data, u64 *val)
struct drm_device *dev = data;
struct drm_i915_private *dev_priv = dev->dev_private;
- *val = atomic_read(&dev_priv->gpu_error.reset_counter);
+ *val = i915_terminally_wedged(&dev_priv->gpu_error);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ffd99d27fac7..5838882e10a1 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -841,23 +841,31 @@ int i915_resume_legacy(struct drm_device *dev)
int i915_reset(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct i915_gpu_error *error = &dev_priv->gpu_error;
+ unsigned reset_counter;
bool simulated;
int ret;
intel_reset_gt_powersave(dev);
mutex_lock(&dev->struct_mutex);
+ atomic_clear_mask(I915_WEDGED, &error->reset_counter);
+ reset_counter = atomic_inc_return(&error->reset_counter);
+ if (WARN_ON(__i915_reset_in_progress(reset_counter))) {
+ ret = -EIO;
+ goto error;
+ }
i915_gem_reset(dev);
- simulated = dev_priv->gpu_error.stop_rings != 0;
+ simulated = error->stop_rings != 0;
ret = intel_gpu_reset(dev);
/* Also reset the gpu hangman. */
if (simulated) {
DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
- dev_priv->gpu_error.stop_rings = 0;
+ error->stop_rings = 0;
if (ret == -ENODEV) {
DRM_INFO("Reset not implemented, but ignoring "
"error for simulated gpu hangs\n");
@@ -870,8 +878,7 @@ int i915_reset(struct drm_device *dev)
if (ret) {
DRM_ERROR("Failed to reset chip: %i\n", ret);
- mutex_unlock(&dev->struct_mutex);
- return ret;
+ goto error;
}
intel_overlay_reset(dev_priv);
@@ -890,20 +897,14 @@ int i915_reset(struct drm_device *dev)
* was running at the time of the reset (i.e. we weren't VT
* switched away).
*/
-
- /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
- dev_priv->gpu_error.reload_in_reset = true;
-
ret = i915_gem_init_hw(dev);
-
- dev_priv->gpu_error.reload_in_reset = false;
-
- mutex_unlock(&dev->struct_mutex);
if (ret) {
DRM_ERROR("Failed hw init on reset %d\n", ret);
- return ret;
+ goto error;
}
+ mutex_unlock(&dev->struct_mutex);
+
/*
* rps/rc6 re-init is necessary to restore state lost after the
* reset and the re-install of gt irqs. Skip for ironlake per
@@ -914,6 +915,11 @@ int i915_reset(struct drm_device *dev)
intel_enable_gt_powersave(dev);
return 0;
+
+error:
+ atomic_set_mask(I915_WEDGED, &error->reset_counter);
+ mutex_unlock(&dev->struct_mutex);
+ return ret;
}
static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3fe933e4e664..aa83b284cb2f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1395,9 +1395,6 @@ struct i915_gpu_error {
/* For missed irq/seqno simulation. */
unsigned int test_irq_rings;
-
- /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
- bool reload_in_reset;
};
enum modeset_restore {
@@ -2157,6 +2154,7 @@ struct drm_i915_gem_request {
/** On Which ring this request was generated */
struct drm_i915_private *i915;
struct intel_engine_cs *engine;
+ unsigned reset_counter;
/** GEM sequence number associated with this request. */
uint32_t seqno;
@@ -2891,23 +2889,47 @@ struct drm_i915_gem_request *
i915_gem_find_active_request(struct intel_engine_cs *ring);
bool i915_gem_retire_requests(struct drm_device *dev);
-int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
+int __must_check i915_gem_check_wedge(unsigned reset_counter,
bool interruptible);
+static inline u32 i915_reset_counter(struct i915_gpu_error *error)
+{
+ return atomic_read(&error->reset_counter);
+}
+
+static inline bool __i915_reset_in_progress(u32 reset)
+{
+ return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG);
+}
+
+static inline bool __i915_reset_in_progress_or_wedged(u32 reset)
+{
+ return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
+}
+
+static inline bool __i915_terminally_wedged(u32 reset)
+{
+ return unlikely(reset & I915_WEDGED);
+}
+
static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
{
- return unlikely(atomic_read(&error->reset_counter)
- & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
+ return __i915_reset_in_progress(i915_reset_counter(error));
+}
+
+static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
+{
+ return __i915_reset_in_progress_or_wedged(i915_reset_counter(error));
}
static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
{
- return atomic_read(&error->reset_counter) & I915_WEDGED;
+ return __i915_terminally_wedged(i915_reset_counter(error));
}
static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
- return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
+ return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2;
}
static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
@@ -2940,7 +2962,6 @@ void __i915_add_request(struct drm_i915_gem_request *req,
#define i915_add_request_no_flush(req) \
__i915_add_request(req, NULL, false)
int __i915_wait_request(struct drm_i915_gem_request *req,
- unsigned reset_counter,
bool interruptible,
s64 *timeout,
struct intel_rps_client *rps);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d3609e111647..6ac9c80244fa 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -85,9 +85,7 @@ i915_gem_wait_for_error(struct i915_gpu_error *error)
{
int ret;
-#define EXIT_COND (!i915_reset_in_progress(error) || \
- i915_terminally_wedged(error))
- if (EXIT_COND)
+ if (!i915_reset_in_progress(error))
return 0;
/*
@@ -96,17 +94,16 @@ i915_gem_wait_for_error(struct i915_gpu_error *error)
* we should simply try to bail out and fail as gracefully as possible.
*/
ret = wait_event_interruptible_timeout(error->reset_queue,
- EXIT_COND,
+ !i915_reset_in_progress(error),
10*HZ);
if (ret == 0) {
DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
return -EIO;
} else if (ret < 0) {
return ret;
+ } else {
+ return 0;
}
-#undef EXIT_COND
-
- return 0;
}
int i915_mutex_lock_interruptible(struct drm_device *dev)
@@ -1112,26 +1109,20 @@ put_rpm:
}
int
-i915_gem_check_wedge(struct i915_gpu_error *error,
+i915_gem_check_wedge(unsigned reset_counter,
bool interruptible)
{
- if (i915_reset_in_progress(error)) {
+ if (__i915_reset_in_progress_or_wedged(reset_counter)) {
/* Non-interruptible callers can't handle -EAGAIN, hence return
* -EIO unconditionally for these. */
if (!interruptible)
return -EIO;
/* Recovery complete, but the reset failed ... */
- if (i915_terminally_wedged(error))
+ if (__i915_terminally_wedged(reset_counter))
return -EIO;
- /*
- * Check if GPU Reset is in progress - we need intel_ring_begin
- * to work properly to reinit the hw state while the gpu is
- * still marked as reset-in-progress. Handle this with a flag.
- */
- if (!error->reload_in_reset)
- return -EAGAIN;
+ return -EAGAIN;
}
return 0;
@@ -1200,7 +1191,6 @@ static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
/**
* __i915_wait_request - wait until execution of request has finished
* @req: duh!
- * @reset_counter: reset sequence associated with the given request
* @interruptible: do an interruptible wait (normally yes)
* @timeout: in - how long to wait (NULL forever); out - how much time remaining
*
@@ -1215,7 +1205,6 @@ static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
* errno with remaining time filled in timeout argument.
*/
int __i915_wait_request(struct drm_i915_gem_request *req,
- unsigned reset_counter,
bool interruptible,
s64 *timeout,
struct intel_rps_client *rps)
@@ -1264,12 +1253,12 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
/* We need to check whether any gpu reset happened in between
* the caller grabbing the seqno and now ... */
- if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
- /* ... but upgrade the -EAGAIN to an -EIO if the gpu
- * is truely gone. */
- ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
- if (ret == 0)
- ret = -EAGAIN;
+ if (req->reset_counter != i915_reset_counter(&dev_priv->gpu_error)) {
+ /* As we do not requeue the request over a GPU reset,
+ * if one does occur we know that the request is
+ * effectively complete.
+ */
+ ret = 0;
break;
}
@@ -1433,13 +1422,7 @@ i915_wait_request(struct drm_i915_gem_request *req)
BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
- ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
- if (ret)
- return ret;
-
- ret = __i915_wait_request(req,
- atomic_read(&dev_priv->gpu_error.reset_counter),
- interruptible, NULL, NULL);
+ ret = __i915_wait_request(req, interruptible, NULL, NULL);
if (ret)
return ret;
@@ -1514,7 +1497,6 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
struct drm_device *dev = obj->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_i915_gem_request *requests[I915_NUM_RINGS];
- unsigned reset_counter;
int ret, i, n = 0;
BUG_ON(!mutex_is_locked(&dev->struct_mutex));
@@ -1523,12 +1505,6 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
if (!obj->active)
return 0;
- ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
- if (ret)
- return ret;
-
- reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
-
if (readonly) {
struct drm_i915_gem_request *req;
@@ -1550,9 +1526,9 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
}
mutex_unlock(&dev->struct_mutex);
+ ret = 0;
for (i = 0; ret == 0 && i < n; i++)
- ret = __i915_wait_request(requests[i], reset_counter, true,
- NULL, rps);
+ ret = __i915_wait_request(requests[i], true, NULL, rps);
mutex_lock(&dev->struct_mutex);
for (i = 0; i < n; i++) {
@@ -2707,6 +2683,7 @@ int i915_gem_request_alloc(struct intel_engine_cs *engine,
struct drm_i915_gem_request **req_out)
{
struct drm_i915_private *dev_priv = to_i915(engine->dev);
+ unsigned reset_counter = i915_reset_counter(&dev_priv->gpu_error);
struct drm_i915_gem_request *req;
int ret;
@@ -2715,6 +2692,10 @@ int i915_gem_request_alloc(struct intel_engine_cs *engine,
*req_out = NULL;
+ ret = i915_gem_check_wedge(reset_counter, dev_priv->mm.interruptible);
+ if (ret)
+ return ret;
+
req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
if (req == NULL)
return -ENOMEM;
@@ -2725,6 +2706,7 @@ int i915_gem_request_alloc(struct intel_engine_cs *engine,
kref_init(&req->ref);
req->i915 = dev_priv;
+ req->reset_counter = reset_counter;
req->engine = engine;
req->ctx = ctx;
i915_gem_context_reference(req->ctx);
@@ -3077,11 +3059,9 @@ void i915_gem_close_object(struct drm_gem_object *gem,
int
i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_i915_gem_wait *args = data;
struct drm_i915_gem_object *obj;
struct drm_i915_gem_request *req[I915_NUM_RINGS];
- unsigned reset_counter;
int i, n = 0;
int ret;
@@ -3115,7 +3095,6 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
}
drm_gem_object_unreference(&obj->base);
- reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
for (i = 0; i < I915_NUM_RINGS; i++) {
if (obj->last_read_req[i] == NULL)
@@ -3128,11 +3107,23 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
for (i = 0; i < n; i++) {
if (ret == 0)
- ret = __i915_wait_request(req[i], reset_counter, true,
+ ret = __i915_wait_request(req[i], true,
args->timeout_ns > 0 ? &args->timeout_ns : NULL,
file->driver_priv);
+
+ /* If the GPU hung before this, report it. Ideally we only
+ * report if this request cannot be completed. Currently
+ * when we don't mark the guilty party and abort all
+ * requests on reset, so just mark all as EIO.
+ */
+ if (ret == 0 &&
+ req[i]->reset_counter != i915_reset_counter(&req[i]->i915->gpu_error))
+ ret = -EIO;
+
i915_gem_request_unreference__unlocked(req[i]);
}
+
+
return ret;
out:
@@ -3160,7 +3151,6 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
if (!i915_semaphore_is_enabled(from_req->i915)) {
struct drm_i915_private *i915 = from_req->i915;
ret = __i915_wait_request(from_req,
- atomic_read(&i915->gpu_error.reset_counter),
i915->mm.interruptible,
NULL,
&i915->rps.semaphores);
@@ -4082,14 +4072,15 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
struct drm_i915_file_private *file_priv = file->driver_priv;
unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
struct drm_i915_gem_request *request, *target = NULL;
- unsigned reset_counter;
int ret;
ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
if (ret)
return ret;
- ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
+ /* ABI: return -EIO if wedged */
+ ret = i915_gem_check_wedge(i915_reset_counter(&dev_priv->gpu_error),
+ false);
if (ret)
return ret;
@@ -4107,7 +4098,6 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
target = request;
}
- reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
if (target)
i915_gem_request_reference(target);
spin_unlock(&file_priv->mm.lock);
@@ -4115,7 +4105,7 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
if (target == NULL)
return 0;
- ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
+ ret = __i915_wait_request(target, true, NULL, NULL);
if (ret == 0)
queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f9f5e9cf7360..186315208462 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2200,7 +2200,6 @@ static void i915_error_wake_up(struct drm_i915_private *dev_priv,
static void i915_reset_and_wakeup(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct i915_gpu_error *error = &dev_priv->gpu_error;
char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
@@ -2218,7 +2217,7 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
* the reset in-progress bit is only ever set by code outside of this
* work we don't need to worry about any other races.
*/
- if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
+ if (i915_reset_in_progress(&dev_priv->gpu_error)) {
DRM_DEBUG_DRIVER("resetting chip\n");
kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
reset_event);
@@ -2246,25 +2245,9 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
intel_runtime_pm_put(dev_priv);
- if (ret == 0) {
- /*
- * After all the gem state is reset, increment the reset
- * counter and wake up everyone waiting for the reset to
- * complete.
- *
- * Since unlock operations are a one-sided barrier only,
- * we need to insert a barrier here to order any seqno
- * updates before
- * the counter increment.
- */
- smp_mb__before_atomic();
- atomic_inc(&dev_priv->gpu_error.reset_counter);
-
+ if (ret == 0)
kobject_uevent_env(&dev->primary->kdev->kobj,
KOBJ_CHANGE, reset_done_event);
- } else {
- atomic_set_mask(I915_WEDGED, &error->reset_counter);
- }
/*
* Note: The wake_up also serves as a memory barrier so that
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cdd6074257af..8cb89320d28d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3298,8 +3298,7 @@ static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
bool pending;
- if (i915_reset_in_progress(&dev_priv->gpu_error) ||
- intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
+ if (intel_crtc->reset_counter != i915_reset_counter(&dev_priv->gpu_error))
return false;
spin_lock_irq(&dev->event_lock);
@@ -10751,8 +10750,7 @@ static bool page_flip_finished(struct intel_crtc *crtc)
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- if (i915_reset_in_progress(&dev_priv->gpu_error) ||
- crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
+ if (crtc->reset_counter != i915_reset_counter(&dev_priv->gpu_error))
return true;
/*
@@ -11180,9 +11178,7 @@ static void intel_mmio_flip_work_func(struct work_struct *work)
container_of(work, struct intel_mmio_flip, work);
if (mmio_flip->req)
- WARN_ON(__i915_wait_request(mmio_flip->req,
- mmio_flip->crtc->reset_counter,
- false, NULL,
+ WARN_ON(__i915_wait_request(mmio_flip->req, false, NULL,
&mmio_flip->i915->rps.mmioflips));
intel_do_mmio_flip(mmio_flip->crtc);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index f33db3495e35..b3538b66353b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2156,9 +2156,7 @@ int intel_ring_idle(struct intel_engine_cs *ring)
list);
/* Make sure we do not trigger any retires */
- return __i915_wait_request(req,
- atomic_read(&req->i915->gpu_error.reset_counter),
- req->i915->mm.interruptible,
+ return __i915_wait_request(req, req->i915->mm.interruptible,
NULL, NULL);
}
@@ -2252,6 +2250,14 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
if (ret)
return ret;
+ /* If the request was completed due to a GPU hang, we want to
+ * error out before we continue to emit more commands to the GPU.
+ */
+ ret = i915_gem_check_wedge(i915_reset_counter(&to_i915(engine->dev)->gpu_error),
+ to_i915(engine->dev)->mm.interruptible);
+ if (ret)
+ return ret;
+
ring->space = space;
return 0;
}
@@ -2316,11 +2322,6 @@ int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
{
int ret;
- ret = i915_gem_check_wedge(&req->i915->gpu_error,
- req->i915->mm.interruptible);
- if (ret)
- return ret;
-
ret = ring_prepare(req, num_dwords * sizeof(uint32_t));
if (ret)
return ret;
--
2.6.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [PATCH 01/12] drm/i915: Convert i915_semaphores_is_enabled over to drm_i915_private
2015-11-20 12:43 [PATCH 01/12] drm/i915: Convert i915_semaphores_is_enabled over to drm_i915_private Chris Wilson
` (10 preceding siblings ...)
2015-11-20 12:43 ` [PATCH 12/12] drm/i915: Cache the reset_counter for the request Chris Wilson
@ 2015-11-24 13:52 ` Daniel Vetter
11 siblings, 0 replies; 41+ messages in thread
From: Daniel Vetter @ 2015-11-24 13:52 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Nov 20, 2015 at 12:43:41PM +0000, Chris Wilson wrote:
> We only need our private device struct for checking semapahore status,
> and to reduce churn later convert the parameter over now.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Assuming gcc hasn't become unhappy:
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_dma.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.c | 8 ++++----
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> drivers/gpu/drm/i915/intel_ringbuffer.c | 20 ++++++++++----------
> 8 files changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 8890b115a2c0..359436162f3d 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2859,7 +2859,7 @@ static int i915_semaphore_status(struct seq_file *m, void *unused)
> int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
> int i, j, ret;
>
> - if (!i915_semaphore_is_enabled(dev)) {
> + if (!i915_semaphore_is_enabled(dev_priv)) {
> seq_puts(m, "Semaphores are disabled\n");
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index cd79ef114b8e..d41bf214fc84 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -127,7 +127,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
> value = 1;
> break;
> case I915_PARAM_HAS_SEMAPHORES:
> - value = i915_semaphore_is_enabled(dev);
> + value = i915_semaphore_is_enabled(dev_priv);
> break;
> case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
> value = 1;
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 1d887459e37f..10c4cc2cece9 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -512,9 +512,9 @@ void intel_detect_pch(struct drm_device *dev)
> pci_dev_put(pch);
> }
>
> -bool i915_semaphore_is_enabled(struct drm_device *dev)
> +bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv)
> {
> - if (INTEL_INFO(dev)->gen < 6)
> + if (INTEL_INFO(dev_priv)->gen < 6)
> return false;
>
> if (i915.semaphores >= 0)
> @@ -525,12 +525,12 @@ bool i915_semaphore_is_enabled(struct drm_device *dev)
> return false;
>
> /* Until we get further testing... */
> - if (IS_GEN8(dev))
> + if (IS_GEN8(dev_priv))
> return false;
>
> #ifdef CONFIG_INTEL_IOMMU
> /* Enable semaphores on SNB when IO remapping is off */
> - if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
> + if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped)
> return false;
> #endif
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 343a0a723d2c..fadf2ceb1f72 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3311,7 +3311,7 @@ extern void intel_detect_pch(struct drm_device *dev);
> extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
> extern int intel_enable_rc6(const struct drm_device *dev);
>
> -extern bool i915_semaphore_is_enabled(struct drm_device *dev);
> +extern bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv);
> int i915_reg_read_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file);
> int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 69d8d5fc750b..e6ac049a4698 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3150,7 +3150,7 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
> if (i915_gem_request_completed(from_req, true))
> return 0;
>
> - if (!i915_semaphore_is_enabled(obj->base.dev)) {
> + if (!i915_semaphore_is_enabled(to_i915(obj->base.dev))) {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> ret = __i915_wait_request(from_req,
> atomic_read(&i915->gpu_error.reset_counter),
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index f2f1e913f17a..55d2985c1dbb 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -483,7 +483,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
> u32 flags = hw_flags | MI_MM_SPACE_GTT;
> const int num_rings =
> /* Use an extended w/a on ivb+ if signalling from other rings */
> - i915_semaphore_is_enabled(ring->dev) ?
> + i915_semaphore_is_enabled(to_i915(ring->dev)) ?
> hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 :
> 0;
> int len, i, ret;
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 0d0a7b1a6b4b..d8e035e126d7 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -816,7 +816,7 @@ static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
> struct intel_engine_cs *to;
> int i;
>
> - if (!i915_semaphore_is_enabled(dev_priv->dev))
> + if (!i915_semaphore_is_enabled(dev_priv))
> return;
>
> if (!error->semaphore_obj)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 0eaaab92dea0..8d8ba717a022 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2594,7 +2594,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> ring->mmio_base = RENDER_RING_BASE;
>
> if (INTEL_INFO(dev)->gen >= 8) {
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> obj = i915_gem_alloc_object(dev, 4096);
> if (obj == NULL) {
> DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
> @@ -2619,7 +2619,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
> ring->get_seqno = gen6_ring_get_seqno;
> ring->set_seqno = ring_set_seqno;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> WARN_ON(!dev_priv->semaphore_obj);
> ring->semaphore.sync_to = gen8_ring_sync;
> ring->semaphore.signal = gen8_rcs_signal;
> @@ -2635,7 +2635,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
> ring->get_seqno = gen6_ring_get_seqno;
> ring->set_seqno = ring_set_seqno;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> ring->semaphore.sync_to = gen6_ring_sync;
> ring->semaphore.signal = gen6_signal;
> /*
> @@ -2756,7 +2756,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> ring->irq_put = gen8_ring_put_irq;
> ring->dispatch_execbuffer =
> gen8_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> ring->semaphore.sync_to = gen8_ring_sync;
> ring->semaphore.signal = gen8_xcs_signal;
> GEN8_RING_SEMAPHORE_INIT;
> @@ -2767,7 +2767,7 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> ring->irq_put = gen6_ring_put_irq;
> ring->dispatch_execbuffer =
> gen6_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> ring->semaphore.sync_to = gen6_ring_sync;
> ring->semaphore.signal = gen6_signal;
> ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
> @@ -2827,7 +2827,7 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
> ring->irq_put = gen8_ring_put_irq;
> ring->dispatch_execbuffer =
> gen8_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> ring->semaphore.sync_to = gen8_ring_sync;
> ring->semaphore.signal = gen8_xcs_signal;
> GEN8_RING_SEMAPHORE_INIT;
> @@ -2857,7 +2857,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
> ring->irq_get = gen8_ring_get_irq;
> ring->irq_put = gen8_ring_put_irq;
> ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> ring->semaphore.sync_to = gen8_ring_sync;
> ring->semaphore.signal = gen8_xcs_signal;
> GEN8_RING_SEMAPHORE_INIT;
> @@ -2867,7 +2867,7 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
> ring->irq_get = gen6_ring_get_irq;
> ring->irq_put = gen6_ring_put_irq;
> ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> ring->semaphore.signal = gen6_signal;
> ring->semaphore.sync_to = gen6_ring_sync;
> /*
> @@ -2915,7 +2915,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
> ring->irq_get = gen8_ring_get_irq;
> ring->irq_put = gen8_ring_put_irq;
> ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> ring->semaphore.sync_to = gen8_ring_sync;
> ring->semaphore.signal = gen8_xcs_signal;
> GEN8_RING_SEMAPHORE_INIT;
> @@ -2925,7 +2925,7 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
> ring->irq_get = hsw_vebox_get_irq;
> ring->irq_put = hsw_vebox_put_irq;
> ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
> - if (i915_semaphore_is_enabled(dev)) {
> + if (i915_semaphore_is_enabled(dev_priv)) {
> ring->semaphore.sync_to = gen6_ring_sync;
> ring->semaphore.signal = gen6_signal;
> ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
> --
> 2.6.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 02/12] drm/i915: Use the new rq->i915 field where appropriate
2015-11-20 12:43 ` [PATCH 02/12] drm/i915: Use the new rq->i915 field where appropriate Chris Wilson
@ 2015-11-24 13:57 ` Daniel Vetter
2015-11-24 14:23 ` Chris Wilson
0 siblings, 1 reply; 41+ messages in thread
From: Daniel Vetter @ 2015-11-24 13:57 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Nov 20, 2015 at 12:43:42PM +0000, Chris Wilson wrote:
> In a few frequent cases, having a direct pointer to the drm_i915_private
> from the request is very useful.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
req->i915 is a bit inconsistent imo, i915_dev would be better. Anyway, not
something you started, just makes the code a bit harder to speed-read ;-)
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 22 +++++++-----------
> drivers/gpu/drm/i915/i915_gem_context.c | 23 +++++++++----------
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 +--
> drivers/gpu/drm/i915/intel_lrc.c | 8 +++----
> drivers/gpu/drm/i915/intel_pm.c | 3 +--
> drivers/gpu/drm/i915/intel_ringbuffer.c | 36 +++++++++++++-----------------
> 6 files changed, 39 insertions(+), 56 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index e6ac049a4698..5c3d11d020f0 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1221,8 +1221,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
> struct intel_rps_client *rps)
> {
> struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
> - struct drm_device *dev = ring->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = req->i915;
> const bool irq_test_in_progress =
> ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
> int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
> @@ -1336,7 +1335,6 @@ out:
> int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
> struct drm_file *file)
> {
> - struct drm_i915_private *dev_private;
> struct drm_i915_file_private *file_priv;
>
> WARN_ON(!req || !file || req->file_priv);
> @@ -1347,7 +1345,6 @@ int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
> if (req->file_priv)
> return -EINVAL;
>
> - dev_private = req->ring->dev->dev_private;
> file_priv = file->driver_priv;
>
> spin_lock(&file_priv->mm.lock);
> @@ -1425,18 +1422,16 @@ __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
> int
> i915_wait_request(struct drm_i915_gem_request *req)
> {
> - struct drm_device *dev;
> struct drm_i915_private *dev_priv;
> bool interruptible;
> int ret;
>
> BUG_ON(req == NULL);
>
> - dev = req->ring->dev;
> - dev_priv = dev->dev_private;
> + dev_priv = req->i915;
> interruptible = dev_priv->mm.interruptible;
>
> - BUG_ON(!mutex_is_locked(&dev->struct_mutex));
> + BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
>
> ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
> if (ret)
> @@ -2568,7 +2563,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
> return;
>
> ring = request->ring;
> - dev_priv = ring->dev->dev_private;
> + dev_priv = request->i915;
> ringbuf = request->ringbuf;
>
> /*
> @@ -3150,8 +3145,8 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
> if (i915_gem_request_completed(from_req, true))
> return 0;
>
> - if (!i915_semaphore_is_enabled(to_i915(obj->base.dev))) {
> - struct drm_i915_private *i915 = to_i915(obj->base.dev);
> + if (!i915_semaphore_is_enabled(from_req->i915)) {
> + struct drm_i915_private *i915 = from_req->i915;
> ret = __i915_wait_request(from_req,
> atomic_read(&i915->gpu_error.reset_counter),
> i915->mm.interruptible,
> @@ -4648,13 +4643,12 @@ err:
> int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
> {
> struct intel_engine_cs *ring = req->ring;
> - struct drm_device *dev = ring->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = req->i915;
> u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
> u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
> int i, ret;
>
> - if (!HAS_L3_DPF(dev) || !remap_info)
> + if (!HAS_L3_DPF(dev_priv) || !remap_info)
> return 0;
>
> ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3);
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 55d2985c1dbb..82a9f7197d32 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -483,8 +483,8 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
> u32 flags = hw_flags | MI_MM_SPACE_GTT;
> const int num_rings =
> /* Use an extended w/a on ivb+ if signalling from other rings */
> - i915_semaphore_is_enabled(to_i915(ring->dev)) ?
> - hweight32(INTEL_INFO(ring->dev)->ring_mask) - 1 :
> + i915_semaphore_is_enabled(req->i915) ?
> + hweight32(INTEL_INFO(req->i915)->ring_mask) - 1 :
> 0;
> int len, i, ret;
>
> @@ -493,21 +493,21 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
> * explicitly, so we rely on the value at ring init, stored in
> * itlb_before_ctx_switch.
> */
> - if (IS_GEN6(ring->dev)) {
> + if (IS_GEN6(req->i915)) {
> ret = ring->flush(req, I915_GEM_GPU_DOMAINS, 0);
> if (ret)
> return ret;
> }
>
> /* These flags are for resource streamer on HSW+ */
> - if (IS_HASWELL(ring->dev) || INTEL_INFO(ring->dev)->gen >= 8)
> + if (IS_HASWELL(req->i915) || INTEL_INFO(req->i915)->gen >= 8)
> flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
> - else if (INTEL_INFO(ring->dev)->gen < 8)
> + else if (INTEL_INFO(req->i915)->gen < 8)
> flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
>
>
> len = 4;
> - if (INTEL_INFO(ring->dev)->gen >= 7)
> + if (INTEL_INFO(req->i915)->gen >= 7)
> len += 2 + (num_rings ? 4*num_rings + 2 : 0);
>
> ret = intel_ring_begin(req, len);
> @@ -515,13 +515,13 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
> return ret;
>
> /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
> - if (INTEL_INFO(ring->dev)->gen >= 7) {
> + if (INTEL_INFO(req->i915)->gen >= 7) {
> intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
> if (num_rings) {
> struct intel_engine_cs *signaller;
>
> intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
> - for_each_ring(signaller, to_i915(ring->dev), i) {
> + for_each_ring(signaller, req->i915, i) {
> if (signaller == ring)
> continue;
>
> @@ -541,12 +541,12 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
> */
> intel_ring_emit(ring, MI_NOOP);
>
> - if (INTEL_INFO(ring->dev)->gen >= 7) {
> + if (INTEL_INFO(req->i915)->gen >= 7) {
> if (num_rings) {
> struct intel_engine_cs *signaller;
>
> intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
> - for_each_ring(signaller, to_i915(ring->dev), i) {
> + for_each_ring(signaller, req->i915, i) {
> if (signaller == ring)
> continue;
>
> @@ -785,10 +785,9 @@ unpin_out:
> int i915_switch_context(struct drm_i915_gem_request *req)
> {
> struct intel_engine_cs *ring = req->ring;
> - struct drm_i915_private *dev_priv = ring->dev->dev_private;
>
> WARN_ON(i915.enable_execlists);
> - WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
> + WARN_ON(!mutex_is_locked(&req->i915->dev->struct_mutex));
>
> if (req->ctx->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */
> if (req->ctx != ring->last_context) {
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 7ac4685e0d3e..e8164b644e0e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1066,7 +1066,6 @@ void
> i915_gem_execbuffer_move_to_active(struct list_head *vmas,
> struct drm_i915_gem_request *req)
> {
> - struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
> struct i915_vma *vma;
>
> list_for_each_entry(vma, vmas, exec_list) {
> @@ -1093,7 +1092,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
> if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
> i915_gem_request_assign(&obj->last_fenced_req, req);
> if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
> - struct drm_i915_private *dev_priv = to_i915(ring->dev);
> + struct drm_i915_private *dev_priv = req->i915;
> list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
> &dev_priv->mm.fence_list);
> }
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 10020505be75..cfa77a59b352 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -307,8 +307,7 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
> {
>
> struct intel_engine_cs *ring = rq0->ring;
> - struct drm_device *dev = ring->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = rq0->i915;
> uint64_t desc[2];
>
> if (rq1) {
> @@ -787,7 +786,7 @@ int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
> int ret;
>
> WARN_ON(req == NULL);
> - dev_priv = req->ring->dev->dev_private;
> + dev_priv = req->i915;
>
> ret = i915_gem_check_wedge(&dev_priv->gpu_error,
> dev_priv->mm.interruptible);
> @@ -1027,8 +1026,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
> int ret, i;
> struct intel_engine_cs *ring = req->ring;
> struct intel_ringbuffer *ringbuf = req->ringbuf;
> - struct drm_device *dev = ring->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = req->i915;
> struct i915_workarounds *w = &dev_priv->workarounds;
>
> if (WARN_ON_ONCE(w->count == 0))
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index aef9eb1c6c33..3d54f76ad176 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7410,8 +7410,7 @@ static void __intel_rps_boost_work(struct work_struct *work)
> struct drm_i915_gem_request *req = boost->req;
>
> if (!i915_gem_request_completed(req, true))
> - intel_rps_boost(to_i915(req->ring->dev), NULL,
> - req->emitted_jiffies);
> + intel_rps_boost(req->i915, NULL, req->emitted_jiffies);
>
> i915_gem_request_unreference__unlocked(req);
> kfree(boost);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 8d8ba717a022..9fbe730aae47 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -123,7 +123,6 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
> u32 flush_domains)
> {
> struct intel_engine_cs *ring = req->ring;
> - struct drm_device *dev = ring->dev;
> u32 cmd;
> int ret;
>
> @@ -162,7 +161,7 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
> cmd |= MI_EXE_FLUSH;
>
> if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
> - (IS_G4X(dev) || IS_GEN5(dev)))
> + (IS_G4X(req->i915) || IS_GEN5(req->i915)))
> cmd |= MI_INVALIDATE_ISP;
>
> ret = intel_ring_begin(req, 2);
> @@ -715,8 +714,7 @@ static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
> {
> int ret, i;
> struct intel_engine_cs *ring = req->ring;
> - struct drm_device *dev = ring->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = req->i915;
> struct i915_workarounds *w = &dev_priv->workarounds;
>
> if (WARN_ON_ONCE(w->count == 0))
> @@ -1187,12 +1185,11 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
> {
> #define MBOX_UPDATE_DWORDS 8
> struct intel_engine_cs *signaller = signaller_req->ring;
> - struct drm_device *dev = signaller->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = signaller_req->i915;
> struct intel_engine_cs *waiter;
> int i, ret, num_rings;
>
> - num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
> + num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
> num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
> #undef MBOX_UPDATE_DWORDS
>
> @@ -1228,12 +1225,11 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
> {
> #define MBOX_UPDATE_DWORDS 6
> struct intel_engine_cs *signaller = signaller_req->ring;
> - struct drm_device *dev = signaller->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = signaller_req->i915;
> struct intel_engine_cs *waiter;
> int i, ret, num_rings;
>
> - num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
> + num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
> num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
> #undef MBOX_UPDATE_DWORDS
>
> @@ -1266,13 +1262,12 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
> unsigned int num_dwords)
> {
> struct intel_engine_cs *signaller = signaller_req->ring;
> - struct drm_device *dev = signaller->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct drm_i915_private *dev_priv = signaller_req->i915;
> struct intel_engine_cs *useless;
> int i, ret, num_rings;
>
> #define MBOX_UPDATE_DWORDS 3
> - num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
> + num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
> num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
> #undef MBOX_UPDATE_DWORDS
>
> @@ -1349,7 +1344,7 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
> u32 seqno)
> {
> struct intel_engine_cs *waiter = waiter_req->ring;
> - struct drm_i915_private *dev_priv = waiter->dev->dev_private;
> + struct drm_i915_private *dev_priv = waiter_req->i915;
> int ret;
>
> ret = intel_ring_begin(waiter_req, 4);
> @@ -2201,8 +2196,8 @@ int intel_ring_idle(struct intel_engine_cs *ring)
>
> /* Make sure we do not trigger any retires */
> return __i915_wait_request(req,
> - atomic_read(&to_i915(ring->dev)->gpu_error.reset_counter),
> - to_i915(ring->dev)->mm.interruptible,
> + atomic_read(&req->i915->gpu_error.reset_counter),
> + req->i915->mm.interruptible,
> NULL, NULL);
> }
>
> @@ -2330,7 +2325,7 @@ int intel_ring_begin(struct drm_i915_gem_request *req,
>
> WARN_ON(req == NULL);
> ring = req->ring;
> - dev_priv = ring->dev->dev_private;
> + dev_priv = req->i915;
>
> ret = i915_gem_check_wedge(&dev_priv->gpu_error,
> dev_priv->mm.interruptible);
> @@ -2467,7 +2462,7 @@ gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
> unsigned dispatch_flags)
> {
> struct intel_engine_cs *ring = req->ring;
> - bool ppgtt = USES_PPGTT(ring->dev) &&
> + bool ppgtt = USES_PPGTT(req->i915) &&
> !(dispatch_flags & I915_DISPATCH_SECURE);
> int ret;
>
> @@ -2541,7 +2536,6 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
> u32 invalidate, u32 flush)
> {
> struct intel_engine_cs *ring = req->ring;
> - struct drm_device *dev = ring->dev;
> uint32_t cmd;
> int ret;
>
> @@ -2550,7 +2544,7 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
> return ret;
>
> cmd = MI_FLUSH_DW;
> - if (INTEL_INFO(dev)->gen >= 8)
> + if (INTEL_INFO(req->i915)->gen >= 8)
> cmd += 1;
>
> /* We always require a command barrier so that subsequent
> @@ -2570,7 +2564,7 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
> cmd |= MI_INVALIDATE_TLB;
> intel_ring_emit(ring, cmd);
> intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
> - if (INTEL_INFO(dev)->gen >= 8) {
> + if (INTEL_INFO(req->i915)->gen >= 8) {
> intel_ring_emit(ring, 0); /* upper addr */
> intel_ring_emit(ring, 0); /* value */
> } else {
> --
> 2.6.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 02/12] drm/i915: Use the new rq->i915 field where appropriate
2015-11-24 13:57 ` Daniel Vetter
@ 2015-11-24 14:23 ` Chris Wilson
2015-11-24 14:41 ` Daniel Vetter
0 siblings, 1 reply; 41+ messages in thread
From: Chris Wilson @ 2015-11-24 14:23 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Tue, Nov 24, 2015 at 02:57:04PM +0100, Daniel Vetter wrote:
> On Fri, Nov 20, 2015 at 12:43:42PM +0000, Chris Wilson wrote:
> > In a few frequent cases, having a direct pointer to the drm_i915_private
> > from the request is very useful.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>
> req->i915 is a bit inconsistent imo, i915_dev would be better. Anyway, not
> something you started, just makes the code a bit harder to speed-read ;-)
How does it strike you as inconsistent? rq->i915 was nicer :-p
The idea I have been trying to sell is i915->drm->dev for the struct
drm_i915_private / struct drm_device / struct device triplet.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 03/12] drm/i915: Unify intel_logical_ring_emit and intel_ring_emit
2015-11-20 12:43 ` [PATCH 03/12] drm/i915: Unify intel_logical_ring_emit and intel_ring_emit Chris Wilson
@ 2015-11-24 14:33 ` Daniel Vetter
2015-11-24 14:52 ` Chris Wilson
0 siblings, 1 reply; 41+ messages in thread
From: Daniel Vetter @ 2015-11-24 14:33 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Nov 20, 2015 at 12:43:43PM +0000, Chris Wilson wrote:
> Both perform the same actions with more or less indirection, so just
> unify the code.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_context.c | 8 +-
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 34 ++++-----
> drivers/gpu/drm/i915/i915_gem_gtt.c | 26 +++----
> drivers/gpu/drm/i915/intel_display.c | 26 +++----
> drivers/gpu/drm/i915/intel_lrc.c | 118 ++++++++++++++---------------
> drivers/gpu/drm/i915/intel_lrc.h | 21 -----
> drivers/gpu/drm/i915/intel_mocs.c | 30 ++++----
> drivers/gpu/drm/i915/intel_overlay.c | 42 +++++-----
> drivers/gpu/drm/i915/intel_ringbuffer.c | 107 +++++++++++++-------------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 15 +---
> 11 files changed, 195 insertions(+), 234 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 5c3d11d020f0..c60105e36263 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4642,7 +4642,7 @@ err:
>
> int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> struct drm_i915_private *dev_priv = req->i915;
> u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
> u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 82a9f7197d32..c3adc121aab4 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -479,7 +479,7 @@ i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
> static inline int
> mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> u32 flags = hw_flags | MI_MM_SPACE_GTT;
> const int num_rings =
> /* Use an extended w/a on ivb+ if signalling from other rings */
> @@ -494,7 +494,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
> * itlb_before_ctx_switch.
> */
> if (IS_GEN6(req->i915)) {
> - ret = ring->flush(req, I915_GEM_GPU_DOMAINS, 0);
> + ret = req->ring->flush(req, I915_GEM_GPU_DOMAINS, 0);
> if (ret)
> return ret;
> }
> @@ -522,7 +522,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
>
> intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
> for_each_ring(signaller, req->i915, i) {
> - if (signaller == ring)
> + if (signaller == req->ring)
> continue;
>
> intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
> @@ -547,7 +547,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
>
> intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
> for_each_ring(signaller, req->i915, i) {
> - if (signaller == ring)
> + if (signaller == req->ring)
> continue;
Tsk, unrelated hunks above. And maybe a cocci to s/req->ring/req->engine/.
At least mention in the commit message that your on a crusade against
superflous ring/dev/whatever pointers and arguments while in the area.
> intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index e8164b644e0e..5f1b9b7df051 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1113,14 +1113,12 @@ i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
> }
>
> static int
> -i915_reset_gen7_sol_offsets(struct drm_device *dev,
> - struct drm_i915_gem_request *req)
> +i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
> {
> - struct intel_engine_cs *ring = req->ring;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_ringbuffer *ring = req->ringbuf;
> int ret, i;
>
> - if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS]) {
> + if (!IS_GEN7(req->i915) || req->ring->id != RCS) {
> DRM_DEBUG("sol reset is gen7/rcs only\n");
> return -EINVAL;
> }
> @@ -1198,9 +1196,8 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
> struct drm_i915_gem_execbuffer2 *args,
> struct list_head *vmas)
> {
> - struct drm_device *dev = params->dev;
> - struct intel_engine_cs *ring = params->ring;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_ringbuffer *ring = params->request->ringbuf;
> + struct drm_i915_private *dev_priv = params->request->i915;
> u64 exec_start, exec_len;
> int instp_mode;
> u32 instp_mask;
> @@ -1214,34 +1211,31 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
> if (ret)
> return ret;
>
> - WARN(params->ctx->ppgtt && params->ctx->ppgtt->pd_dirty_rings & (1<<ring->id),
> - "%s didn't clear reload\n", ring->name);
> -
> instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
> instp_mask = I915_EXEC_CONSTANTS_MASK;
> switch (instp_mode) {
> case I915_EXEC_CONSTANTS_REL_GENERAL:
> case I915_EXEC_CONSTANTS_ABSOLUTE:
> case I915_EXEC_CONSTANTS_REL_SURFACE:
> - if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
> + if (instp_mode != 0 && params->ring->id != RCS) {
> DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
> return -EINVAL;
> }
>
> if (instp_mode != dev_priv->relative_constants_mode) {
> - if (INTEL_INFO(dev)->gen < 4) {
> + if (INTEL_INFO(dev_priv)->gen < 4) {
> DRM_DEBUG("no rel constants on pre-gen4\n");
> return -EINVAL;
> }
>
> - if (INTEL_INFO(dev)->gen > 5 &&
> + if (INTEL_INFO(dev_priv)->gen > 5 &&
> instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
> DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
> return -EINVAL;
> }
>
> /* The HW changed the meaning on this bit on gen6 */
> - if (INTEL_INFO(dev)->gen >= 6)
> + if (INTEL_INFO(dev_priv)->gen >= 6)
> instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
> }
> break;
> @@ -1250,7 +1244,7 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
> return -EINVAL;
> }
>
> - if (ring == &dev_priv->ring[RCS] &&
> + if (params->ring->id == RCS &&
> instp_mode != dev_priv->relative_constants_mode) {
> ret = intel_ring_begin(params->request, 4);
> if (ret)
> @@ -1266,7 +1260,7 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
> }
>
> if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
> - ret = i915_reset_gen7_sol_offsets(dev, params->request);
> + ret = i915_reset_gen7_sol_offsets(params->request);
> if (ret)
> return ret;
> }
> @@ -1275,9 +1269,9 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
> exec_start = params->batch_obj_vm_offset +
> params->args_batch_start_offset;
>
> - ret = ring->dispatch_execbuffer(params->request,
> - exec_start, exec_len,
> - params->dispatch_flags);
> + ret = params->ring->dispatch_execbuffer(params->request,
> + exec_start, exec_len,
> + params->dispatch_flags);
I guess we should just shovel all the stuff in params into request
eventually ...
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 7820e8983136..4608884adfc8 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -651,7 +651,7 @@ static int gen8_write_pdp(struct drm_i915_gem_request *req,
> unsigned entry,
> dma_addr_t addr)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> int ret;
>
> BUG_ON(entry >= 4);
> @@ -661,10 +661,10 @@ static int gen8_write_pdp(struct drm_i915_gem_request *req,
> return ret;
>
> intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
> - intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
> + intel_ring_emit(ring, GEN8_RING_PDP_UDW(req->ring, entry));
> intel_ring_emit(ring, upper_32_bits(addr));
> intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
> - intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
> + intel_ring_emit(ring, GEN8_RING_PDP_LDW(req->ring, entry));
> intel_ring_emit(ring, lower_32_bits(addr));
> intel_ring_advance(ring);
>
> @@ -1588,11 +1588,11 @@ static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
> static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
> struct drm_i915_gem_request *req)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> int ret;
>
> /* NB: TLBs must be flushed and invalidated before a switch */
> - ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> + ret = req->ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> if (ret)
> return ret;
>
> @@ -1601,9 +1601,9 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
> return ret;
>
> intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
> - intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
> + intel_ring_emit(ring, RING_PP_DIR_DCLV(req->ring));
> intel_ring_emit(ring, PP_DIR_DCLV_2G);
> - intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
> + intel_ring_emit(ring, RING_PP_DIR_BASE(req->ring));
> intel_ring_emit(ring, get_pd_offset(ppgtt));
> intel_ring_emit(ring, MI_NOOP);
> intel_ring_advance(ring);
> @@ -1625,11 +1625,11 @@ static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
> static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
> struct drm_i915_gem_request *req)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> int ret;
>
> /* NB: TLBs must be flushed and invalidated before a switch */
> - ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> + ret = req->ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> if (ret)
> return ret;
>
> @@ -1638,16 +1638,16 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
> return ret;
>
> intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
> - intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
> + intel_ring_emit(ring, RING_PP_DIR_DCLV(req->ring));
> intel_ring_emit(ring, PP_DIR_DCLV_2G);
> - intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
> + intel_ring_emit(ring, RING_PP_DIR_BASE(req->ring));
> intel_ring_emit(ring, get_pd_offset(ppgtt));
> intel_ring_emit(ring, MI_NOOP);
> intel_ring_advance(ring);
>
> /* XXX: RCS is the only one to auto invalidate the TLBs? */
> - if (ring->id != RCS) {
> - ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> + if (req->ring->id != RCS) {
> + ret = req->ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> if (ret)
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6bd204980b70..f6dae2cfd9c9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10824,7 +10824,7 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
> struct drm_i915_gem_request *req,
> uint32_t flags)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> u32 flip_mask;
> int ret;
> @@ -10859,7 +10859,7 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
> struct drm_i915_gem_request *req,
> uint32_t flags)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> u32 flip_mask;
> int ret;
> @@ -10891,8 +10891,8 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
> struct drm_i915_gem_request *req,
> uint32_t flags)
> {
> - struct intel_engine_cs *ring = req->ring;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_ringbuffer *ring = req->ringbuf;
> + struct drm_i915_private *dev_priv = req->i915;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> uint32_t pf, pipesrc;
> int ret;
> @@ -10930,8 +10930,8 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
> struct drm_i915_gem_request *req,
> uint32_t flags)
> {
> - struct intel_engine_cs *ring = req->ring;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_ringbuffer *ring = req->ringbuf;
> + struct drm_i915_private *dev_priv = req->i915;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> uint32_t pf, pipesrc;
> int ret;
> @@ -10966,7 +10966,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
> struct drm_i915_gem_request *req,
> uint32_t flags)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> uint32_t plane_bit = 0;
> int len, ret;
> @@ -10987,14 +10987,14 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
> }
>
> len = 4;
> - if (ring->id == RCS) {
> + if (req->ring->id == RCS) {
> len += 6;
> /*
> * On Gen 8, SRM is now taking an extra dword to accommodate
> * 48bits addresses, and we need a NOOP for the batch size to
> * stay even.
> */
> - if (IS_GEN8(dev))
> + if (IS_GEN8(req->i915))
> len += 2;
> }
>
> @@ -11025,21 +11025,21 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
> * for the RCS also doesn't appear to drop events. Setting the DERRMR
> * to zero does lead to lockups within MI_DISPLAY_FLIP.
> */
> - if (ring->id == RCS) {
> + if (req->ring->id == RCS) {
> intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
> intel_ring_emit(ring, DERRMR);
> intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
> DERRMR_PIPEB_PRI_FLIP_DONE |
> DERRMR_PIPEC_PRI_FLIP_DONE));
> - if (IS_GEN8(dev))
> + if (IS_GEN8(req->i915))
> intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
> MI_SRM_LRM_GLOBAL_GTT);
> else
> intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
> MI_SRM_LRM_GLOBAL_GTT);
> intel_ring_emit(ring, DERRMR);
> - intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
> - if (IS_GEN8(dev)) {
> + intel_ring_emit(ring, req->ring->scratch.gtt_offset + 256);
> + if (IS_GEN8(req->i915)) {
> intel_ring_emit(ring, 0);
> intel_ring_emit(ring, MI_NOOP);
> }
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index cfa77a59b352..0db23c474045 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -700,11 +700,9 @@ static int logical_ring_wait_for_space(struct drm_i915_gem_request *req,
> static void
> intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
> {
> - struct intel_engine_cs *ring = request->ring;
> -
> - intel_logical_ring_advance(request->ringbuf);
> + intel_ring_advance(request->ringbuf);
>
> - if (intel_ring_stopped(ring))
> + if (intel_ring_stopped(request->ring))
> return;
>
> execlists_context_queue(request);
> @@ -887,11 +885,11 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
> if (ret)
> return ret;
>
> - intel_logical_ring_emit(ringbuf, MI_NOOP);
> - intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
> - intel_logical_ring_emit(ringbuf, INSTPM);
> - intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
> - intel_logical_ring_advance(ringbuf);
> + intel_ring_emit(ringbuf, MI_NOOP);
> + intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
> + intel_ring_emit(ringbuf, INSTPM);
> + intel_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
> + intel_ring_advance(ringbuf);
>
> dev_priv->relative_constants_mode = instp_mode;
> }
> @@ -1041,14 +1039,14 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
> if (ret)
> return ret;
>
> - intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
> + intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
> for (i = 0; i < w->count; i++) {
> - intel_logical_ring_emit(ringbuf, w->reg[i].addr);
> - intel_logical_ring_emit(ringbuf, w->reg[i].value);
> + intel_ring_emit(ringbuf, w->reg[i].addr);
> + intel_ring_emit(ringbuf, w->reg[i].value);
> }
> - intel_logical_ring_emit(ringbuf, MI_NOOP);
> + intel_ring_emit(ringbuf, MI_NOOP);
>
> - intel_logical_ring_advance(ringbuf);
> + intel_ring_advance(ringbuf);
>
> ring->gpu_caches_dirty = true;
> ret = logical_ring_flush_all_caches(req);
> @@ -1478,18 +1476,18 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
> if (ret)
> return ret;
>
> - intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
> + intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
> for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
> const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
>
> - intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i));
> - intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr));
> - intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i));
> - intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr));
> + intel_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i));
> + intel_ring_emit(ringbuf, upper_32_bits(pd_daddr));
> + intel_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i));
> + intel_ring_emit(ringbuf, lower_32_bits(pd_daddr));
> }
>
> - intel_logical_ring_emit(ringbuf, MI_NOOP);
> - intel_logical_ring_advance(ringbuf);
> + intel_ring_emit(ringbuf, MI_NOOP);
> + intel_ring_advance(ringbuf);
>
> return 0;
> }
> @@ -1523,14 +1521,14 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
> return ret;
>
> /* FIXME(BDW): Address space and security selectors. */
> - intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
> - (ppgtt<<8) |
> - (dispatch_flags & I915_DISPATCH_RS ?
> - MI_BATCH_RESOURCE_STREAMER : 0));
> - intel_logical_ring_emit(ringbuf, lower_32_bits(offset));
> - intel_logical_ring_emit(ringbuf, upper_32_bits(offset));
> - intel_logical_ring_emit(ringbuf, MI_NOOP);
> - intel_logical_ring_advance(ringbuf);
> + intel_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
> + (ppgtt<<8) |
> + (dispatch_flags & I915_DISPATCH_RS ?
> + MI_BATCH_RESOURCE_STREAMER : 0));
> + intel_ring_emit(ringbuf, lower_32_bits(offset));
> + intel_ring_emit(ringbuf, upper_32_bits(offset));
> + intel_ring_emit(ringbuf, MI_NOOP);
> + intel_ring_advance(ringbuf);
>
> return 0;
> }
> @@ -1598,13 +1596,13 @@ static int gen8_emit_flush(struct drm_i915_gem_request *request,
> cmd |= MI_INVALIDATE_BSD;
> }
>
> - intel_logical_ring_emit(ringbuf, cmd);
> - intel_logical_ring_emit(ringbuf,
> - I915_GEM_HWS_SCRATCH_ADDR |
> - MI_FLUSH_DW_USE_GTT);
> - intel_logical_ring_emit(ringbuf, 0); /* upper addr */
> - intel_logical_ring_emit(ringbuf, 0); /* value */
> - intel_logical_ring_advance(ringbuf);
> + intel_ring_emit(ringbuf, cmd);
> + intel_ring_emit(ringbuf,
> + I915_GEM_HWS_SCRATCH_ADDR |
> + MI_FLUSH_DW_USE_GTT);
> + intel_ring_emit(ringbuf, 0); /* upper addr */
> + intel_ring_emit(ringbuf, 0); /* value */
> + intel_ring_advance(ringbuf);
>
> return 0;
> }
> @@ -1651,21 +1649,21 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> return ret;
>
> if (vf_flush_wa) {
> - intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
> - intel_logical_ring_emit(ringbuf, 0);
> - intel_logical_ring_emit(ringbuf, 0);
> - intel_logical_ring_emit(ringbuf, 0);
> - intel_logical_ring_emit(ringbuf, 0);
> - intel_logical_ring_emit(ringbuf, 0);
> + intel_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
> + intel_ring_emit(ringbuf, 0);
> + intel_ring_emit(ringbuf, 0);
> + intel_ring_emit(ringbuf, 0);
> + intel_ring_emit(ringbuf, 0);
> + intel_ring_emit(ringbuf, 0);
> }
>
> - intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
> - intel_logical_ring_emit(ringbuf, flags);
> - intel_logical_ring_emit(ringbuf, scratch_addr);
> - intel_logical_ring_emit(ringbuf, 0);
> - intel_logical_ring_emit(ringbuf, 0);
> - intel_logical_ring_emit(ringbuf, 0);
> - intel_logical_ring_advance(ringbuf);
> + intel_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
> + intel_ring_emit(ringbuf, flags);
> + intel_ring_emit(ringbuf, scratch_addr);
> + intel_ring_emit(ringbuf, 0);
> + intel_ring_emit(ringbuf, 0);
> + intel_ring_emit(ringbuf, 0);
> + intel_ring_advance(ringbuf);
>
> return 0;
> }
> @@ -1699,23 +1697,23 @@ static int gen8_emit_request(struct drm_i915_gem_request *request)
> cmd = MI_STORE_DWORD_IMM_GEN4;
> cmd |= MI_GLOBAL_GTT;
>
> - intel_logical_ring_emit(ringbuf, cmd);
> - intel_logical_ring_emit(ringbuf,
> - (ring->status_page.gfx_addr +
> - (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
> - intel_logical_ring_emit(ringbuf, 0);
> - intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
> - intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT);
> - intel_logical_ring_emit(ringbuf, MI_NOOP);
> + intel_ring_emit(ringbuf, cmd);
> + intel_ring_emit(ringbuf,
> + (ring->status_page.gfx_addr +
> + (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
> + intel_ring_emit(ringbuf, 0);
> + intel_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
> + intel_ring_emit(ringbuf, MI_USER_INTERRUPT);
> + intel_ring_emit(ringbuf, MI_NOOP);
> intel_logical_ring_advance_and_submit(request);
>
> /*
> * Here we add two extra NOOPs as padding to avoid
> * lite restore of a context with HEAD==TAIL.
> */
> - intel_logical_ring_emit(ringbuf, MI_NOOP);
> - intel_logical_ring_emit(ringbuf, MI_NOOP);
> - intel_logical_ring_advance(ringbuf);
> + intel_ring_emit(ringbuf, MI_NOOP);
> + intel_ring_emit(ringbuf, MI_NOOP);
> + intel_ring_advance(ringbuf);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> index 8b56fb934763..861668919e5a 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/intel_lrc.h
> @@ -45,27 +45,6 @@ int intel_logical_rings_init(struct drm_device *dev);
> int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords);
>
> int logical_ring_flush_all_caches(struct drm_i915_gem_request *req);
> -/**
> - * intel_logical_ring_advance() - advance the ringbuffer tail
> - * @ringbuf: Ringbuffer to advance.
> - *
> - * The tail is only updated in our logical ringbuffer struct.
> - */
> -static inline void intel_logical_ring_advance(struct intel_ringbuffer *ringbuf)
> -{
> - intel_ringbuffer_advance(ringbuf);
> -}
> -
> -/**
> - * intel_logical_ring_emit() - write a DWORD to the ringbuffer.
> - * @ringbuf: Ringbuffer to write to.
> - * @data: DWORD to write.
> - */
> -static inline void intel_logical_ring_emit(struct intel_ringbuffer *ringbuf,
> - u32 data)
> -{
> - intel_ringbuffer_emit(ringbuf, data);
> -}
>
> /* Logical Ring Contexts */
> void intel_lr_context_free(struct intel_context *ctx);
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index 6d3c6c0a5c62..399a131a94b6 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -187,13 +187,11 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
> return ret;
> }
>
> - intel_logical_ring_emit(ringbuf,
> - MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
> + intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
>
> for (index = 0; index < table->size; index++) {
> - intel_logical_ring_emit(ringbuf, reg_base + index * 4);
> - intel_logical_ring_emit(ringbuf,
> - table->table[index].control_value);
> + intel_ring_emit(ringbuf, reg_base + index * 4);
> + intel_ring_emit(ringbuf, table->table[index].control_value);
> }
>
> /*
> @@ -205,12 +203,12 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
> * that value to all the used entries.
> */
> for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
> - intel_logical_ring_emit(ringbuf, reg_base + index * 4);
> - intel_logical_ring_emit(ringbuf, table->table[0].control_value);
> + intel_ring_emit(ringbuf, reg_base + index * 4);
> + intel_ring_emit(ringbuf, table->table[0].control_value);
> }
>
> - intel_logical_ring_emit(ringbuf, MI_NOOP);
> - intel_logical_ring_advance(ringbuf);
> + intel_ring_emit(ringbuf, MI_NOOP);
> + intel_ring_advance(ringbuf);
>
> return 0;
> }
> @@ -246,15 +244,15 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
> return ret;
> }
>
> - intel_logical_ring_emit(ringbuf,
> + intel_ring_emit(ringbuf,
> MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2));
>
> for (i = 0, count = 0; i < table->size / 2; i++, count += 2) {
> value = (table->table[count].l3cc_value & 0xffff) |
> ((table->table[count + 1].l3cc_value & 0xffff) << 16);
>
> - intel_logical_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);
> - intel_logical_ring_emit(ringbuf, value);
> + intel_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);
> + intel_ring_emit(ringbuf, value);
> }
>
> if (table->size & 0x01) {
> @@ -270,14 +268,14 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
> * they are reserved by the hardware.
> */
> for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
> - intel_logical_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);
> - intel_logical_ring_emit(ringbuf, value);
> + intel_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);
> + intel_ring_emit(ringbuf, value);
>
> value = filler;
> }
>
> - intel_logical_ring_emit(ringbuf, MI_NOOP);
> - intel_logical_ring_advance(ringbuf);
> + intel_ring_emit(ringbuf, MI_NOOP);
> + intel_ring_advance(ringbuf);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
> index 444542696a2c..5e9c7c15a84b 100644
> --- a/drivers/gpu/drm/i915/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/intel_overlay.c
> @@ -252,11 +252,11 @@ static int intel_overlay_on(struct intel_overlay *overlay)
>
> overlay->active = true;
>
> - intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
> - intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE);
> - intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
> - intel_ring_emit(ring, MI_NOOP);
> - intel_ring_advance(ring);
> + intel_ring_emit(req->ringbuf, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
> + intel_ring_emit(req->ringbuf, overlay->flip_addr | OFC_UPDATE);
> + intel_ring_emit(req->ringbuf, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
> + intel_ring_emit(req->ringbuf, MI_NOOP);
> + intel_ring_advance(req->ringbuf);
>
> return intel_overlay_do_wait_request(overlay, req, NULL);
> }
> @@ -293,9 +293,9 @@ static int intel_overlay_continue(struct intel_overlay *overlay,
> return ret;
> }
>
> - intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
> - intel_ring_emit(ring, flip_addr);
> - intel_ring_advance(ring);
> + intel_ring_emit(req->ringbuf, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
> + intel_ring_emit(req->ringbuf, flip_addr);
> + intel_ring_advance(req->ringbuf);
>
> WARN_ON(overlay->last_flip_req);
> i915_gem_request_assign(&overlay->last_flip_req, req);
> @@ -360,22 +360,22 @@ static int intel_overlay_off(struct intel_overlay *overlay)
> }
>
> /* wait for overlay to go idle */
> - intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
> - intel_ring_emit(ring, flip_addr);
> - intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
> + intel_ring_emit(req->ringbuf, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
> + intel_ring_emit(req->ringbuf, flip_addr);
> + intel_ring_emit(req->ringbuf, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
> /* turn overlay off */
> if (IS_I830(dev)) {
> /* Workaround: Don't disable the overlay fully, since otherwise
> * it dies on the next OVERLAY_ON cmd. */
> - intel_ring_emit(ring, MI_NOOP);
> - intel_ring_emit(ring, MI_NOOP);
> - intel_ring_emit(ring, MI_NOOP);
> + intel_ring_emit(req->ringbuf, MI_NOOP);
> + intel_ring_emit(req->ringbuf, MI_NOOP);
> + intel_ring_emit(req->ringbuf, MI_NOOP);
> } else {
> - intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
> - intel_ring_emit(ring, flip_addr);
> - intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
> + intel_ring_emit(req->ringbuf, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
> + intel_ring_emit(req->ringbuf, flip_addr);
> + intel_ring_emit(req->ringbuf, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
> }
> - intel_ring_advance(ring);
> + intel_ring_advance(req->ringbuf);
>
> return intel_overlay_do_wait_request(overlay, req, intel_overlay_off_tail);
> }
> @@ -433,9 +433,9 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
> return ret;
> }
>
> - intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
> - intel_ring_emit(ring, MI_NOOP);
> - intel_ring_advance(ring);
> + intel_ring_emit(req->ringbuf, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
> + intel_ring_emit(req->ringbuf, MI_NOOP);
> + intel_ring_advance(req->ringbuf);
>
> ret = intel_overlay_do_wait_request(overlay, req,
> intel_overlay_release_old_vid_tail);
Any reason for not doing your usual transform to intel_ringbuffer for the
local ring here in the overlay code? Or does that happen when
intel_ring_begin falls?
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 9fbe730aae47..b3de8b1fde2f 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -95,7 +95,7 @@ gen2_render_ring_flush(struct drm_i915_gem_request *req,
> u32 invalidate_domains,
> u32 flush_domains)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> u32 cmd;
> int ret;
>
> @@ -122,7 +122,7 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
> u32 invalidate_domains,
> u32 flush_domains)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> u32 cmd;
> int ret;
>
> @@ -215,8 +215,8 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
> static int
> intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
> {
> - struct intel_engine_cs *ring = req->ring;
> - u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> + struct intel_ringbuffer *ring = req->ringbuf;
> + u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> int ret;
>
> ret = intel_ring_begin(req, 6);
> @@ -251,9 +251,9 @@ static int
> gen6_render_ring_flush(struct drm_i915_gem_request *req,
> u32 invalidate_domains, u32 flush_domains)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> u32 flags = 0;
> - u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> + u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> int ret;
>
> /* Force SNB workarounds for PIPE_CONTROL flushes */
> @@ -303,7 +303,7 @@ gen6_render_ring_flush(struct drm_i915_gem_request *req,
> static int
> gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> int ret;
>
> ret = intel_ring_begin(req, 4);
> @@ -324,9 +324,9 @@ static int
> gen7_render_ring_flush(struct drm_i915_gem_request *req,
> u32 invalidate_domains, u32 flush_domains)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> u32 flags = 0;
> - u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> + u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> int ret;
>
> /*
> @@ -387,7 +387,7 @@ static int
> gen8_emit_pipe_control(struct drm_i915_gem_request *req,
> u32 flags, u32 scratch_addr)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> int ret;
>
> ret = intel_ring_begin(req, 6);
> @@ -712,15 +712,15 @@ err:
>
> static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
> {
> - int ret, i;
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> struct drm_i915_private *dev_priv = req->i915;
> struct i915_workarounds *w = &dev_priv->workarounds;
> + int ret, i;
>
> if (WARN_ON_ONCE(w->count == 0))
> return 0;
>
> - ring->gpu_caches_dirty = true;
> + req->ring->gpu_caches_dirty = true;
> ret = intel_ring_flush_all_caches(req);
> if (ret)
> return ret;
> @@ -738,7 +738,7 @@ static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
>
> intel_ring_advance(ring);
>
> - ring->gpu_caches_dirty = true;
> + req->ring->gpu_caches_dirty = true;
> ret = intel_ring_flush_all_caches(req);
> if (ret)
> return ret;
> @@ -1184,7 +1184,7 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
> unsigned int num_dwords)
> {
> #define MBOX_UPDATE_DWORDS 8
> - struct intel_engine_cs *signaller = signaller_req->ring;
> + struct intel_ringbuffer *signaller = signaller_req->ringbuf;
> struct drm_i915_private *dev_priv = signaller_req->i915;
> struct intel_engine_cs *waiter;
> int i, ret, num_rings;
> @@ -1199,7 +1199,7 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
>
> for_each_ring(waiter, dev_priv, i) {
> u32 seqno;
> - u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
> + u64 gtt_offset = signaller_req->ring->semaphore.signal_ggtt[i];
> if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
> continue;
>
> @@ -1224,7 +1224,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
> unsigned int num_dwords)
> {
> #define MBOX_UPDATE_DWORDS 6
> - struct intel_engine_cs *signaller = signaller_req->ring;
> + struct intel_ringbuffer *signaller = signaller_req->ringbuf;
> struct drm_i915_private *dev_priv = signaller_req->i915;
> struct intel_engine_cs *waiter;
> int i, ret, num_rings;
> @@ -1239,7 +1239,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
>
> for_each_ring(waiter, dev_priv, i) {
> u32 seqno;
> - u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
> + u64 gtt_offset = signaller_req->ring->semaphore.signal_ggtt[i];
> if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
> continue;
>
> @@ -1261,7 +1261,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
> static int gen6_signal(struct drm_i915_gem_request *signaller_req,
> unsigned int num_dwords)
> {
> - struct intel_engine_cs *signaller = signaller_req->ring;
> + struct intel_ringbuffer *signaller = signaller_req->ringbuf;
> struct drm_i915_private *dev_priv = signaller_req->i915;
> struct intel_engine_cs *useless;
> int i, ret, num_rings;
> @@ -1276,7 +1276,7 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
> return ret;
>
> for_each_ring(useless, dev_priv, i) {
> - u32 mbox_reg = signaller->semaphore.mbox.signal[i];
> + u32 mbox_reg = signaller_req->ring->semaphore.mbox.signal[i];
> if (mbox_reg != GEN6_NOSYNC) {
> u32 seqno = i915_gem_request_get_seqno(signaller_req);
> intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
> @@ -1303,11 +1303,11 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
> static int
> gen6_add_request(struct drm_i915_gem_request *req)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> int ret;
>
> - if (ring->semaphore.signal)
> - ret = ring->semaphore.signal(req, 4);
> + if (req->ring->semaphore.signal)
> + ret = req->ring->semaphore.signal(req, 4);
> else
> ret = intel_ring_begin(req, 4);
>
> @@ -1318,15 +1318,14 @@ gen6_add_request(struct drm_i915_gem_request *req)
> intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
> intel_ring_emit(ring, i915_gem_request_get_seqno(req));
> intel_ring_emit(ring, MI_USER_INTERRUPT);
> - __intel_ring_advance(ring);
> + __intel_ring_advance(req->ring);
>
> return 0;
> }
>
> -static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
> +static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv,
> u32 seqno)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> return dev_priv->last_seqno < seqno;
> }
>
> @@ -1343,7 +1342,7 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
> struct intel_engine_cs *signaller,
> u32 seqno)
> {
> - struct intel_engine_cs *waiter = waiter_req->ring;
> + struct intel_ringbuffer *waiter = waiter_req->ringbuf;
> struct drm_i915_private *dev_priv = waiter_req->i915;
> int ret;
>
> @@ -1357,9 +1356,11 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
> MI_SEMAPHORE_SAD_GTE_SDD);
> intel_ring_emit(waiter, seqno);
> intel_ring_emit(waiter,
> - lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
> + lower_32_bits(GEN8_WAIT_OFFSET(waiter_req->ring,
> + signaller->id)));
> intel_ring_emit(waiter,
> - upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
> + upper_32_bits(GEN8_WAIT_OFFSET(waiter_req->ring,
> + signaller->id)));
> intel_ring_advance(waiter);
> return 0;
> }
> @@ -1369,11 +1370,11 @@ gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
> struct intel_engine_cs *signaller,
> u32 seqno)
> {
> - struct intel_engine_cs *waiter = waiter_req->ring;
> + struct intel_ringbuffer *waiter = waiter_req->ringbuf;
> u32 dw1 = MI_SEMAPHORE_MBOX |
> MI_SEMAPHORE_COMPARE |
> MI_SEMAPHORE_REGISTER;
> - u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
> + u32 wait_mbox = signaller->semaphore.mbox.wait[waiter_req->ring->id];
> int ret;
>
> /* Throughout all of the GEM code, seqno passed implies our current
> @@ -1389,7 +1390,7 @@ gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
> return ret;
>
> /* If seqno wrap happened, omit the wait with no-ops */
> - if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
> + if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) {
> intel_ring_emit(waiter, dw1 | wait_mbox);
> intel_ring_emit(waiter, seqno);
> intel_ring_emit(waiter, 0);
> @@ -1417,8 +1418,8 @@ do { \
> static int
> pc_render_add_request(struct drm_i915_gem_request *req)
> {
> - struct intel_engine_cs *ring = req->ring;
> - u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> + struct intel_ringbuffer *ring = req->ringbuf;
> + u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> int ret;
>
> /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
> @@ -1436,7 +1437,7 @@ pc_render_add_request(struct drm_i915_gem_request *req)
> intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
> PIPE_CONTROL_WRITE_FLUSH |
> PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
> - intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
> + intel_ring_emit(ring, req->ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
> intel_ring_emit(ring, i915_gem_request_get_seqno(req));
> intel_ring_emit(ring, 0);
> PIPE_CONTROL_FLUSH(ring, scratch_addr);
> @@ -1455,10 +1456,10 @@ pc_render_add_request(struct drm_i915_gem_request *req)
> PIPE_CONTROL_WRITE_FLUSH |
> PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
> PIPE_CONTROL_NOTIFY);
> - intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
> + intel_ring_emit(ring, req->ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
> intel_ring_emit(ring, i915_gem_request_get_seqno(req));
> intel_ring_emit(ring, 0);
> - __intel_ring_advance(ring);
> + __intel_ring_advance(req->ring);
>
> return 0;
> }
> @@ -1611,7 +1612,7 @@ bsd_ring_flush(struct drm_i915_gem_request *req,
> u32 invalidate_domains,
> u32 flush_domains)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> int ret;
>
> ret = intel_ring_begin(req, 2);
> @@ -1627,7 +1628,7 @@ bsd_ring_flush(struct drm_i915_gem_request *req,
> static int
> i9xx_add_request(struct drm_i915_gem_request *req)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> int ret;
>
> ret = intel_ring_begin(req, 4);
> @@ -1638,7 +1639,7 @@ i9xx_add_request(struct drm_i915_gem_request *req)
> intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
> intel_ring_emit(ring, i915_gem_request_get_seqno(req));
> intel_ring_emit(ring, MI_USER_INTERRUPT);
> - __intel_ring_advance(ring);
> + __intel_ring_advance(req->ring);
>
> return 0;
> }
> @@ -1772,7 +1773,7 @@ i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
> u64 offset, u32 length,
> unsigned dispatch_flags)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> int ret;
>
> ret = intel_ring_begin(req, 2);
> @@ -1799,8 +1800,8 @@ i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
> u64 offset, u32 len,
> unsigned dispatch_flags)
> {
> - struct intel_engine_cs *ring = req->ring;
> - u32 cs_offset = ring->scratch.gtt_offset;
> + struct intel_ringbuffer *ring = req->ringbuf;
> + u32 cs_offset = req->ring->scratch.gtt_offset;
> int ret;
>
> ret = intel_ring_begin(req, 6);
> @@ -1862,7 +1863,7 @@ i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
> u64 offset, u32 len,
> unsigned dispatch_flags)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> int ret;
>
> ret = intel_ring_begin(req, 2);
> @@ -2343,8 +2344,8 @@ int intel_ring_begin(struct drm_i915_gem_request *req,
> /* Align the ring tail to a cacheline boundary */
> int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
> {
> - struct intel_engine_cs *ring = req->ring;
> - int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
> + struct intel_ringbuffer *ring = req->ringbuf;
> + int num_dwords = (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
> int ret;
>
> if (num_dwords == 0)
> @@ -2415,7 +2416,7 @@ static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
> static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
> u32 invalidate, u32 flush)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> uint32_t cmd;
> int ret;
>
> @@ -2424,7 +2425,7 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
> return ret;
>
> cmd = MI_FLUSH_DW;
> - if (INTEL_INFO(ring->dev)->gen >= 8)
> + if (INTEL_INFO(req->i915)->gen >= 8)
> cmd += 1;
>
> /* We always require a command barrier so that subsequent
> @@ -2445,7 +2446,7 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
>
> intel_ring_emit(ring, cmd);
> intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
> - if (INTEL_INFO(ring->dev)->gen >= 8) {
> + if (INTEL_INFO(req->i915)->gen >= 8) {
> intel_ring_emit(ring, 0); /* upper addr */
> intel_ring_emit(ring, 0); /* value */
> } else {
> @@ -2461,7 +2462,7 @@ gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
> u64 offset, u32 len,
> unsigned dispatch_flags)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> bool ppgtt = USES_PPGTT(req->i915) &&
> !(dispatch_flags & I915_DISPATCH_SECURE);
> int ret;
> @@ -2487,7 +2488,7 @@ hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
> u64 offset, u32 len,
> unsigned dispatch_flags)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> int ret;
>
> ret = intel_ring_begin(req, 2);
> @@ -2512,7 +2513,7 @@ gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
> u64 offset, u32 len,
> unsigned dispatch_flags)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> int ret;
>
> ret = intel_ring_begin(req, 2);
> @@ -2535,7 +2536,7 @@ gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
> static int gen6_ring_flush(struct drm_i915_gem_request *req,
> u32 invalidate, u32 flush)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_ringbuffer *ring = req->ringbuf;
> uint32_t cmd;
> int ret;
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 10f80df5f121..212b402818f9 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -427,25 +427,16 @@ int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request);
>
> int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n);
> int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req);
> -static inline void intel_ringbuffer_emit(struct intel_ringbuffer *rb,
> - u32 data)
> +static inline void intel_ring_emit(struct intel_ringbuffer *rb,
> + u32 data)
> {
> *(uint32_t *)(rb->virtual_start + rb->tail) = data;
> rb->tail += 4;
> }
> -static inline void intel_ringbuffer_advance(struct intel_ringbuffer *rb)
> +static inline void intel_ring_advance(struct intel_ringbuffer *rb)
> {
> rb->tail &= rb->size - 1;
> }
> -static inline void intel_ring_emit(struct intel_engine_cs *ring,
> - u32 data)
> -{
> - intel_ringbuffer_emit(ring->buffer, data);
> -}
> -static inline void intel_ring_advance(struct intel_engine_cs *ring)
> -{
> - intel_ringbuffer_advance(ring->buffer);
> -}
> int __intel_ring_space(int head, int tail, int size);
> void intel_ring_update_space(struct intel_ringbuffer *ringbuf);
> int intel_ring_space(struct intel_ringbuffer *ringbuf);
At the end of this crusade we should add some pretty kerneldoc for our
ringbuffer interface.
Anyway, with some notes about your dev_priv/ringbuffer/whatver crusade
added to the commit message, just to align and clarify the new naming
convention:
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 04/12] drm/i915: Unify intel_ring_begin()
2015-11-20 12:43 ` [PATCH 04/12] drm/i915: Unify intel_ring_begin() Chris Wilson
@ 2015-11-24 14:38 ` Daniel Vetter
2015-11-24 14:58 ` Chris Wilson
0 siblings, 1 reply; 41+ messages in thread
From: Daniel Vetter @ 2015-11-24 14:38 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Nov 20, 2015 at 12:43:44PM +0000, Chris Wilson wrote:
> Combine the near identical implementations of intel_logical_ring_begin()
> and intel_ring_begin() - the only difference is that the logical wait
> has to check for a matching ring (which is assumed by legacy).
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Hm, I originally punted on this one since OCD-me wanted to move
engine->request_list to ring->request_list first. But hey just adding the
check works too and gives us the immediate improvement faster!
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 149 ++------------------------------
> drivers/gpu/drm/i915/intel_lrc.h | 1 -
> drivers/gpu/drm/i915/intel_mocs.c | 12 +--
> drivers/gpu/drm/i915/intel_ringbuffer.c | 115 ++++++++++++------------
> 4 files changed, 71 insertions(+), 206 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 0db23c474045..02f798e4c726 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -646,48 +646,6 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request
> return 0;
> }
>
> -static int logical_ring_wait_for_space(struct drm_i915_gem_request *req,
> - int bytes)
> -{
> - struct intel_ringbuffer *ringbuf = req->ringbuf;
> - struct intel_engine_cs *ring = req->ring;
> - struct drm_i915_gem_request *target;
> - unsigned space;
> - int ret;
> -
> - if (intel_ring_space(ringbuf) >= bytes)
> - return 0;
> -
> - /* The whole point of reserving space is to not wait! */
> - WARN_ON(ringbuf->reserved_in_use);
> -
> - list_for_each_entry(target, &ring->request_list, list) {
> - /*
> - * The request queue is per-engine, so can contain requests
> - * from multiple ringbuffers. Here, we must ignore any that
> - * aren't from the ringbuffer we're considering.
> - */
> - if (target->ringbuf != ringbuf)
> - continue;
> -
> - /* Would completion of this request free enough space? */
> - space = __intel_ring_space(target->postfix, ringbuf->tail,
> - ringbuf->size);
> - if (space >= bytes)
> - break;
> - }
> -
> - if (WARN_ON(&target->list == &ring->request_list))
> - return -ENOSPC;
> -
> - ret = i915_wait_request(target);
> - if (ret)
> - return ret;
> -
> - ringbuf->space = space;
> - return 0;
> -}
> -
> /*
> * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload
> * @request: Request to advance the logical ringbuffer of.
> @@ -708,97 +666,6 @@ intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
> execlists_context_queue(request);
> }
>
> -static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
> -{
> - int rem = ringbuf->size - ringbuf->tail;
> - memset(ringbuf->virtual_start + ringbuf->tail, 0, rem);
> -
> - ringbuf->tail = 0;
> - intel_ring_update_space(ringbuf);
> -}
> -
> -static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes)
> -{
> - struct intel_ringbuffer *ringbuf = req->ringbuf;
> - int remain_usable = ringbuf->effective_size - ringbuf->tail;
> - int remain_actual = ringbuf->size - ringbuf->tail;
> - int ret, total_bytes, wait_bytes = 0;
> - bool need_wrap = false;
> -
> - if (ringbuf->reserved_in_use)
> - total_bytes = bytes;
> - else
> - total_bytes = bytes + ringbuf->reserved_size;
> -
> - if (unlikely(bytes > remain_usable)) {
> - /*
> - * Not enough space for the basic request. So need to flush
> - * out the remainder and then wait for base + reserved.
> - */
> - wait_bytes = remain_actual + total_bytes;
> - need_wrap = true;
> - } else {
> - if (unlikely(total_bytes > remain_usable)) {
> - /*
> - * The base request will fit but the reserved space
> - * falls off the end. So only need to to wait for the
> - * reserved size after flushing out the remainder.
> - */
> - wait_bytes = remain_actual + ringbuf->reserved_size;
> - need_wrap = true;
> - } else if (total_bytes > ringbuf->space) {
> - /* No wrapping required, just waiting. */
> - wait_bytes = total_bytes;
> - }
> - }
> -
> - if (wait_bytes) {
> - ret = logical_ring_wait_for_space(req, wait_bytes);
> - if (unlikely(ret))
> - return ret;
> -
> - if (need_wrap)
> - __wrap_ring_buffer(ringbuf);
> - }
> -
> - return 0;
> -}
> -
> -/**
> - * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands
> - *
> - * @request: The request to start some new work for
> - * @ctx: Logical ring context whose ringbuffer is being prepared.
> - * @num_dwords: number of DWORDs that we plan to write to the ringbuffer.
> - *
> - * The ringbuffer might not be ready to accept the commands right away (maybe it needs to
> - * be wrapped, or wait a bit for the tail to be updated). This function takes care of that
> - * and also preallocates a request (every workload submission is still mediated through
> - * requests, same as it did with legacy ringbuffer submission).
> - *
> - * Return: non-zero if the ringbuffer is not ready to be written to.
> - */
> -int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
> -{
> - struct drm_i915_private *dev_priv;
> - int ret;
> -
> - WARN_ON(req == NULL);
> - dev_priv = req->i915;
> -
> - ret = i915_gem_check_wedge(&dev_priv->gpu_error,
> - dev_priv->mm.interruptible);
> - if (ret)
> - return ret;
> -
> - ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t));
> - if (ret)
> - return ret;
> -
> - req->ringbuf->space -= num_dwords * sizeof(uint32_t);
> - return 0;
> -}
> -
> int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
> {
> /*
> @@ -811,7 +678,7 @@ int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
> */
> intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
>
> - return intel_logical_ring_begin(request, 0);
> + return intel_ring_begin(request, 0);
> }
>
> /**
> @@ -881,7 +748,7 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
>
> if (ring == &dev_priv->ring[RCS] &&
> instp_mode != dev_priv->relative_constants_mode) {
> - ret = intel_logical_ring_begin(params->request, 4);
> + ret = intel_ring_begin(params->request, 4);
> if (ret)
> return ret;
>
> @@ -1035,7 +902,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
> if (ret)
> return ret;
>
> - ret = intel_logical_ring_begin(req, w->count * 2 + 2);
> + ret = intel_ring_begin(req, w->count * 2 + 2);
> if (ret)
> return ret;
>
> @@ -1472,7 +1339,7 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
> const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
> int i, ret;
>
> - ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2);
> + ret = intel_ring_begin(req, num_lri_cmds * 2 + 2);
> if (ret)
> return ret;
>
> @@ -1516,7 +1383,7 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
> req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring);
> }
>
> - ret = intel_logical_ring_begin(req, 4);
> + ret = intel_ring_begin(req, 4);
> if (ret)
> return ret;
>
> @@ -1577,7 +1444,7 @@ static int gen8_emit_flush(struct drm_i915_gem_request *request,
> uint32_t cmd;
> int ret;
>
> - ret = intel_logical_ring_begin(request, 4);
> + ret = intel_ring_begin(request, 4);
> if (ret)
> return ret;
>
> @@ -1644,7 +1511,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
> flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
>
> - ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6);
> + ret = intel_ring_begin(request, vf_flush_wa ? 12 : 6);
> if (ret)
> return ret;
>
> @@ -1690,7 +1557,7 @@ static int gen8_emit_request(struct drm_i915_gem_request *request)
> * used as a workaround for not being allowed to do lite
> * restore with HEAD==TAIL (WaIdleLiteRestore).
> */
> - ret = intel_logical_ring_begin(request, 8);
> + ret = intel_ring_begin(request, 8);
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> index 861668919e5a..5402eca78a07 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/intel_lrc.h
> @@ -42,7 +42,6 @@ int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
> void intel_logical_ring_stop(struct intel_engine_cs *ring);
> void intel_logical_ring_cleanup(struct intel_engine_cs *ring);
> int intel_logical_rings_init(struct drm_device *dev);
> -int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords);
>
> int logical_ring_flush_all_caches(struct drm_i915_gem_request *req);
>
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index 399a131a94b6..ac0a982bbf55 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -181,11 +181,9 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
> if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
> return -ENODEV;
>
> - ret = intel_logical_ring_begin(req, 2 + 2 * GEN9_NUM_MOCS_ENTRIES);
> - if (ret) {
> - DRM_DEBUG("intel_logical_ring_begin failed %d\n", ret);
> + ret = intel_ring_begin(req, 2 + 2 * GEN9_NUM_MOCS_ENTRIES);
> + if (ret)
> return ret;
> - }
>
> intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
>
> @@ -238,11 +236,9 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
> if (WARN_ON(table->size > GEN9_NUM_MOCS_ENTRIES))
> return -ENODEV;
>
> - ret = intel_logical_ring_begin(req, 2 + GEN9_NUM_MOCS_ENTRIES);
> - if (ret) {
> - DRM_DEBUG("intel_logical_ring_begin failed %d\n", ret);
> + ret = intel_ring_begin(req, 2 + GEN9_NUM_MOCS_ENTRIES);
> + if (ret)
> return ret;
> - }
>
> intel_ring_emit(ringbuf,
> MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2));
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index b3de8b1fde2f..fbee790ddaf0 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2143,46 +2143,6 @@ void intel_cleanup_ring_buffer(struct intel_engine_cs *ring)
> ring->buffer = NULL;
> }
>
> -static int ring_wait_for_space(struct intel_engine_cs *ring, int n)
> -{
> - struct intel_ringbuffer *ringbuf = ring->buffer;
> - struct drm_i915_gem_request *request;
> - unsigned space;
> - int ret;
> -
> - if (intel_ring_space(ringbuf) >= n)
> - return 0;
> -
> - /* The whole point of reserving space is to not wait! */
> - WARN_ON(ringbuf->reserved_in_use);
> -
> - list_for_each_entry(request, &ring->request_list, list) {
> - space = __intel_ring_space(request->postfix, ringbuf->tail,
> - ringbuf->size);
> - if (space >= n)
> - break;
> - }
> -
> - if (WARN_ON(&request->list == &ring->request_list))
> - return -ENOSPC;
> -
> - ret = i915_wait_request(request);
> - if (ret)
> - return ret;
> -
> - ringbuf->space = space;
> - return 0;
> -}
> -
> -static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
> -{
> - int rem = ringbuf->size - ringbuf->tail;
> - memset(ringbuf->virtual_start + ringbuf->tail, 0, rem);
> -
> - ringbuf->tail = 0;
> - intel_ring_update_space(ringbuf);
> -}
> -
> int intel_ring_idle(struct intel_engine_cs *ring)
> {
> struct drm_i915_gem_request *req;
> @@ -2270,9 +2230,59 @@ void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
> ringbuf->reserved_in_use = false;
> }
>
> -static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
> +static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> {
> - struct intel_ringbuffer *ringbuf = ring->buffer;
> + struct intel_ringbuffer *ringbuf = req->ringbuf;
> + struct intel_engine_cs *ring = req->ring;
> + struct drm_i915_gem_request *target;
> + unsigned space;
> + int ret;
> +
> + if (intel_ring_space(ringbuf) >= bytes)
> + return 0;
> +
> + /* The whole point of reserving space is to not wait! */
> + WARN_ON(ringbuf->reserved_in_use);
> +
> + list_for_each_entry(target, &ring->request_list, list) {
> + /*
> + * The request queue is per-engine, so can contain requests
> + * from multiple ringbuffers. Here, we must ignore any that
> + * aren't from the ringbuffer we're considering.
> + */
> + if (target->ringbuf != ringbuf)
> + continue;
> +
> + /* Would completion of this request free enough space? */
> + space = __intel_ring_space(target->postfix, ringbuf->tail,
> + ringbuf->size);
> + if (space >= bytes)
> + break;
> + }
> +
> + if (WARN_ON(&target->list == &ring->request_list))
> + return -ENOSPC;
> +
> + ret = i915_wait_request(target);
> + if (ret)
> + return ret;
> +
> + ringbuf->space = space;
> + return 0;
> +}
> +
> +static void ring_wrap(struct intel_ringbuffer *ringbuf)
> +{
> + int rem = ringbuf->size - ringbuf->tail;
> + memset(ringbuf->virtual_start + ringbuf->tail, 0, rem);
> +
> + ringbuf->tail = 0;
> + intel_ring_update_space(ringbuf);
> +}
> +
> +static int ring_prepare(struct drm_i915_gem_request *req, int bytes)
> +{
> + struct intel_ringbuffer *ringbuf = req->ringbuf;
> int remain_usable = ringbuf->effective_size - ringbuf->tail;
> int remain_actual = ringbuf->size - ringbuf->tail;
> int ret, total_bytes, wait_bytes = 0;
> @@ -2306,38 +2316,31 @@ static int __intel_ring_prepare(struct intel_engine_cs *ring, int bytes)
> }
>
> if (wait_bytes) {
> - ret = ring_wait_for_space(ring, wait_bytes);
> + ret = wait_for_space(req, wait_bytes);
> if (unlikely(ret))
> return ret;
>
> if (need_wrap)
> - __wrap_ring_buffer(ringbuf);
> + ring_wrap(ringbuf);
> }
>
> return 0;
> }
>
> -int intel_ring_begin(struct drm_i915_gem_request *req,
> - int num_dwords)
> +int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
> {
> - struct intel_engine_cs *ring;
> - struct drm_i915_private *dev_priv;
> int ret;
>
> - WARN_ON(req == NULL);
> - ring = req->ring;
> - dev_priv = req->i915;
> -
> - ret = i915_gem_check_wedge(&dev_priv->gpu_error,
> - dev_priv->mm.interruptible);
> + ret = i915_gem_check_wedge(&req->i915->gpu_error,
> + req->i915->mm.interruptible);
> if (ret)
> return ret;
>
> - ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t));
> + ret = ring_prepare(req, num_dwords * sizeof(uint32_t));
> if (ret)
> return ret;
>
> - ring->buffer->space -= num_dwords * sizeof(uint32_t);
> + req->ringbuf->space -= num_dwords * sizeof(uint32_t);
> return 0;
> }
>
> --
> 2.6.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 02/12] drm/i915: Use the new rq->i915 field where appropriate
2015-11-24 14:23 ` Chris Wilson
@ 2015-11-24 14:41 ` Daniel Vetter
0 siblings, 0 replies; 41+ messages in thread
From: Daniel Vetter @ 2015-11-24 14:41 UTC (permalink / raw)
To: Chris Wilson, Daniel Vetter, intel-gfx
On Tue, Nov 24, 2015 at 02:23:03PM +0000, Chris Wilson wrote:
> On Tue, Nov 24, 2015 at 02:57:04PM +0100, Daniel Vetter wrote:
> > On Fri, Nov 20, 2015 at 12:43:42PM +0000, Chris Wilson wrote:
> > > In a few frequent cases, having a direct pointer to the drm_i915_private
> > > from the request is very useful.
> > >
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> >
> > req->i915 is a bit inconsistent imo, i915_dev would be better. Anyway, not
> > something you started, just makes the code a bit harder to speed-read ;-)
>
> How does it strike you as inconsistent? rq->i915 was nicer :-p
>
> The idea I have been trying to sell is i915->drm->dev for the struct
> drm_i915_private / struct drm_device / struct device triplet.
Hm, we should do an overview section in i915 docs about best practices in
variable naming. I'm serious about this, since we have similar fun with
modeset stuff:
- Preferred: crtc for struct intel_crtc, drm_crtc for struct drm_crtc.
- Transitinoal: crtc for struct drm_crtc, intel_crtc for struct
intel_crtc. But if you have only one, then don't use that.
Maybe we should mention intel_ vs. i915_ vs. platform prefixes too?
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 05/12] drm/i915: Remove the identical implementations of request space reservation
2015-11-20 12:43 ` [PATCH 05/12] drm/i915: Remove the identical implementations of request space reservation Chris Wilson
@ 2015-11-24 14:42 ` Daniel Vetter
0 siblings, 0 replies; 41+ messages in thread
From: Daniel Vetter @ 2015-11-24 14:42 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Nov 20, 2015 at 12:43:45PM +0000, Chris Wilson wrote:
> Now that we share intel_ring_begin(), reserving space for the tail of
> the request is identical between legacy/execlists and so the tautology
> can be removed.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 7 +++----
> drivers/gpu/drm/i915/intel_lrc.c | 15 ---------------
> drivers/gpu/drm/i915/intel_lrc.h | 1 -
> drivers/gpu/drm/i915/intel_ringbuffer.c | 15 ---------------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 3 ---
> 5 files changed, 3 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index c60105e36263..030fc9d14385 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2743,10 +2743,9 @@ int i915_gem_request_alloc(struct intel_engine_cs *ring,
> * to be redone if the request is not actually submitted straight
> * away, e.g. because a GPU scheduler has deferred it.
> */
> - if (i915.enable_execlists)
> - ret = intel_logical_ring_reserve_space(req);
> - else
> - ret = intel_ring_reserve_space(req);
> + intel_ring_reserved_space_reserve(req->ringbuf,
> + MIN_SPACE_FOR_ADD_REQUEST);
> + ret = intel_ring_begin(req, 0);
> if (ret) {
> /*
> * At this point, the request is fully allocated even if not
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 02f798e4c726..2458804c521d 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -666,21 +666,6 @@ intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
> execlists_context_queue(request);
> }
>
> -int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request)
> -{
> - /*
> - * The first call merely notes the reserve request and is common for
> - * all back ends. The subsequent localised _begin() call actually
> - * ensures that the reservation is available. Without the begin, if
> - * the request creator immediately submitted the request without
> - * adding any commands to it then there might not actually be
> - * sufficient room for the submission commands.
> - */
> - intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
> -
> - return intel_ring_begin(request, 0);
> -}
> -
> /**
> * execlists_submission() - submit a batchbuffer for execution, Execlists style
> * @dev: DRM device.
> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> index 5402eca78a07..9981e989fcaf 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/intel_lrc.h
> @@ -38,7 +38,6 @@
>
> /* Logical Rings */
> int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
> -int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
> void intel_logical_ring_stop(struct intel_engine_cs *ring);
> void intel_logical_ring_cleanup(struct intel_engine_cs *ring);
> int intel_logical_rings_init(struct drm_device *dev);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index fbee790ddaf0..9821c2a8074a 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2168,21 +2168,6 @@ int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
> return 0;
> }
>
> -int intel_ring_reserve_space(struct drm_i915_gem_request *request)
> -{
> - /*
> - * The first call merely notes the reserve request and is common for
> - * all back ends. The subsequent localised _begin() call actually
> - * ensures that the reservation is available. Without the begin, if
> - * the request creator immediately submitted the request without
> - * adding any commands to it then there might not actually be
> - * sufficient room for the submission commands.
> - */
> - intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
> -
> - return intel_ring_begin(request, 0);
> -}
> -
> void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
> {
> WARN_ON(ringbuf->reserved_size);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 212b402818f9..368d9b0454ed 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -487,7 +487,4 @@ void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf);
> /* Finish with the reserved space - for use by i915_add_request() only. */
> void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf);
>
> -/* Legacy ringbuffer specific portion of reservation code: */
> -int intel_ring_reserve_space(struct drm_i915_gem_request *request);
> -
> #endif /* _INTEL_RINGBUFFER_H_ */
> --
> 2.6.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 06/12] drm/i915: Rename request->ring to request->engine
2015-11-20 12:43 ` [PATCH 06/12] drm/i915: Rename request->ring to request->engine Chris Wilson
@ 2015-11-24 14:48 ` Daniel Vetter
0 siblings, 0 replies; 41+ messages in thread
From: Daniel Vetter @ 2015-11-24 14:48 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Nov 20, 2015 at 12:43:46PM +0000, Chris Wilson wrote:
> In order to disambiguate between the pointer to the intel_engine_cs
> (called ring) and the intel_ringbuffer (called ringbuf), rename
> s/ring/engine/.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Ah, here we go. Slight amend for the commit message:
"Where known that req is non-NULL replace get_ring() with req->engine too
while at it. And also use dev_priv more while touching code."
With that Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 11 ++-
> drivers/gpu/drm/i915/i915_drv.h | 12 +--
> drivers/gpu/drm/i915/i915_gem.c | 76 ++++++++--------
> drivers/gpu/drm/i915/i915_gem_context.c | 63 ++++++-------
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 8 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 49 +++++-----
> drivers/gpu/drm/i915/i915_gem_render_state.c | 18 ++--
> drivers/gpu/drm/i915/i915_gpu_error.c | 3 +-
> drivers/gpu/drm/i915/i915_trace.h | 34 +++----
> drivers/gpu/drm/i915/intel_display.c | 12 +--
> drivers/gpu/drm/i915/intel_lrc.c | 128 +++++++++++++--------------
> drivers/gpu/drm/i915/intel_mocs.c | 10 +--
> drivers/gpu/drm/i915/intel_ringbuffer.c | 66 +++++++-------
> 13 files changed, 239 insertions(+), 251 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 359436162f3d..56375c36b381 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -190,8 +190,7 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
> seq_printf(m, " (%s mappable)", s);
> }
> if (obj->last_write_req != NULL)
> - seq_printf(m, " (%s)",
> - i915_gem_request_get_ring(obj->last_write_req)->name);
> + seq_printf(m, " (%s)", obj->last_write_req->engine->name);
> if (obj->frontbuffer_bits)
> seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
> }
> @@ -594,14 +593,14 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data)
> pipe, plane);
> }
> if (work->flip_queued_req) {
> - struct intel_engine_cs *ring =
> - i915_gem_request_get_ring(work->flip_queued_req);
> + struct intel_engine_cs *engine =
> + work->flip_queued_req->engine;
>
> seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
> - ring->name,
> + engine->name,
> i915_gem_request_get_seqno(work->flip_queued_req),
> dev_priv->next_seqno,
> - ring->get_seqno(ring, true),
> + engine->get_seqno(engine, true),
> i915_gem_request_completed(work->flip_queued_req, true));
> } else
> seq_printf(m, "Flip not associated with any ring\n");
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fadf2ceb1f72..9ce8b3fcb3a0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2156,7 +2156,7 @@ struct drm_i915_gem_request {
>
> /** On Which ring this request was generated */
> struct drm_i915_private *i915;
> - struct intel_engine_cs *ring;
> + struct intel_engine_cs *engine;
>
> /** GEM sequence number associated with this request. */
> uint32_t seqno;
> @@ -2240,9 +2240,9 @@ i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
> }
>
> static inline struct intel_engine_cs *
> -i915_gem_request_get_ring(struct drm_i915_gem_request *req)
> +i915_gem_request_get_engine(struct drm_i915_gem_request *req)
> {
> - return req ? req->ring : NULL;
> + return req ? req->engine : NULL;
> }
>
> static inline struct drm_i915_gem_request *
> @@ -2256,7 +2256,7 @@ i915_gem_request_reference(struct drm_i915_gem_request *req)
> static inline void
> i915_gem_request_unreference(struct drm_i915_gem_request *req)
> {
> - WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
> + WARN_ON(!mutex_is_locked(&req->i915->dev->struct_mutex));
> kref_put(&req->ref, i915_gem_request_free);
> }
>
> @@ -2268,7 +2268,7 @@ i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
> if (!req)
> return;
>
> - dev = req->ring->dev;
> + dev = req->i915->dev;
> if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
> mutex_unlock(&dev->struct_mutex);
> }
> @@ -2877,7 +2877,7 @@ static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
>
> BUG_ON(req == NULL);
>
> - seqno = req->ring->get_seqno(req->ring, lazy_coherency);
> + seqno = req->engine->get_seqno(req->engine, lazy_coherency);
>
> return i915_seqno_passed(seqno, req->seqno);
> }
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 030fc9d14385..5a1b51a27fe3 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1174,7 +1174,7 @@ static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
> u64 timeout;
> unsigned cpu;
>
> - if (i915_gem_request_get_ring(req)->irq_refcount)
> + if (req->engine->irq_refcount)
> return -EBUSY;
>
> timeout = local_clock_us(&cpu) + 2;
> @@ -1220,10 +1220,10 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
> s64 *timeout,
> struct intel_rps_client *rps)
> {
> - struct intel_engine_cs *ring = i915_gem_request_get_ring(req);
> + struct intel_engine_cs *engine = req->engine;
> struct drm_i915_private *dev_priv = req->i915;
> const bool irq_test_in_progress =
> - ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
> + ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(engine);
> int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
> DEFINE_WAIT(wait);
> unsigned long timeout_expire;
> @@ -1252,7 +1252,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
> if (ret == 0)
> goto out;
>
> - if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) {
> + if (!irq_test_in_progress && WARN_ON(!engine->irq_get(engine))) {
> ret = -ENODEV;
> goto out;
> }
> @@ -1260,7 +1260,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
> for (;;) {
> struct timer_list timer;
>
> - prepare_to_wait(&ring->irq_queue, &wait, state);
> + prepare_to_wait(&engine->irq_queue, &wait, state);
>
> /* We need to check whether any gpu reset happened in between
> * the caller grabbing the seqno and now ... */
> @@ -1289,11 +1289,11 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
> }
>
> timer.function = NULL;
> - if (timeout || missed_irq(dev_priv, ring)) {
> + if (timeout || missed_irq(dev_priv, engine)) {
> unsigned long expire;
>
> setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
> - expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
> + expire = missed_irq(dev_priv, engine) ? jiffies + 1 : timeout_expire;
> mod_timer(&timer, expire);
> }
>
> @@ -1305,9 +1305,9 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
> }
> }
> if (!irq_test_in_progress)
> - ring->irq_put(ring);
> + engine->irq_put(engine);
>
> - finish_wait(&ring->irq_queue, &wait);
> + finish_wait(&engine->irq_queue, &wait);
>
> out:
> now = ktime_get_raw_ns();
> @@ -1397,7 +1397,7 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request)
> static void
> __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
> {
> - struct intel_engine_cs *engine = req->ring;
> + struct intel_engine_cs *engine = req->engine;
> struct drm_i915_gem_request *tmp;
>
> lockdep_assert_held(&engine->dev->struct_mutex);
> @@ -1466,7 +1466,7 @@ i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
> if (ret)
> return ret;
>
> - i = obj->last_write_req->ring->id;
> + i = obj->last_write_req->engine->id;
> if (obj->last_read_req[i] == obj->last_write_req)
> i915_gem_object_retire__read(obj, i);
> else
> @@ -1493,7 +1493,7 @@ static void
> i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
> struct drm_i915_gem_request *req)
> {
> - int ring = req->ring->id;
> + int ring = req->engine->id;
>
> if (obj->last_read_req[ring] == req)
> i915_gem_object_retire__read(obj, ring);
> @@ -2415,17 +2415,15 @@ void i915_vma_move_to_active(struct i915_vma *vma,
> struct drm_i915_gem_request *req)
> {
> struct drm_i915_gem_object *obj = vma->obj;
> - struct intel_engine_cs *ring;
> -
> - ring = i915_gem_request_get_ring(req);
> + struct intel_engine_cs *engine = req->engine;;
>
> /* Add a reference if we're newly entering the active list. */
> if (obj->active == 0)
> drm_gem_object_reference(&obj->base);
> - obj->active |= intel_ring_flag(ring);
> + obj->active |= intel_ring_flag(engine);
>
> - list_move_tail(&obj->ring_list[ring->id], &ring->active_list);
> - i915_gem_request_assign(&obj->last_read_req[ring->id], req);
> + list_move_tail(&obj->ring_list[engine->id], &engine->active_list);
> + i915_gem_request_assign(&obj->last_read_req[engine->id], req);
>
> list_move_tail(&vma->mm_list, &vma->vm->active_list);
> }
> @@ -2434,7 +2432,7 @@ static void
> i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
> {
> RQ_BUG_ON(obj->last_write_req == NULL);
> - RQ_BUG_ON(!(obj->active & intel_ring_flag(obj->last_write_req->ring)));
> + RQ_BUG_ON(!(obj->active & intel_ring_flag(obj->last_write_req->engine)));
>
> i915_gem_request_assign(&obj->last_write_req, NULL);
> intel_fb_obj_flush(obj, true, ORIGIN_CS);
> @@ -2451,7 +2449,7 @@ i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
> list_del_init(&obj->ring_list[ring]);
> i915_gem_request_assign(&obj->last_read_req[ring], NULL);
>
> - if (obj->last_write_req && obj->last_write_req->ring->id == ring)
> + if (obj->last_write_req && obj->last_write_req->engine->id == ring)
> i915_gem_object_retire__write(obj);
>
> obj->active &= ~(1 << ring);
> @@ -2553,7 +2551,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
> struct drm_i915_gem_object *obj,
> bool flush_caches)
> {
> - struct intel_engine_cs *ring;
> + struct intel_engine_cs *engine;
> struct drm_i915_private *dev_priv;
> struct intel_ringbuffer *ringbuf;
> u32 request_start;
> @@ -2562,7 +2560,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
> if (WARN_ON(request == NULL))
> return;
>
> - ring = request->ring;
> + engine = request->engine;
> dev_priv = request->i915;
> ringbuf = request->ringbuf;
>
> @@ -2598,9 +2596,9 @@ void __i915_add_request(struct drm_i915_gem_request *request,
> request->postfix = intel_ring_get_tail(ringbuf);
>
> if (i915.enable_execlists)
> - ret = ring->emit_request(request);
> + ret = engine->emit_request(request);
> else {
> - ret = ring->add_request(request);
> + ret = engine->add_request(request);
>
> request->tail = intel_ring_get_tail(ringbuf);
> }
> @@ -2618,12 +2616,12 @@ void __i915_add_request(struct drm_i915_gem_request *request,
> request->batch_obj = obj;
>
> request->emitted_jiffies = jiffies;
> - ring->last_submitted_seqno = request->seqno;
> - list_add_tail(&request->list, &ring->request_list);
> + engine->last_submitted_seqno = request->seqno;
> + list_add_tail(&request->list, &engine->request_list);
>
> trace_i915_gem_request_add(request);
>
> - i915_queue_hangcheck(ring->dev);
> + i915_queue_hangcheck(engine->dev);
>
> queue_delayed_work(dev_priv->wq,
> &dev_priv->mm.retire_work,
> @@ -2690,7 +2688,7 @@ void i915_gem_request_free(struct kref *req_ref)
>
> if (ctx) {
> if (i915.enable_execlists) {
> - if (ctx != req->ring->default_context)
> + if (ctx != req->engine->default_context)
> intel_lr_context_unpin(req);
> }
>
> @@ -2700,11 +2698,11 @@ void i915_gem_request_free(struct kref *req_ref)
> kmem_cache_free(req->i915->requests, req);
> }
>
> -int i915_gem_request_alloc(struct intel_engine_cs *ring,
> +int i915_gem_request_alloc(struct intel_engine_cs *engine,
> struct intel_context *ctx,
> struct drm_i915_gem_request **req_out)
> {
> - struct drm_i915_private *dev_priv = to_i915(ring->dev);
> + struct drm_i915_private *dev_priv = to_i915(engine->dev);
> struct drm_i915_gem_request *req;
> int ret;
>
> @@ -2717,13 +2715,13 @@ int i915_gem_request_alloc(struct intel_engine_cs *ring,
> if (req == NULL)
> return -ENOMEM;
>
> - ret = i915_gem_get_seqno(ring->dev, &req->seqno);
> + ret = i915_gem_get_seqno(engine->dev, &req->seqno);
> if (ret)
> goto err;
>
> kref_init(&req->ref);
> req->i915 = dev_priv;
> - req->ring = ring;
> + req->engine = engine;
> req->ctx = ctx;
> i915_gem_context_reference(req->ctx);
>
> @@ -3137,7 +3135,7 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
> struct intel_engine_cs *from;
> int ret;
>
> - from = i915_gem_request_get_ring(from_req);
> + from = from_req->engine;
> if (to == from)
> return 0;
>
> @@ -4308,7 +4306,7 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
> BUILD_BUG_ON(I915_NUM_RINGS > 16);
> args->busy = obj->active << 16;
> if (obj->last_write_req)
> - args->busy |= obj->last_write_req->ring->id;
> + args->busy |= obj->last_write_req->engine->id;
>
> unref:
> drm_gem_object_unreference(&obj->base);
> @@ -4641,7 +4639,6 @@ err:
>
> int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> struct drm_i915_private *dev_priv = req->i915;
> u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
> u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
> @@ -4660,12 +4657,11 @@ int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
> * at initialization time.
> */
> for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
> - intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
> - intel_ring_emit(ring, reg_base + i);
> - intel_ring_emit(ring, remap_info[i/4]);
> + intel_ring_emit(req->ringbuf, MI_LOAD_REGISTER_IMM(1));
> + intel_ring_emit(req->ringbuf, reg_base + i);
> + intel_ring_emit(req->ringbuf, remap_info[i/4]);
> }
> -
> - intel_ring_advance(ring);
> + intel_ring_advance(req->ringbuf);
>
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index c3adc121aab4..047c2f94bd22 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -410,14 +410,14 @@ void i915_gem_context_fini(struct drm_device *dev)
>
> int i915_gem_context_enable(struct drm_i915_gem_request *req)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_engine_cs *engine = req->engine;
> int ret;
>
> if (i915.enable_execlists) {
> - if (ring->init_context == NULL)
> + if (engine->init_context == NULL)
> return 0;
>
> - ret = ring->init_context(req);
> + ret = engine->init_context(req);
> } else
> ret = i915_switch_context(req);
>
> @@ -494,7 +494,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
> * itlb_before_ctx_switch.
> */
> if (IS_GEN6(req->i915)) {
> - ret = req->ring->flush(req, I915_GEM_GPU_DOMAINS, 0);
> + ret = req->engine->flush(req, I915_GEM_GPU_DOMAINS, 0);
> if (ret)
> return ret;
> }
> @@ -522,7 +522,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
>
> intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
> for_each_ring(signaller, req->i915, i) {
> - if (signaller == req->ring)
> + if (signaller == req->engine)
> continue;
>
> intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
> @@ -547,7 +547,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
>
> intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
> for_each_ring(signaller, req->i915, i) {
> - if (signaller == req->ring)
> + if (signaller == req->engine)
> continue;
>
> intel_ring_emit(ring, RING_PSMI_CTL(signaller->mmio_base));
> @@ -618,19 +618,19 @@ needs_pd_load_post(struct intel_engine_cs *ring, struct intel_context *to,
> static int do_switch(struct drm_i915_gem_request *req)
> {
> struct intel_context *to = req->ctx;
> - struct intel_engine_cs *ring = req->ring;
> - struct intel_context *from = ring->last_context;
> + struct intel_engine_cs *engine = req->engine;
> + struct intel_context *from = engine->last_context;
> u32 hw_flags = 0;
> bool uninitialized = false;
> int ret, i;
>
> - if (should_skip_switch(ring, from, to))
> + if (should_skip_switch(engine, from, to))
> return 0;
>
> /* Trying to pin first makes error handling easier. */
> - if (ring->id == RCS) {
> + if (engine->id == RCS) {
> ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state,
> - get_context_alignment(ring->dev), 0);
> + get_context_alignment(engine->dev), 0);
> if (ret)
> return ret;
> }
> @@ -640,23 +640,23 @@ static int do_switch(struct drm_i915_gem_request *req)
> * evict_everything - as a last ditch gtt defrag effort that also
> * switches to the default context. Hence we need to reload from here.
> */
> - from = ring->last_context;
> + from = engine->last_context;
>
> - if (needs_pd_load_pre(ring, to)) {
> + if (needs_pd_load_pre(engine, to)) {
> /* Older GENs and non render rings still want the load first,
> * "PP_DCLV followed by PP_DIR_BASE register through Load
> * Register Immediate commands in Ring Buffer before submitting
> * a context."*/
> - trace_switch_mm(ring, to);
> + trace_switch_mm(engine, to);
> ret = to->ppgtt->switch_mm(to->ppgtt, req);
> if (ret)
> goto unpin_out;
>
> /* Doing a PD load always reloads the page dirs */
> - to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring);
> + to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(engine);
> }
>
> - if (ring->id != RCS) {
> + if (engine->id != RCS) {
> if (from)
> i915_gem_context_unreference(from);
> goto done;
> @@ -681,14 +681,14 @@ static int do_switch(struct drm_i915_gem_request *req)
> * space. This means we must enforce that a page table load
> * occur when this occurs. */
> } else if (to->ppgtt &&
> - (intel_ring_flag(ring) & to->ppgtt->pd_dirty_rings)) {
> + (intel_ring_flag(engine) & to->ppgtt->pd_dirty_rings)) {
> hw_flags |= MI_FORCE_RESTORE;
> - to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(ring);
> + to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(engine);
> }
>
> /* We should never emit switch_mm more than once */
> - WARN_ON(needs_pd_load_pre(ring, to) &&
> - needs_pd_load_post(ring, to, hw_flags));
> + WARN_ON(needs_pd_load_pre(engine, to) &&
> + needs_pd_load_post(engine, to, hw_flags));
>
> ret = mi_set_context(req, hw_flags);
> if (ret)
> @@ -697,8 +697,8 @@ static int do_switch(struct drm_i915_gem_request *req)
> /* GEN8 does *not* require an explicit reload if the PDPs have been
> * setup, and we do not wish to move them.
> */
> - if (needs_pd_load_post(ring, to, hw_flags)) {
> - trace_switch_mm(ring, to);
> + if (needs_pd_load_post(engine, to, hw_flags)) {
> + trace_switch_mm(engine, to);
> ret = to->ppgtt->switch_mm(to->ppgtt, req);
> /* The hardware context switch is emitted, but we haven't
> * actually changed the state - so it's probably safe to bail
> @@ -751,11 +751,11 @@ static int do_switch(struct drm_i915_gem_request *req)
>
> done:
> i915_gem_context_reference(to);
> - ring->last_context = to;
> + engine->last_context = to;
>
> if (uninitialized) {
> - if (ring->init_context) {
> - ret = ring->init_context(req);
> + if (engine->init_context) {
> + ret = engine->init_context(req);
> if (ret)
> DRM_ERROR("ring init context: %d\n", ret);
> }
> @@ -764,7 +764,7 @@ done:
> return 0;
>
> unpin_out:
> - if (ring->id == RCS)
> + if (engine->id == RCS)
> i915_gem_object_ggtt_unpin(to->legacy_hw_ctx.rcs_state);
> return ret;
> }
> @@ -784,17 +784,18 @@ unpin_out:
> */
> int i915_switch_context(struct drm_i915_gem_request *req)
> {
> - struct intel_engine_cs *ring = req->ring;
>
> WARN_ON(i915.enable_execlists);
> WARN_ON(!mutex_is_locked(&req->i915->dev->struct_mutex));
>
> if (req->ctx->legacy_hw_ctx.rcs_state == NULL) { /* We have the fake context */
> - if (req->ctx != ring->last_context) {
> + struct intel_engine_cs *engine = req->engine;
> +
> + if (req->ctx != engine->last_context) {
> i915_gem_context_reference(req->ctx);
> - if (ring->last_context)
> - i915_gem_context_unreference(ring->last_context);
> - ring->last_context = req->ctx;
> + if (engine->last_context)
> + i915_gem_context_unreference(engine->last_context);
> + engine->last_context = req->ctx;
> }
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 5f1b9b7df051..32c2d08bdd4c 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -922,7 +922,7 @@ static int
> i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
> struct list_head *vmas)
> {
> - const unsigned other_rings = ~intel_ring_flag(req->ring);
> + const unsigned other_rings = ~intel_ring_flag(req->engine);
> struct i915_vma *vma;
> uint32_t flush_domains = 0;
> bool flush_chipset = false;
> @@ -932,7 +932,7 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
> struct drm_i915_gem_object *obj = vma->obj;
>
> if (obj->active & other_rings) {
> - ret = i915_gem_object_sync(obj, req->ring, &req);
> + ret = i915_gem_object_sync(obj, req->engine, &req);
> if (ret)
> return ret;
> }
> @@ -944,7 +944,7 @@ i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
> }
>
> if (flush_chipset)
> - i915_gem_chipset_flush(req->ring->dev);
> + i915_gem_chipset_flush(req->engine->dev);
>
> if (flush_domains & I915_GEM_DOMAIN_GTT)
> wmb();
> @@ -1118,7 +1118,7 @@ i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
> struct intel_ringbuffer *ring = req->ringbuf;
> int ret, i;
>
> - if (!IS_GEN7(req->i915) || req->ring->id != RCS) {
> + if (!IS_GEN7(req->i915) || req->engine->id != RCS) {
> DRM_DEBUG("sol reset is gen7/rcs only\n");
> return -EINVAL;
> }
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 4608884adfc8..c222456961fb 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -661,10 +661,10 @@ static int gen8_write_pdp(struct drm_i915_gem_request *req,
> return ret;
>
> intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
> - intel_ring_emit(ring, GEN8_RING_PDP_UDW(req->ring, entry));
> + intel_ring_emit(ring, GEN8_RING_PDP_UDW(req->engine, entry));
> intel_ring_emit(ring, upper_32_bits(addr));
> intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
> - intel_ring_emit(ring, GEN8_RING_PDP_LDW(req->ring, entry));
> + intel_ring_emit(ring, GEN8_RING_PDP_LDW(req->engine, entry));
> intel_ring_emit(ring, lower_32_bits(addr));
> intel_ring_advance(ring);
>
> @@ -1592,7 +1592,9 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
> int ret;
>
> /* NB: TLBs must be flushed and invalidated before a switch */
> - ret = req->ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> + ret = req->engine->flush(req,
> + I915_GEM_GPU_DOMAINS,
> + I915_GEM_GPU_DOMAINS);
> if (ret)
> return ret;
>
> @@ -1601,9 +1603,9 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
> return ret;
>
> intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
> - intel_ring_emit(ring, RING_PP_DIR_DCLV(req->ring));
> + intel_ring_emit(ring, RING_PP_DIR_DCLV(req->engine));
> intel_ring_emit(ring, PP_DIR_DCLV_2G);
> - intel_ring_emit(ring, RING_PP_DIR_BASE(req->ring));
> + intel_ring_emit(ring, RING_PP_DIR_BASE(req->engine));
> intel_ring_emit(ring, get_pd_offset(ppgtt));
> intel_ring_emit(ring, MI_NOOP);
> intel_ring_advance(ring);
> @@ -1614,11 +1616,10 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
> static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
> struct drm_i915_gem_request *req)
> {
> - struct intel_engine_cs *ring = req->ring;
> - struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
> + struct drm_i915_private *dev_priv = req->i915;
>
> - I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
> - I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
> + I915_WRITE(RING_PP_DIR_DCLV(req->engine), PP_DIR_DCLV_2G);
> + I915_WRITE(RING_PP_DIR_BASE(req->engine), get_pd_offset(ppgtt));
> return 0;
> }
>
> @@ -1629,7 +1630,9 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
> int ret;
>
> /* NB: TLBs must be flushed and invalidated before a switch */
> - ret = req->ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> + ret = req->engine->flush(req,
> + I915_GEM_GPU_DOMAINS,
> + I915_GEM_GPU_DOMAINS);
> if (ret)
> return ret;
>
> @@ -1638,16 +1641,18 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
> return ret;
>
> intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
> - intel_ring_emit(ring, RING_PP_DIR_DCLV(req->ring));
> + intel_ring_emit(ring, RING_PP_DIR_DCLV(req->engine));
> intel_ring_emit(ring, PP_DIR_DCLV_2G);
> - intel_ring_emit(ring, RING_PP_DIR_BASE(req->ring));
> + intel_ring_emit(ring, RING_PP_DIR_BASE(req->engine));
> intel_ring_emit(ring, get_pd_offset(ppgtt));
> intel_ring_emit(ring, MI_NOOP);
> intel_ring_advance(ring);
>
> /* XXX: RCS is the only one to auto invalidate the TLBs? */
> - if (req->ring->id != RCS) {
> - ret = req->ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
> + if (req->engine->id != RCS) {
> + ret = req->engine->flush(req,
> + I915_GEM_GPU_DOMAINS,
> + I915_GEM_GPU_DOMAINS);
> if (ret)
> return ret;
> }
> @@ -1658,15 +1663,12 @@ static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
> static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
> struct drm_i915_gem_request *req)
> {
> - struct intel_engine_cs *ring = req->ring;
> - struct drm_device *dev = ppgtt->base.dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> -
> + struct drm_i915_private *dev_priv = req->i915;
>
> - I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
> - I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
> + I915_WRITE(RING_PP_DIR_DCLV(req->engine), PP_DIR_DCLV_2G);
> + I915_WRITE(RING_PP_DIR_BASE(req->engine), get_pd_offset(ppgtt));
>
> - POSTING_READ(RING_PP_DIR_DCLV(ring));
> + POSTING_READ(RING_PP_DIR_DCLV(req->engine));
>
> return 0;
> }
> @@ -2101,8 +2103,7 @@ int i915_ppgtt_init_hw(struct drm_device *dev)
>
> int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
> {
> - struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
> - struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
> + struct i915_hw_ppgtt *ppgtt = req->i915->mm.aliasing_ppgtt;
> int ret;
>
> if (i915.enable_execlists)
> @@ -2115,7 +2116,7 @@ int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
> if (ret)
> return ret;
>
> - ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring);
> + ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->engine);
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
> index 5026a6267a88..f11e8685b1af 100644
> --- a/drivers/gpu/drm/i915/i915_gem_render_state.c
> +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
> @@ -198,25 +198,25 @@ int i915_gem_render_state_init(struct drm_i915_gem_request *req)
> struct render_state so;
> int ret;
>
> - ret = i915_gem_render_state_prepare(req->ring, &so);
> + ret = i915_gem_render_state_prepare(req->engine, &so);
> if (ret)
> return ret;
>
> if (so.rodata == NULL)
> return 0;
>
> - ret = req->ring->dispatch_execbuffer(req, so.ggtt_offset,
> - so.rodata->batch_items * 4,
> - I915_DISPATCH_SECURE);
> + ret = req->engine->dispatch_execbuffer(req, so.ggtt_offset,
> + so.rodata->batch_items * 4,
> + I915_DISPATCH_SECURE);
> if (ret)
> goto out;
>
> if (so.aux_batch_size > 8) {
> - ret = req->ring->dispatch_execbuffer(req,
> - (so.ggtt_offset +
> - so.aux_batch_offset),
> - so.aux_batch_size,
> - I915_DISPATCH_SECURE);
> + ret = req->engine->dispatch_execbuffer(req,
> + (so.ggtt_offset +
> + so.aux_batch_offset),
> + so.aux_batch_size,
> + I915_DISPATCH_SECURE);
> if (ret)
> goto out;
> }
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index d8e035e126d7..974e3481e449 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -709,8 +709,7 @@ static void capture_bo(struct drm_i915_error_buffer *err,
> err->dirty = obj->dirty;
> err->purgeable = obj->madv != I915_MADV_WILLNEED;
> err->userptr = obj->userptr.mm != NULL;
> - err->ring = obj->last_write_req ?
> - i915_gem_request_get_ring(obj->last_write_req)->id : -1;
> + err->ring = obj->last_write_req ? obj->last_write_req->engine->id : -1;
> err->cache_level = obj->cache_level;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
> index ad64d6ba13a2..533b6a87fd1d 100644
> --- a/drivers/gpu/drm/i915/i915_trace.h
> +++ b/drivers/gpu/drm/i915/i915_trace.h
> @@ -498,7 +498,7 @@ TRACE_EVENT(i915_gem_ring_sync_to,
> TP_fast_assign(
> __entry->dev = from->dev->primary->index;
> __entry->sync_from = from->id;
> - __entry->sync_to = to_req->ring->id;
> + __entry->sync_to = to_req->engine->id;
> __entry->seqno = i915_gem_request_get_seqno(req);
> ),
>
> @@ -520,13 +520,11 @@ TRACE_EVENT(i915_gem_ring_dispatch,
> ),
>
> TP_fast_assign(
> - struct intel_engine_cs *ring =
> - i915_gem_request_get_ring(req);
> - __entry->dev = ring->dev->primary->index;
> - __entry->ring = ring->id;
> - __entry->seqno = i915_gem_request_get_seqno(req);
> + __entry->dev = req->i915->dev->primary->index;
> + __entry->ring = req->engine->id;
> + __entry->seqno = req->seqno;
> __entry->flags = flags;
> - i915_trace_irq_get(ring, req);
> + i915_trace_irq_get(req->engine, req);
> ),
>
> TP_printk("dev=%u, ring=%u, seqno=%u, flags=%x",
> @@ -545,8 +543,8 @@ TRACE_EVENT(i915_gem_ring_flush,
> ),
>
> TP_fast_assign(
> - __entry->dev = req->ring->dev->primary->index;
> - __entry->ring = req->ring->id;
> + __entry->dev = req->engine->dev->primary->index;
> + __entry->ring = req->engine->id;
> __entry->invalidate = invalidate;
> __entry->flush = flush;
> ),
> @@ -567,11 +565,9 @@ DECLARE_EVENT_CLASS(i915_gem_request,
> ),
>
> TP_fast_assign(
> - struct intel_engine_cs *ring =
> - i915_gem_request_get_ring(req);
> - __entry->dev = ring->dev->primary->index;
> - __entry->ring = ring->id;
> - __entry->seqno = i915_gem_request_get_seqno(req);
> + __entry->dev = req->i915->dev->primary->index;
> + __entry->ring = req->engine->id;
> + __entry->seqno = req->seqno;
> ),
>
> TP_printk("dev=%u, ring=%u, seqno=%u",
> @@ -631,13 +627,11 @@ TRACE_EVENT(i915_gem_request_wait_begin,
> * less desirable.
> */
> TP_fast_assign(
> - struct intel_engine_cs *ring =
> - i915_gem_request_get_ring(req);
> - __entry->dev = ring->dev->primary->index;
> - __entry->ring = ring->id;
> - __entry->seqno = i915_gem_request_get_seqno(req);
> + __entry->dev = req->i915->dev->primary->index;
> + __entry->ring = req->engine->id;
> + __entry->seqno = req->seqno;
> __entry->blocking =
> - mutex_is_locked(&ring->dev->struct_mutex);
> + mutex_is_locked(&req->i915->dev->struct_mutex);
> ),
>
> TP_printk("dev=%u, ring=%u, seqno=%u, blocking=%s",
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index f6dae2cfd9c9..2447f1a36fb0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10987,7 +10987,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
> }
>
> len = 4;
> - if (req->ring->id == RCS) {
> + if (req->engine->id == RCS) {
> len += 6;
> /*
> * On Gen 8, SRM is now taking an extra dword to accommodate
> @@ -11025,7 +11025,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
> * for the RCS also doesn't appear to drop events. Setting the DERRMR
> * to zero does lead to lockups within MI_DISPLAY_FLIP.
> */
> - if (req->ring->id == RCS) {
> + if (req->engine->id == RCS) {
> intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
> intel_ring_emit(ring, DERRMR);
> intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
> @@ -11038,7 +11038,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
> intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
> MI_SRM_LRM_GLOBAL_GTT);
> intel_ring_emit(ring, DERRMR);
> - intel_ring_emit(ring, req->ring->scratch.gtt_offset + 256);
> + intel_ring_emit(ring, req->engine->scratch.gtt_offset + 256);
> if (IS_GEN8(req->i915)) {
> intel_ring_emit(ring, 0);
> intel_ring_emit(ring, MI_NOOP);
> @@ -11078,7 +11078,7 @@ static bool use_mmio_flip(struct intel_engine_cs *ring,
> else if (i915.enable_execlists)
> return true;
> else
> - return ring != i915_gem_request_get_ring(obj->last_write_req);
> + return ring != i915_gem_request_get_engine(obj->last_write_req);
> }
>
> static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
> @@ -11395,7 +11395,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
> } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
> ring = &dev_priv->ring[BCS];
> } else if (INTEL_INFO(dev)->gen >= 7) {
> - ring = i915_gem_request_get_ring(obj->last_write_req);
> + ring = i915_gem_request_get_engine(obj->last_write_req);
> if (ring == NULL || ring->id != RCS)
> ring = &dev_priv->ring[BCS];
> } else {
> @@ -11411,7 +11411,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
> */
> ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
> crtc->primary->state,
> - mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
> + mmio_flip ? i915_gem_request_get_engine(obj->last_write_req) : ring, &request);
> if (ret)
> goto cleanup_pending;
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 2458804c521d..1502e53d2ad6 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -272,17 +272,16 @@ u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
>
> static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_request *rq)
> {
> - struct intel_engine_cs *ring = rq->ring;
> - struct drm_device *dev = ring->dev;
> - struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
> - uint64_t desc;
> + int ring = rq->engine->id;
> + struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring].state;
> uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj);
> + uint64_t desc;
>
> WARN_ON(lrca & 0xFFFFFFFF00000FFFULL);
>
> desc = GEN8_CTX_VALID;
> - desc |= GEN8_CTX_ADDRESSING_MODE(dev) << GEN8_CTX_ADDRESSING_MODE_SHIFT;
> - if (IS_GEN8(ctx_obj->base.dev))
> + desc |= GEN8_CTX_ADDRESSING_MODE(rq->i915) << GEN8_CTX_ADDRESSING_MODE_SHIFT;
> + if (IS_GEN8(rq->i915))
> desc |= GEN8_CTX_L3LLC_COHERENT;
> desc |= GEN8_CTX_PRIVILEGE;
> desc |= lrca;
> @@ -293,10 +292,10 @@ static uint64_t execlists_ctx_descriptor(struct drm_i915_gem_request *rq)
> /* desc |= GEN8_CTX_FORCE_RESTORE; */
>
> /* WaEnableForceRestoreInCtxtDescForVCS:skl */
> - if (IS_GEN9(dev) &&
> - INTEL_REVID(dev) <= SKL_REVID_B0 &&
> - (ring->id == BCS || ring->id == VCS ||
> - ring->id == VECS || ring->id == VCS2))
> + if (IS_GEN9(rq->i915) &&
> + INTEL_REVID(rq->i915) <= SKL_REVID_B0 &&
> + (ring == BCS || ring == VCS ||
> + ring == VECS || ring == VCS2))
> desc |= GEN8_CTX_FORCE_RESTORE;
>
> return desc;
> @@ -306,7 +305,7 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
> struct drm_i915_gem_request *rq1)
> {
>
> - struct intel_engine_cs *ring = rq0->ring;
> + struct intel_engine_cs *engine = rq0->engine;
> struct drm_i915_private *dev_priv = rq0->i915;
> uint64_t desc[2];
>
> @@ -323,24 +322,23 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
> /* You must always write both descriptors in the order below. */
> spin_lock(&dev_priv->uncore.lock);
> intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL);
> - I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[1]));
> - I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[1]));
> + I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[1]));
> + I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[1]));
>
> - I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[0]));
> + I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[0]));
> /* The context is automatically loaded after the following */
> - I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[0]));
> + I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[0]));
>
> /* ELSP is a wo register, use another nearby reg for posting */
> - POSTING_READ_FW(RING_EXECLIST_STATUS(ring));
> + POSTING_READ_FW(RING_EXECLIST_STATUS(engine));
> intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL);
> spin_unlock(&dev_priv->uncore.lock);
> }
>
> static int execlists_update_context(struct drm_i915_gem_request *rq)
> {
> - struct intel_engine_cs *ring = rq->ring;
> struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
> - struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
> + struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[rq->engine->id].state;
> struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
> struct page *page;
> uint32_t *reg_state;
> @@ -355,7 +353,7 @@ static int execlists_update_context(struct drm_i915_gem_request *rq)
> reg_state[CTX_RING_TAIL+1] = rq->tail;
> reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj);
>
> - if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
> + if (ppgtt && !USES_FULL_48BIT_PPGTT(rq->i915)) {
> /* True 32b PPGTT with dynamic page allocation: update PDP
> * registers and point the unallocated PDPs to scratch page.
> * PML4 is allocated during ppgtt init, so this is not needed
> @@ -538,27 +536,27 @@ void intel_lrc_irq_handler(struct intel_engine_cs *ring)
>
> static int execlists_context_queue(struct drm_i915_gem_request *request)
> {
> - struct intel_engine_cs *ring = request->ring;
> + struct intel_engine_cs *engine = request->engine;
> struct drm_i915_gem_request *cursor;
> int num_elements = 0;
>
> - if (request->ctx != ring->default_context)
> + if (request->ctx != engine->default_context)
> intel_lr_context_pin(request);
>
> i915_gem_request_reference(request);
>
> request->tail = request->ringbuf->tail;
>
> - spin_lock_irq(&ring->execlist_lock);
> + spin_lock_irq(&engine->execlist_lock);
>
> - list_for_each_entry(cursor, &ring->execlist_queue, execlist_link)
> + list_for_each_entry(cursor, &engine->execlist_queue, execlist_link)
> if (++num_elements > 2)
> break;
>
> if (num_elements > 2) {
> struct drm_i915_gem_request *tail_req;
>
> - tail_req = list_last_entry(&ring->execlist_queue,
> + tail_req = list_last_entry(&engine->execlist_queue,
> struct drm_i915_gem_request,
> execlist_link);
>
> @@ -567,41 +565,41 @@ static int execlists_context_queue(struct drm_i915_gem_request *request)
> "More than 2 already-submitted reqs queued\n");
> list_del(&tail_req->execlist_link);
> list_add_tail(&tail_req->execlist_link,
> - &ring->execlist_retired_req_list);
> + &engine->execlist_retired_req_list);
> }
> }
>
> - list_add_tail(&request->execlist_link, &ring->execlist_queue);
> + list_add_tail(&request->execlist_link, &engine->execlist_queue);
> if (num_elements == 0)
> - execlists_context_unqueue(ring);
> + execlists_context_unqueue(engine);
>
> - spin_unlock_irq(&ring->execlist_lock);
> + spin_unlock_irq(&engine->execlist_lock);
>
> return 0;
> }
>
> static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_engine_cs *engine = req->engine;
> uint32_t flush_domains;
> int ret;
>
> flush_domains = 0;
> - if (ring->gpu_caches_dirty)
> + if (engine->gpu_caches_dirty)
> flush_domains = I915_GEM_GPU_DOMAINS;
>
> - ret = ring->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
> + ret = engine->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
> if (ret)
> return ret;
>
> - ring->gpu_caches_dirty = false;
> + engine->gpu_caches_dirty = false;
> return 0;
> }
>
> static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
> struct list_head *vmas)
> {
> - const unsigned other_rings = ~intel_ring_flag(req->ring);
> + const unsigned other_rings = ~intel_ring_flag(req->engine);
> struct i915_vma *vma;
> uint32_t flush_domains = 0;
> bool flush_chipset = false;
> @@ -611,7 +609,7 @@ static int execlists_move_to_gpu(struct drm_i915_gem_request *req,
> struct drm_i915_gem_object *obj = vma->obj;
>
> if (obj->active & other_rings) {
> - ret = i915_gem_object_sync(obj, req->ring, &req);
> + ret = i915_gem_object_sync(obj, req->engine, &req);
> if (ret)
> return ret;
> }
> @@ -635,9 +633,9 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request
> {
> int ret;
>
> - request->ringbuf = request->ctx->engine[request->ring->id].ringbuf;
> + request->ringbuf = request->ctx->engine[request->engine->id].ringbuf;
>
> - if (request->ctx != request->ring->default_context) {
> + if (request->ctx != request->engine->default_context) {
> ret = intel_lr_context_pin(request);
> if (ret)
> return ret;
> @@ -660,7 +658,7 @@ intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
> {
> intel_ring_advance(request->ringbuf);
>
> - if (intel_ring_stopped(request->ring))
> + if (intel_ring_stopped(request->engine))
> return;
>
> execlists_context_queue(request);
> @@ -811,35 +809,35 @@ void intel_logical_ring_stop(struct intel_engine_cs *ring)
>
> int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_engine_cs *engine = req->engine;
> int ret;
>
> - if (!ring->gpu_caches_dirty)
> + if (!engine->gpu_caches_dirty)
> return 0;
>
> - ret = ring->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
> + ret = engine->emit_flush(req, 0, I915_GEM_GPU_DOMAINS);
> if (ret)
> return ret;
>
> - ring->gpu_caches_dirty = false;
> + engine->gpu_caches_dirty = false;
> return 0;
> }
>
> static int intel_lr_context_pin(struct drm_i915_gem_request *rq)
> {
> - struct intel_engine_cs *ring = rq->ring;
> - struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
> + int engine = rq->engine->id;
> + struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[engine].state;
> struct intel_ringbuffer *ringbuf = rq->ringbuf;
> int ret = 0;
>
> - WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
> - if (rq->ctx->engine[ring->id].pin_count++ == 0) {
> + WARN_ON(!mutex_is_locked(&rq->i915->dev->struct_mutex));
> + if (rq->ctx->engine[engine].pin_count++ == 0) {
> ret = i915_gem_obj_ggtt_pin(ctx_obj,
> GEN8_LR_CONTEXT_ALIGN, 0);
> if (ret)
> goto reset_pin_count;
>
> - ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf);
> + ret = intel_pin_and_map_ringbuffer_obj(rq->i915->dev, ringbuf);
> if (ret)
> goto unpin_ctx_obj;
>
> @@ -851,20 +849,20 @@ static int intel_lr_context_pin(struct drm_i915_gem_request *rq)
> unpin_ctx_obj:
> i915_gem_object_ggtt_unpin(ctx_obj);
> reset_pin_count:
> - rq->ctx->engine[ring->id].pin_count = 0;
> + rq->ctx->engine[engine].pin_count = 0;
>
> return ret;
> }
>
> void intel_lr_context_unpin(struct drm_i915_gem_request *rq)
> {
> - struct intel_engine_cs *ring = rq->ring;
> - struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state;
> + int engine = rq->engine->id;
> + struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[engine].state;
> struct intel_ringbuffer *ringbuf = rq->ringbuf;
>
> if (ctx_obj) {
> - WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex));
> - if (--rq->ctx->engine[ring->id].pin_count == 0) {
> + WARN_ON(!mutex_is_locked(&rq->i915->dev->struct_mutex));
> + if (--rq->ctx->engine[engine].pin_count == 0) {
> intel_unpin_ringbuffer_obj(ringbuf);
> i915_gem_object_ggtt_unpin(ctx_obj);
> }
> @@ -874,7 +872,7 @@ void intel_lr_context_unpin(struct drm_i915_gem_request *rq)
> static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
> {
> int ret, i;
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_engine_cs *engine = req->engine;
> struct intel_ringbuffer *ringbuf = req->ringbuf;
> struct drm_i915_private *dev_priv = req->i915;
> struct i915_workarounds *w = &dev_priv->workarounds;
> @@ -882,7 +880,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
> if (WARN_ON_ONCE(w->count == 0))
> return 0;
>
> - ring->gpu_caches_dirty = true;
> + engine->gpu_caches_dirty = true;
> ret = logical_ring_flush_all_caches(req);
> if (ret)
> return ret;
> @@ -900,7 +898,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
>
> intel_ring_advance(ringbuf);
>
> - ring->gpu_caches_dirty = true;
> + engine->gpu_caches_dirty = true;
> ret = logical_ring_flush_all_caches(req);
> if (ret)
> return ret;
> @@ -1319,7 +1317,7 @@ static int gen9_init_render_ring(struct intel_engine_cs *ring)
> static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
> {
> struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_engine_cs *engine = req->engine;
> struct intel_ringbuffer *ringbuf = req->ringbuf;
> const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
> int i, ret;
> @@ -1332,9 +1330,9 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
> for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
> const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
>
> - intel_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i));
> + intel_ring_emit(ringbuf, GEN8_RING_PDP_UDW(engine, i));
> intel_ring_emit(ringbuf, upper_32_bits(pd_daddr));
> - intel_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i));
> + intel_ring_emit(ringbuf, GEN8_RING_PDP_LDW(engine, i));
> intel_ring_emit(ringbuf, lower_32_bits(pd_daddr));
> }
>
> @@ -1358,14 +1356,14 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
> * not idle). PML4 is allocated during ppgtt init so this is
> * not needed in 48-bit.*/
> if (req->ctx->ppgtt &&
> - (intel_ring_flag(req->ring) & req->ctx->ppgtt->pd_dirty_rings)) {
> + (intel_ring_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
> if (!USES_FULL_48BIT_PPGTT(req->i915)) {
> ret = intel_logical_ring_emit_pdps(req);
> if (ret)
> return ret;
> }
>
> - req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring);
> + req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->engine);
> }
>
> ret = intel_ring_begin(req, 4);
> @@ -1575,21 +1573,21 @@ static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
> struct render_state so;
> int ret;
>
> - ret = i915_gem_render_state_prepare(req->ring, &so);
> + ret = i915_gem_render_state_prepare(req->engine, &so);
> if (ret)
> return ret;
>
> if (so.rodata == NULL)
> return 0;
>
> - ret = req->ring->emit_bb_start(req, so.ggtt_offset,
> - I915_DISPATCH_SECURE);
> + ret = req->engine->emit_bb_start(req, so.ggtt_offset,
> + I915_DISPATCH_SECURE);
> if (ret)
> goto out;
>
> - ret = req->ring->emit_bb_start(req,
> - (so.ggtt_offset + so.aux_batch_offset),
> - I915_DISPATCH_SECURE);
> + ret = req->engine->emit_bb_start(req,
> + (so.ggtt_offset + so.aux_batch_offset),
> + I915_DISPATCH_SECURE);
> if (ret)
> goto out;
>
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index ac0a982bbf55..d79c9c0bbffb 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -138,21 +138,21 @@ static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
> *
> * Return: true if there are applicable MOCS settings for the device.
> */
> -static bool get_mocs_settings(struct drm_device *dev,
> +static bool get_mocs_settings(struct drm_i915_private *dev_priv,
> struct drm_i915_mocs_table *table)
> {
> bool result = false;
>
> - if (IS_SKYLAKE(dev)) {
> + if (IS_SKYLAKE(dev_priv)) {
> table->size = ARRAY_SIZE(skylake_mocs_table);
> table->table = skylake_mocs_table;
> result = true;
> - } else if (IS_BROXTON(dev)) {
> + } else if (IS_BROXTON(dev_priv)) {
> table->size = ARRAY_SIZE(broxton_mocs_table);
> table->table = broxton_mocs_table;
> result = true;
> } else {
> - WARN_ONCE(INTEL_INFO(dev)->gen >= 9,
> + WARN_ONCE(INTEL_INFO(dev_priv)->gen >= 9,
> "Platform that should have a MOCS table does not.\n");
> }
>
> @@ -297,7 +297,7 @@ int intel_rcs_context_init_mocs(struct drm_i915_gem_request *req)
> struct drm_i915_mocs_table t;
> int ret;
>
> - if (get_mocs_settings(req->ring->dev, &t)) {
> + if (get_mocs_settings(req->i915, &t)) {
> /* Program the control registers */
> ret = emit_mocs_control_table(req, &t, GEN9_GFX_MOCS_0);
> if (ret)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 9821c2a8074a..cc060588a287 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -216,7 +216,7 @@ static int
> intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
> {
> struct intel_ringbuffer *ring = req->ringbuf;
> - u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> + u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> int ret;
>
> ret = intel_ring_begin(req, 6);
> @@ -253,7 +253,7 @@ gen6_render_ring_flush(struct drm_i915_gem_request *req,
> {
> struct intel_ringbuffer *ring = req->ringbuf;
> u32 flags = 0;
> - u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> + u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> int ret;
>
> /* Force SNB workarounds for PIPE_CONTROL flushes */
> @@ -326,7 +326,7 @@ gen7_render_ring_flush(struct drm_i915_gem_request *req,
> {
> struct intel_ringbuffer *ring = req->ringbuf;
> u32 flags = 0;
> - u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> + u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> int ret;
>
> /*
> @@ -410,7 +410,7 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
> u32 invalidate_domains, u32 flush_domains)
> {
> u32 flags = 0;
> - u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> + u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> int ret;
>
> flags |= PIPE_CONTROL_CS_STALL;
> @@ -720,7 +720,7 @@ static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
> if (WARN_ON_ONCE(w->count == 0))
> return 0;
>
> - req->ring->gpu_caches_dirty = true;
> + req->engine->gpu_caches_dirty = true;
> ret = intel_ring_flush_all_caches(req);
> if (ret)
> return ret;
> @@ -738,7 +738,7 @@ static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
>
> intel_ring_advance(ring);
>
> - req->ring->gpu_caches_dirty = true;
> + req->engine->gpu_caches_dirty = true;
> ret = intel_ring_flush_all_caches(req);
> if (ret)
> return ret;
> @@ -1199,7 +1199,7 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
>
> for_each_ring(waiter, dev_priv, i) {
> u32 seqno;
> - u64 gtt_offset = signaller_req->ring->semaphore.signal_ggtt[i];
> + u64 gtt_offset = signaller_req->engine->semaphore.signal_ggtt[i];
> if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
> continue;
>
> @@ -1239,7 +1239,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
>
> for_each_ring(waiter, dev_priv, i) {
> u32 seqno;
> - u64 gtt_offset = signaller_req->ring->semaphore.signal_ggtt[i];
> + u64 gtt_offset = signaller_req->engine->semaphore.signal_ggtt[i];
> if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
> continue;
>
> @@ -1276,7 +1276,7 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
> return ret;
>
> for_each_ring(useless, dev_priv, i) {
> - u32 mbox_reg = signaller_req->ring->semaphore.mbox.signal[i];
> + u32 mbox_reg = signaller_req->engine->semaphore.mbox.signal[i];
> if (mbox_reg != GEN6_NOSYNC) {
> u32 seqno = i915_gem_request_get_seqno(signaller_req);
> intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
> @@ -1306,8 +1306,8 @@ gen6_add_request(struct drm_i915_gem_request *req)
> struct intel_ringbuffer *ring = req->ringbuf;
> int ret;
>
> - if (req->ring->semaphore.signal)
> - ret = req->ring->semaphore.signal(req, 4);
> + if (req->engine->semaphore.signal)
> + ret = req->engine->semaphore.signal(req, 4);
> else
> ret = intel_ring_begin(req, 4);
>
> @@ -1318,7 +1318,7 @@ gen6_add_request(struct drm_i915_gem_request *req)
> intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
> intel_ring_emit(ring, i915_gem_request_get_seqno(req));
> intel_ring_emit(ring, MI_USER_INTERRUPT);
> - __intel_ring_advance(req->ring);
> + __intel_ring_advance(req->engine);
>
> return 0;
> }
> @@ -1356,10 +1356,10 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
> MI_SEMAPHORE_SAD_GTE_SDD);
> intel_ring_emit(waiter, seqno);
> intel_ring_emit(waiter,
> - lower_32_bits(GEN8_WAIT_OFFSET(waiter_req->ring,
> + lower_32_bits(GEN8_WAIT_OFFSET(waiter_req->engine,
> signaller->id)));
> intel_ring_emit(waiter,
> - upper_32_bits(GEN8_WAIT_OFFSET(waiter_req->ring,
> + upper_32_bits(GEN8_WAIT_OFFSET(waiter_req->engine,
> signaller->id)));
> intel_ring_advance(waiter);
> return 0;
> @@ -1374,7 +1374,7 @@ gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
> u32 dw1 = MI_SEMAPHORE_MBOX |
> MI_SEMAPHORE_COMPARE |
> MI_SEMAPHORE_REGISTER;
> - u32 wait_mbox = signaller->semaphore.mbox.wait[waiter_req->ring->id];
> + u32 wait_mbox = signaller->semaphore.mbox.wait[waiter_req->engine->id];
> int ret;
>
> /* Throughout all of the GEM code, seqno passed implies our current
> @@ -1419,7 +1419,7 @@ static int
> pc_render_add_request(struct drm_i915_gem_request *req)
> {
> struct intel_ringbuffer *ring = req->ringbuf;
> - u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> + u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> int ret;
>
> /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
> @@ -1437,7 +1437,7 @@ pc_render_add_request(struct drm_i915_gem_request *req)
> intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
> PIPE_CONTROL_WRITE_FLUSH |
> PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
> - intel_ring_emit(ring, req->ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
> + intel_ring_emit(ring, req->engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
> intel_ring_emit(ring, i915_gem_request_get_seqno(req));
> intel_ring_emit(ring, 0);
> PIPE_CONTROL_FLUSH(ring, scratch_addr);
> @@ -1456,10 +1456,10 @@ pc_render_add_request(struct drm_i915_gem_request *req)
> PIPE_CONTROL_WRITE_FLUSH |
> PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
> PIPE_CONTROL_NOTIFY);
> - intel_ring_emit(ring, req->ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
> + intel_ring_emit(ring, req->engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
> intel_ring_emit(ring, i915_gem_request_get_seqno(req));
> intel_ring_emit(ring, 0);
> - __intel_ring_advance(req->ring);
> + __intel_ring_advance(req->engine);
>
> return 0;
> }
> @@ -1639,7 +1639,7 @@ i9xx_add_request(struct drm_i915_gem_request *req)
> intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
> intel_ring_emit(ring, i915_gem_request_get_seqno(req));
> intel_ring_emit(ring, MI_USER_INTERRUPT);
> - __intel_ring_advance(req->ring);
> + __intel_ring_advance(req->engine);
>
> return 0;
> }
> @@ -1801,7 +1801,7 @@ i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
> unsigned dispatch_flags)
> {
> struct intel_ringbuffer *ring = req->ringbuf;
> - u32 cs_offset = req->ring->scratch.gtt_offset;
> + u32 cs_offset = req->engine->scratch.gtt_offset;
> int ret;
>
> ret = intel_ring_begin(req, 6);
> @@ -2164,7 +2164,7 @@ int intel_ring_idle(struct intel_engine_cs *ring)
>
> int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
> {
> - request->ringbuf = request->ring->buffer;
> + request->ringbuf = request->engine->buffer;
> return 0;
> }
>
> @@ -2218,7 +2218,7 @@ void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
> static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> {
> struct intel_ringbuffer *ringbuf = req->ringbuf;
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_engine_cs *engine = req->engine;
> struct drm_i915_gem_request *target;
> unsigned space;
> int ret;
> @@ -2229,7 +2229,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> /* The whole point of reserving space is to not wait! */
> WARN_ON(ringbuf->reserved_in_use);
>
> - list_for_each_entry(target, &ring->request_list, list) {
> + list_for_each_entry(target, &engine->request_list, list) {
> /*
> * The request queue is per-engine, so can contain requests
> * from multiple ringbuffers. Here, we must ignore any that
> @@ -2245,7 +2245,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> break;
> }
>
> - if (WARN_ON(&target->list == &ring->request_list))
> + if (WARN_ON(&target->list == &engine->request_list))
> return -ENOSPC;
>
> ret = i915_wait_request(target);
> @@ -2931,40 +2931,40 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
> int
> intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_engine_cs *engine = req->engine;
> int ret;
>
> - if (!ring->gpu_caches_dirty)
> + if (!engine->gpu_caches_dirty)
> return 0;
>
> - ret = ring->flush(req, 0, I915_GEM_GPU_DOMAINS);
> + ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
> if (ret)
> return ret;
>
> trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
>
> - ring->gpu_caches_dirty = false;
> + engine->gpu_caches_dirty = false;
> return 0;
> }
>
> int
> intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
> {
> - struct intel_engine_cs *ring = req->ring;
> + struct intel_engine_cs *engine = req->engine;
> uint32_t flush_domains;
> int ret;
>
> flush_domains = 0;
> - if (ring->gpu_caches_dirty)
> + if (engine->gpu_caches_dirty)
> flush_domains = I915_GEM_GPU_DOMAINS;
>
> - ret = ring->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
> + ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
> if (ret)
> return ret;
>
> trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
>
> - ring->gpu_caches_dirty = false;
> + engine->gpu_caches_dirty = false;
> return 0;
> }
>
> --
> 2.6.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 07/12] drm/i915: Rename request->ringbuf to request->ring
2015-11-20 12:43 ` [PATCH 07/12] drm/i915: Rename request->ringbuf to request->ring Chris Wilson
@ 2015-11-24 14:51 ` Daniel Vetter
2015-11-24 15:08 ` Tvrtko Ursulin
1 sibling, 0 replies; 41+ messages in thread
From: Daniel Vetter @ 2015-11-24 14:51 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Nov 20, 2015 at 12:43:47PM +0000, Chris Wilson wrote:
> Now that we have disambuigated ring and engine, we can use the clearer
> and more consistent name for the intel_ringbuffer pointer in the
> request.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem.c | 28 +++---
> drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +-
> drivers/gpu/drm/i915/intel_display.c | 10 +-
> drivers/gpu/drm/i915/intel_lrc.c | 149 ++++++++++++++---------------
> drivers/gpu/drm/i915/intel_mocs.c | 32 +++----
> drivers/gpu/drm/i915/intel_overlay.c | 42 ++++----
> drivers/gpu/drm/i915/intel_ringbuffer.c | 86 ++++++++---------
> 10 files changed, 178 insertions(+), 183 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 9ce8b3fcb3a0..b7eaa2deb437 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2185,7 +2185,7 @@ struct drm_i915_gem_request {
> * context.
> */
> struct intel_context *ctx;
> - struct intel_ringbuffer *ringbuf;
> + struct intel_ringbuffer *ring;
>
> /** Batch buffer related to this request if any (used for
> error state dump only) */
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 5a1b51a27fe3..d6706dd4117c 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -1386,7 +1386,7 @@ static void i915_gem_request_retire(struct drm_i915_gem_request *request)
> * Note this requires that we are always called in request
> * completion order.
> */
> - request->ringbuf->last_retired_head = request->postfix;
> + request->ring->last_retired_head = request->postfix;
>
> list_del_init(&request->list);
> i915_gem_request_remove_from_client(request);
> @@ -2553,7 +2553,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
> {
> struct intel_engine_cs *engine;
> struct drm_i915_private *dev_priv;
> - struct intel_ringbuffer *ringbuf;
> + struct intel_ringbuffer *ring;
> u32 request_start;
> int ret;
>
> @@ -2562,16 +2562,16 @@ void __i915_add_request(struct drm_i915_gem_request *request,
>
> engine = request->engine;
> dev_priv = request->i915;
> - ringbuf = request->ringbuf;
> + ring = request->ring;
>
> /*
> * To ensure that this call will not fail, space for its emissions
> * should already have been reserved in the ring buffer. Let the ring
> * know that it is time to use that space up.
> */
> - intel_ring_reserved_space_use(ringbuf);
> + intel_ring_reserved_space_use(ring);
>
> - request_start = intel_ring_get_tail(ringbuf);
> + request_start = intel_ring_get_tail(ring);
> /*
> * Emit any outstanding flushes - execbuf can fail to emit the flush
> * after having emitted the batchbuffer command. Hence we need to fix
> @@ -2593,14 +2593,14 @@ void __i915_add_request(struct drm_i915_gem_request *request,
> * GPU processing the request, we never over-estimate the
> * position of the head.
> */
> - request->postfix = intel_ring_get_tail(ringbuf);
> + request->postfix = intel_ring_get_tail(ring);
>
> if (i915.enable_execlists)
> ret = engine->emit_request(request);
> else {
> ret = engine->add_request(request);
>
> - request->tail = intel_ring_get_tail(ringbuf);
> + request->tail = intel_ring_get_tail(ring);
> }
> /* Not allowed to fail! */
> WARN(ret, "emit|add_request failed: %d!\n", ret);
> @@ -2629,7 +2629,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
> intel_mark_busy(dev_priv->dev);
>
> /* Sanity check that the reserved size was large enough. */
> - intel_ring_reserved_space_end(ringbuf);
> + intel_ring_reserved_space_end(ring);
> }
>
> static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
> @@ -2741,7 +2741,7 @@ int i915_gem_request_alloc(struct intel_engine_cs *engine,
> * to be redone if the request is not actually submitted straight
> * away, e.g. because a GPU scheduler has deferred it.
> */
> - intel_ring_reserved_space_reserve(req->ringbuf,
> + intel_ring_reserved_space_reserve(req->ring,
> MIN_SPACE_FOR_ADD_REQUEST);
> ret = intel_ring_begin(req, 0);
> if (ret) {
> @@ -2764,7 +2764,7 @@ err:
>
> void i915_gem_request_cancel(struct drm_i915_gem_request *req)
> {
> - intel_ring_reserved_space_cancel(req->ringbuf);
> + intel_ring_reserved_space_cancel(req->ring);
>
> i915_gem_request_unreference(req);
> }
> @@ -4657,11 +4657,11 @@ int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
> * at initialization time.
> */
> for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
> - intel_ring_emit(req->ringbuf, MI_LOAD_REGISTER_IMM(1));
> - intel_ring_emit(req->ringbuf, reg_base + i);
> - intel_ring_emit(req->ringbuf, remap_info[i/4]);
> + intel_ring_emit(req->ring, MI_LOAD_REGISTER_IMM(1));
> + intel_ring_emit(req->ring, reg_base + i);
> + intel_ring_emit(req->ring, remap_info[i/4]);
> }
> - intel_ring_advance(req->ringbuf);
> + intel_ring_advance(req->ring);
>
> return ret;
> }
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
> index 047c2f94bd22..5d0516930b16 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -479,7 +479,7 @@ i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
> static inline int
> mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> u32 flags = hw_flags | MI_MM_SPACE_GTT;
> const int num_rings =
> /* Use an extended w/a on ivb+ if signalling from other rings */
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 32c2d08bdd4c..afa930dab632 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -1115,7 +1115,7 @@ i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
> static int
> i915_reset_gen7_sol_offsets(struct drm_i915_gem_request *req)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> int ret, i;
>
> if (!IS_GEN7(req->i915) || req->engine->id != RCS) {
> @@ -1196,7 +1196,7 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
> struct drm_i915_gem_execbuffer2 *args,
> struct list_head *vmas)
> {
> - struct intel_ringbuffer *ring = params->request->ringbuf;
> + struct intel_ringbuffer *ring = params->request->ring;
> struct drm_i915_private *dev_priv = params->request->i915;
> u64 exec_start, exec_len;
> int instp_mode;
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index c222456961fb..b1ee6f89e70b 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -651,7 +651,7 @@ static int gen8_write_pdp(struct drm_i915_gem_request *req,
> unsigned entry,
> dma_addr_t addr)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> int ret;
>
> BUG_ON(entry >= 4);
> @@ -1588,7 +1588,7 @@ static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
> static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
> struct drm_i915_gem_request *req)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> int ret;
>
> /* NB: TLBs must be flushed and invalidated before a switch */
> @@ -1626,7 +1626,7 @@ static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
> static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
> struct drm_i915_gem_request *req)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> int ret;
>
> /* NB: TLBs must be flushed and invalidated before a switch */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2447f1a36fb0..cdd6074257af 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10824,7 +10824,7 @@ static int intel_gen2_queue_flip(struct drm_device *dev,
> struct drm_i915_gem_request *req,
> uint32_t flags)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> u32 flip_mask;
> int ret;
> @@ -10859,7 +10859,7 @@ static int intel_gen3_queue_flip(struct drm_device *dev,
> struct drm_i915_gem_request *req,
> uint32_t flags)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> u32 flip_mask;
> int ret;
> @@ -10891,7 +10891,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev,
> struct drm_i915_gem_request *req,
> uint32_t flags)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> struct drm_i915_private *dev_priv = req->i915;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> uint32_t pf, pipesrc;
> @@ -10930,7 +10930,7 @@ static int intel_gen6_queue_flip(struct drm_device *dev,
> struct drm_i915_gem_request *req,
> uint32_t flags)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> struct drm_i915_private *dev_priv = req->i915;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> uint32_t pf, pipesrc;
> @@ -10966,7 +10966,7 @@ static int intel_gen7_queue_flip(struct drm_device *dev,
> struct drm_i915_gem_request *req,
> uint32_t flags)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> uint32_t plane_bit = 0;
> int len, ret;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 1502e53d2ad6..5c37922c3cde 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -339,7 +339,7 @@ static int execlists_update_context(struct drm_i915_gem_request *rq)
> {
> struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
> struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[rq->engine->id].state;
> - struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj;
> + struct drm_i915_gem_object *rb_obj = rq->ring->obj;
> struct page *page;
> uint32_t *reg_state;
>
> @@ -545,7 +545,7 @@ static int execlists_context_queue(struct drm_i915_gem_request *request)
>
> i915_gem_request_reference(request);
>
> - request->tail = request->ringbuf->tail;
> + request->tail = request->ring->tail;
>
> spin_lock_irq(&engine->execlist_lock);
>
> @@ -633,7 +633,7 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request
> {
> int ret;
>
> - request->ringbuf = request->ctx->engine[request->engine->id].ringbuf;
> + request->ring = request->ctx->engine[request->engine->id].ringbuf;
>
> if (request->ctx != request->engine->default_context) {
> ret = intel_lr_context_pin(request);
> @@ -656,7 +656,7 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request
> static void
> intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
> {
> - intel_ring_advance(request->ringbuf);
> + intel_ring_advance(request->ring);
>
> if (intel_ring_stopped(request->engine))
> return;
> @@ -686,9 +686,9 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
> struct list_head *vmas)
> {
> struct drm_device *dev = params->dev;
> - struct intel_engine_cs *ring = params->ring;
> + struct intel_engine_cs *engine = params->ring;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf;
> + struct intel_ringbuffer *ring = params->request->ring;
> u64 exec_start;
> int instp_mode;
> u32 instp_mask;
> @@ -700,7 +700,7 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
> case I915_EXEC_CONSTANTS_REL_GENERAL:
> case I915_EXEC_CONSTANTS_ABSOLUTE:
> case I915_EXEC_CONSTANTS_REL_SURFACE:
> - if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) {
> + if (instp_mode != 0 && engine->id != RCS) {
> DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
> return -EINVAL;
> }
> @@ -729,17 +729,17 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
> if (ret)
> return ret;
>
> - if (ring == &dev_priv->ring[RCS] &&
> + if (engine->id == RCS &&
> instp_mode != dev_priv->relative_constants_mode) {
> ret = intel_ring_begin(params->request, 4);
> if (ret)
> return ret;
>
> - intel_ring_emit(ringbuf, MI_NOOP);
> - intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1));
> - intel_ring_emit(ringbuf, INSTPM);
> - intel_ring_emit(ringbuf, instp_mask << 16 | instp_mode);
> - intel_ring_advance(ringbuf);
> + intel_ring_emit(ring, MI_NOOP);
> + intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
> + intel_ring_emit(ring, INSTPM);
> + intel_ring_emit(ring, instp_mask << 16 | instp_mode);
> + intel_ring_advance(ring);
>
> dev_priv->relative_constants_mode = instp_mode;
> }
> @@ -747,7 +747,7 @@ int intel_execlists_submission(struct i915_execbuffer_params *params,
> exec_start = params->batch_obj_vm_offset +
> args->batch_start_offset;
>
> - ret = ring->emit_bb_start(params->request, exec_start, params->dispatch_flags);
> + ret = engine->emit_bb_start(params->request, exec_start, params->dispatch_flags);
> if (ret)
> return ret;
>
> @@ -827,7 +827,7 @@ static int intel_lr_context_pin(struct drm_i915_gem_request *rq)
> {
> int engine = rq->engine->id;
> struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[engine].state;
> - struct intel_ringbuffer *ringbuf = rq->ringbuf;
> + struct intel_ringbuffer *ring = rq->ring;
> int ret = 0;
>
> WARN_ON(!mutex_is_locked(&rq->i915->dev->struct_mutex));
> @@ -837,7 +837,7 @@ static int intel_lr_context_pin(struct drm_i915_gem_request *rq)
> if (ret)
> goto reset_pin_count;
>
> - ret = intel_pin_and_map_ringbuffer_obj(rq->i915->dev, ringbuf);
> + ret = intel_pin_and_map_ringbuffer_obj(rq->i915->dev, ring);
> if (ret)
> goto unpin_ctx_obj;
>
> @@ -858,12 +858,12 @@ void intel_lr_context_unpin(struct drm_i915_gem_request *rq)
> {
> int engine = rq->engine->id;
> struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[engine].state;
> - struct intel_ringbuffer *ringbuf = rq->ringbuf;
> + struct intel_ringbuffer *ring = rq->ring;
>
> if (ctx_obj) {
> WARN_ON(!mutex_is_locked(&rq->i915->dev->struct_mutex));
> if (--rq->ctx->engine[engine].pin_count == 0) {
> - intel_unpin_ringbuffer_obj(ringbuf);
> + intel_unpin_ringbuffer_obj(ring);
> i915_gem_object_ggtt_unpin(ctx_obj);
> }
> }
> @@ -873,7 +873,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
> {
> int ret, i;
> struct intel_engine_cs *engine = req->engine;
> - struct intel_ringbuffer *ringbuf = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> struct drm_i915_private *dev_priv = req->i915;
> struct i915_workarounds *w = &dev_priv->workarounds;
>
> @@ -889,14 +889,14 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
> if (ret)
> return ret;
>
> - intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count));
> + intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
> for (i = 0; i < w->count; i++) {
> - intel_ring_emit(ringbuf, w->reg[i].addr);
> - intel_ring_emit(ringbuf, w->reg[i].value);
> + intel_ring_emit(ring, w->reg[i].addr);
> + intel_ring_emit(ring, w->reg[i].value);
> }
> - intel_ring_emit(ringbuf, MI_NOOP);
> + intel_ring_emit(ring, MI_NOOP);
>
> - intel_ring_advance(ringbuf);
> + intel_ring_advance(ring);
>
> engine->gpu_caches_dirty = true;
> ret = logical_ring_flush_all_caches(req);
> @@ -1318,7 +1318,7 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
> {
> struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
> struct intel_engine_cs *engine = req->engine;
> - struct intel_ringbuffer *ringbuf = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
> int i, ret;
>
> @@ -1326,18 +1326,18 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
> if (ret)
> return ret;
>
> - intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds));
> + intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_lri_cmds));
> for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
> const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
>
> - intel_ring_emit(ringbuf, GEN8_RING_PDP_UDW(engine, i));
> - intel_ring_emit(ringbuf, upper_32_bits(pd_daddr));
> - intel_ring_emit(ringbuf, GEN8_RING_PDP_LDW(engine, i));
> - intel_ring_emit(ringbuf, lower_32_bits(pd_daddr));
> + intel_ring_emit(ring, GEN8_RING_PDP_UDW(engine, i));
> + intel_ring_emit(ring, upper_32_bits(pd_daddr));
> + intel_ring_emit(ring, GEN8_RING_PDP_LDW(engine, i));
> + intel_ring_emit(ring, lower_32_bits(pd_daddr));
> }
>
> - intel_ring_emit(ringbuf, MI_NOOP);
> - intel_ring_advance(ringbuf);
> + intel_ring_emit(ring, MI_NOOP);
> + intel_ring_advance(ring);
>
> return 0;
> }
> @@ -1345,7 +1345,7 @@ static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
> static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
> u64 offset, unsigned dispatch_flags)
> {
> - struct intel_ringbuffer *ringbuf = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
> int ret;
>
> @@ -1371,14 +1371,14 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
> return ret;
>
> /* FIXME(BDW): Address space and security selectors. */
> - intel_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 |
> + intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 |
> (ppgtt<<8) |
> (dispatch_flags & I915_DISPATCH_RS ?
> MI_BATCH_RESOURCE_STREAMER : 0));
> - intel_ring_emit(ringbuf, lower_32_bits(offset));
> - intel_ring_emit(ringbuf, upper_32_bits(offset));
> - intel_ring_emit(ringbuf, MI_NOOP);
> - intel_ring_advance(ringbuf);
> + intel_ring_emit(ring, lower_32_bits(offset));
> + intel_ring_emit(ring, upper_32_bits(offset));
> + intel_ring_emit(ring, MI_NOOP);
> + intel_ring_advance(ring);
>
> return 0;
> }
> @@ -1420,10 +1420,7 @@ static int gen8_emit_flush(struct drm_i915_gem_request *request,
> u32 invalidate_domains,
> u32 unused)
> {
> - struct intel_ringbuffer *ringbuf = request->ringbuf;
> - struct intel_engine_cs *ring = ringbuf->ring;
> - struct drm_device *dev = ring->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_ringbuffer *ring = request->ring;
> uint32_t cmd;
> int ret;
>
> @@ -1442,17 +1439,17 @@ static int gen8_emit_flush(struct drm_i915_gem_request *request,
>
> if (invalidate_domains & I915_GEM_GPU_DOMAINS) {
> cmd |= MI_INVALIDATE_TLB;
> - if (ring == &dev_priv->ring[VCS])
> + if (request->engine->id == VCS)
> cmd |= MI_INVALIDATE_BSD;
> }
>
> - intel_ring_emit(ringbuf, cmd);
> - intel_ring_emit(ringbuf,
> + intel_ring_emit(ring, cmd);
> + intel_ring_emit(ring,
> I915_GEM_HWS_SCRATCH_ADDR |
> MI_FLUSH_DW_USE_GTT);
> - intel_ring_emit(ringbuf, 0); /* upper addr */
> - intel_ring_emit(ringbuf, 0); /* value */
> - intel_ring_advance(ringbuf);
> + intel_ring_emit(ring, 0); /* upper addr */
> + intel_ring_emit(ring, 0); /* value */
> + intel_ring_advance(ring);
>
> return 0;
> }
> @@ -1461,9 +1458,8 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> u32 invalidate_domains,
> u32 flush_domains)
> {
> - struct intel_ringbuffer *ringbuf = request->ringbuf;
> - struct intel_engine_cs *ring = ringbuf->ring;
> - u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> + struct intel_ringbuffer *ring = request->ring;
> + u32 scratch_addr = request->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> bool vf_flush_wa;
> u32 flags = 0;
> int ret;
> @@ -1491,7 +1487,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe
> * control.
> */
> - vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 &&
> + vf_flush_wa = INTEL_INFO(request->i915)->gen >= 9 &&
> flags & PIPE_CONTROL_VF_CACHE_INVALIDATE;
>
> ret = intel_ring_begin(request, vf_flush_wa ? 12 : 6);
> @@ -1499,21 +1495,21 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
> return ret;
>
> if (vf_flush_wa) {
> - intel_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
> - intel_ring_emit(ringbuf, 0);
> - intel_ring_emit(ringbuf, 0);
> - intel_ring_emit(ringbuf, 0);
> - intel_ring_emit(ringbuf, 0);
> - intel_ring_emit(ringbuf, 0);
> + intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
> + intel_ring_emit(ring, 0);
> + intel_ring_emit(ring, 0);
> + intel_ring_emit(ring, 0);
> + intel_ring_emit(ring, 0);
> + intel_ring_emit(ring, 0);
> }
>
> - intel_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6));
> - intel_ring_emit(ringbuf, flags);
> - intel_ring_emit(ringbuf, scratch_addr);
> - intel_ring_emit(ringbuf, 0);
> - intel_ring_emit(ringbuf, 0);
> - intel_ring_emit(ringbuf, 0);
> - intel_ring_advance(ringbuf);
> + intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
> + intel_ring_emit(ring, flags);
> + intel_ring_emit(ring, scratch_addr);
> + intel_ring_emit(ring, 0);
> + intel_ring_emit(ring, 0);
> + intel_ring_emit(ring, 0);
> + intel_ring_advance(ring);
>
> return 0;
> }
> @@ -1530,8 +1526,7 @@ static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno)
>
> static int gen8_emit_request(struct drm_i915_gem_request *request)
> {
> - struct intel_ringbuffer *ringbuf = request->ringbuf;
> - struct intel_engine_cs *ring = ringbuf->ring;
> + struct intel_ringbuffer *ring = request->ring;
> u32 cmd;
> int ret;
>
> @@ -1547,23 +1542,23 @@ static int gen8_emit_request(struct drm_i915_gem_request *request)
> cmd = MI_STORE_DWORD_IMM_GEN4;
> cmd |= MI_GLOBAL_GTT;
>
> - intel_ring_emit(ringbuf, cmd);
> - intel_ring_emit(ringbuf,
> - (ring->status_page.gfx_addr +
> + intel_ring_emit(ring, cmd);
> + intel_ring_emit(ring,
> + (request->engine->status_page.gfx_addr +
> (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT)));
> - intel_ring_emit(ringbuf, 0);
> - intel_ring_emit(ringbuf, i915_gem_request_get_seqno(request));
> - intel_ring_emit(ringbuf, MI_USER_INTERRUPT);
> - intel_ring_emit(ringbuf, MI_NOOP);
> + intel_ring_emit(ring, 0);
> + intel_ring_emit(ring, i915_gem_request_get_seqno(request));
> + intel_ring_emit(ring, MI_USER_INTERRUPT);
> + intel_ring_emit(ring, MI_NOOP);
> intel_logical_ring_advance_and_submit(request);
>
> /*
> * Here we add two extra NOOPs as padding to avoid
> * lite restore of a context with HEAD==TAIL.
> */
> - intel_ring_emit(ringbuf, MI_NOOP);
> - intel_ring_emit(ringbuf, MI_NOOP);
> - intel_ring_advance(ringbuf);
> + intel_ring_emit(ring, MI_NOOP);
> + intel_ring_emit(ring, MI_NOOP);
> + intel_ring_advance(ring);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
> index d79c9c0bbffb..3a1bd5f7af55 100644
> --- a/drivers/gpu/drm/i915/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/intel_mocs.c
> @@ -174,7 +174,7 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
> const struct drm_i915_mocs_table *table,
> u32 reg_base)
> {
> - struct intel_ringbuffer *ringbuf = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> unsigned int index;
> int ret;
>
> @@ -185,11 +185,11 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
> if (ret)
> return ret;
>
> - intel_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
> + intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES));
>
> for (index = 0; index < table->size; index++) {
> - intel_ring_emit(ringbuf, reg_base + index * 4);
> - intel_ring_emit(ringbuf, table->table[index].control_value);
> + intel_ring_emit(ring, reg_base + index * 4);
> + intel_ring_emit(ring, table->table[index].control_value);
> }
>
> /*
> @@ -201,12 +201,12 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
> * that value to all the used entries.
> */
> for (; index < GEN9_NUM_MOCS_ENTRIES; index++) {
> - intel_ring_emit(ringbuf, reg_base + index * 4);
> - intel_ring_emit(ringbuf, table->table[0].control_value);
> + intel_ring_emit(ring, reg_base + index * 4);
> + intel_ring_emit(ring, table->table[0].control_value);
> }
>
> - intel_ring_emit(ringbuf, MI_NOOP);
> - intel_ring_advance(ringbuf);
> + intel_ring_emit(ring, MI_NOOP);
> + intel_ring_advance(ring);
>
> return 0;
> }
> @@ -225,7 +225,7 @@ static int emit_mocs_control_table(struct drm_i915_gem_request *req,
> static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
> const struct drm_i915_mocs_table *table)
> {
> - struct intel_ringbuffer *ringbuf = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> unsigned int count;
> unsigned int i;
> u32 value;
> @@ -240,15 +240,15 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
> if (ret)
> return ret;
>
> - intel_ring_emit(ringbuf,
> + intel_ring_emit(ring,
> MI_LOAD_REGISTER_IMM(GEN9_NUM_MOCS_ENTRIES / 2));
>
> for (i = 0, count = 0; i < table->size / 2; i++, count += 2) {
> value = (table->table[count].l3cc_value & 0xffff) |
> ((table->table[count + 1].l3cc_value & 0xffff) << 16);
>
> - intel_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);
> - intel_ring_emit(ringbuf, value);
> + intel_ring_emit(ring, GEN9_LNCFCMOCS0 + i * 4);
> + intel_ring_emit(ring, value);
> }
>
> if (table->size & 0x01) {
> @@ -264,14 +264,14 @@ static int emit_mocs_l3cc_table(struct drm_i915_gem_request *req,
> * they are reserved by the hardware.
> */
> for (; i < GEN9_NUM_MOCS_ENTRIES / 2; i++) {
> - intel_ring_emit(ringbuf, GEN9_LNCFCMOCS0 + i * 4);
> - intel_ring_emit(ringbuf, value);
> + intel_ring_emit(ring, GEN9_LNCFCMOCS0 + i * 4);
> + intel_ring_emit(ring, value);
>
> value = filler;
> }
>
> - intel_ring_emit(ringbuf, MI_NOOP);
> - intel_ring_advance(ringbuf);
> + intel_ring_emit(ring, MI_NOOP);
> + intel_ring_advance(ring);
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
> index 5e9c7c15a84b..451c59b8f526 100644
> --- a/drivers/gpu/drm/i915/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/intel_overlay.c
> @@ -252,11 +252,11 @@ static int intel_overlay_on(struct intel_overlay *overlay)
>
> overlay->active = true;
>
> - intel_ring_emit(req->ringbuf, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
> - intel_ring_emit(req->ringbuf, overlay->flip_addr | OFC_UPDATE);
> - intel_ring_emit(req->ringbuf, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
> - intel_ring_emit(req->ringbuf, MI_NOOP);
> - intel_ring_advance(req->ringbuf);
> + intel_ring_emit(req->ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
> + intel_ring_emit(req->ring, overlay->flip_addr | OFC_UPDATE);
> + intel_ring_emit(req->ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
> + intel_ring_emit(req->ring, MI_NOOP);
> + intel_ring_advance(req->ring);
>
> return intel_overlay_do_wait_request(overlay, req, NULL);
> }
> @@ -293,9 +293,9 @@ static int intel_overlay_continue(struct intel_overlay *overlay,
> return ret;
> }
>
> - intel_ring_emit(req->ringbuf, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
> - intel_ring_emit(req->ringbuf, flip_addr);
> - intel_ring_advance(req->ringbuf);
> + intel_ring_emit(req->ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
> + intel_ring_emit(req->ring, flip_addr);
> + intel_ring_advance(req->ring);
>
> WARN_ON(overlay->last_flip_req);
> i915_gem_request_assign(&overlay->last_flip_req, req);
> @@ -360,22 +360,22 @@ static int intel_overlay_off(struct intel_overlay *overlay)
> }
>
> /* wait for overlay to go idle */
> - intel_ring_emit(req->ringbuf, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
> - intel_ring_emit(req->ringbuf, flip_addr);
> - intel_ring_emit(req->ringbuf, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
> + intel_ring_emit(req->ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
> + intel_ring_emit(req->ring, flip_addr);
> + intel_ring_emit(req->ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
> /* turn overlay off */
> if (IS_I830(dev)) {
> /* Workaround: Don't disable the overlay fully, since otherwise
> * it dies on the next OVERLAY_ON cmd. */
> - intel_ring_emit(req->ringbuf, MI_NOOP);
> - intel_ring_emit(req->ringbuf, MI_NOOP);
> - intel_ring_emit(req->ringbuf, MI_NOOP);
> + intel_ring_emit(req->ring, MI_NOOP);
> + intel_ring_emit(req->ring, MI_NOOP);
> + intel_ring_emit(req->ring, MI_NOOP);
> } else {
> - intel_ring_emit(req->ringbuf, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
> - intel_ring_emit(req->ringbuf, flip_addr);
> - intel_ring_emit(req->ringbuf, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
> + intel_ring_emit(req->ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
> + intel_ring_emit(req->ring, flip_addr);
> + intel_ring_emit(req->ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
> }
> - intel_ring_advance(req->ringbuf);
> + intel_ring_advance(req->ring);
>
> return intel_overlay_do_wait_request(overlay, req, intel_overlay_off_tail);
> }
> @@ -433,9 +433,9 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
> return ret;
> }
>
> - intel_ring_emit(req->ringbuf, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
> - intel_ring_emit(req->ringbuf, MI_NOOP);
> - intel_ring_advance(req->ringbuf);
> + intel_ring_emit(req->ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
> + intel_ring_emit(req->ring, MI_NOOP);
> + intel_ring_advance(req->ring);
>
> ret = intel_overlay_do_wait_request(overlay, req,
> intel_overlay_release_old_vid_tail);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index cc060588a287..c4610c727c49 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -95,7 +95,7 @@ gen2_render_ring_flush(struct drm_i915_gem_request *req,
> u32 invalidate_domains,
> u32 flush_domains)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> u32 cmd;
> int ret;
>
> @@ -122,7 +122,7 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
> u32 invalidate_domains,
> u32 flush_domains)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> u32 cmd;
> int ret;
>
> @@ -215,7 +215,7 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
> static int
> intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> int ret;
>
> @@ -251,7 +251,7 @@ static int
> gen6_render_ring_flush(struct drm_i915_gem_request *req,
> u32 invalidate_domains, u32 flush_domains)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> u32 flags = 0;
> u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> int ret;
> @@ -303,7 +303,7 @@ gen6_render_ring_flush(struct drm_i915_gem_request *req,
> static int
> gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> int ret;
>
> ret = intel_ring_begin(req, 4);
> @@ -324,7 +324,7 @@ static int
> gen7_render_ring_flush(struct drm_i915_gem_request *req,
> u32 invalidate_domains, u32 flush_domains)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> u32 flags = 0;
> u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> int ret;
> @@ -387,7 +387,7 @@ static int
> gen8_emit_pipe_control(struct drm_i915_gem_request *req,
> u32 flags, u32 scratch_addr)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> int ret;
>
> ret = intel_ring_begin(req, 6);
> @@ -712,7 +712,7 @@ err:
>
> static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> struct drm_i915_private *dev_priv = req->i915;
> struct i915_workarounds *w = &dev_priv->workarounds;
> int ret, i;
> @@ -1184,7 +1184,7 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
> unsigned int num_dwords)
> {
> #define MBOX_UPDATE_DWORDS 8
> - struct intel_ringbuffer *signaller = signaller_req->ringbuf;
> + struct intel_ringbuffer *signaller = signaller_req->ring;
> struct drm_i915_private *dev_priv = signaller_req->i915;
> struct intel_engine_cs *waiter;
> int i, ret, num_rings;
> @@ -1224,7 +1224,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
> unsigned int num_dwords)
> {
> #define MBOX_UPDATE_DWORDS 6
> - struct intel_ringbuffer *signaller = signaller_req->ringbuf;
> + struct intel_ringbuffer *signaller = signaller_req->ring;
> struct drm_i915_private *dev_priv = signaller_req->i915;
> struct intel_engine_cs *waiter;
> int i, ret, num_rings;
> @@ -1261,7 +1261,7 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
> static int gen6_signal(struct drm_i915_gem_request *signaller_req,
> unsigned int num_dwords)
> {
> - struct intel_ringbuffer *signaller = signaller_req->ringbuf;
> + struct intel_ringbuffer *signaller = signaller_req->ring;
> struct drm_i915_private *dev_priv = signaller_req->i915;
> struct intel_engine_cs *useless;
> int i, ret, num_rings;
> @@ -1303,7 +1303,7 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
> static int
> gen6_add_request(struct drm_i915_gem_request *req)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> int ret;
>
> if (req->engine->semaphore.signal)
> @@ -1342,7 +1342,7 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
> struct intel_engine_cs *signaller,
> u32 seqno)
> {
> - struct intel_ringbuffer *waiter = waiter_req->ringbuf;
> + struct intel_ringbuffer *waiter = waiter_req->ring;
> struct drm_i915_private *dev_priv = waiter_req->i915;
> int ret;
>
> @@ -1370,7 +1370,7 @@ gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
> struct intel_engine_cs *signaller,
> u32 seqno)
> {
> - struct intel_ringbuffer *waiter = waiter_req->ringbuf;
> + struct intel_ringbuffer *waiter = waiter_req->ring;
> u32 dw1 = MI_SEMAPHORE_MBOX |
> MI_SEMAPHORE_COMPARE |
> MI_SEMAPHORE_REGISTER;
> @@ -1418,7 +1418,7 @@ do { \
> static int
> pc_render_add_request(struct drm_i915_gem_request *req)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
> int ret;
>
> @@ -1612,7 +1612,7 @@ bsd_ring_flush(struct drm_i915_gem_request *req,
> u32 invalidate_domains,
> u32 flush_domains)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> int ret;
>
> ret = intel_ring_begin(req, 2);
> @@ -1628,7 +1628,7 @@ bsd_ring_flush(struct drm_i915_gem_request *req,
> static int
> i9xx_add_request(struct drm_i915_gem_request *req)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> int ret;
>
> ret = intel_ring_begin(req, 4);
> @@ -1773,7 +1773,7 @@ i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
> u64 offset, u32 length,
> unsigned dispatch_flags)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> int ret;
>
> ret = intel_ring_begin(req, 2);
> @@ -1800,7 +1800,7 @@ i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
> u64 offset, u32 len,
> unsigned dispatch_flags)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> u32 cs_offset = req->engine->scratch.gtt_offset;
> int ret;
>
> @@ -1863,7 +1863,7 @@ i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
> u64 offset, u32 len,
> unsigned dispatch_flags)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> int ret;
>
> ret = intel_ring_begin(req, 2);
> @@ -2164,7 +2164,7 @@ int intel_ring_idle(struct intel_engine_cs *ring)
>
> int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
> {
> - request->ringbuf = request->engine->buffer;
> + request->ring = request->engine->buffer;
> return 0;
> }
>
> @@ -2217,17 +2217,17 @@ void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
>
> static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> {
> - struct intel_ringbuffer *ringbuf = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> struct intel_engine_cs *engine = req->engine;
> struct drm_i915_gem_request *target;
> unsigned space;
> int ret;
>
> - if (intel_ring_space(ringbuf) >= bytes)
> + if (intel_ring_space(ring) >= bytes)
> return 0;
>
> /* The whole point of reserving space is to not wait! */
> - WARN_ON(ringbuf->reserved_in_use);
> + WARN_ON(ring->reserved_in_use);
>
> list_for_each_entry(target, &engine->request_list, list) {
> /*
> @@ -2235,12 +2235,12 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> * from multiple ringbuffers. Here, we must ignore any that
> * aren't from the ringbuffer we're considering.
> */
> - if (target->ringbuf != ringbuf)
> + if (target->ring != ring)
> continue;
>
> /* Would completion of this request free enough space? */
> - space = __intel_ring_space(target->postfix, ringbuf->tail,
> - ringbuf->size);
> + space = __intel_ring_space(target->postfix, ring->tail,
> + ring->size);
> if (space >= bytes)
> break;
> }
> @@ -2252,7 +2252,7 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> if (ret)
> return ret;
>
> - ringbuf->space = space;
> + ring->space = space;
> return 0;
> }
>
> @@ -2267,16 +2267,16 @@ static void ring_wrap(struct intel_ringbuffer *ringbuf)
>
> static int ring_prepare(struct drm_i915_gem_request *req, int bytes)
> {
> - struct intel_ringbuffer *ringbuf = req->ringbuf;
> - int remain_usable = ringbuf->effective_size - ringbuf->tail;
> - int remain_actual = ringbuf->size - ringbuf->tail;
> + struct intel_ringbuffer *ring = req->ring;
> + int remain_usable = ring->effective_size - ring->tail;
> + int remain_actual = ring->size - ring->tail;
> int ret, total_bytes, wait_bytes = 0;
> bool need_wrap = false;
>
> - if (ringbuf->reserved_in_use)
> + if (ring->reserved_in_use)
> total_bytes = bytes;
> else
> - total_bytes = bytes + ringbuf->reserved_size;
> + total_bytes = bytes + ring->reserved_size;
>
> if (unlikely(bytes > remain_usable)) {
> /*
> @@ -2292,9 +2292,9 @@ static int ring_prepare(struct drm_i915_gem_request *req, int bytes)
> * falls off the end. So only need to to wait for the
> * reserved size after flushing out the remainder.
> */
> - wait_bytes = remain_actual + ringbuf->reserved_size;
> + wait_bytes = remain_actual + ring->reserved_size;
> need_wrap = true;
> - } else if (total_bytes > ringbuf->space) {
> + } else if (total_bytes > ring->space) {
> /* No wrapping required, just waiting. */
> wait_bytes = total_bytes;
> }
> @@ -2306,7 +2306,7 @@ static int ring_prepare(struct drm_i915_gem_request *req, int bytes)
> return ret;
>
> if (need_wrap)
> - ring_wrap(ringbuf);
> + ring_wrap(ring);
> }
>
> return 0;
> @@ -2325,14 +2325,14 @@ int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
> if (ret)
> return ret;
>
> - req->ringbuf->space -= num_dwords * sizeof(uint32_t);
> + req->ring->space -= num_dwords * sizeof(uint32_t);
> return 0;
> }
>
> /* Align the ring tail to a cacheline boundary */
> int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> int num_dwords = (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
> int ret;
>
> @@ -2404,7 +2404,7 @@ static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring,
> static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
> u32 invalidate, u32 flush)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> uint32_t cmd;
> int ret;
>
> @@ -2450,7 +2450,7 @@ gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
> u64 offset, u32 len,
> unsigned dispatch_flags)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> bool ppgtt = USES_PPGTT(req->i915) &&
> !(dispatch_flags & I915_DISPATCH_SECURE);
> int ret;
> @@ -2476,7 +2476,7 @@ hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
> u64 offset, u32 len,
> unsigned dispatch_flags)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> int ret;
>
> ret = intel_ring_begin(req, 2);
> @@ -2501,7 +2501,7 @@ gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
> u64 offset, u32 len,
> unsigned dispatch_flags)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> int ret;
>
> ret = intel_ring_begin(req, 2);
> @@ -2524,7 +2524,7 @@ gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
> static int gen6_ring_flush(struct drm_i915_gem_request *req,
> u32 invalidate, u32 flush)
> {
> - struct intel_ringbuffer *ring = req->ringbuf;
> + struct intel_ringbuffer *ring = req->ring;
> uint32_t cmd;
> int ret;
>
> --
> 2.6.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 03/12] drm/i915: Unify intel_logical_ring_emit and intel_ring_emit
2015-11-24 14:33 ` Daniel Vetter
@ 2015-11-24 14:52 ` Chris Wilson
0 siblings, 0 replies; 41+ messages in thread
From: Chris Wilson @ 2015-11-24 14:52 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Tue, Nov 24, 2015 at 03:33:12PM +0100, Daniel Vetter wrote:
> On Fri, Nov 20, 2015 at 12:43:43PM +0000, Chris Wilson wrote:
> > @@ -547,7 +547,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
> >
> > intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_rings));
> > for_each_ring(signaller, req->i915, i) {
> > - if (signaller == ring)
> > + if (signaller == req->ring)
> > continue;
>
> Tsk, unrelated hunks above. And maybe a cocci to s/req->ring/req->engine/.
> At least mention in the commit message that your on a crusade against
> superflous ring/dev/whatever pointers and arguments while in the area.
It was hard to tell where one patch began and another ended.
> > @@ -1275,9 +1269,9 @@ i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
> > exec_start = params->batch_obj_vm_offset +
> > params->args_batch_start_offset;
> >
> > - ret = ring->dispatch_execbuffer(params->request,
> > - exec_start, exec_len,
> > - params->dispatch_flags);
> > + ret = params->ring->dispatch_execbuffer(params->request,
> > + exec_start, exec_len,
> > + params->dispatch_flags);
>
> I guess we should just shovel all the stuff in params into request
> eventually ...
Have you been reading ahead? The only argument for these exact
parameters to be recorded would be for hangcheck. But we do get to
cleanup execbuf dispatch eventually as well.
> > diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
> > index 444542696a2c..5e9c7c15a84b 100644
> > --- a/drivers/gpu/drm/i915/intel_overlay.c
> > +++ b/drivers/gpu/drm/i915/intel_overlay.c
> > @@ -433,9 +433,9 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
> > return ret;
> > }
> >
> > - intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
> > - intel_ring_emit(ring, MI_NOOP);
> > - intel_ring_advance(ring);
> > + intel_ring_emit(req->ringbuf, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
> > + intel_ring_emit(req->ringbuf, MI_NOOP);
> > + intel_ring_advance(req->ringbuf);
> >
> > ret = intel_overlay_do_wait_request(overlay, req,
> > intel_overlay_release_old_vid_tail);
>
> Any reason for not doing your usual transform to intel_ringbuffer for the
> local ring here in the overlay code? Or does that happen when
> intel_ring_begin falls?
Later patches looked a bit neater with not adding a temporary
intel_engine_cs *ring; intel_ringbuf *ringbuf. That was my thinking at
least.
> At the end of this crusade we should add some pretty kerneldoc for our
> ringbuffer interface.
request_create
ring_begin{ ring_emit }ring_advance
request_commit (add_request)
But one may ask how do we go from request to ring. Wouldn't it be neat
to have that explicit in the interface:
req = request_create()
..
ring = ring_begin(req);
ring_emit(ring)...
ring_advance(ring)
...
request_commit(req);
Deja vu.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 08/12] drm/i915: Rename backpointer from intel_ringbuffer to intel_engine_cs
2015-11-20 12:43 ` [PATCH 08/12] drm/i915: Rename backpointer from intel_ringbuffer to intel_engine_cs Chris Wilson
@ 2015-11-24 14:58 ` Daniel Vetter
2015-11-24 15:10 ` Chris Wilson
2015-11-24 15:15 ` Chris Wilson
0 siblings, 2 replies; 41+ messages in thread
From: Daniel Vetter @ 2015-11-24 14:58 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Nov 20, 2015 at 12:43:48PM +0000, Chris Wilson wrote:
> Having ringbuf->ring point to an engine is confusing, so rename it once
> again to ring->engine.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This massively conflicts with
commit e84fe80337dc85cca07d0417ea97edbec4789d8b
Author: Nick Hoath <nicholas.hoath@intel.com>
Date: Fri Sep 11 12:53:46 2015 +0100
drm/i915: Split alloc from init for lrc
since this patch touches piles of old code now removed. But no functional
conflict afaics, so Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Maybe rebase before sending ;-)
-Daniel
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 46 ++++++++++++++++-----------------
> drivers/gpu/drm/i915/intel_ringbuffer.c | 36 +++++++++++++-------------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
> 3 files changed, 42 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 5c37922c3cde..346f5889738e 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -2089,13 +2089,13 @@ void intel_lr_context_free(struct intel_context *ctx)
> if (ctx_obj) {
> struct intel_ringbuffer *ringbuf =
> ctx->engine[i].ringbuf;
> - struct intel_engine_cs *ring = ringbuf->ring;
> + struct intel_engine_cs *engine = ringbuf->engine;
>
> - if (ctx == ring->default_context) {
> + if (ctx == engine->default_context) {
> intel_unpin_ringbuffer_obj(ringbuf);
> i915_gem_object_ggtt_unpin(ctx_obj);
> }
> - WARN_ON(ctx->engine[ring->id].pin_count);
> + WARN_ON(ctx->engine[engine->id].pin_count);
> intel_destroy_ringbuffer_obj(ringbuf);
> kfree(ringbuf);
> drm_gem_object_unreference(&ctx_obj->base);
> @@ -2158,19 +2158,19 @@ static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring,
> * Return: non-zero on error.
> */
> int intel_lr_context_deferred_create(struct intel_context *ctx,
> - struct intel_engine_cs *ring)
> + struct intel_engine_cs *engine)
> {
> - const bool is_global_default_ctx = (ctx == ring->default_context);
> - struct drm_device *dev = ring->dev;
> + const bool is_global_default_ctx = (ctx == engine->default_context);
> + struct drm_device *dev = engine->dev;
> struct drm_i915_gem_object *ctx_obj;
> uint32_t context_size;
> struct intel_ringbuffer *ringbuf;
> int ret;
>
> WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
> - WARN_ON(ctx->engine[ring->id].state);
> + WARN_ON(ctx->engine[engine->id].state);
>
> - context_size = round_up(get_lr_context_size(ring), 4096);
> + context_size = round_up(get_lr_context_size(engine), 4096);
>
> ctx_obj = i915_gem_alloc_object(dev, context_size);
> if (!ctx_obj) {
> @@ -2191,12 +2191,12 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
> ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
> if (!ringbuf) {
> DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
> - ring->name);
> + engine->name);
> ret = -ENOMEM;
> goto error_unpin_ctx;
> }
>
> - ringbuf->ring = ring;
> + ringbuf->engine = engine;
>
> ringbuf->size = 32 * PAGE_SIZE;
> ringbuf->effective_size = ringbuf->size;
> @@ -2210,7 +2210,7 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
> if (ret) {
> DRM_DEBUG_DRIVER(
> "Failed to allocate ringbuffer obj %s: %d\n",
> - ring->name, ret);
> + engine->name, ret);
> goto error_free_rbuf;
> }
>
> @@ -2219,38 +2219,38 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
> if (ret) {
> DRM_ERROR(
> "Failed to pin and map ringbuffer %s: %d\n",
> - ring->name, ret);
> + engine->name, ret);
> goto error_destroy_rbuf;
> }
> }
>
> }
>
> - ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf);
> + ret = populate_lr_context(ctx, ctx_obj, engine, ringbuf);
> if (ret) {
> DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
> goto error;
> }
>
> - ctx->engine[ring->id].ringbuf = ringbuf;
> - ctx->engine[ring->id].state = ctx_obj;
> + ctx->engine[engine->id].ringbuf = ringbuf;
> + ctx->engine[engine->id].state = ctx_obj;
>
> - if (ctx == ring->default_context)
> - lrc_setup_hardware_status_page(ring, ctx_obj);
> - else if (ring->id == RCS && !ctx->rcs_initialized) {
> - if (ring->init_context) {
> + if (ctx == engine->default_context)
> + lrc_setup_hardware_status_page(engine, ctx_obj);
> + else if (engine->id == RCS && !ctx->rcs_initialized) {
> + if (engine->init_context) {
> struct drm_i915_gem_request *req;
>
> - ret = i915_gem_request_alloc(ring, ctx, &req);
> + ret = i915_gem_request_alloc(engine, ctx, &req);
> if (ret)
> return ret;
>
> - ret = ring->init_context(req);
> + ret = engine->init_context(req);
> if (ret) {
> DRM_ERROR("ring init context: %d\n", ret);
> i915_gem_request_cancel(req);
> - ctx->engine[ring->id].ringbuf = NULL;
> - ctx->engine[ring->id].state = NULL;
> + ctx->engine[engine->id].ringbuf = NULL;
> + ctx->engine[engine->id].state = NULL;
> goto error;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index c4610c727c49..1d43a24b6268 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2043,36 +2043,36 @@ int intel_alloc_ringbuffer_obj(struct drm_device *dev,
> }
>
> static int intel_init_ring_buffer(struct drm_device *dev,
> - struct intel_engine_cs *ring)
> + struct intel_engine_cs *engine)
> {
> struct intel_ringbuffer *ringbuf;
> int ret;
>
> - WARN_ON(ring->buffer);
> + WARN_ON(engine->buffer);
>
> ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
> if (!ringbuf)
> return -ENOMEM;
> - ring->buffer = ringbuf;
> + engine->buffer = ringbuf;
>
> - ring->dev = dev;
> - INIT_LIST_HEAD(&ring->active_list);
> - INIT_LIST_HEAD(&ring->request_list);
> - INIT_LIST_HEAD(&ring->execlist_queue);
> - i915_gem_batch_pool_init(dev, &ring->batch_pool);
> + engine->dev = dev;
> + INIT_LIST_HEAD(&engine->active_list);
> + INIT_LIST_HEAD(&engine->request_list);
> + INIT_LIST_HEAD(&engine->execlist_queue);
> + i915_gem_batch_pool_init(dev, &engine->batch_pool);
> ringbuf->size = 32 * PAGE_SIZE;
> - ringbuf->ring = ring;
> - memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno));
> + ringbuf->engine = engine;
> + memset(engine->semaphore.sync_seqno, 0, sizeof(engine->semaphore.sync_seqno));
>
> - init_waitqueue_head(&ring->irq_queue);
> + init_waitqueue_head(&engine->irq_queue);
>
> if (I915_NEED_GFX_HWS(dev)) {
> - ret = init_status_page(ring);
> + ret = init_status_page(engine);
> if (ret)
> goto error;
> } else {
> - BUG_ON(ring->id != RCS);
> - ret = init_phys_status_page(ring);
> + BUG_ON(engine->id != RCS);
> + ret = init_phys_status_page(engine);
> if (ret)
> goto error;
> }
> @@ -2082,14 +2082,14 @@ static int intel_init_ring_buffer(struct drm_device *dev,
> ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
> if (ret) {
> DRM_ERROR("Failed to allocate ringbuffer %s: %d\n",
> - ring->name, ret);
> + engine->name, ret);
> goto error;
> }
>
> ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
> if (ret) {
> DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
> - ring->name, ret);
> + engine->name, ret);
> intel_destroy_ringbuffer_obj(ringbuf);
> goto error;
> }
> @@ -2102,7 +2102,7 @@ static int intel_init_ring_buffer(struct drm_device *dev,
> if (IS_I830(dev) || IS_845G(dev))
> ringbuf->effective_size -= 2 * CACHELINE_BYTES;
>
> - ret = i915_cmd_parser_init_ring(ring);
> + ret = i915_cmd_parser_init_ring(engine);
> if (ret)
> goto error;
>
> @@ -2110,7 +2110,7 @@ static int intel_init_ring_buffer(struct drm_device *dev,
>
> error:
> kfree(ringbuf);
> - ring->buffer = NULL;
> + engine->buffer = NULL;
> return ret;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 368d9b0454ed..6a9056e3ac46 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -99,7 +99,7 @@ struct intel_ringbuffer {
> struct drm_i915_gem_object *obj;
> void *virtual_start;
>
> - struct intel_engine_cs *ring;
> + struct intel_engine_cs *engine;
>
> u32 head;
> u32 tail;
> --
> 2.6.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 04/12] drm/i915: Unify intel_ring_begin()
2015-11-24 14:38 ` Daniel Vetter
@ 2015-11-24 14:58 ` Chris Wilson
0 siblings, 0 replies; 41+ messages in thread
From: Chris Wilson @ 2015-11-24 14:58 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Tue, Nov 24, 2015 at 03:38:46PM +0100, Daniel Vetter wrote:
> On Fri, Nov 20, 2015 at 12:43:44PM +0000, Chris Wilson wrote:
> > Combine the near identical implementations of intel_logical_ring_begin()
> > and intel_ring_begin() - the only difference is that the logical wait
> > has to check for a matching ring (which is assumed by legacy).
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>
> Hm, I originally punted on this one since OCD-me wanted to move
> engine->request_list to ring->request_list first. But hey just adding the
> check works too and gives us the immediate improvement faster!
I was too lazy to add the breadcrumb list I used last time. Or rather, I
used that list for more than just wait_for_space() and didn't want to
try and get the whole semaphore/interrupt mitigation reviewed. There is
still the complaint for media wakeups caused by our breadcrumb being too
heavy handed.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 09/12] drm/i915: Rename intel_context[engine].ringbuf
2015-11-20 12:43 ` [PATCH 09/12] drm/i915: Rename intel_context[engine].ringbuf Chris Wilson
@ 2015-11-24 14:59 ` Daniel Vetter
2015-11-24 15:09 ` Tvrtko Ursulin
1 sibling, 0 replies; 41+ messages in thread
From: Daniel Vetter @ 2015-11-24 14:59 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Nov 20, 2015 at 12:43:49PM +0000, Chris Wilson wrote:
> Perform s/ringbuf/ring/ on the context struct for consistency with the
> ring/engine split.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
I presume all ringbuf are now gone?
Anyway, Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 4 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
> drivers/gpu/drm/i915/intel_lrc.c | 85 ++++++++++++++++-----------------
> drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++---
> 5 files changed, 52 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 56375c36b381..630717fec688 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1950,7 +1950,7 @@ static int i915_context_status(struct seq_file *m, void *unused)
> struct drm_i915_gem_object *ctx_obj =
> ctx->engine[i].state;
> struct intel_ringbuffer *ringbuf =
> - ctx->engine[i].ringbuf;
> + ctx->engine[i].ring;
>
> seq_printf(m, "%s: ", ring->name);
> if (ctx_obj)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b7eaa2deb437..d8bd58cbb727 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -882,9 +882,9 @@ struct intel_context {
>
> /* Execlists */
> bool rcs_initialized;
> - struct {
> + struct intel_context_engine {
> struct drm_i915_gem_object *state;
> - struct intel_ringbuffer *ringbuf;
> + struct intel_ringbuffer *ring;
> int pin_count;
> } engine[I915_NUM_RINGS];
>
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 974e3481e449..8b37f72bd91f 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1040,9 +1040,9 @@ static void i915_gem_record_rings(struct drm_device *dev,
> * executed).
> */
> if (request)
> - rbuf = request->ctx->engine[ring->id].ringbuf;
> + rbuf = request->ctx->engine[ring->id].ring;
> else
> - rbuf = ring->default_context->engine[ring->id].ringbuf;
> + rbuf = ring->default_context->engine[ring->id].ring;
> } else
> rbuf = ring->buffer;
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 346f5889738e..222ae8383f48 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -381,24 +381,24 @@ static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
> execlists_elsp_write(rq0, rq1);
> }
>
> -static void execlists_context_unqueue(struct intel_engine_cs *ring)
> +static void execlists_context_unqueue(struct intel_engine_cs *engine)
> {
> struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
> struct drm_i915_gem_request *cursor = NULL, *tmp = NULL;
>
> - assert_spin_locked(&ring->execlist_lock);
> + assert_spin_locked(&engine->execlist_lock);
>
> /*
> * If irqs are not active generate a warning as batches that finish
> * without the irqs may get lost and a GPU Hang may occur.
> */
> - WARN_ON(!intel_irqs_enabled(ring->dev->dev_private));
> + WARN_ON(!intel_irqs_enabled(engine->dev->dev_private));
>
> - if (list_empty(&ring->execlist_queue))
> + if (list_empty(&engine->execlist_queue))
> return;
>
> /* Try to read in pairs */
> - list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue,
> + list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue,
> execlist_link) {
> if (!req0) {
> req0 = cursor;
> @@ -408,7 +408,7 @@ static void execlists_context_unqueue(struct intel_engine_cs *ring)
> cursor->elsp_submitted = req0->elsp_submitted;
> list_del(&req0->execlist_link);
> list_add_tail(&req0->execlist_link,
> - &ring->execlist_retired_req_list);
> + &engine->execlist_retired_req_list);
> req0 = cursor;
> } else {
> req1 = cursor;
> @@ -416,7 +416,7 @@ static void execlists_context_unqueue(struct intel_engine_cs *ring)
> }
> }
>
> - if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) {
> + if (IS_GEN8(engine->dev) || IS_GEN9(engine->dev)) {
> /*
> * WaIdleLiteRestore: make sure we never cause a lite
> * restore with HEAD==TAIL
> @@ -428,11 +428,11 @@ static void execlists_context_unqueue(struct intel_engine_cs *ring)
> * for where we prepare the padding after the end of the
> * request.
> */
> - struct intel_ringbuffer *ringbuf;
> + struct intel_ringbuffer *ring;
>
> - ringbuf = req0->ctx->engine[ring->id].ringbuf;
> + ring = req0->ctx->engine[engine->id].ring;
> req0->tail += 8;
> - req0->tail &= ringbuf->size - 1;
> + req0->tail &= ring->size - 1;
> }
> }
>
> @@ -633,7 +633,7 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request
> {
> int ret;
>
> - request->ring = request->ctx->engine[request->engine->id].ringbuf;
> + request->ring = request->ctx->engine[request->engine->id].ring;
>
> if (request->ctx != request->engine->default_context) {
> ret = intel_lr_context_pin(request);
> @@ -2087,17 +2087,16 @@ void intel_lr_context_free(struct intel_context *ctx)
> struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
>
> if (ctx_obj) {
> - struct intel_ringbuffer *ringbuf =
> - ctx->engine[i].ringbuf;
> - struct intel_engine_cs *engine = ringbuf->engine;
> + struct intel_ringbuffer *ring = ctx->engine[i].ring;
> + struct intel_engine_cs *engine = ring->engine;
>
> if (ctx == engine->default_context) {
> - intel_unpin_ringbuffer_obj(ringbuf);
> + intel_unpin_ringbuffer_obj(ring);
> i915_gem_object_ggtt_unpin(ctx_obj);
> }
> WARN_ON(ctx->engine[engine->id].pin_count);
> - intel_destroy_ringbuffer_obj(ringbuf);
> - kfree(ringbuf);
> + intel_destroy_ringbuffer_obj(ring);
> + kfree(ring);
> drm_gem_object_unreference(&ctx_obj->base);
> }
> }
> @@ -2164,7 +2163,7 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
> struct drm_device *dev = engine->dev;
> struct drm_i915_gem_object *ctx_obj;
> uint32_t context_size;
> - struct intel_ringbuffer *ringbuf;
> + struct intel_ringbuffer *ring;
> int ret;
>
> WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL);
> @@ -2188,25 +2187,25 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
> }
> }
>
> - ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL);
> - if (!ringbuf) {
> + ring = kzalloc(sizeof(*ring), GFP_KERNEL);
> + if (!ring) {
> DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
> engine->name);
> ret = -ENOMEM;
> goto error_unpin_ctx;
> }
>
> - ringbuf->engine = engine;
> + ring->engine = engine;
>
> - ringbuf->size = 32 * PAGE_SIZE;
> - ringbuf->effective_size = ringbuf->size;
> - ringbuf->head = 0;
> - ringbuf->tail = 0;
> - ringbuf->last_retired_head = -1;
> - intel_ring_update_space(ringbuf);
> + ring->size = 32 * PAGE_SIZE;
> + ring->effective_size = ring->size;
> + ring->head = 0;
> + ring->tail = 0;
> + ring->last_retired_head = -1;
> + intel_ring_update_space(ring);
>
> - if (ringbuf->obj == NULL) {
> - ret = intel_alloc_ringbuffer_obj(dev, ringbuf);
> + if (ring->obj == NULL) {
> + ret = intel_alloc_ringbuffer_obj(dev, ring);
> if (ret) {
> DRM_DEBUG_DRIVER(
> "Failed to allocate ringbuffer obj %s: %d\n",
> @@ -2215,7 +2214,7 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
> }
>
> if (is_global_default_ctx) {
> - ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
> + ret = intel_pin_and_map_ringbuffer_obj(dev, ring);
> if (ret) {
> DRM_ERROR(
> "Failed to pin and map ringbuffer %s: %d\n",
> @@ -2226,13 +2225,13 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
>
> }
>
> - ret = populate_lr_context(ctx, ctx_obj, engine, ringbuf);
> + ret = populate_lr_context(ctx, ctx_obj, engine, ring);
> if (ret) {
> DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
> goto error;
> }
>
> - ctx->engine[engine->id].ringbuf = ringbuf;
> + ctx->engine[engine->id].ring = ring;
> ctx->engine[engine->id].state = ctx_obj;
>
> if (ctx == engine->default_context)
> @@ -2249,7 +2248,7 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
> if (ret) {
> DRM_ERROR("ring init context: %d\n", ret);
> i915_gem_request_cancel(req);
> - ctx->engine[engine->id].ringbuf = NULL;
> + ctx->engine[engine->id].ring = NULL;
> ctx->engine[engine->id].state = NULL;
> goto error;
> }
> @@ -2264,11 +2263,11 @@ int intel_lr_context_deferred_create(struct intel_context *ctx,
>
> error:
> if (is_global_default_ctx)
> - intel_unpin_ringbuffer_obj(ringbuf);
> + intel_unpin_ringbuffer_obj(ring);
> error_destroy_rbuf:
> - intel_destroy_ringbuffer_obj(ringbuf);
> + intel_destroy_ringbuffer_obj(ring);
> error_free_rbuf:
> - kfree(ringbuf);
> + kfree(ring);
> error_unpin_ctx:
> if (is_global_default_ctx)
> i915_gem_object_ggtt_unpin(ctx_obj);
> @@ -2280,14 +2279,12 @@ void intel_lr_context_reset(struct drm_device *dev,
> struct intel_context *ctx)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_engine_cs *ring;
> + struct intel_engine_cs *unused;
> int i;
>
> - for_each_ring(ring, dev_priv, i) {
> - struct drm_i915_gem_object *ctx_obj =
> - ctx->engine[ring->id].state;
> - struct intel_ringbuffer *ringbuf =
> - ctx->engine[ring->id].ringbuf;
> + for_each_ring(unused, dev_priv, i) {
> + struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
> + struct intel_ringbuffer *ring = ctx->engine[i].ring;
> uint32_t *reg_state;
> struct page *page;
>
> @@ -2306,7 +2303,7 @@ void intel_lr_context_reset(struct drm_device *dev,
>
> kunmap_atomic(reg_state);
>
> - ringbuf->head = 0;
> - ringbuf->tail = 0;
> + ring->head = 0;
> + ring->tail = 0;
> }
> }
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 1d43a24b6268..f6b7e209cc3c 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -34,20 +34,20 @@
> #include "intel_drv.h"
>
> bool
> -intel_ring_initialized(struct intel_engine_cs *ring)
> +intel_ring_initialized(struct intel_engine_cs *engine)
> {
> - struct drm_device *dev = ring->dev;
> + struct drm_device *dev = engine->dev;
>
> if (!dev)
> return false;
>
> if (i915.enable_execlists) {
> - struct intel_context *dctx = ring->default_context;
> - struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf;
> + struct intel_context *dctx = engine->default_context;
> + struct intel_ringbuffer *ring = dctx->engine[engine->id].ring;
>
> - return ringbuf->obj;
> + return ring->obj;
> } else
> - return ring->buffer && ring->buffer->obj;
> + return engine->buffer && engine->buffer->obj;
> }
>
> int __intel_ring_space(int head, int tail, int size)
> --
> 2.6.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 10/12] drm/i915: Reduce the pointer dance of i915_is_ggtt()
2015-11-20 12:43 ` [PATCH 10/12] drm/i915: Reduce the pointer dance of i915_is_ggtt() Chris Wilson
@ 2015-11-24 15:08 ` Daniel Vetter
0 siblings, 0 replies; 41+ messages in thread
From: Daniel Vetter @ 2015-11-24 15:08 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Nov 20, 2015 at 12:43:50PM +0000, Chris Wilson wrote:
> The multiple levels of indirect do nothing but hinder the compiler and
> the pointer chasing turns to be quite painful but painless to fix.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
vma->is_ggtt = vm->is_ggtt is robust enough for me to carry it twice.
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 14 ++++++-------
> drivers/gpu/drm/i915/i915_drv.h | 9 +--------
> drivers/gpu/drm/i915/i915_gem.c | 32 +++++++++++++-----------------
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 5 ++---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 21 +++++++++-----------
> drivers/gpu/drm/i915/i915_gem_gtt.h | 3 +++
> drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
> drivers/gpu/drm/i915/i915_trace.h | 27 ++++++++-----------------
> 8 files changed, 44 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 630717fec688..d83f35c8df34 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -123,8 +123,7 @@ static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
> struct i915_vma *vma;
>
> list_for_each_entry(vma, &obj->vma_list, vma_link) {
> - if (i915_is_ggtt(vma->vm) &&
> - drm_mm_node_allocated(&vma->node))
> + if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
> size += vma->node.size;
> }
>
> @@ -171,12 +170,11 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
> seq_printf(m, " (fence: %d)", obj->fence_reg);
> list_for_each_entry(vma, &obj->vma_list, vma_link) {
> seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
> - i915_is_ggtt(vma->vm) ? "g" : "pp",
> + vma->is_ggtt ? "g" : "pp",
> vma->node.start, vma->node.size);
> - if (i915_is_ggtt(vma->vm))
> - seq_printf(m, ", type: %u)", vma->ggtt_view.type);
> - else
> - seq_puts(m, ")");
> + if (vma->is_ggtt)
> + seq_printf(m, ", type: %u", vma->ggtt_view.type);
> + seq_puts(m, ")");
> }
> if (obj->stolen)
> seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
> @@ -348,7 +346,7 @@ static int per_file_stats(int id, void *ptr, void *data)
> if (!drm_mm_node_allocated(&vma->node))
> continue;
>
> - if (i915_is_ggtt(vma->vm)) {
> + if (vma->is_ggtt) {
> stats->global += obj->base.size;
> continue;
> }
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index d8bd58cbb727..e86e1188deb0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3023,18 +3023,11 @@ bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
> /* Some GGTT VM helpers */
> #define i915_obj_to_ggtt(obj) \
> (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
> -static inline bool i915_is_ggtt(struct i915_address_space *vm)
> -{
> - struct i915_address_space *ggtt =
> - &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
> - return vm == ggtt;
> -}
>
> static inline struct i915_hw_ppgtt *
> i915_vm_to_ppgtt(struct i915_address_space *vm)
> {
> - WARN_ON(i915_is_ggtt(vm));
> -
> + WARN_ON(vm->is_ggtt);
> return container_of(vm, struct i915_hw_ppgtt, base);
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index d6706dd4117c..390cb9c15bad 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3300,8 +3300,7 @@ int i915_vma_unbind(struct i915_vma *vma)
> * cause memory corruption through use-after-free.
> */
>
> - if (i915_is_ggtt(vma->vm) &&
> - vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
> + if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
> i915_gem_object_finish_gtt(obj);
>
> /* release the fence reg _after_ flushing */
> @@ -3316,7 +3315,7 @@ int i915_vma_unbind(struct i915_vma *vma)
> vma->bound = 0;
>
> list_del_init(&vma->mm_list);
> - if (i915_is_ggtt(vma->vm)) {
> + if (vma->is_ggtt) {
> if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
> obj->map_and_fenceable = false;
> } else if (vma->ggtt_view.pages) {
> @@ -3427,7 +3426,7 @@ i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
> struct i915_vma *vma;
> int ret;
>
> - if (i915_is_ggtt(vm)) {
> + if (vm->is_ggtt) {
> u32 fence_size, fence_alignment, unfenced_alignment;
> u64 view_size;
>
> @@ -4177,13 +4176,13 @@ i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
> if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
> return -ENODEV;
>
> - if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
> + if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !vm->is_ggtt))
> return -EINVAL;
>
> if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
> return -EINVAL;
>
> - if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
> + if (WARN_ON(vm->is_ggtt != !!ggtt_view))
> return -EINVAL;
>
> vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
> @@ -4245,7 +4244,7 @@ i915_gem_object_pin(struct drm_i915_gem_object *obj,
> uint64_t flags)
> {
> return i915_gem_object_do_pin(obj, vm,
> - i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
> + vm->is_ggtt ? &i915_ggtt_view_normal : NULL,
> size, alignment, flags);
> }
>
> @@ -4550,7 +4549,7 @@ struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
> {
> struct i915_vma *vma;
> list_for_each_entry(vma, &obj->vma_list, vma_link) {
> - if (i915_is_ggtt(vma->vm) &&
> + if (vma->is_ggtt &&
> vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
> continue;
> if (vma->vm == vm)
> @@ -4577,17 +4576,14 @@ struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
>
> void i915_gem_vma_destroy(struct i915_vma *vma)
> {
> - struct i915_address_space *vm = NULL;
> WARN_ON(vma->node.allocated);
>
> /* Keep the vma as a placeholder in the execbuffer reservation lists */
> if (!list_empty(&vma->exec_list))
> return;
>
> - vm = vma->vm;
> -
> - if (!i915_is_ggtt(vm))
> - i915_ppgtt_put(i915_vm_to_ppgtt(vm));
> + if (!vma->is_ggtt)
> + i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm));
>
> list_del(&vma->vma_link);
>
> @@ -4984,7 +4980,7 @@ init_ring_lists(struct intel_engine_cs *ring)
> void i915_init_vm(struct drm_i915_private *dev_priv,
> struct i915_address_space *vm)
> {
> - if (!i915_is_ggtt(vm))
> + if (!vm->is_ggtt)
> drm_mm_init(&vm->mm, vm->start, vm->total);
> vm->dev = dev_priv->dev;
> INIT_LIST_HEAD(&vm->active_list);
> @@ -5148,7 +5144,7 @@ u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
> WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
>
> list_for_each_entry(vma, &o->vma_list, vma_link) {
> - if (i915_is_ggtt(vma->vm) &&
> + if (vma->is_ggtt &&
> vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
> continue;
> if (vma->vm == vm)
> @@ -5156,7 +5152,7 @@ u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
> }
>
> WARN(1, "%s vma for this object not found.\n",
> - i915_is_ggtt(vm) ? "global" : "ppgtt");
> + vm->is_ggtt ? "global" : "ppgtt");
> return -1;
> }
>
> @@ -5181,7 +5177,7 @@ bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
> struct i915_vma *vma;
>
> list_for_each_entry(vma, &o->vma_list, vma_link) {
> - if (i915_is_ggtt(vma->vm) &&
> + if (vma->is_ggtt &&
> vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
> continue;
> if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
> @@ -5228,7 +5224,7 @@ unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
> BUG_ON(list_empty(&o->vma_list));
>
> list_for_each_entry(vma, &o->vma_list, vma_link) {
> - if (i915_is_ggtt(vma->vm) &&
> + if (vma->is_ggtt &&
> vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
> continue;
> if (vma->vm == vm)
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index afa930dab632..46907f5da4f2 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -652,7 +652,7 @@ need_reloc_mappable(struct i915_vma *vma)
> if (entry->relocation_count == 0)
> return false;
>
> - if (!i915_is_ggtt(vma->vm))
> + if (!vma->is_ggtt)
> return false;
>
> /* See also use_cpu_reloc() */
> @@ -671,8 +671,7 @@ eb_vma_misplaced(struct i915_vma *vma)
> struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
> struct drm_i915_gem_object *obj = vma->obj;
>
> - WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP &&
> - !i915_is_ggtt(vma->vm));
> + WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && !vma->is_ggtt);
>
> if (entry->alignment &&
> vma->node.start & (entry->alignment - 1))
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index b1ee6f89e70b..8bb1102608fd 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2456,7 +2456,6 @@ static int ggtt_bind_vma(struct i915_vma *vma,
> if (obj->gt_ro)
> pte_flags |= PTE_READ_ONLY;
>
> -
> if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
> vma->vm->insert_entries(vma->vm, pages,
> vma->node.start,
> @@ -3027,6 +3026,7 @@ int i915_gem_gtt_init(struct drm_device *dev)
> }
>
> gtt->base.dev = dev;
> + gtt->base.is_ggtt = true;
>
> ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size,
> >t->mappable_base, >t->mappable_end);
> @@ -3105,7 +3105,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev)
> container_of(vm, struct i915_hw_ppgtt,
> base);
>
> - if (i915_is_ggtt(vm))
> + if (vm->is_ggtt)
> ppgtt = dev_priv->mm.aliasing_ppgtt;
>
> gen6_write_page_range(dev_priv, &ppgtt->pd,
> @@ -3123,7 +3123,7 @@ __i915_gem_vma_create(struct drm_i915_gem_object *obj,
> {
> struct i915_vma *vma;
>
> - if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
> + if (WARN_ON(vm->is_ggtt != !!ggtt_view))
> return ERR_PTR(-EINVAL);
>
> vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
> @@ -3135,13 +3135,14 @@ __i915_gem_vma_create(struct drm_i915_gem_object *obj,
> INIT_LIST_HEAD(&vma->exec_list);
> vma->vm = vm;
> vma->obj = obj;
> + vma->is_ggtt = vm->is_ggtt;
>
> - if (i915_is_ggtt(vm))
> + if (vm->is_ggtt)
> vma->ggtt_view = *ggtt_view;
> + else
> + i915_ppgtt_get(i915_vm_to_ppgtt(vm));
>
> list_add_tail(&vma->vma_link, &obj->vma_list);
> - if (!i915_is_ggtt(vm))
> - i915_ppgtt_get(i915_vm_to_ppgtt(vm));
>
> return vma;
> }
> @@ -3155,7 +3156,7 @@ i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
> vma = i915_gem_obj_to_vma(obj, vm);
> if (!vma)
> vma = __i915_gem_vma_create(obj, vm,
> - i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
> + vm->is_ggtt ? &i915_ggtt_view_normal : NULL);
>
> return vma;
> }
> @@ -3381,13 +3382,9 @@ int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
> return 0;
>
> if (vma->bound == 0 && vma->vm->allocate_va_range) {
> - trace_i915_va_alloc(vma->vm,
> - vma->node.start,
> - vma->node.size,
> - VM_TO_TRACE_NAME(vma->vm));
> -
> /* XXX: i915_vma_pin() will fix this +- hack */
> vma->pin_count++;
> + trace_i915_va_alloc(vma);
> ret = vma->vm->allocate_va_range(vma->vm,
> vma->node.start,
> vma->node.size);
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index 82750073d5b3..9b506ec6b90c 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -183,6 +183,7 @@ struct i915_vma {
> #define GLOBAL_BIND (1<<0)
> #define LOCAL_BIND (1<<1)
> unsigned int bound : 4;
> + unsigned is_ggtt : 1;
>
> /**
> * Support different GGTT views into the same object.
> @@ -275,6 +276,8 @@ struct i915_address_space {
> u64 start; /* Start offset always 0 for dri2 */
> u64 total; /* size addr space maps (ex. 2GB for ggtt) */
>
> + bool is_ggtt;
> +
> struct i915_page_scratch *scratch_page;
> struct i915_page_table *scratch_pt;
> struct i915_page_directory *scratch_pd;
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index 8b37f72bd91f..8afc49600835 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -612,7 +612,7 @@ i915_error_object_create(struct drm_i915_private *dev_priv,
> dst->gtt_offset = -1;
>
> reloc_offset = dst->gtt_offset;
> - if (i915_is_ggtt(vm))
> + if (vm->is_ggtt)
> vma = i915_gem_obj_to_ggtt(src);
> use_ggtt = (src->cache_level == I915_CACHE_NONE &&
> vma && (vma->bound & GLOBAL_BIND) &&
> diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
> index 533b6a87fd1d..58ef4e0ccea1 100644
> --- a/drivers/gpu/drm/i915/i915_trace.h
> +++ b/drivers/gpu/drm/i915/i915_trace.h
> @@ -175,35 +175,24 @@ TRACE_EVENT(i915_vma_unbind,
> __entry->obj, __entry->offset, __entry->size, __entry->vm)
> );
>
> -#define VM_TO_TRACE_NAME(vm) \
> - (i915_is_ggtt(vm) ? "G" : \
> - "P")
> -
> -DECLARE_EVENT_CLASS(i915_va,
> - TP_PROTO(struct i915_address_space *vm, u64 start, u64 length, const char *name),
> - TP_ARGS(vm, start, length, name),
> +TRACE_EVENT(i915_va_alloc,
> + TP_PROTO(struct i915_vma *vma),
> + TP_ARGS(vma),
>
> TP_STRUCT__entry(
> __field(struct i915_address_space *, vm)
> __field(u64, start)
> __field(u64, end)
> - __string(name, name)
> ),
>
> TP_fast_assign(
> - __entry->vm = vm;
> - __entry->start = start;
> - __entry->end = start + length - 1;
> - __assign_str(name, name);
> + __entry->vm = vma->vm;
> + __entry->start = vma->node.start;
> + __entry->end = vma->node.start + vma->node.size - 1;
> ),
>
> - TP_printk("vm=%p (%s), 0x%llx-0x%llx",
> - __entry->vm, __get_str(name), __entry->start, __entry->end)
> -);
> -
> -DEFINE_EVENT(i915_va, i915_va_alloc,
> - TP_PROTO(struct i915_address_space *vm, u64 start, u64 length, const char *name),
> - TP_ARGS(vm, start, length, name)
> + TP_printk("vm=%p (%c), 0x%llx-0x%llx",
> + __entry->vm, __entry->vm->is_ggtt ? 'G' : 'P', __entry->start, __entry->end)
> );
>
> DECLARE_EVENT_CLASS(i915_px_entry,
> --
> 2.6.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 07/12] drm/i915: Rename request->ringbuf to request->ring
2015-11-20 12:43 ` [PATCH 07/12] drm/i915: Rename request->ringbuf to request->ring Chris Wilson
2015-11-24 14:51 ` Daniel Vetter
@ 2015-11-24 15:08 ` Tvrtko Ursulin
2015-11-24 15:25 ` Chris Wilson
1 sibling, 1 reply; 41+ messages in thread
From: Tvrtko Ursulin @ 2015-11-24 15:08 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 20/11/15 12:43, Chris Wilson wrote:
> Now that we have disambuigated ring and engine, we can use the clearer
> and more consistent name for the intel_ringbuffer pointer in the
> request.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_gem.c | 28 +++---
> drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +-
> drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +-
> drivers/gpu/drm/i915/intel_display.c | 10 +-
> drivers/gpu/drm/i915/intel_lrc.c | 149 ++++++++++++++---------------
> drivers/gpu/drm/i915/intel_mocs.c | 32 +++----
> drivers/gpu/drm/i915/intel_overlay.c | 42 ++++----
> drivers/gpu/drm/i915/intel_ringbuffer.c | 86 ++++++++---------
> 10 files changed, 178 insertions(+), 183 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 9ce8b3fcb3a0..b7eaa2deb437 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2185,7 +2185,7 @@ struct drm_i915_gem_request {
> * context.
> */
> struct intel_context *ctx;
> - struct intel_ringbuffer *ringbuf;
> + struct intel_ringbuffer *ring;
What was the problem with ringbuf? Struct is still called ringbuf and
the files as well after the patch series.
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 09/12] drm/i915: Rename intel_context[engine].ringbuf
2015-11-20 12:43 ` [PATCH 09/12] drm/i915: Rename intel_context[engine].ringbuf Chris Wilson
2015-11-24 14:59 ` Daniel Vetter
@ 2015-11-24 15:09 ` Tvrtko Ursulin
2015-11-24 15:27 ` Chris Wilson
1 sibling, 1 reply; 41+ messages in thread
From: Tvrtko Ursulin @ 2015-11-24 15:09 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 20/11/15 12:43, Chris Wilson wrote:
> Perform s/ringbuf/ring/ on the context struct for consistency with the
> ring/engine split.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 4 +-
> drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
> drivers/gpu/drm/i915/intel_lrc.c | 85 ++++++++++++++++-----------------
> drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++---
> 5 files changed, 52 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 56375c36b381..630717fec688 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1950,7 +1950,7 @@ static int i915_context_status(struct seq_file *m, void *unused)
> struct drm_i915_gem_object *ctx_obj =
> ctx->engine[i].state;
> struct intel_ringbuffer *ringbuf =
Elsewhere you were renaming this to ring, why not here? I am not sure it
makes sense (renaming) but it is at least not consistent.
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 08/12] drm/i915: Rename backpointer from intel_ringbuffer to intel_engine_cs
2015-11-24 14:58 ` Daniel Vetter
@ 2015-11-24 15:10 ` Chris Wilson
2015-11-24 15:15 ` Chris Wilson
1 sibling, 0 replies; 41+ messages in thread
From: Chris Wilson @ 2015-11-24 15:10 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Tue, Nov 24, 2015 at 03:58:13PM +0100, Daniel Vetter wrote:
> On Fri, Nov 20, 2015 at 12:43:48PM +0000, Chris Wilson wrote:
> > Having ringbuf->ring point to an engine is confusing, so rename it once
> > again to ring->engine.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>
> This massively conflicts with
>
> commit e84fe80337dc85cca07d0417ea97edbec4789d8b
> Author: Nick Hoath <nicholas.hoath@intel.com>
> Date: Fri Sep 11 12:53:46 2015 +0100
>
> drm/i915: Split alloc from init for lrc
>
> since this patch touches piles of old code now removed. But no functional
> conflict afaics, so Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> Maybe rebase before sending ;-)
Depends on how much you value testing.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 08/12] drm/i915: Rename backpointer from intel_ringbuffer to intel_engine_cs
2015-11-24 14:58 ` Daniel Vetter
2015-11-24 15:10 ` Chris Wilson
@ 2015-11-24 15:15 ` Chris Wilson
2015-11-24 15:36 ` Daniel Vetter
1 sibling, 1 reply; 41+ messages in thread
From: Chris Wilson @ 2015-11-24 15:15 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Tue, Nov 24, 2015 at 03:58:13PM +0100, Daniel Vetter wrote:
> On Fri, Nov 20, 2015 at 12:43:48PM +0000, Chris Wilson wrote:
> > Having ringbuf->ring point to an engine is confusing, so rename it once
> > again to ring->engine.
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>
> This massively conflicts with
>
> commit e84fe80337dc85cca07d0417ea97edbec4789d8b
> Author: Nick Hoath <nicholas.hoath@intel.com>
> Date: Fri Sep 11 12:53:46 2015 +0100
>
> drm/i915: Split alloc from init for lrc
That patch still didn't implement what I suggested in review to remove
more code and reduce the layering violation. What I was trying to get
Nick to achieve was
http://cgit.freedesktop.org/~ickle/linux-2.6/commit/?h=nightly&id=210680144b780b491de1de9b49125d9042054eb6
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 07/12] drm/i915: Rename request->ringbuf to request->ring
2015-11-24 15:08 ` Tvrtko Ursulin
@ 2015-11-24 15:25 ` Chris Wilson
2015-11-25 10:22 ` Tvrtko Ursulin
0 siblings, 1 reply; 41+ messages in thread
From: Chris Wilson @ 2015-11-24 15:25 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
On Tue, Nov 24, 2015 at 03:08:09PM +0000, Tvrtko Ursulin wrote:
>
> On 20/11/15 12:43, Chris Wilson wrote:
> >Now that we have disambuigated ring and engine, we can use the clearer
> >and more consistent name for the intel_ringbuffer pointer in the
> >request.
> >
> >Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> >---
> > drivers/gpu/drm/i915/i915_drv.h | 2 +-
> > drivers/gpu/drm/i915/i915_gem.c | 28 +++---
> > drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
> > drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +-
> > drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +-
> > drivers/gpu/drm/i915/intel_display.c | 10 +-
> > drivers/gpu/drm/i915/intel_lrc.c | 149 ++++++++++++++---------------
> > drivers/gpu/drm/i915/intel_mocs.c | 32 +++----
> > drivers/gpu/drm/i915/intel_overlay.c | 42 ++++----
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 86 ++++++++---------
> > 10 files changed, 178 insertions(+), 183 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> >index 9ce8b3fcb3a0..b7eaa2deb437 100644
> >--- a/drivers/gpu/drm/i915/i915_drv.h
> >+++ b/drivers/gpu/drm/i915/i915_drv.h
> >@@ -2185,7 +2185,7 @@ struct drm_i915_gem_request {
> > * context.
> > */
> > struct intel_context *ctx;
> >- struct intel_ringbuffer *ringbuf;
> >+ struct intel_ringbuffer *ring;
>
> What was the problem with ringbuf? Struct is still called ringbuf
> and the files as well after the patch series.
It introduced a major naming clash with existing code. I am trying to
remove the needlessly duplicated interfaces, and restore the historic
naming conventions.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 09/12] drm/i915: Rename intel_context[engine].ringbuf
2015-11-24 15:09 ` Tvrtko Ursulin
@ 2015-11-24 15:27 ` Chris Wilson
0 siblings, 0 replies; 41+ messages in thread
From: Chris Wilson @ 2015-11-24 15:27 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
On Tue, Nov 24, 2015 at 03:09:42PM +0000, Tvrtko Ursulin wrote:
>
> On 20/11/15 12:43, Chris Wilson wrote:
> >Perform s/ringbuf/ring/ on the context struct for consistency with the
> >ring/engine split.
> >
> >Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> >---
> > drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> > drivers/gpu/drm/i915/i915_drv.h | 4 +-
> > drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
> > drivers/gpu/drm/i915/intel_lrc.c | 85 ++++++++++++++++-----------------
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++---
> > 5 files changed, 52 insertions(+), 55 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> >index 56375c36b381..630717fec688 100644
> >--- a/drivers/gpu/drm/i915/i915_debugfs.c
> >+++ b/drivers/gpu/drm/i915/i915_debugfs.c
> >@@ -1950,7 +1950,7 @@ static int i915_context_status(struct seq_file *m, void *unused)
> > struct drm_i915_gem_object *ctx_obj =
> > ctx->engine[i].state;
> > struct intel_ringbuffer *ringbuf =
>
> Elsewhere you were renaming this to ring, why not here? I am not
> sure it makes sense (renaming) but it is at least not consistent.
If I change everything at once, the patches get ignored.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 08/12] drm/i915: Rename backpointer from intel_ringbuffer to intel_engine_cs
2015-11-24 15:15 ` Chris Wilson
@ 2015-11-24 15:36 ` Daniel Vetter
0 siblings, 0 replies; 41+ messages in thread
From: Daniel Vetter @ 2015-11-24 15:36 UTC (permalink / raw)
To: Chris Wilson, Daniel Vetter, intel-gfx
On Tue, Nov 24, 2015 at 03:15:57PM +0000, Chris Wilson wrote:
> On Tue, Nov 24, 2015 at 03:58:13PM +0100, Daniel Vetter wrote:
> > On Fri, Nov 20, 2015 at 12:43:48PM +0000, Chris Wilson wrote:
> > > Having ringbuf->ring point to an engine is confusing, so rename it once
> > > again to ring->engine.
> > >
> > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> >
> > This massively conflicts with
> >
> > commit e84fe80337dc85cca07d0417ea97edbec4789d8b
> > Author: Nick Hoath <nicholas.hoath@intel.com>
> > Date: Fri Sep 11 12:53:46 2015 +0100
> >
> > drm/i915: Split alloc from init for lrc
>
> That patch still didn't implement what I suggested in review to remove
> more code and reduce the layering violation. What I was trying to get
> Nick to achieve was
> http://cgit.freedesktop.org/~ickle/linux-2.6/commit/?h=nightly&id=210680144b780b491de1de9b49125d9042054eb6
Yeah that's even prettier. But Nick's patch did at least get some of the
init code flow maze sorted out.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 12/12] drm/i915: Cache the reset_counter for the request
2015-11-20 12:43 ` [PATCH 12/12] drm/i915: Cache the reset_counter for the request Chris Wilson
@ 2015-11-24 16:43 ` Daniel Vetter
2015-11-24 21:43 ` Chris Wilson
0 siblings, 1 reply; 41+ messages in thread
From: Daniel Vetter @ 2015-11-24 16:43 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Nov 20, 2015 at 12:43:52PM +0000, Chris Wilson wrote:
> Instead of querying the reset counter before every access to the ring,
> query it the first time we touch the ring, and do a final compare when
> submitting the request. For correctness, we need to then sanitize how
> the reset_counter is incremented to prevent broken submission and
> waiting across resets, in the process fixing the persistent -EIO we
> still see today on failed waits.
tbh that explanation went straight over my head. Questions:
- Where do we wait again over a reset? With all the wakeups we should
catch them properly. I guess this needs the detailed scenario to help me
out, since I have dim memories that there is something wrong ;-)
- What precisely is the effect for waiters? I only see moving the
atomic_inc under the dev->struct_mutex, which shouldn't do a hole lot
for anyone. Plus not returning -EAGAIN when reset_in_progress, which
looks like it might result in missed wakeups and deadlocks with the
reset work.
I /thought/ that the -EIO is from check_wedge in intel_ring_begin, but
that part seems essentially unchanged.
Aside from all that, shuffling the atomic_inc (if I can convince myself
that it's safe) to avoid the reload_in_reset hack looks like a good
improvement.
More confused comments below.
-Daniel
> v2: Rebase
> v3: Now with added testcase
>
> Testcase: igt/gem_eio
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.c | 32 +++++++-----
> drivers/gpu/drm/i915/i915_drv.h | 39 ++++++++++----
> drivers/gpu/drm/i915/i915_gem.c | 90 +++++++++++++++------------------
> drivers/gpu/drm/i915/i915_irq.c | 21 +-------
> drivers/gpu/drm/i915/intel_display.c | 10 ++--
> drivers/gpu/drm/i915/intel_ringbuffer.c | 17 ++++---
> 7 files changed, 104 insertions(+), 107 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index d83f35c8df34..107711ec956f 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -4415,7 +4415,7 @@ i915_wedged_get(void *data, u64 *val)
> struct drm_device *dev = data;
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - *val = atomic_read(&dev_priv->gpu_error.reset_counter);
> + *val = i915_terminally_wedged(&dev_priv->gpu_error);
Don't we have a few tests left that look at this still?
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index ffd99d27fac7..5838882e10a1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -841,23 +841,31 @@ int i915_resume_legacy(struct drm_device *dev)
> int i915_reset(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> + struct i915_gpu_error *error = &dev_priv->gpu_error;
> + unsigned reset_counter;
> bool simulated;
> int ret;
>
> intel_reset_gt_powersave(dev);
>
> mutex_lock(&dev->struct_mutex);
> + atomic_clear_mask(I915_WEDGED, &error->reset_counter);
> + reset_counter = atomic_inc_return(&error->reset_counter);
This publishes the reset-complete too early for the modeset code I think.
At least it crucially relies upon dev->struct_mutex serializing
everything in our driver, and I don't like to cement that assumption in
even more.
Why do we need to move that atomic_inc again?
I guess what we could try is set it right after we've reset the hw, but
before we start to re-initialize it. So move the atomic stuff below
intel_gpu_reset, with some neat barrier again. Maybe we should even push
i915_gem_reset down below that too. Not sure.
> + if (WARN_ON(__i915_reset_in_progress(reset_counter))) {
> + ret = -EIO;
> + goto error;
> + }
>
> i915_gem_reset(dev);
>
> - simulated = dev_priv->gpu_error.stop_rings != 0;
> + simulated = error->stop_rings != 0;
>
> ret = intel_gpu_reset(dev);
>
> /* Also reset the gpu hangman. */
> if (simulated) {
> DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
> - dev_priv->gpu_error.stop_rings = 0;
> + error->stop_rings = 0;
> if (ret == -ENODEV) {
> DRM_INFO("Reset not implemented, but ignoring "
> "error for simulated gpu hangs\n");
> @@ -870,8 +878,7 @@ int i915_reset(struct drm_device *dev)
>
> if (ret) {
> DRM_ERROR("Failed to reset chip: %i\n", ret);
> - mutex_unlock(&dev->struct_mutex);
> - return ret;
> + goto error;
> }
>
> intel_overlay_reset(dev_priv);
> @@ -890,20 +897,14 @@ int i915_reset(struct drm_device *dev)
> * was running at the time of the reset (i.e. we weren't VT
> * switched away).
> */
> -
> - /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
> - dev_priv->gpu_error.reload_in_reset = true;
> -
> ret = i915_gem_init_hw(dev);
> -
> - dev_priv->gpu_error.reload_in_reset = false;
> -
> - mutex_unlock(&dev->struct_mutex);
> if (ret) {
> DRM_ERROR("Failed hw init on reset %d\n", ret);
> - return ret;
> + goto error;
> }
>
> + mutex_unlock(&dev->struct_mutex);
> +
> /*
> * rps/rc6 re-init is necessary to restore state lost after the
> * reset and the re-install of gt irqs. Skip for ironlake per
> @@ -914,6 +915,11 @@ int i915_reset(struct drm_device *dev)
> intel_enable_gt_powersave(dev);
>
> return 0;
> +
> +error:
> + atomic_set_mask(I915_WEDGED, &error->reset_counter);
> + mutex_unlock(&dev->struct_mutex);
> + return ret;
> }
>
> static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3fe933e4e664..aa83b284cb2f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1395,9 +1395,6 @@ struct i915_gpu_error {
>
> /* For missed irq/seqno simulation. */
> unsigned int test_irq_rings;
> -
> - /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
> - bool reload_in_reset;
> };
>
> enum modeset_restore {
> @@ -2157,6 +2154,7 @@ struct drm_i915_gem_request {
> /** On Which ring this request was generated */
> struct drm_i915_private *i915;
> struct intel_engine_cs *engine;
> + unsigned reset_counter;
>
> /** GEM sequence number associated with this request. */
> uint32_t seqno;
> @@ -2891,23 +2889,47 @@ struct drm_i915_gem_request *
> i915_gem_find_active_request(struct intel_engine_cs *ring);
>
> bool i915_gem_retire_requests(struct drm_device *dev);
> -int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
> +int __must_check i915_gem_check_wedge(unsigned reset_counter,
> bool interruptible);
>
> +static inline u32 i915_reset_counter(struct i915_gpu_error *error)
> +{
> + return atomic_read(&error->reset_counter);
> +}
> +
> +static inline bool __i915_reset_in_progress(u32 reset)
> +{
> + return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG);
> +}
> +
> +static inline bool __i915_reset_in_progress_or_wedged(u32 reset)
> +{
> + return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
> +}
> +
> +static inline bool __i915_terminally_wedged(u32 reset)
> +{
> + return unlikely(reset & I915_WEDGED);
> +}
> +
> static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
> {
> - return unlikely(atomic_read(&error->reset_counter)
> - & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
> + return __i915_reset_in_progress(i915_reset_counter(error));
> +}
> +
> +static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
> +{
> + return __i915_reset_in_progress_or_wedged(i915_reset_counter(error));
> }
>
> static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
> {
> - return atomic_read(&error->reset_counter) & I915_WEDGED;
> + return __i915_terminally_wedged(i915_reset_counter(error));
> }
>
> static inline u32 i915_reset_count(struct i915_gpu_error *error)
> {
> - return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
> + return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2;
> }
>
> static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
> @@ -2940,7 +2962,6 @@ void __i915_add_request(struct drm_i915_gem_request *req,
> #define i915_add_request_no_flush(req) \
> __i915_add_request(req, NULL, false)
> int __i915_wait_request(struct drm_i915_gem_request *req,
> - unsigned reset_counter,
> bool interruptible,
> s64 *timeout,
> struct intel_rps_client *rps);
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index d3609e111647..6ac9c80244fa 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -85,9 +85,7 @@ i915_gem_wait_for_error(struct i915_gpu_error *error)
> {
> int ret;
>
> -#define EXIT_COND (!i915_reset_in_progress(error) || \
> - i915_terminally_wedged(error))
> - if (EXIT_COND)
> + if (!i915_reset_in_progress(error))
> return 0;
>
> /*
> @@ -96,17 +94,16 @@ i915_gem_wait_for_error(struct i915_gpu_error *error)
> * we should simply try to bail out and fail as gracefully as possible.
> */
> ret = wait_event_interruptible_timeout(error->reset_queue,
> - EXIT_COND,
> + !i915_reset_in_progress(error),
> 10*HZ);
> if (ret == 0) {
> DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
> return -EIO;
> } else if (ret < 0) {
> return ret;
> + } else {
> + return 0;
> }
> -#undef EXIT_COND
> -
> - return 0;
I like the existing color better ;-)
> }
>
> int i915_mutex_lock_interruptible(struct drm_device *dev)
> @@ -1112,26 +1109,20 @@ put_rpm:
> }
>
> int
> -i915_gem_check_wedge(struct i915_gpu_error *error,
> +i915_gem_check_wedge(unsigned reset_counter,
> bool interruptible)
> {
> - if (i915_reset_in_progress(error)) {
> + if (__i915_reset_in_progress_or_wedged(reset_counter)) {
> /* Non-interruptible callers can't handle -EAGAIN, hence return
> * -EIO unconditionally for these. */
> if (!interruptible)
> return -EIO;
>
> /* Recovery complete, but the reset failed ... */
> - if (i915_terminally_wedged(error))
> + if (__i915_terminally_wedged(reset_counter))
> return -EIO;
>
> - /*
> - * Check if GPU Reset is in progress - we need intel_ring_begin
> - * to work properly to reinit the hw state while the gpu is
> - * still marked as reset-in-progress. Handle this with a flag.
> - */
> - if (!error->reload_in_reset)
> - return -EAGAIN;
> + return -EAGAIN;
This only works because you move the check_wedge from ring_begin to
wait_space, so assumes that we never change that again. Rather fragile
imo.
> }
>
> return 0;
> @@ -1200,7 +1191,6 @@ static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
> /**
> * __i915_wait_request - wait until execution of request has finished
> * @req: duh!
> - * @reset_counter: reset sequence associated with the given request
> * @interruptible: do an interruptible wait (normally yes)
> * @timeout: in - how long to wait (NULL forever); out - how much time remaining
> *
> @@ -1215,7 +1205,6 @@ static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
> * errno with remaining time filled in timeout argument.
> */
> int __i915_wait_request(struct drm_i915_gem_request *req,
> - unsigned reset_counter,
> bool interruptible,
> s64 *timeout,
> struct intel_rps_client *rps)
> @@ -1264,12 +1253,12 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
>
> /* We need to check whether any gpu reset happened in between
> * the caller grabbing the seqno and now ... */
> - if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
> - /* ... but upgrade the -EAGAIN to an -EIO if the gpu
> - * is truely gone. */
> - ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
> - if (ret == 0)
> - ret = -EAGAIN;
> + if (req->reset_counter != i915_reset_counter(&dev_priv->gpu_error)) {
> + /* As we do not requeue the request over a GPU reset,
> + * if one does occur we know that the request is
> + * effectively complete.
> + */
> + ret = 0;
> break;
This now no longer bails out straight when a reset is in progress with
-EAGAIN. I fear for the deadlocks.
> }
>
> @@ -1433,13 +1422,7 @@ i915_wait_request(struct drm_i915_gem_request *req)
>
> BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
>
> - ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
> - if (ret)
> - return ret;
> -
> - ret = __i915_wait_request(req,
> - atomic_read(&dev_priv->gpu_error.reset_counter),
> - interruptible, NULL, NULL);
> + ret = __i915_wait_request(req, interruptible, NULL, NULL);
> if (ret)
> return ret;
>
> @@ -1514,7 +1497,6 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
> struct drm_device *dev = obj->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct drm_i915_gem_request *requests[I915_NUM_RINGS];
> - unsigned reset_counter;
> int ret, i, n = 0;
>
> BUG_ON(!mutex_is_locked(&dev->struct_mutex));
> @@ -1523,12 +1505,6 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
> if (!obj->active)
> return 0;
>
> - ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
> - if (ret)
> - return ret;
> -
> - reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
> -
> if (readonly) {
> struct drm_i915_gem_request *req;
>
> @@ -1550,9 +1526,9 @@ i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
> }
>
> mutex_unlock(&dev->struct_mutex);
> + ret = 0;
> for (i = 0; ret == 0 && i < n; i++)
> - ret = __i915_wait_request(requests[i], reset_counter, true,
> - NULL, rps);
> + ret = __i915_wait_request(requests[i], true, NULL, rps);
> mutex_lock(&dev->struct_mutex);
>
> for (i = 0; i < n; i++) {
> @@ -2707,6 +2683,7 @@ int i915_gem_request_alloc(struct intel_engine_cs *engine,
> struct drm_i915_gem_request **req_out)
> {
> struct drm_i915_private *dev_priv = to_i915(engine->dev);
> + unsigned reset_counter = i915_reset_counter(&dev_priv->gpu_error);
> struct drm_i915_gem_request *req;
> int ret;
>
> @@ -2715,6 +2692,10 @@ int i915_gem_request_alloc(struct intel_engine_cs *engine,
>
> *req_out = NULL;
>
> + ret = i915_gem_check_wedge(reset_counter, dev_priv->mm.interruptible);
> + if (ret)
> + return ret;
> +
> req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
> if (req == NULL)
> return -ENOMEM;
> @@ -2725,6 +2706,7 @@ int i915_gem_request_alloc(struct intel_engine_cs *engine,
>
> kref_init(&req->ref);
> req->i915 = dev_priv;
> + req->reset_counter = reset_counter;
> req->engine = engine;
> req->ctx = ctx;
> i915_gem_context_reference(req->ctx);
> @@ -3077,11 +3059,9 @@ void i915_gem_close_object(struct drm_gem_object *gem,
> int
> i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> {
> - struct drm_i915_private *dev_priv = dev->dev_private;
> struct drm_i915_gem_wait *args = data;
> struct drm_i915_gem_object *obj;
> struct drm_i915_gem_request *req[I915_NUM_RINGS];
> - unsigned reset_counter;
> int i, n = 0;
> int ret;
>
> @@ -3115,7 +3095,6 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
> }
>
> drm_gem_object_unreference(&obj->base);
> - reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
>
> for (i = 0; i < I915_NUM_RINGS; i++) {
> if (obj->last_read_req[i] == NULL)
> @@ -3128,11 +3107,23 @@ i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
>
> for (i = 0; i < n; i++) {
> if (ret == 0)
> - ret = __i915_wait_request(req[i], reset_counter, true,
> + ret = __i915_wait_request(req[i], true,
> args->timeout_ns > 0 ? &args->timeout_ns : NULL,
> file->driver_priv);
> +
> + /* If the GPU hung before this, report it. Ideally we only
> + * report if this request cannot be completed. Currently
> + * when we don't mark the guilty party and abort all
> + * requests on reset, so just mark all as EIO.
> + */
> + if (ret == 0 &&
> + req[i]->reset_counter != i915_reset_counter(&req[i]->i915->gpu_error))
> + ret = -EIO;
> +
> i915_gem_request_unreference__unlocked(req[i]);
> }
> +
> +
> return ret;
>
> out:
> @@ -3160,7 +3151,6 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
> if (!i915_semaphore_is_enabled(from_req->i915)) {
> struct drm_i915_private *i915 = from_req->i915;
> ret = __i915_wait_request(from_req,
> - atomic_read(&i915->gpu_error.reset_counter),
> i915->mm.interruptible,
> NULL,
> &i915->rps.semaphores);
> @@ -4082,14 +4072,15 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
> struct drm_i915_file_private *file_priv = file->driver_priv;
> unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
> struct drm_i915_gem_request *request, *target = NULL;
> - unsigned reset_counter;
> int ret;
>
> ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
> if (ret)
> return ret;
>
> - ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
> + /* ABI: return -EIO if wedged */
> + ret = i915_gem_check_wedge(i915_reset_counter(&dev_priv->gpu_error),
> + false);
> if (ret)
> return ret;
>
> @@ -4107,7 +4098,6 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
>
> target = request;
> }
> - reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
> if (target)
> i915_gem_request_reference(target);
> spin_unlock(&file_priv->mm.lock);
> @@ -4115,7 +4105,7 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
> if (target == NULL)
> return 0;
>
> - ret = __i915_wait_request(target, reset_counter, true, NULL, NULL);
> + ret = __i915_wait_request(target, true, NULL, NULL);
> if (ret == 0)
> queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index f9f5e9cf7360..186315208462 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2200,7 +2200,6 @@ static void i915_error_wake_up(struct drm_i915_private *dev_priv,
> static void i915_reset_and_wakeup(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct i915_gpu_error *error = &dev_priv->gpu_error;
> char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
> char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
> char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
> @@ -2218,7 +2217,7 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
> * the reset in-progress bit is only ever set by code outside of this
> * work we don't need to worry about any other races.
> */
> - if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
> + if (i915_reset_in_progress(&dev_priv->gpu_error)) {
> DRM_DEBUG_DRIVER("resetting chip\n");
> kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
> reset_event);
> @@ -2246,25 +2245,9 @@ static void i915_reset_and_wakeup(struct drm_device *dev)
>
> intel_runtime_pm_put(dev_priv);
>
> - if (ret == 0) {
> - /*
> - * After all the gem state is reset, increment the reset
> - * counter and wake up everyone waiting for the reset to
> - * complete.
> - *
> - * Since unlock operations are a one-sided barrier only,
> - * we need to insert a barrier here to order any seqno
> - * updates before
> - * the counter increment.
> - */
> - smp_mb__before_atomic();
> - atomic_inc(&dev_priv->gpu_error.reset_counter);
> -
> + if (ret == 0)
> kobject_uevent_env(&dev->primary->kdev->kobj,
> KOBJ_CHANGE, reset_done_event);
> - } else {
> - atomic_set_mask(I915_WEDGED, &error->reset_counter);
> - }
>
> /*
> * Note: The wake_up also serves as a memory barrier so that
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index cdd6074257af..8cb89320d28d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3298,8 +3298,7 @@ static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> bool pending;
>
> - if (i915_reset_in_progress(&dev_priv->gpu_error) ||
> - intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
> + if (intel_crtc->reset_counter != i915_reset_counter(&dev_priv->gpu_error))
> return false;
>
> spin_lock_irq(&dev->event_lock);
> @@ -10751,8 +10750,7 @@ static bool page_flip_finished(struct intel_crtc *crtc)
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> - if (i915_reset_in_progress(&dev_priv->gpu_error) ||
> - crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
> + if (crtc->reset_counter != i915_reset_counter(&dev_priv->gpu_error))
> return true;
>
> /*
> @@ -11180,9 +11178,7 @@ static void intel_mmio_flip_work_func(struct work_struct *work)
> container_of(work, struct intel_mmio_flip, work);
>
> if (mmio_flip->req)
> - WARN_ON(__i915_wait_request(mmio_flip->req,
> - mmio_flip->crtc->reset_counter,
> - false, NULL,
> + WARN_ON(__i915_wait_request(mmio_flip->req, false, NULL,
> &mmio_flip->i915->rps.mmioflips));
>
> intel_do_mmio_flip(mmio_flip->crtc);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index f33db3495e35..b3538b66353b 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -2156,9 +2156,7 @@ int intel_ring_idle(struct intel_engine_cs *ring)
> list);
>
> /* Make sure we do not trigger any retires */
> - return __i915_wait_request(req,
> - atomic_read(&req->i915->gpu_error.reset_counter),
> - req->i915->mm.interruptible,
> + return __i915_wait_request(req, req->i915->mm.interruptible,
> NULL, NULL);
> }
>
> @@ -2252,6 +2250,14 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> if (ret)
> return ret;
>
> + /* If the request was completed due to a GPU hang, we want to
> + * error out before we continue to emit more commands to the GPU.
> + */
> + ret = i915_gem_check_wedge(i915_reset_counter(&to_i915(engine->dev)->gpu_error),
> + to_i915(engine->dev)->mm.interruptible);
> + if (ret)
> + return ret;
Don't we still have the problem with -EIO now here, just less likely than
from intel_ring_begin?
> +
> ring->space = space;
> return 0;
> }
> @@ -2316,11 +2322,6 @@ int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
> {
> int ret;
>
> - ret = i915_gem_check_wedge(&req->i915->gpu_error,
> - req->i915->mm.interruptible);
> - if (ret)
> - return ret;
> -
> ret = ring_prepare(req, num_dwords * sizeof(uint32_t));
> if (ret)
> return ret;
> --
> 2.6.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 12/12] drm/i915: Cache the reset_counter for the request
2015-11-24 16:43 ` Daniel Vetter
@ 2015-11-24 21:43 ` Chris Wilson
2015-11-25 9:12 ` Daniel Vetter
0 siblings, 1 reply; 41+ messages in thread
From: Chris Wilson @ 2015-11-24 21:43 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Tue, Nov 24, 2015 at 05:43:22PM +0100, Daniel Vetter wrote:
> On Fri, Nov 20, 2015 at 12:43:52PM +0000, Chris Wilson wrote:
> > Instead of querying the reset counter before every access to the ring,
> > query it the first time we touch the ring, and do a final compare when
> > submitting the request. For correctness, we need to then sanitize how
> > the reset_counter is incremented to prevent broken submission and
> > waiting across resets, in the process fixing the persistent -EIO we
> > still see today on failed waits.
>
> tbh that explanation went straight over my head. Questions:
> - Where do we wait again over a reset? With all the wakeups we should
> catch them properly. I guess this needs the detailed scenario to help me
> out, since I have dim memories that there is something wrong ;-)
TDR. In the future (and in past speculative patches) we have proposed
keeping requests over a reset and requeuing them. That is a complication
to the simplification of bailing out from the wait. What I have in mind,
is the recovery code has to fix up the request list somehow, though that
will be fun.
> - What precisely is the effect for waiters? I only see moving the
> atomic_inc under the dev->struct_mutex, which shouldn't do a hole lot
> for anyone. Plus not returning -EAGAIN when reset_in_progress, which
> looks like it might result in missed wakeups and deadlocks with the
> reset work.
At the moment, I can trivially wedge the machine. This patch fixes that.
The patch also ensures that we cannot raise unhandled errors from
wait-request (EIO/EAGAIN handling has to be explicitly added to the
caller).
The wait-request interface still has the wait-seqno legacy of having to
acquire the reset_counter under the mutex before calling. That is quite
hairy and causes a major complication later where we want to amalgamate
waiters.
Re EAGAIN. No, it cannot result in missed wakeups since that is internal
to the wait_request function, nor can it result in new deadlocks with the
reset worker.
> I /thought/ that the -EIO is from check_wedge in intel_ring_begin, but
> that part seems essentially unchanged.
For two reasons, we need to to protect the access to the ring, and you
argued that (reporting of EIO from previous wedged GPUs) it was part of
the ABI. The other ABI that I think is important, is the reporting of
EIO if the user explicits waits on a request and it is incomplete (i.e.
wait_ioctl).
> Aside from all that, shuffling the atomic_inc (if I can convince myself
> that it's safe) to avoid the reload_in_reset hack looks like a good
> improvement.
That's what I said at the time :-p
> More confused comments below.
A large proportion of the actual patch is spent trying to make using the
atomic reset_counter safer (wrt to it changing values between multiple
tests and subsequent action).
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index d83f35c8df34..107711ec956f 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -4415,7 +4415,7 @@ i915_wedged_get(void *data, u64 *val)
> > struct drm_device *dev = data;
> > struct drm_i915_private *dev_priv = dev->dev_private;
> >
> > - *val = atomic_read(&dev_priv->gpu_error.reset_counter);
> > + *val = i915_terminally_wedged(&dev_priv->gpu_error);
>
> Don't we have a few tests left that look at this still?
One. I strongly believe that the debug interface should not be reporting
the reset_counter but the wedged status (as that is what it is called).
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index ffd99d27fac7..5838882e10a1 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -841,23 +841,31 @@ int i915_resume_legacy(struct drm_device *dev)
> > int i915_reset(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > + struct i915_gpu_error *error = &dev_priv->gpu_error;
> > + unsigned reset_counter;
> > bool simulated;
> > int ret;
> >
> > intel_reset_gt_powersave(dev);
> >
> > mutex_lock(&dev->struct_mutex);
> > + atomic_clear_mask(I915_WEDGED, &error->reset_counter);
> > + reset_counter = atomic_inc_return(&error->reset_counter);
>
> This publishes the reset-complete too early for the modeset code I think.
> At least it crucially relies upon dev->struct_mutex serializing
> everything in our driver, and I don't like to cement that assumption in
> even more.
Hmm? It is already concreted in as the reset / continuation is ordered
with the struct_mutex. We have kicks in place for the modesetting code,
but we have not actually ordered that with anything inside the reset
recovery code. Judging by the few changes to i915_reset(), I am doubtful
that has actually been improved for atomic, so that it basically relies
on display being unaffected by anything but pending work.
> Why do we need to move that atomic_inc again?
The inc is to acknowledge the reset and to allow us to begin using the
device again (inside the reset func). It is the equivalent of adding
another bit for reload_in_reset. I moved it to the beginning for my
convenience.
> I guess what we could try is set it right after we've reset the hw, but
> before we start to re-initialize it. So move the atomic stuff below
> intel_gpu_reset, with some neat barrier again. Maybe we should even push
> i915_gem_reset down below that too. Not sure.
Sure, I liked the simplicity though :)
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > index d3609e111647..6ac9c80244fa 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -85,9 +85,7 @@ i915_gem_wait_for_error(struct i915_gpu_error *error)
> > {
> > int ret;
> >
> > -#define EXIT_COND (!i915_reset_in_progress(error) || \
> > - i915_terminally_wedged(error))
> > - if (EXIT_COND)
> > + if (!i915_reset_in_progress(error))
> > return 0;
> >
> > /*
> > @@ -96,17 +94,16 @@ i915_gem_wait_for_error(struct i915_gpu_error *error)
> > * we should simply try to bail out and fail as gracefully as possible.
> > */
> > ret = wait_event_interruptible_timeout(error->reset_queue,
> > - EXIT_COND,
> > + !i915_reset_in_progress(error),
> > 10*HZ);
> > if (ret == 0) {
> > DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
> > return -EIO;
> > } else if (ret < 0) {
> > return ret;
> > + } else {
> > + return 0;
> > }
> > -#undef EXIT_COND
> > -
> > - return 0;
>
> I like the existing color better ;-)
You would like
#define EXIT_COND (!i915_reset_in_progress(error))) ?
> > int
> > -i915_gem_check_wedge(struct i915_gpu_error *error,
> > +i915_gem_check_wedge(unsigned reset_counter,
> > bool interruptible)
> > {
> > - if (i915_reset_in_progress(error)) {
> > + if (__i915_reset_in_progress_or_wedged(reset_counter)) {
> > /* Non-interruptible callers can't handle -EAGAIN, hence return
> > * -EIO unconditionally for these. */
> > if (!interruptible)
> > return -EIO;
> >
> > /* Recovery complete, but the reset failed ... */
> > - if (i915_terminally_wedged(error))
> > + if (__i915_terminally_wedged(reset_counter))
> > return -EIO;
> >
> > - /*
> > - * Check if GPU Reset is in progress - we need intel_ring_begin
> > - * to work properly to reinit the hw state while the gpu is
> > - * still marked as reset-in-progress. Handle this with a flag.
> > - */
> > - if (!error->reload_in_reset)
> > - return -EAGAIN;
> > + return -EAGAIN;
>
> This only works because you move the check_wedge from ring_begin to
> wait_space, so assumes that we never change that again. Rather fragile
> imo.
Pardon? If you argue that intel_ring_begin() is a better place to check
you have misunderstood the reason behind the patch entirely. Note that
we still call this function to preserve ABI. The second reason for
checking in wait_for_space is that is the only place where we do care
about the masked pending reset.
> > @@ -1200,7 +1191,6 @@ static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
> > /**
> > * __i915_wait_request - wait until execution of request has finished
> > * @req: duh!
> > - * @reset_counter: reset sequence associated with the given request
> > * @interruptible: do an interruptible wait (normally yes)
> > * @timeout: in - how long to wait (NULL forever); out - how much time remaining
> > *
> > @@ -1215,7 +1205,6 @@ static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
> > * errno with remaining time filled in timeout argument.
> > */
> > int __i915_wait_request(struct drm_i915_gem_request *req,
> > - unsigned reset_counter,
> > bool interruptible,
> > s64 *timeout,
> > struct intel_rps_client *rps)
> > @@ -1264,12 +1253,12 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
> >
> > /* We need to check whether any gpu reset happened in between
> > * the caller grabbing the seqno and now ... */
> > - if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
> > - /* ... but upgrade the -EAGAIN to an -EIO if the gpu
> > - * is truely gone. */
> > - ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
> > - if (ret == 0)
> > - ret = -EAGAIN;
> > + if (req->reset_counter != i915_reset_counter(&dev_priv->gpu_error)) {
> > + /* As we do not requeue the request over a GPU reset,
> > + * if one does occur we know that the request is
> > + * effectively complete.
> > + */
> > + ret = 0;
> > break;
>
> This now no longer bails out straight when a reset is in progress with
> -EAGAIN. I fear for the deadlocks.
You fear incorrectly here. Either we hold the struct_mutex in which case
the reset waits and we complete our work without needing anything else,
or we may want to take the struct_mutex to complete our work and so may
end up waiting for the reset to complete. Either way the state of this
request is the same as to when the GPU reset actually occurs. There is
an inconsistency that we don't mark it as complete though, so we would
may try and wait on it again (only to find that the reset is in
progress and bail out again).
The issue is not a potential deadlock (because that would be an already
existing ABBA in the code) but resources that can be depleted by
requests.
> > @@ -2252,6 +2250,14 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> > if (ret)
> > return ret;
> >
> > + /* If the request was completed due to a GPU hang, we want to
> > + * error out before we continue to emit more commands to the GPU.
> > + */
> > + ret = i915_gem_check_wedge(i915_reset_counter(&to_i915(engine->dev)->gpu_error),
> > + to_i915(engine->dev)->mm.interruptible);
> > + if (ret)
> > + return ret;
>
> Don't we still have the problem with -EIO now here, just less likely than
> from intel_ring_begin?
What's the problem? intel_ring_begin() is supposed to return
-EIO/-EAGAIN.
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 12/12] drm/i915: Cache the reset_counter for the request
2015-11-24 21:43 ` Chris Wilson
@ 2015-11-25 9:12 ` Daniel Vetter
2015-11-25 12:17 ` Chris Wilson
2015-11-25 17:11 ` Chris Wilson
0 siblings, 2 replies; 41+ messages in thread
From: Daniel Vetter @ 2015-11-25 9:12 UTC (permalink / raw)
To: Chris Wilson, Daniel Vetter, intel-gfx
On Tue, Nov 24, 2015 at 09:43:32PM +0000, Chris Wilson wrote:
> On Tue, Nov 24, 2015 at 05:43:22PM +0100, Daniel Vetter wrote:
> > On Fri, Nov 20, 2015 at 12:43:52PM +0000, Chris Wilson wrote:
> > > Instead of querying the reset counter before every access to the ring,
> > > query it the first time we touch the ring, and do a final compare when
> > > submitting the request. For correctness, we need to then sanitize how
> > > the reset_counter is incremented to prevent broken submission and
> > > waiting across resets, in the process fixing the persistent -EIO we
> > > still see today on failed waits.
> >
> > tbh that explanation went straight over my head. Questions:
> > - Where do we wait again over a reset? With all the wakeups we should
> > catch them properly. I guess this needs the detailed scenario to help me
> > out, since I have dim memories that there is something wrong ;-)
>
> TDR. In the future (and in past speculative patches) we have proposed
> keeping requests over a reset and requeuing them. That is a complication
> to the simplification of bailing out from the wait. What I have in mind,
> is the recovery code has to fix up the request list somehow, though that
> will be fun.
But even with requeueing the waiters need to bail out and restart the
ioctl. So I don't see why requeueing of requests matter.
And my question was about what exactly is broken when waiting over a
reset? As long as we detect the reset and restart the ioctl we should pick
up any kinds of state fixups the reset work has done and recover
perfectly. Irrespective of whether the reset work has requeued some of the
requests or not.
> > - What precisely is the effect for waiters? I only see moving the
> > atomic_inc under the dev->struct_mutex, which shouldn't do a hole lot
> > for anyone. Plus not returning -EAGAIN when reset_in_progress, which
> > looks like it might result in missed wakeups and deadlocks with the
> > reset work.
>
> At the moment, I can trivially wedge the machine. This patch fixes that.
> The patch also ensures that we cannot raise unhandled errors from
> wait-request (EIO/EAGAIN handling has to be explicitly added to the
> caller).
Hm, how/where do we wedge the machine, and how does the fix work?
> The wait-request interface still has the wait-seqno legacy of having to
> acquire the reset_counter under the mutex before calling. That is quite
> hairy and causes a major complication later where we want to amalgamate
> waiters.
Yeah, that's a sensible change. But since I don't yet understand where
exactly the current logic results in a wedge gpu I can't convince myself
that the new one is ok.
> Re EAGAIN. No, it cannot result in missed wakeups since that is internal
> to the wait_request function, nor can it result in new deadlocks with the
> reset worker.
Yeah I think today with just struct_mutex it's impossible. But if we have
more locks the waiting thread could continue to grab more locks instead of
bailing out straight. And then the reset handler would be somewhat screwed
since it isn't guaranteed to make forward progress.
> > I /thought/ that the -EIO is from check_wedge in intel_ring_begin, but
> > that part seems essentially unchanged.
>
> For two reasons, we need to to protect the access to the ring, and you
> argued that (reporting of EIO from previous wedged GPUs) it was part of
> the ABI. The other ABI that I think is important, is the reporting of
> EIO if the user explicits waits on a request and it is incomplete (i.e.
> wait_ioctl).
Well then I don't get where the -EIO is from. That leaves a truly wedge
gpu as the cause, and for that case I don't get how it can happen by
accident with the current code.
> > Aside from all that, shuffling the atomic_inc (if I can convince myself
> > that it's safe) to avoid the reload_in_reset hack looks like a good
> > improvement.
>
> That's what I said at the time :-p
>
> > More confused comments below.
>
> A large proportion of the actual patch is spent trying to make using the
> atomic reset_counter safer (wrt to it changing values between multiple
> tests and subsequent action).
>
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index d83f35c8df34..107711ec956f 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -4415,7 +4415,7 @@ i915_wedged_get(void *data, u64 *val)
> > > struct drm_device *dev = data;
> > > struct drm_i915_private *dev_priv = dev->dev_private;
> > >
> > > - *val = atomic_read(&dev_priv->gpu_error.reset_counter);
> > > + *val = i915_terminally_wedged(&dev_priv->gpu_error);
> >
> > Don't we have a few tests left that look at this still?
>
> One. I strongly believe that the debug interface should not be reporting
> the reset_counter but the wedged status (as that is what it is called).
And that one only writes, so we're perfectly fine I think.
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > index ffd99d27fac7..5838882e10a1 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -841,23 +841,31 @@ int i915_resume_legacy(struct drm_device *dev)
> > > int i915_reset(struct drm_device *dev)
> > > {
> > > struct drm_i915_private *dev_priv = dev->dev_private;
> > > + struct i915_gpu_error *error = &dev_priv->gpu_error;
> > > + unsigned reset_counter;
> > > bool simulated;
> > > int ret;
> > >
> > > intel_reset_gt_powersave(dev);
> > >
> > > mutex_lock(&dev->struct_mutex);
> > > + atomic_clear_mask(I915_WEDGED, &error->reset_counter);
> > > + reset_counter = atomic_inc_return(&error->reset_counter);
> >
> > This publishes the reset-complete too early for the modeset code I think.
> > At least it crucially relies upon dev->struct_mutex serializing
> > everything in our driver, and I don't like to cement that assumption in
> > even more.
>
> Hmm? It is already concreted in as the reset / continuation is ordered
> with the struct_mutex. We have kicks in place for the modesetting code,
> but we have not actually ordered that with anything inside the reset
> recovery code. Judging by the few changes to i915_reset(), I am doubtful
> that has actually been improved for atomic, so that it basically relies
> on display being unaffected by anything but pending work.
Currently the reset/continuation is ordered with the 2-phase atomic_inc of
the reset counter, with the requirement that anyone who sees
reset_in_progress hauls out of the kernel asap. That most of gem is
serialized with struct_mutex is just a side-effect of the current gem
locking. With the current design we could rework gem locking and it should
all still work, with this approach we pretty much cement the BKL locking
approach I think.
> > Why do we need to move that atomic_inc again?
>
> The inc is to acknowledge the reset and to allow us to begin using the
> device again (inside the reset func). It is the equivalent of adding
> another bit for reload_in_reset. I moved it to the beginning for my
> convenience.
Ok, this needs a code comment I think.
But I thought that the crucial change was to move check_wedge from
ring_begin to wait_for_space and so move it out from ever being hit from
the reset code.
> > I guess what we could try is set it right after we've reset the hw, but
> > before we start to re-initialize it. So move the atomic stuff below
> > intel_gpu_reset, with some neat barrier again. Maybe we should even push
> > i915_gem_reset down below that too. Not sure.
>
> Sure, I liked the simplicity though :)
>
> > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > > index d3609e111647..6ac9c80244fa 100644
> > > --- a/drivers/gpu/drm/i915/i915_gem.c
> > > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > > @@ -85,9 +85,7 @@ i915_gem_wait_for_error(struct i915_gpu_error *error)
> > > {
> > > int ret;
> > >
> > > -#define EXIT_COND (!i915_reset_in_progress(error) || \
> > > - i915_terminally_wedged(error))
> > > - if (EXIT_COND)
> > > + if (!i915_reset_in_progress(error))
> > > return 0;
> > >
> > > /*
> > > @@ -96,17 +94,16 @@ i915_gem_wait_for_error(struct i915_gpu_error *error)
> > > * we should simply try to bail out and fail as gracefully as possible.
> > > */
> > > ret = wait_event_interruptible_timeout(error->reset_queue,
> > > - EXIT_COND,
> > > + !i915_reset_in_progress(error),
> > > 10*HZ);
> > > if (ret == 0) {
> > > DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
> > > return -EIO;
> > > } else if (ret < 0) {
> > > return ret;
> > > + } else {
> > > + return 0;
> > > }
> > > -#undef EXIT_COND
> > > -
> > > - return 0;
> >
> > I like the existing color better ;-)
>
> You would like
> #define EXIT_COND (!i915_reset_in_progress(error))) ?
>
> > > int
> > > -i915_gem_check_wedge(struct i915_gpu_error *error,
> > > +i915_gem_check_wedge(unsigned reset_counter,
> > > bool interruptible)
> > > {
> > > - if (i915_reset_in_progress(error)) {
> > > + if (__i915_reset_in_progress_or_wedged(reset_counter)) {
> > > /* Non-interruptible callers can't handle -EAGAIN, hence return
> > > * -EIO unconditionally for these. */
> > > if (!interruptible)
> > > return -EIO;
> > >
> > > /* Recovery complete, but the reset failed ... */
> > > - if (i915_terminally_wedged(error))
> > > + if (__i915_terminally_wedged(reset_counter))
> > > return -EIO;
> > >
> > > - /*
> > > - * Check if GPU Reset is in progress - we need intel_ring_begin
> > > - * to work properly to reinit the hw state while the gpu is
> > > - * still marked as reset-in-progress. Handle this with a flag.
> > > - */
> > > - if (!error->reload_in_reset)
> > > - return -EAGAIN;
> > > + return -EAGAIN;
> >
> > This only works because you move the check_wedge from ring_begin to
> > wait_space, so assumes that we never change that again. Rather fragile
> > imo.
>
> Pardon? If you argue that intel_ring_begin() is a better place to check
> you have misunderstood the reason behind the patch entirely. Note that
> we still call this function to preserve ABI. The second reason for
> checking in wait_for_space is that is the only place where we do care
> about the masked pending reset.
I looked at this under the assumption that the atomic_inc(reset_counter)
stays where it currently is.
> > > @@ -1200,7 +1191,6 @@ static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
> > > /**
> > > * __i915_wait_request - wait until execution of request has finished
> > > * @req: duh!
> > > - * @reset_counter: reset sequence associated with the given request
> > > * @interruptible: do an interruptible wait (normally yes)
> > > * @timeout: in - how long to wait (NULL forever); out - how much time remaining
> > > *
> > > @@ -1215,7 +1205,6 @@ static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
> > > * errno with remaining time filled in timeout argument.
> > > */
> > > int __i915_wait_request(struct drm_i915_gem_request *req,
> > > - unsigned reset_counter,
> > > bool interruptible,
> > > s64 *timeout,
> > > struct intel_rps_client *rps)
> > > @@ -1264,12 +1253,12 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
> > >
> > > /* We need to check whether any gpu reset happened in between
> > > * the caller grabbing the seqno and now ... */
> > > - if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
> > > - /* ... but upgrade the -EAGAIN to an -EIO if the gpu
> > > - * is truely gone. */
> > > - ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
> > > - if (ret == 0)
> > > - ret = -EAGAIN;
> > > + if (req->reset_counter != i915_reset_counter(&dev_priv->gpu_error)) {
> > > + /* As we do not requeue the request over a GPU reset,
> > > + * if one does occur we know that the request is
> > > + * effectively complete.
> > > + */
> > > + ret = 0;
> > > break;
> >
> > This now no longer bails out straight when a reset is in progress with
> > -EAGAIN. I fear for the deadlocks.
>
> You fear incorrectly here. Either we hold the struct_mutex in which case
> the reset waits and we complete our work without needing anything else,
> or we may want to take the struct_mutex to complete our work and so may
> end up waiting for the reset to complete. Either way the state of this
> request is the same as to when the GPU reset actually occurs. There is
> an inconsistency that we don't mark it as complete though, so we would
> may try and wait on it again (only to find that the reset is in
> progress and bail out again).
We only bail once per reset since we wait for resets to complete before
acquiring dev->struct_mutex. On the modeset side we unfortunately can't do
that since that code is in the drm core.
> The issue is not a potential deadlock (because that would be an already
> existing ABBA in the code) but resources that can be depleted by
> requests.
Besides deadlocks my other concern is that you encode reset behaviour
outside of the reset code here. If we unconditionally EAGAIN here, then
everyone will pick up whatever kind of fixup the reset code applied. Which
means requeueing of requests is contained to the reset logic. But if we
stop doing the unconditional EAGAIN then we have to fix up things here
too.
On the flip side I don't see what's easier by returning 0 here instead of
EAGAIN?
> > > @@ -2252,6 +2250,14 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> > > if (ret)
> > > return ret;
> > >
> > > + /* If the request was completed due to a GPU hang, we want to
> > > + * error out before we continue to emit more commands to the GPU.
> > > + */
> > > + ret = i915_gem_check_wedge(i915_reset_counter(&to_i915(engine->dev)->gpu_error),
> > > + to_i915(engine->dev)->mm.interruptible);
> > > + if (ret)
> > > + return ret;
> >
> > Don't we still have the problem with -EIO now here, just less likely than
> > from intel_ring_begin?
>
> What's the problem? intel_ring_begin() is supposed to return
> -EIO/-EAGAIN.
Hm, I thought the entire problem was that ring_begin can return -EIO,
since that's how mesa usually dies. But with your mail your saying that we
accidentally wedge the gpu, and that's the part I don't understand yet.
Probably best if I figure this out with an irc chat directly ;-)
But without that figured out I'm not sure how to best untangle the other
bits (specifically reload_in_reset) you're changing in here.
Thanks, Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 07/12] drm/i915: Rename request->ringbuf to request->ring
2015-11-24 15:25 ` Chris Wilson
@ 2015-11-25 10:22 ` Tvrtko Ursulin
0 siblings, 0 replies; 41+ messages in thread
From: Tvrtko Ursulin @ 2015-11-25 10:22 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 24/11/15 15:25, Chris Wilson wrote:
> On Tue, Nov 24, 2015 at 03:08:09PM +0000, Tvrtko Ursulin wrote:
>>
>> On 20/11/15 12:43, Chris Wilson wrote:
>>> Now that we have disambuigated ring and engine, we can use the clearer
>>> and more consistent name for the intel_ringbuffer pointer in the
>>> request.
>>>
>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>> ---
>>> drivers/gpu/drm/i915/i915_drv.h | 2 +-
>>> drivers/gpu/drm/i915/i915_gem.c | 28 +++---
>>> drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
>>> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +-
>>> drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +-
>>> drivers/gpu/drm/i915/intel_display.c | 10 +-
>>> drivers/gpu/drm/i915/intel_lrc.c | 149 ++++++++++++++---------------
>>> drivers/gpu/drm/i915/intel_mocs.c | 32 +++----
>>> drivers/gpu/drm/i915/intel_overlay.c | 42 ++++----
>>> drivers/gpu/drm/i915/intel_ringbuffer.c | 86 ++++++++---------
>>> 10 files changed, 178 insertions(+), 183 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>>> index 9ce8b3fcb3a0..b7eaa2deb437 100644
>>> --- a/drivers/gpu/drm/i915/i915_drv.h
>>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>>> @@ -2185,7 +2185,7 @@ struct drm_i915_gem_request {
>>> * context.
>>> */
>>> struct intel_context *ctx;
>>> - struct intel_ringbuffer *ringbuf;
>>> + struct intel_ringbuffer *ring;
>>
>> What was the problem with ringbuf? Struct is still called ringbuf
>> and the files as well after the patch series.
>
> It introduced a major naming clash with existing code. I am trying to
> remove the needlessly duplicated interfaces, and restore the historic
> naming conventions.
Ok my point was that I am not sure if it is worth renaming things a)
partially, and b) that ring is a good name for intel_ringbuffer. Ringbuf
sounds at least just as good, in fact better to me. So this renaming
feels like unnecessary churn. And the fact you don't even do all of them
in the patch series just reinforces that.
But as Daniel already approved this it doesn't really matter apart for
"for the record".
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 12/12] drm/i915: Cache the reset_counter for the request
2015-11-25 9:12 ` Daniel Vetter
@ 2015-11-25 12:17 ` Chris Wilson
2015-11-26 9:21 ` Daniel Vetter
2015-11-25 17:11 ` Chris Wilson
1 sibling, 1 reply; 41+ messages in thread
From: Chris Wilson @ 2015-11-25 12:17 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Wed, Nov 25, 2015 at 10:12:53AM +0100, Daniel Vetter wrote:
> On Tue, Nov 24, 2015 at 09:43:32PM +0000, Chris Wilson wrote:
> > On Tue, Nov 24, 2015 at 05:43:22PM +0100, Daniel Vetter wrote:
> > > On Fri, Nov 20, 2015 at 12:43:52PM +0000, Chris Wilson wrote:
> > > > Instead of querying the reset counter before every access to the ring,
> > > > query it the first time we touch the ring, and do a final compare when
> > > > submitting the request. For correctness, we need to then sanitize how
> > > > the reset_counter is incremented to prevent broken submission and
> > > > waiting across resets, in the process fixing the persistent -EIO we
> > > > still see today on failed waits.
> > >
> > > tbh that explanation went straight over my head. Questions:
> > > - Where do we wait again over a reset? With all the wakeups we should
> > > catch them properly. I guess this needs the detailed scenario to help me
> > > out, since I have dim memories that there is something wrong ;-)
> >
> > TDR. In the future (and in past speculative patches) we have proposed
> > keeping requests over a reset and requeuing them. That is a complication
> > to the simplification of bailing out from the wait. What I have in mind,
> > is the recovery code has to fix up the request list somehow, though that
> > will be fun.
>
> But even with requeueing the waiters need to bail out and restart the
> ioctl. So I don't see why requeueing of requests matter.
But why should the waiter even wake up? It is not holding any locks, all
it is just waiting for the request to complete. It is only those holding
a lock required to reset that we need to kick.
> And my question was about what exactly is broken when waiting over a
> reset? As long as we detect the reset and restart the ioctl we should pick
> up any kinds of state fixups the reset work has done and recover
> perfectly. Irrespective of whether the reset work has requeued some of the
> requests or not.
But... The reset handler clears the requests, we cannot wait over a
reset. So waiting over a reset today is clearly a bug in the kernel.
Only in the future do we contemplate situations where a request may
survive a reset.
> > > - What precisely is the effect for waiters? I only see moving the
> > > atomic_inc under the dev->struct_mutex, which shouldn't do a hole lot
> > > for anyone. Plus not returning -EAGAIN when reset_in_progress, which
> > > looks like it might result in missed wakeups and deadlocks with the
> > > reset work.
> >
> > At the moment, I can trivially wedge the machine. This patch fixes that.
> > The patch also ensures that we cannot raise unhandled errors from
> > wait-request (EIO/EAGAIN handling has to be explicitly added to the
> > caller).
>
> Hm, how/where do we wedge the machine, and how does the fix work?
Being able to reset a previously wedged machine.
> > The wait-request interface still has the wait-seqno legacy of having to
> > acquire the reset_counter under the mutex before calling. That is quite
> > hairy and causes a major complication later where we want to amalgamate
> > waiters.
>
> Yeah, that's a sensible change. But since I don't yet understand where
> exactly the current logic results in a wedge gpu I can't convince myself
> that the new one is ok.
>
> > Re EAGAIN. No, it cannot result in missed wakeups since that is internal
> > to the wait_request function, nor can it result in new deadlocks with the
> > reset worker.
>
> Yeah I think today with just struct_mutex it's impossible. But if we have
> more locks the waiting thread could continue to grab more locks instead of
> bailing out straight. And then the reset handler would be somewhat screwed
> since it isn't guaranteed to make forward progress.
So basically if you add a deadlock/livelock, it may deadlock/livelock.
> > > I /thought/ that the -EIO is from check_wedge in intel_ring_begin, but
> > > that part seems essentially unchanged.
> >
> > For two reasons, we need to to protect the access to the ring, and you
> > argued that (reporting of EIO from previous wedged GPUs) it was part of
> > the ABI. The other ABI that I think is important, is the reporting of
> > EIO if the user explicits waits on a request and it is incomplete (i.e.
> > wait_ioctl).
>
> Well then I don't get where the -EIO is from. That leaves a truly wedge
> gpu as the cause, and for that case I don't get how it can happen by
> accident with the current code.
We fail a reset, or to recover. Happens often enough.
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > > index ffd99d27fac7..5838882e10a1 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > > @@ -841,23 +841,31 @@ int i915_resume_legacy(struct drm_device *dev)
> > > > int i915_reset(struct drm_device *dev)
> > > > {
> > > > struct drm_i915_private *dev_priv = dev->dev_private;
> > > > + struct i915_gpu_error *error = &dev_priv->gpu_error;
> > > > + unsigned reset_counter;
> > > > bool simulated;
> > > > int ret;
> > > >
> > > > intel_reset_gt_powersave(dev);
> > > >
> > > > mutex_lock(&dev->struct_mutex);
> > > > + atomic_clear_mask(I915_WEDGED, &error->reset_counter);
> > > > + reset_counter = atomic_inc_return(&error->reset_counter);
> > >
> > > This publishes the reset-complete too early for the modeset code I think.
> > > At least it crucially relies upon dev->struct_mutex serializing
> > > everything in our driver, and I don't like to cement that assumption in
> > > even more.
> >
> > Hmm? It is already concreted in as the reset / continuation is ordered
> > with the struct_mutex. We have kicks in place for the modesetting code,
> > but we have not actually ordered that with anything inside the reset
> > recovery code. Judging by the few changes to i915_reset(), I am doubtful
> > that has actually been improved for atomic, so that it basically relies
> > on display being unaffected by anything but pending work.
>
> Currently the reset/continuation is ordered with the 2-phase atomic_inc of
> the reset counter, with the requirement that anyone who sees
> reset_in_progress hauls out of the kernel asap. That most of gem is
> serialized with struct_mutex is just a side-effect of the current gem
> locking. With the current design we could rework gem locking and it should
> all still work, with this approach we pretty much cement the BKL locking
> approach I think.
No. It doesn't add anything more to the scheme. All it does is change
the order in which the second increment is applied so that after the
HW/SW reset happens we can start using it from inside the reset handler
to reinitialise the state.
> > > Why do we need to move that atomic_inc again?
> >
> > The inc is to acknowledge the reset and to allow us to begin using the
> > device again (inside the reset func). It is the equivalent of adding
> > another bit for reload_in_reset. I moved it to the beginning for my
> > convenience.
>
> Ok, this needs a code comment I think.
>
> But I thought that the crucial change was to move check_wedge from
> ring_begin to wait_for_space and so move it out from ever being hit from
> the reset code.
No. That has nothing to do with the reset code, as by the time we ever
call intel_ring_begin() in the recovery code, all previous
waits/requests are completed i.e. (excluding execlists bugs ahem) the
rings should be empty.
> > > > @@ -1200,7 +1191,6 @@ static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
> > > > /**
> > > > * __i915_wait_request - wait until execution of request has finished
> > > > * @req: duh!
> > > > - * @reset_counter: reset sequence associated with the given request
> > > > * @interruptible: do an interruptible wait (normally yes)
> > > > * @timeout: in - how long to wait (NULL forever); out - how much time remaining
> > > > *
> > > > @@ -1215,7 +1205,6 @@ static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
> > > > * errno with remaining time filled in timeout argument.
> > > > */
> > > > int __i915_wait_request(struct drm_i915_gem_request *req,
> > > > - unsigned reset_counter,
> > > > bool interruptible,
> > > > s64 *timeout,
> > > > struct intel_rps_client *rps)
> > > > @@ -1264,12 +1253,12 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
> > > >
> > > > /* We need to check whether any gpu reset happened in between
> > > > * the caller grabbing the seqno and now ... */
> > > > - if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
> > > > - /* ... but upgrade the -EAGAIN to an -EIO if the gpu
> > > > - * is truely gone. */
> > > > - ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
> > > > - if (ret == 0)
> > > > - ret = -EAGAIN;
> > > > + if (req->reset_counter != i915_reset_counter(&dev_priv->gpu_error)) {
> > > > + /* As we do not requeue the request over a GPU reset,
> > > > + * if one does occur we know that the request is
> > > > + * effectively complete.
> > > > + */
> > > > + ret = 0;
> > > > break;
> > >
> > > This now no longer bails out straight when a reset is in progress with
> > > -EAGAIN. I fear for the deadlocks.
> >
> > You fear incorrectly here. Either we hold the struct_mutex in which case
> > the reset waits and we complete our work without needing anything else,
> > or we may want to take the struct_mutex to complete our work and so may
> > end up waiting for the reset to complete. Either way the state of this
> > request is the same as to when the GPU reset actually occurs. There is
> > an inconsistency that we don't mark it as complete though, so we would
> > may try and wait on it again (only to find that the reset is in
> > progress and bail out again).
>
> We only bail once per reset since we wait for resets to complete before
> acquiring dev->struct_mutex. On the modeset side we unfortunately can't do
> that since that code is in the drm core.
>
> > The issue is not a potential deadlock (because that would be an already
> > existing ABBA in the code) but resources that can be depleted by
> > requests.
>
> Besides deadlocks my other concern is that you encode reset behaviour
> outside of the reset code here. If we unconditionally EAGAIN here, then
> everyone will pick up whatever kind of fixup the reset code applied. Which
> means requeueing of requests is contained to the reset logic. But if we
> stop doing the unconditional EAGAIN then we have to fix up things here
> too.
>
> On the flip side I don't see what's easier by returning 0 here instead of
> EAGAIN?
My fundamental argument for the last 5 years is that resets complete
requests, i.e. i915_wait_seqno/i915_wait_request should report 0 as the
object is no longer active by the GPU. Only in special circumstances do
we actually care that a reset happened (ABI), and rather than encode
that logic inside the core, that is better expressed as exceptions in
the caller.
e.g. set-to-domain works correctly even if the last request on the
object ended in a hang (and from that we can deduce that a very large
proportion of the API is also correct.)
From my perspective, by completing the requests following a hang, we
make the kernel and userspace much more fault tolerant.
> > > > @@ -2252,6 +2250,14 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> > > > if (ret)
> > > > return ret;
> > > >
> > > > + /* If the request was completed due to a GPU hang, we want to
> > > > + * error out before we continue to emit more commands to the GPU.
> > > > + */
> > > > + ret = i915_gem_check_wedge(i915_reset_counter(&to_i915(engine->dev)->gpu_error),
> > > > + to_i915(engine->dev)->mm.interruptible);
> > > > + if (ret)
> > > > + return ret;
> > >
> > > Don't we still have the problem with -EIO now here, just less likely than
> > > from intel_ring_begin?
> >
> > What's the problem? intel_ring_begin() is supposed to return
> > -EIO/-EAGAIN.
>
> Hm, I thought the entire problem was that ring_begin can return -EIO,
> since that's how mesa usually dies. But with your mail your saying that we
> accidentally wedge the gpu, and that's the part I don't understand yet.
Nah, mesa dies all the time from unchecked errors elsewhere. It just
calls fprintf/exit on intel_do_flush_locked(), so that is the visible one.
By the way, how are you getting on reviewing my mesa patches to fix that?
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 12/12] drm/i915: Cache the reset_counter for the request
2015-11-25 9:12 ` Daniel Vetter
2015-11-25 12:17 ` Chris Wilson
@ 2015-11-25 17:11 ` Chris Wilson
1 sibling, 0 replies; 41+ messages in thread
From: Chris Wilson @ 2015-11-25 17:11 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Wed, Nov 25, 2015 at 10:12:53AM +0100, Daniel Vetter wrote:
> On Tue, Nov 24, 2015 at 09:43:32PM +0000, Chris Wilson wrote:
> > The wait-request interface still has the wait-seqno legacy of having to
> > acquire the reset_counter under the mutex before calling. That is quite
> > hairy and causes a major complication later where we want to amalgamate
> > waiters.
>
> Yeah, that's a sensible change. But since I don't yet understand where
> exactly the current logic results in a wedge gpu I can't convince myself
> that the new one is ok.
Just to show where I am going with the interface change and why I think
it so important (other than it removes a hairy dance that we've have had
to copy all around the code):
http://cgit.freedesktop.org/~ickle/linux-2.6/commit/?h=nightly&id=75e73616f72f14ab82037adb1b2b054e2e500c21
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 12/12] drm/i915: Cache the reset_counter for the request
2015-11-25 12:17 ` Chris Wilson
@ 2015-11-26 9:21 ` Daniel Vetter
2015-11-26 9:50 ` Chris Wilson
0 siblings, 1 reply; 41+ messages in thread
From: Daniel Vetter @ 2015-11-26 9:21 UTC (permalink / raw)
To: Chris Wilson, Daniel Vetter, intel-gfx
On Wed, Nov 25, 2015 at 12:17:08PM +0000, Chris Wilson wrote:
> On Wed, Nov 25, 2015 at 10:12:53AM +0100, Daniel Vetter wrote:
> > On Tue, Nov 24, 2015 at 09:43:32PM +0000, Chris Wilson wrote:
> > > On Tue, Nov 24, 2015 at 05:43:22PM +0100, Daniel Vetter wrote:
> > > > On Fri, Nov 20, 2015 at 12:43:52PM +0000, Chris Wilson wrote:
> > > > > Instead of querying the reset counter before every access to the ring,
> > > > > query it the first time we touch the ring, and do a final compare when
> > > > > submitting the request. For correctness, we need to then sanitize how
> > > > > the reset_counter is incremented to prevent broken submission and
> > > > > waiting across resets, in the process fixing the persistent -EIO we
> > > > > still see today on failed waits.
> > > >
> > > > tbh that explanation went straight over my head. Questions:
> > > > - Where do we wait again over a reset? With all the wakeups we should
> > > > catch them properly. I guess this needs the detailed scenario to help me
> > > > out, since I have dim memories that there is something wrong ;-)
> > >
> > > TDR. In the future (and in past speculative patches) we have proposed
> > > keeping requests over a reset and requeuing them. That is a complication
> > > to the simplification of bailing out from the wait. What I have in mind,
> > > is the recovery code has to fix up the request list somehow, though that
> > > will be fun.
> >
> > But even with requeueing the waiters need to bail out and restart the
> > ioctl. So I don't see why requeueing of requests matter.
>
> But why should the waiter even wake up? It is not holding any locks, all
> it is just waiting for the request to complete. It is only those holding
> a lock required to reset that we need to kick.
Because the request might not actually be completed when we do partial
resets like with TDR. And then we'd have to undo this.
> > And my question was about what exactly is broken when waiting over a
> > reset? As long as we detect the reset and restart the ioctl we should pick
> > up any kinds of state fixups the reset work has done and recover
> > perfectly. Irrespective of whether the reset work has requeued some of the
> > requests or not.
>
> But... The reset handler clears the requests, we cannot wait over a
> reset. So waiting over a reset today is clearly a bug in the kernel.
>
> Only in the future do we contemplate situations where a request may
> survive a reset.
I think I phrased my question badly: What's broken with current waiters
racing against resets? Currently the should all get woken and restart, and
that seems to work. It does create some ioctl restart work when a reset
happens, but I think that overhead is justified given that it allows us to
have no knowledge of how exactly we reset hw and sw outside of reset
functions.
> > > > - What precisely is the effect for waiters? I only see moving the
> > > > atomic_inc under the dev->struct_mutex, which shouldn't do a hole lot
> > > > for anyone. Plus not returning -EAGAIN when reset_in_progress, which
> > > > looks like it might result in missed wakeups and deadlocks with the
> > > > reset work.
> > >
> > > At the moment, I can trivially wedge the machine. This patch fixes that.
> > > The patch also ensures that we cannot raise unhandled errors from
> > > wait-request (EIO/EAGAIN handling has to be explicitly added to the
> > > caller).
> >
> > Hm, how/where do we wedge the machine, and how does the fix work?
>
> Being able to reset a previously wedged machine.
Ok, I think I get that problem now, after looking at gem_eio work.
echo 1 > i915_wedged seems to have been broken since years. I haven't ever
noticed that since I generally just kick the machine and restart when that
happens.
> > > The wait-request interface still has the wait-seqno legacy of having to
> > > acquire the reset_counter under the mutex before calling. That is quite
> > > hairy and causes a major complication later where we want to amalgamate
> > > waiters.
> >
> > Yeah, that's a sensible change. But since I don't yet understand where
> > exactly the current logic results in a wedge gpu I can't convince myself
> > that the new one is ok.
> >
> > > Re EAGAIN. No, it cannot result in missed wakeups since that is internal
> > > to the wait_request function, nor can it result in new deadlocks with the
> > > reset worker.
> >
> > Yeah I think today with just struct_mutex it's impossible. But if we have
> > more locks the waiting thread could continue to grab more locks instead of
> > bailing out straight. And then the reset handler would be somewhat screwed
> > since it isn't guaranteed to make forward progress.
>
> So basically if you add a deadlock/livelock, it may deadlock/livelock.
The two-phase reset logic is some kind of hand-rolled special lock which
makes sure nothing bad happens. As long as it's really two-phase.
Essentially reset_in_progress means "everyone get of locks and stay of
locks". With some small short-lived exceptions here and there (and well
not so short-lived ones).
Of course we can just write reset code that doesn't deadlock, but given
our history in this area I much prefer something that's more obviously
correct.
> > > > I /thought/ that the -EIO is from check_wedge in intel_ring_begin, but
> > > > that part seems essentially unchanged.
> > >
> > > For two reasons, we need to to protect the access to the ring, and you
> > > argued that (reporting of EIO from previous wedged GPUs) it was part of
> > > the ABI. The other ABI that I think is important, is the reporting of
> > > EIO if the user explicits waits on a request and it is incomplete (i.e.
> > > wait_ioctl).
> >
> > Well then I don't get where the -EIO is from. That leaves a truly wedge
> > gpu as the cause, and for that case I don't get how it can happen by
> > accident with the current code.
>
> We fail a reset, or to recover. Happens often enough.
Ok, looking at gem_eio the only case where we put out an EIO and shouldn't
seems to be set_domain_ioctl. Is that right?
Well there's all the modeset stuff, and that just became a bit worse with
Maarten's recent changes. So probably we need the same -EIO eating there
too.
> > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > > > > index ffd99d27fac7..5838882e10a1 100644
> > > > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > > > @@ -841,23 +841,31 @@ int i915_resume_legacy(struct drm_device *dev)
> > > > > int i915_reset(struct drm_device *dev)
> > > > > {
> > > > > struct drm_i915_private *dev_priv = dev->dev_private;
> > > > > + struct i915_gpu_error *error = &dev_priv->gpu_error;
> > > > > + unsigned reset_counter;
> > > > > bool simulated;
> > > > > int ret;
> > > > >
> > > > > intel_reset_gt_powersave(dev);
> > > > >
> > > > > mutex_lock(&dev->struct_mutex);
> > > > > + atomic_clear_mask(I915_WEDGED, &error->reset_counter);
> > > > > + reset_counter = atomic_inc_return(&error->reset_counter);
> > > >
> > > > This publishes the reset-complete too early for the modeset code I think.
> > > > At least it crucially relies upon dev->struct_mutex serializing
> > > > everything in our driver, and I don't like to cement that assumption in
> > > > even more.
> > >
> > > Hmm? It is already concreted in as the reset / continuation is ordered
> > > with the struct_mutex. We have kicks in place for the modesetting code,
> > > but we have not actually ordered that with anything inside the reset
> > > recovery code. Judging by the few changes to i915_reset(), I am doubtful
> > > that has actually been improved for atomic, so that it basically relies
> > > on display being unaffected by anything but pending work.
> >
> > Currently the reset/continuation is ordered with the 2-phase atomic_inc of
> > the reset counter, with the requirement that anyone who sees
> > reset_in_progress hauls out of the kernel asap. That most of gem is
> > serialized with struct_mutex is just a side-effect of the current gem
> > locking. With the current design we could rework gem locking and it should
> > all still work, with this approach we pretty much cement the BKL locking
> > approach I think.
>
> No. It doesn't add anything more to the scheme. All it does is change
> the order in which the second increment is applied so that after the
> HW/SW reset happens we can start using it from inside the reset handler
> to reinitialise the state.
Well we can make that work, but it still feels like trading considerable
amounts of complexity to get rid of reload_in_reset. Well it's not really
any complexity right now with the BKL we have, but I don't see things as
that simple when/if we ever split things up.
> > > > Why do we need to move that atomic_inc again?
> > >
> > > The inc is to acknowledge the reset and to allow us to begin using the
> > > device again (inside the reset func). It is the equivalent of adding
> > > another bit for reload_in_reset. I moved it to the beginning for my
> > > convenience.
> >
> > Ok, this needs a code comment I think.
> >
> > But I thought that the crucial change was to move check_wedge from
> > ring_begin to wait_for_space and so move it out from ever being hit from
> > the reset code.
>
> No. That has nothing to do with the reset code, as by the time we ever
> call intel_ring_begin() in the recovery code, all previous
> waits/requests are completed i.e. (excluding execlists bugs ahem) the
> rings should be empty.
>
> > > > > @@ -1200,7 +1191,6 @@ static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
> > > > > /**
> > > > > * __i915_wait_request - wait until execution of request has finished
> > > > > * @req: duh!
> > > > > - * @reset_counter: reset sequence associated with the given request
> > > > > * @interruptible: do an interruptible wait (normally yes)
> > > > > * @timeout: in - how long to wait (NULL forever); out - how much time remaining
> > > > > *
> > > > > @@ -1215,7 +1205,6 @@ static int __i915_spin_request(struct drm_i915_gem_request *req, int state)
> > > > > * errno with remaining time filled in timeout argument.
> > > > > */
> > > > > int __i915_wait_request(struct drm_i915_gem_request *req,
> > > > > - unsigned reset_counter,
> > > > > bool interruptible,
> > > > > s64 *timeout,
> > > > > struct intel_rps_client *rps)
> > > > > @@ -1264,12 +1253,12 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
> > > > >
> > > > > /* We need to check whether any gpu reset happened in between
> > > > > * the caller grabbing the seqno and now ... */
> > > > > - if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
> > > > > - /* ... but upgrade the -EAGAIN to an -EIO if the gpu
> > > > > - * is truely gone. */
> > > > > - ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
> > > > > - if (ret == 0)
> > > > > - ret = -EAGAIN;
> > > > > + if (req->reset_counter != i915_reset_counter(&dev_priv->gpu_error)) {
> > > > > + /* As we do not requeue the request over a GPU reset,
> > > > > + * if one does occur we know that the request is
> > > > > + * effectively complete.
> > > > > + */
> > > > > + ret = 0;
> > > > > break;
> > > >
> > > > This now no longer bails out straight when a reset is in progress with
> > > > -EAGAIN. I fear for the deadlocks.
> > >
> > > You fear incorrectly here. Either we hold the struct_mutex in which case
> > > the reset waits and we complete our work without needing anything else,
> > > or we may want to take the struct_mutex to complete our work and so may
> > > end up waiting for the reset to complete. Either way the state of this
> > > request is the same as to when the GPU reset actually occurs. There is
> > > an inconsistency that we don't mark it as complete though, so we would
> > > may try and wait on it again (only to find that the reset is in
> > > progress and bail out again).
> >
> > We only bail once per reset since we wait for resets to complete before
> > acquiring dev->struct_mutex. On the modeset side we unfortunately can't do
> > that since that code is in the drm core.
> >
> > > The issue is not a potential deadlock (because that would be an already
> > > existing ABBA in the code) but resources that can be depleted by
> > > requests.
> >
> > Besides deadlocks my other concern is that you encode reset behaviour
> > outside of the reset code here. If we unconditionally EAGAIN here, then
> > everyone will pick up whatever kind of fixup the reset code applied. Which
> > means requeueing of requests is contained to the reset logic. But if we
> > stop doing the unconditional EAGAIN then we have to fix up things here
> > too.
> >
> > On the flip side I don't see what's easier by returning 0 here instead of
> > EAGAIN?
>
> My fundamental argument for the last 5 years is that resets complete
> requests, i.e. i915_wait_seqno/i915_wait_request should report 0 as the
> object is no longer active by the GPU. Only in special circumstances do
> we actually care that a reset happened (ABI), and rather than encode
> that logic inside the core, that is better expressed as exceptions in
> the caller.
>
> e.g. set-to-domain works correctly even if the last request on the
> object ended in a hang (and from that we can deduce that a very large
> proportion of the API is also correct.)
>
> From my perspective, by completing the requests following a hang, we
> make the kernel and userspace much more fault tolerant.
Userspace must restart when we return -EAGAIN. That's also ABI. Which
means yes it will only ever see 0 here.
What we can do is drop the check_wedge out of wait_request, since that
should make a pile of things more robust. But imo the -EAGAIN really needs
to stay. It doesn't hurt, userspace never sees it, and we keep
encapsulation of how exactly sw/hw reset is done contained in the reset
worker.
I'll respin and retest my gem_eio patch with removing check_wedge from
wait_request, but keeping the -EAGAIN.
> > > > > @@ -2252,6 +2250,14 @@ static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
> > > > > if (ret)
> > > > > return ret;
> > > > >
> > > > > + /* If the request was completed due to a GPU hang, we want to
> > > > > + * error out before we continue to emit more commands to the GPU.
> > > > > + */
> > > > > + ret = i915_gem_check_wedge(i915_reset_counter(&to_i915(engine->dev)->gpu_error),
> > > > > + to_i915(engine->dev)->mm.interruptible);
> > > > > + if (ret)
> > > > > + return ret;
> > > >
> > > > Don't we still have the problem with -EIO now here, just less likely than
> > > > from intel_ring_begin?
> > >
> > > What's the problem? intel_ring_begin() is supposed to return
> > > -EIO/-EAGAIN.
> >
> > Hm, I thought the entire problem was that ring_begin can return -EIO,
> > since that's how mesa usually dies. But with your mail your saying that we
> > accidentally wedge the gpu, and that's the part I don't understand yet.
>
> Nah, mesa dies all the time from unchecked errors elsewhere. It just
> calls fprintf/exit on intel_do_flush_locked(), so that is the visible one.
> By the way, how are you getting on reviewing my mesa patches to fix that?
Hm, I hoped mesa folks would do that ;-)
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [PATCH 12/12] drm/i915: Cache the reset_counter for the request
2015-11-26 9:21 ` Daniel Vetter
@ 2015-11-26 9:50 ` Chris Wilson
0 siblings, 0 replies; 41+ messages in thread
From: Chris Wilson @ 2015-11-26 9:50 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx
On Thu, Nov 26, 2015 at 10:21:38AM +0100, Daniel Vetter wrote:
> On Wed, Nov 25, 2015 at 12:17:08PM +0000, Chris Wilson wrote:
> > On Wed, Nov 25, 2015 at 10:12:53AM +0100, Daniel Vetter wrote:
> > > On Tue, Nov 24, 2015 at 09:43:32PM +0000, Chris Wilson wrote:
> > > > On Tue, Nov 24, 2015 at 05:43:22PM +0100, Daniel Vetter wrote:
> > > > > On Fri, Nov 20, 2015 at 12:43:52PM +0000, Chris Wilson wrote:
> > > > > > Instead of querying the reset counter before every access to the ring,
> > > > > > query it the first time we touch the ring, and do a final compare when
> > > > > > submitting the request. For correctness, we need to then sanitize how
> > > > > > the reset_counter is incremented to prevent broken submission and
> > > > > > waiting across resets, in the process fixing the persistent -EIO we
> > > > > > still see today on failed waits.
> > > > >
> > > > > tbh that explanation went straight over my head. Questions:
> > > > > - Where do we wait again over a reset? With all the wakeups we should
> > > > > catch them properly. I guess this needs the detailed scenario to help me
> > > > > out, since I have dim memories that there is something wrong ;-)
> > > >
> > > > TDR. In the future (and in past speculative patches) we have proposed
> > > > keeping requests over a reset and requeuing them. That is a complication
> > > > to the simplification of bailing out from the wait. What I have in mind,
> > > > is the recovery code has to fix up the request list somehow, though that
> > > > will be fun.
> > >
> > > But even with requeueing the waiters need to bail out and restart the
> > > ioctl. So I don't see why requeueing of requests matter.
> >
> > But why should the waiter even wake up? It is not holding any locks, all
> > it is just waiting for the request to complete. It is only those holding
> > a lock required to reset that we need to kick.
>
> Because the request might not actually be completed when we do partial
> resets like with TDR. And then we'd have to undo this.
I don't think you have to undo. TDR and wait_request already doesn't
mesh well, so it needs to be solved either way. More than likely we
simply don't increment the global reset counter and just bump the seqno
for skipped requests.
> > > And my question was about what exactly is broken when waiting over a
> > > reset? As long as we detect the reset and restart the ioctl we should pick
> > > up any kinds of state fixups the reset work has done and recover
> > > perfectly. Irrespective of whether the reset work has requeued some of the
> > > requests or not.
> >
> > But... The reset handler clears the requests, we cannot wait over a
> > reset. So waiting over a reset today is clearly a bug in the kernel.
> >
> > Only in the future do we contemplate situations where a request may
> > survive a reset.
>
> I think I phrased my question badly: What's broken with current waiters
> racing against resets? Currently the should all get woken and restart, and
> that seems to work. It does create some ioctl restart work when a reset
> happens, but I think that overhead is justified given that it allows us to
> have no knowledge of how exactly we reset hw and sw outside of reset
> functions.
Good. Because that doesn't change.
> > > > > - What precisely is the effect for waiters? I only see moving the
> > > > > atomic_inc under the dev->struct_mutex, which shouldn't do a hole lot
> > > > > for anyone. Plus not returning -EAGAIN when reset_in_progress, which
> > > > > looks like it might result in missed wakeups and deadlocks with the
> > > > > reset work.
> > > >
> > > > At the moment, I can trivially wedge the machine. This patch fixes that.
> > > > The patch also ensures that we cannot raise unhandled errors from
> > > > wait-request (EIO/EAGAIN handling has to be explicitly added to the
> > > > caller).
> > >
> > > Hm, how/where do we wedge the machine, and how does the fix work?
> >
> > Being able to reset a previously wedged machine.
>
> Ok, I think I get that problem now, after looking at gem_eio work.
> echo 1 > i915_wedged seems to have been broken since years. I haven't ever
> noticed that since I generally just kick the machine and restart when that
> happens.
It has been my get-of-jail card for a long time: manually grab the GPU
state and reset? Yes, please.
> The two-phase reset logic is some kind of hand-rolled special lock which
> makes sure nothing bad happens. As long as it's really two-phase.
> Essentially reset_in_progress means "everyone get of locks and stay of
> locks". With some small short-lived exceptions here and there (and well
> not so short-lived ones).
>
> Of course we can just write reset code that doesn't deadlock, but given
> our history in this area I much prefer something that's more obviously
> correct.
No. It is nothing more than a crude leaky hack to allow you call the ring
accessors from inside the reset handler.
> > > > > I /thought/ that the -EIO is from check_wedge in intel_ring_begin, but
> > > > > that part seems essentially unchanged.
> > > >
> > > > For two reasons, we need to to protect the access to the ring, and you
> > > > argued that (reporting of EIO from previous wedged GPUs) it was part of
> > > > the ABI. The other ABI that I think is important, is the reporting of
> > > > EIO if the user explicits waits on a request and it is incomplete (i.e.
> > > > wait_ioctl).
> > >
> > > Well then I don't get where the -EIO is from. That leaves a truly wedge
> > > gpu as the cause, and for that case I don't get how it can happen by
> > > accident with the current code.
> >
> > We fail a reset, or to recover. Happens often enough.
>
> Ok, looking at gem_eio the only case where we put out an EIO and shouldn't
> seems to be set_domain_ioctl. Is that right?
Not really. That we see EIO from set-domain is just fallout from the igt
framework. The only things gem_eio tests are the ABI points where EIO is
expected to see, it doesn't contain the negative tests for all the paths
that should never generate EIO.
> Well there's all the modeset stuff, and that just became a bit worse with
> Maarten's recent changes. So probably we need the same -EIO eating there
> too.
I'm puzzled, since i915_reset() only handles GPU reset not the display
engine. The modesetting code should only have to worry about its
interactions with the GPU (any MI commands it is waiting on, or
activity) both of which should be through requests.
> > No. It doesn't add anything more to the scheme. All it does is change
> > the order in which the second increment is applied so that after the
> > HW/SW reset happens we can start using it from inside the reset handler
> > to reinitialise the state.
>
> Well we can make that work, but it still feels like trading considerable
> amounts of complexity to get rid of reload_in_reset. Well it's not really
> any complexity right now with the BKL we have, but I don't see things as
> that simple when/if we ever split things up.
I disagree (now and then). reload_in_reset is crude and adds fragility
to the reset mechanism that you have had had to add extra code to handle.
> > From my perspective, by completing the requests following a hang, we
> > make the kernel and userspace much more fault tolerant.
>
> Userspace must restart when we return -EAGAIN. That's also ABI. Which
> means yes it will only ever see 0 here.
Hahahaha. My point is that the kernel breaks quite often. It doesn't
matter if userspace doesn't die if the kernel doesn't behave correctly
if it still means the screen is frozen. Having access to the screen
without the GPU or driver breakage is paramount to a robust system.
> What we can do is drop the check_wedge out of wait_request, since that
> should make a pile of things more robust. But imo the -EAGAIN really needs
> to stay. It doesn't hurt, userspace never sees it, and we keep
> encapsulation of how exactly sw/hw reset is done contained in the reset
> worker.
Why though? That is skipping over the question of "when is a request
complete" that I feel is central to the argument here. You still need
the code to decide whether to return 0 or EAGAIN, or else you still
cause false WARN.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 41+ messages in thread
end of thread, other threads:[~2015-11-26 9:50 UTC | newest]
Thread overview: 41+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-11-20 12:43 [PATCH 01/12] drm/i915: Convert i915_semaphores_is_enabled over to drm_i915_private Chris Wilson
2015-11-20 12:43 ` [PATCH 02/12] drm/i915: Use the new rq->i915 field where appropriate Chris Wilson
2015-11-24 13:57 ` Daniel Vetter
2015-11-24 14:23 ` Chris Wilson
2015-11-24 14:41 ` Daniel Vetter
2015-11-20 12:43 ` [PATCH 03/12] drm/i915: Unify intel_logical_ring_emit and intel_ring_emit Chris Wilson
2015-11-24 14:33 ` Daniel Vetter
2015-11-24 14:52 ` Chris Wilson
2015-11-20 12:43 ` [PATCH 04/12] drm/i915: Unify intel_ring_begin() Chris Wilson
2015-11-24 14:38 ` Daniel Vetter
2015-11-24 14:58 ` Chris Wilson
2015-11-20 12:43 ` [PATCH 05/12] drm/i915: Remove the identical implementations of request space reservation Chris Wilson
2015-11-24 14:42 ` Daniel Vetter
2015-11-20 12:43 ` [PATCH 06/12] drm/i915: Rename request->ring to request->engine Chris Wilson
2015-11-24 14:48 ` Daniel Vetter
2015-11-20 12:43 ` [PATCH 07/12] drm/i915: Rename request->ringbuf to request->ring Chris Wilson
2015-11-24 14:51 ` Daniel Vetter
2015-11-24 15:08 ` Tvrtko Ursulin
2015-11-24 15:25 ` Chris Wilson
2015-11-25 10:22 ` Tvrtko Ursulin
2015-11-20 12:43 ` [PATCH 08/12] drm/i915: Rename backpointer from intel_ringbuffer to intel_engine_cs Chris Wilson
2015-11-24 14:58 ` Daniel Vetter
2015-11-24 15:10 ` Chris Wilson
2015-11-24 15:15 ` Chris Wilson
2015-11-24 15:36 ` Daniel Vetter
2015-11-20 12:43 ` [PATCH 09/12] drm/i915: Rename intel_context[engine].ringbuf Chris Wilson
2015-11-24 14:59 ` Daniel Vetter
2015-11-24 15:09 ` Tvrtko Ursulin
2015-11-24 15:27 ` Chris Wilson
2015-11-20 12:43 ` [PATCH 10/12] drm/i915: Reduce the pointer dance of i915_is_ggtt() Chris Wilson
2015-11-24 15:08 ` Daniel Vetter
2015-11-20 12:43 ` [PATCH 11/12] drm/i915: Remove request retirement before each batch Chris Wilson
2015-11-20 12:43 ` [PATCH 12/12] drm/i915: Cache the reset_counter for the request Chris Wilson
2015-11-24 16:43 ` Daniel Vetter
2015-11-24 21:43 ` Chris Wilson
2015-11-25 9:12 ` Daniel Vetter
2015-11-25 12:17 ` Chris Wilson
2015-11-26 9:21 ` Daniel Vetter
2015-11-26 9:50 ` Chris Wilson
2015-11-25 17:11 ` Chris Wilson
2015-11-24 13:52 ` [PATCH 01/12] drm/i915: Convert i915_semaphores_is_enabled over to drm_i915_private Daniel Vetter
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