From: Qais Yousef <qais.yousef@imgtec.com> To: <linux-kernel@vger.kernel.org> Cc: <tglx@linutronix.de>, <jason@lakedaemon.net>, <marc.zyngier@arm.com>, <jiang.liu@linux.intel.com>, <ralf@linux-mips.org>, <linux-mips@linux-mips.org>, Qais Yousef <qais.yousef@imgtec.com> Subject: [PATCH v2 16/19] MIPS: Add generic SMP IPI support Date: Wed, 25 Nov 2015 12:06:54 +0000 [thread overview] Message-ID: <1448453217-3874-17-git-send-email-qais.yousef@imgtec.com> (raw) In-Reply-To: <1448453217-3874-1-git-send-email-qais.yousef@imgtec.com> Use the new generic IPI layer to provide generic SMP IPI support if the irqchip supports it. Signed-off-by: Qais Yousef <qais.yousef@imgtec.com> --- arch/mips/kernel/smp.c | 139 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 139 insertions(+) diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index bd4385a8e6e8..7d0a440a2b02 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -33,12 +33,16 @@ #include <linux/cpu.h> #include <linux/err.h> #include <linux/ftrace.h> +#include <linux/irqdomain.h> +#include <linux/of.h> +#include <linux/of_irq.h> #include <linux/atomic.h> #include <asm/cpu.h> #include <asm/processor.h> #include <asm/idle.h> #include <asm/r4k-timer.h> +#include <asm/mips-cpc.h> #include <asm/mmu_context.h> #include <asm/time.h> #include <asm/setup.h> @@ -79,6 +83,11 @@ static cpumask_t cpu_core_setup_map; cpumask_t cpu_coherent_mask; +#ifdef CONFIG_GENERIC_IRQ_IPI +static struct irq_desc *call_desc; +static struct irq_desc *sched_desc; +#endif + static inline void set_cpu_sibling_map(int cpu) { int i; @@ -145,6 +154,136 @@ void register_smp_ops(struct plat_smp_ops *ops) mp_ops = ops; } +#ifdef CONFIG_GENERIC_IRQ_IPI +void mips_smp_send_ipi_single(int cpu, unsigned int action) +{ + mips_smp_send_ipi_mask(cpumask_of(cpu), action); +} + +void mips_smp_send_ipi_mask(const struct cpumask *mask, unsigned int action) +{ + unsigned long flags; + unsigned int core; + int cpu; + + local_irq_save(flags); + + switch (action) { + case SMP_CALL_FUNCTION: + ipi_send_mask(call_desc, mask); + break; + + case SMP_RESCHEDULE_YOURSELF: + ipi_send_mask(sched_desc, mask); + break; + + default: + BUG(); + } + + if (mips_cpc_present()) { + for_each_cpu(cpu, mask) { + core = cpu_data[cpu].core; + + if (core == current_cpu_data.core) + continue; + + while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) { + mips_cpc_lock_other(core); + write_cpc_co_cmd(CPC_Cx_CMD_PWRUP); + mips_cpc_unlock_other(); + } + } + } + + local_irq_restore(flags); +} + + +static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) +{ + scheduler_ipi(); + + return IRQ_HANDLED; +} + +static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) +{ + generic_smp_call_function_interrupt(); + + return IRQ_HANDLED; +} + +static struct irqaction irq_resched = { + .handler = ipi_resched_interrupt, + .flags = IRQF_PERCPU, + .name = "IPI resched" +}; + +static struct irqaction irq_call = { + .handler = ipi_call_interrupt, + .flags = IRQF_PERCPU, + .name = "IPI call" +}; + +static __init void smp_ipi_init_one(unsigned int virq, + struct irqaction *action) +{ + int ret; + + irq_set_handler(virq, handle_percpu_irq); + ret = setup_irq(virq, action); + BUG_ON(ret); +} + +static int __init mips_smp_ipi_init(void) +{ + unsigned int call_virq, sched_virq; + struct irq_domain *ipidomain; + struct device_node *node; + struct ipi_mask ipimask; + + node = of_irq_find_parent(of_root); + ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI); + + /* + * Some platforms have half DT setup. So if we found irq node but + * didn't find an ipidomain, try to search for one that is not in the + * DT. + */ + if (node && !ipidomain) + ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI); + + BUG_ON(!ipidomain); + + ipi_mask_set_cpumask(&ipimask, cpu_possible_mask); + + call_virq = irq_reserve_ipi(ipidomain, &ipimask); + BUG_ON(!call_virq); + + sched_virq = irq_reserve_ipi(ipidomain, &ipimask); + BUG_ON(!sched_virq); + + if (irq_domain_is_ipi_per_cpu(ipidomain)) { + int cpu; + + for_each_cpu(cpu, cpu_possible_mask) { + smp_ipi_init_one(call_virq + cpu, &irq_call); + smp_ipi_init_one(sched_virq + cpu, &irq_resched); + } + } else { + smp_ipi_init_one(call_virq, &irq_call); + smp_ipi_init_one(sched_virq, &irq_resched); + } + + call_desc = irq_to_desc(call_virq); + sched_desc = irq_to_desc(sched_virq); + + return 0; +} +early_initcall(mips_smp_ipi_init); +#endif + /* * First C code run on the secondary CPUs after being started up by * the master. -- 2.1.0
WARNING: multiple messages have this Message-ID (diff)
From: Qais Yousef <qais.yousef@imgtec.com> To: linux-kernel@vger.kernel.org Cc: tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, jiang.liu@linux.intel.com, ralf@linux-mips.org, linux-mips@linux-mips.org, Qais Yousef <qais.yousef@imgtec.com> Subject: [PATCH v2 16/19] MIPS: Add generic SMP IPI support Date: Wed, 25 Nov 2015 12:06:54 +0000 [thread overview] Message-ID: <1448453217-3874-17-git-send-email-qais.yousef@imgtec.com> (raw) Message-ID: <20151125120654.g90qCzqy124npbxMFXhbXBg2l1uL7PlxxNLQ23wpraQ@z> (raw) In-Reply-To: <1448453217-3874-1-git-send-email-qais.yousef@imgtec.com> Use the new generic IPI layer to provide generic SMP IPI support if the irqchip supports it. Signed-off-by: Qais Yousef <qais.yousef@imgtec.com> --- arch/mips/kernel/smp.c | 139 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 139 insertions(+) diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index bd4385a8e6e8..7d0a440a2b02 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -33,12 +33,16 @@ #include <linux/cpu.h> #include <linux/err.h> #include <linux/ftrace.h> +#include <linux/irqdomain.h> +#include <linux/of.h> +#include <linux/of_irq.h> #include <linux/atomic.h> #include <asm/cpu.h> #include <asm/processor.h> #include <asm/idle.h> #include <asm/r4k-timer.h> +#include <asm/mips-cpc.h> #include <asm/mmu_context.h> #include <asm/time.h> #include <asm/setup.h> @@ -79,6 +83,11 @@ static cpumask_t cpu_core_setup_map; cpumask_t cpu_coherent_mask; +#ifdef CONFIG_GENERIC_IRQ_IPI +static struct irq_desc *call_desc; +static struct irq_desc *sched_desc; +#endif + static inline void set_cpu_sibling_map(int cpu) { int i; @@ -145,6 +154,136 @@ void register_smp_ops(struct plat_smp_ops *ops) mp_ops = ops; } +#ifdef CONFIG_GENERIC_IRQ_IPI +void mips_smp_send_ipi_single(int cpu, unsigned int action) +{ + mips_smp_send_ipi_mask(cpumask_of(cpu), action); +} + +void mips_smp_send_ipi_mask(const struct cpumask *mask, unsigned int action) +{ + unsigned long flags; + unsigned int core; + int cpu; + + local_irq_save(flags); + + switch (action) { + case SMP_CALL_FUNCTION: + ipi_send_mask(call_desc, mask); + break; + + case SMP_RESCHEDULE_YOURSELF: + ipi_send_mask(sched_desc, mask); + break; + + default: + BUG(); + } + + if (mips_cpc_present()) { + for_each_cpu(cpu, mask) { + core = cpu_data[cpu].core; + + if (core == current_cpu_data.core) + continue; + + while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) { + mips_cpc_lock_other(core); + write_cpc_co_cmd(CPC_Cx_CMD_PWRUP); + mips_cpc_unlock_other(); + } + } + } + + local_irq_restore(flags); +} + + +static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) +{ + scheduler_ipi(); + + return IRQ_HANDLED; +} + +static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) +{ + generic_smp_call_function_interrupt(); + + return IRQ_HANDLED; +} + +static struct irqaction irq_resched = { + .handler = ipi_resched_interrupt, + .flags = IRQF_PERCPU, + .name = "IPI resched" +}; + +static struct irqaction irq_call = { + .handler = ipi_call_interrupt, + .flags = IRQF_PERCPU, + .name = "IPI call" +}; + +static __init void smp_ipi_init_one(unsigned int virq, + struct irqaction *action) +{ + int ret; + + irq_set_handler(virq, handle_percpu_irq); + ret = setup_irq(virq, action); + BUG_ON(ret); +} + +static int __init mips_smp_ipi_init(void) +{ + unsigned int call_virq, sched_virq; + struct irq_domain *ipidomain; + struct device_node *node; + struct ipi_mask ipimask; + + node = of_irq_find_parent(of_root); + ipidomain = irq_find_matching_host(node, DOMAIN_BUS_IPI); + + /* + * Some platforms have half DT setup. So if we found irq node but + * didn't find an ipidomain, try to search for one that is not in the + * DT. + */ + if (node && !ipidomain) + ipidomain = irq_find_matching_host(NULL, DOMAIN_BUS_IPI); + + BUG_ON(!ipidomain); + + ipi_mask_set_cpumask(&ipimask, cpu_possible_mask); + + call_virq = irq_reserve_ipi(ipidomain, &ipimask); + BUG_ON(!call_virq); + + sched_virq = irq_reserve_ipi(ipidomain, &ipimask); + BUG_ON(!sched_virq); + + if (irq_domain_is_ipi_per_cpu(ipidomain)) { + int cpu; + + for_each_cpu(cpu, cpu_possible_mask) { + smp_ipi_init_one(call_virq + cpu, &irq_call); + smp_ipi_init_one(sched_virq + cpu, &irq_resched); + } + } else { + smp_ipi_init_one(call_virq, &irq_call); + smp_ipi_init_one(sched_virq, &irq_resched); + } + + call_desc = irq_to_desc(call_virq); + sched_desc = irq_to_desc(sched_virq); + + return 0; +} +early_initcall(mips_smp_ipi_init); +#endif + /* * First C code run on the secondary CPUs after being started up by * the master. -- 2.1.0
next prev parent reply other threads:[~2015-11-25 12:08 UTC|newest] Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-11-25 12:06 [PATCH v2 00/19] Implement generic IPI support mechanism Qais Yousef 2015-11-25 12:06 ` Qais Yousef 2015-11-25 12:06 ` [PATCH v2 01/19] genirq: Add new IRQ_DOMAIN_FLAGS_IPI Qais Yousef 2015-11-25 12:06 ` Qais Yousef 2015-11-25 12:06 ` [PATCH v2 02/19] genirq: Add DOMAIN_BUS_IPI Qais Yousef 2015-11-25 12:06 ` Qais Yousef 2015-11-25 12:06 ` [PATCH v2 03/19] genirq: Add GENERIC_IRQ_IPI Kconfig symbol Qais Yousef 2015-11-25 12:06 ` Qais Yousef 2015-11-25 12:06 ` [PATCH v2 04/19] genirq: Add new struct ipi_mask and helper functions Qais Yousef 2015-11-25 12:06 ` Qais Yousef 2015-11-30 11:20 ` Thomas Gleixner 2015-11-30 11:48 ` Qais Yousef 2015-11-30 11:48 ` Qais Yousef 2015-11-30 13:11 ` Thomas Gleixner 2015-11-30 13:57 ` Qais Yousef 2015-11-30 13:57 ` Qais Yousef 2015-11-25 12:06 ` [PATCH v2 05/19] genirq: Add struct ipi_mask to irq_data Qais Yousef 2015-11-25 12:06 ` Qais Yousef 2015-11-25 12:06 ` [PATCH v2 06/19] genirq: Add struct ipi_mapping and its helper functions Qais Yousef 2015-11-25 12:06 ` Qais Yousef 2015-11-25 12:06 ` [PATCH v2 07/19] genirq: Make irq_domain_alloc_descs() non static Qais Yousef 2015-11-25 12:06 ` Qais Yousef 2015-11-25 12:06 ` [PATCH v2 08/19] genirq: Add a new generic IPI reservation code to irq core Qais Yousef 2015-11-25 12:06 ` Qais Yousef 2015-11-25 12:06 ` [PATCH v2 09/19] genirq: Add a new function to get IPI reverse mapping Qais Yousef 2015-11-25 12:06 ` Qais Yousef 2015-11-27 11:46 ` Qais Yousef 2015-11-27 11:46 ` Qais Yousef 2015-11-30 10:40 ` Thomas Gleixner 2015-11-30 10:53 ` Qais Yousef 2015-11-30 10:53 ` Qais Yousef 2015-11-30 11:22 ` Thomas Gleixner 2015-11-30 11:59 ` Qais Yousef 2015-11-30 11:59 ` Qais Yousef 2015-12-01 10:47 ` Qais Yousef 2015-12-01 10:47 ` Qais Yousef 2015-11-25 12:06 ` [PATCH v2 10/19] genirq: Add a new irq_send_ipi() to irq_chip Qais Yousef 2015-11-25 12:06 ` Qais Yousef 2015-11-25 12:06 ` [PATCH v2 11/19] genirq: Implement ipi_send_{mask, single}() Qais Yousef 2015-11-25 12:06 ` Qais Yousef 2015-11-25 12:06 ` [PATCH v2 12/19] irqchip/mips-gic: Add a IPI hierarchy domain Qais Yousef 2015-11-25 12:06 ` Qais Yousef 2015-11-25 12:06 ` [PATCH v2 13/19] irqchip/mips-gic: Add device " Qais Yousef 2015-11-25 12:06 ` Qais Yousef 2015-11-25 12:06 ` [PATCH v2 14/19] irqchip/mips-gic: Use gic_vpes instead of NR_CPUS Qais Yousef 2015-11-25 12:06 ` Qais Yousef 2015-11-25 12:06 ` [PATCH v2 15/19] irqchip/mips-gic: Clear percpu_masks correctly when mapping Qais Yousef 2015-11-25 12:06 ` Qais Yousef 2015-11-25 12:06 ` Qais Yousef [this message] 2015-11-25 12:06 ` [PATCH v2 16/19] MIPS: Add generic SMP IPI support Qais Yousef 2015-11-25 12:06 ` [PATCH v2 17/19] MIPS: Make smp CMP, CPS and MT use the new generic IPI functions Qais Yousef 2015-11-25 12:06 ` Qais Yousef 2015-11-25 12:06 ` [PATCH v2 18/19] MIPS: Delete smp-gic.c Qais Yousef 2015-11-25 12:06 ` Qais Yousef 2015-11-25 12:06 ` [PATCH v2 19/19] irqchip/mips-gic: Add new DT property to reserve IPIs Qais Yousef 2015-11-25 12:06 ` Qais Yousef 2015-11-25 16:09 ` Rob Herring
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