* [PATCH v2 1/2] dt-bindings: Misc fix for the ATH79 MISC interrupt controllers
@ 2015-11-29 12:40 Alban Bedel
[not found] ` <1448800812-7469-1-git-send-email-albeu-GANU6spQydw@public.gmane.org>
0 siblings, 1 reply; 4+ messages in thread
From: Alban Bedel @ 2015-11-29 12:40 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Alban Bedel, trivial-DgEjT+Ai2ygdnm+yROfE0A
Add a missing quote in the example
Signed-off-by: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
CC: trivial-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
---
.../devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
index ec96b1f..475ae9b 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
@@ -22,7 +22,7 @@ Interrupt Controllers bindings used by client devices.
Example:
interrupt-controller@18060010 {
- compatible = "qca,ar9132-misc-intc", qca,ar7100-misc-intc";
+ compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
reg = <0x18060010 0x4>;
interrupt-parent = <&cpuintc>;
--
2.0.0
--
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* [PATCH v2 2/2] dt-bindings: Misc fix for the ATH79 DDR controllers
[not found] ` <1448800812-7469-1-git-send-email-albeu-GANU6spQydw@public.gmane.org>
@ 2015-11-29 12:40 ` Alban Bedel
[not found] ` <1448800812-7469-2-git-send-email-albeu-GANU6spQydw@public.gmane.org>
2015-12-04 18:47 ` [PATCH v2 1/2] dt-bindings: Misc fix for the ATH79 MISC interrupt controllers Rob Herring
1 sibling, 1 reply; 4+ messages in thread
From: Alban Bedel @ 2015-11-29 12:40 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Alban Bedel, trivial-DgEjT+Ai2ygdnm+yROfE0A
Fix a few typos and reword the description of the
'#qca,ddr-wb-channel-cells' property.
Signed-off-by: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
CC: trivial-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
---
Changlog:
v2: * Fixed the truncated log message because of a
line starting with a #.
---
.../bindings/memory-controllers/ath79-ddr-controller.txt | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt b/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt
index efe35a06..c81af75 100644
--- a/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt
@@ -1,6 +1,6 @@
Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
-The DDR controller of the ARxxx and AR9xxx families provides an interface
+The DDR controller of the AR7xxx and AR9xxx families provides an interface
to flush the FIFO between various devices and the DDR. This is mainly used
by the IRQ controller to flush the FIFO before running the interrupt handler
of such devices.
@@ -11,9 +11,9 @@ Required properties:
"qca,[ar7100|ar7240]-ddr-controller" as fallback.
On SoC with PCI support "qca,ar7100-ddr-controller" should be used as
fallback, otherwise "qca,ar7240-ddr-controller" should be used.
-- reg: Base address and size of the controllers memory area
-- #qca,ddr-wb-channel-cells: has to be 1, the index of the write buffer
- channel
+- reg: Base address and size of the controller's memory area
+- #qca,ddr-wb-channel-cells: Specifies the number of cells needed to encode
+ the write buffer channel index, should be 1.
Example:
--
2.0.0
--
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* Re: [PATCH v2 1/2] dt-bindings: Misc fix for the ATH79 MISC interrupt controllers
[not found] ` <1448800812-7469-1-git-send-email-albeu-GANU6spQydw@public.gmane.org>
2015-11-29 12:40 ` [PATCH v2 2/2] dt-bindings: Misc fix for the ATH79 DDR controllers Alban Bedel
@ 2015-12-04 18:47 ` Rob Herring
1 sibling, 0 replies; 4+ messages in thread
From: Rob Herring @ 2015-12-04 18:47 UTC (permalink / raw)
To: Alban Bedel
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, trivial-DgEjT+Ai2ygdnm+yROfE0A
On Sun, Nov 29, 2015 at 01:40:11PM +0100, Alban Bedel wrote:
> Add a missing quote in the example
>
> Signed-off-by: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
> CC: trivial-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
Applied, thanks.
Rob
> ---
> .../devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
> index ec96b1f..475ae9b 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/qca,ath79-misc-intc.txt
> @@ -22,7 +22,7 @@ Interrupt Controllers bindings used by client devices.
> Example:
>
> interrupt-controller@18060010 {
> - compatible = "qca,ar9132-misc-intc", qca,ar7100-misc-intc";
> + compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
> reg = <0x18060010 0x4>;
>
> interrupt-parent = <&cpuintc>;
> --
> 2.0.0
>
--
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* Re: [PATCH v2 2/2] dt-bindings: Misc fix for the ATH79 DDR controllers
[not found] ` <1448800812-7469-2-git-send-email-albeu-GANU6spQydw@public.gmane.org>
@ 2015-12-04 18:52 ` Rob Herring
0 siblings, 0 replies; 4+ messages in thread
From: Rob Herring @ 2015-12-04 18:52 UTC (permalink / raw)
To: Alban Bedel
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, trivial-DgEjT+Ai2ygdnm+yROfE0A
On Sun, Nov 29, 2015 at 01:40:12PM +0100, Alban Bedel wrote:
> Fix a few typos and reword the description of the
> '#qca,ddr-wb-channel-cells' property.
>
> Signed-off-by: Alban Bedel <albeu-GANU6spQydw@public.gmane.org>
> CC: trivial-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org
Applied, thanks.
Rob
> ---
> Changlog:
> v2: * Fixed the truncated log message because of a
> line starting with a #.
> ---
> .../bindings/memory-controllers/ath79-ddr-controller.txt | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt b/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt
> index efe35a06..c81af75 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt
> +++ b/Documentation/devicetree/bindings/memory-controllers/ath79-ddr-controller.txt
> @@ -1,6 +1,6 @@
> Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
>
> -The DDR controller of the ARxxx and AR9xxx families provides an interface
> +The DDR controller of the AR7xxx and AR9xxx families provides an interface
> to flush the FIFO between various devices and the DDR. This is mainly used
> by the IRQ controller to flush the FIFO before running the interrupt handler
> of such devices.
> @@ -11,9 +11,9 @@ Required properties:
> "qca,[ar7100|ar7240]-ddr-controller" as fallback.
> On SoC with PCI support "qca,ar7100-ddr-controller" should be used as
> fallback, otherwise "qca,ar7240-ddr-controller" should be used.
> -- reg: Base address and size of the controllers memory area
> -- #qca,ddr-wb-channel-cells: has to be 1, the index of the write buffer
> - channel
> +- reg: Base address and size of the controller's memory area
> +- #qca,ddr-wb-channel-cells: Specifies the number of cells needed to encode
> + the write buffer channel index, should be 1.
>
> Example:
>
> --
> 2.0.0
>
--
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2015-11-29 12:40 [PATCH v2 1/2] dt-bindings: Misc fix for the ATH79 MISC interrupt controllers Alban Bedel
[not found] ` <1448800812-7469-1-git-send-email-albeu-GANU6spQydw@public.gmane.org>
2015-11-29 12:40 ` [PATCH v2 2/2] dt-bindings: Misc fix for the ATH79 DDR controllers Alban Bedel
[not found] ` <1448800812-7469-2-git-send-email-albeu-GANU6spQydw@public.gmane.org>
2015-12-04 18:52 ` Rob Herring
2015-12-04 18:47 ` [PATCH v2 1/2] dt-bindings: Misc fix for the ATH79 MISC interrupt controllers Rob Herring
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