[U-Boot] [PATCHv3 0/9] ARM: socfpga: Add minimal support for Arria10

[U-Boot] [PATCHv3 0/9] ARM: socfpga: Add minimal support for Arria10

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Hi,

This is v3 of the patch series that adds minimal support for Altera's Arria10
platform.

v3:
- Add CONFIG_SOCFPGA_GEN5 for building for Arria5 and Cyclone5
- Clean up socfpga_arria10_socdk
- Add patch to remove the macro SYSMGR_SDMMC_CTRL_SET
- Move system_manager_a10.h into system_manager.h
- Rebase to u-boot-socfpga/master

v2:
- Removes the need for a separate /mach-socfpga/arria10 directory
- Tries to re-use alot of the Arria5/Cyclone5 code
- Removes the usage of unions bitfields in the SDRAM defines

v1:
The series builds for
the Altera Arria10 SoCDK, but is not entirely functional on the hardware yet.
This series really just add the defines, build and Kconfig layout for Arria10.

There are few TODO after this series:
- Add DTS file for the devkit
- Add clock manager
- The Arria10 Pin Mux requires the FPGA to get programmed before the SDRAM
  controller can be usable. So another patch is needed to make use of the fpga
  manager to program the FPGA within the limited size of the OCRAM.

Thanks,

Dinh Nguyen (9):
  arm: socfpga: introduce SOCFPGA_GEN5 config property
  arm: socfpga: arria10: add system manager defines
  arm: socfpga: arria10: add reset manager for Arria10
  arm: socfpga: arria10: add misc functions for Arria10
  arm: socfpga: arria10: add socfpga_arria10_socdk config
  arm: socfpga: arria10: add socfpga_arria10_defconfig
  arm: socfpga: arria10: add config option build for arria10
  arm: socfpga: remove building scan manager
  arm: socfpga: fix up a questionable macro for SDMMC

 arch/arm/Kconfig                                   |   4 +-
 arch/arm/mach-socfpga/Kconfig                      |  15 +++
 arch/arm/mach-socfpga/Makefile                     |   5 +-
 arch/arm/mach-socfpga/include/mach/reset_manager.h |  65 +++++++++++
 .../arm/mach-socfpga/include/mach/system_manager.h | 130 ++++++++++++++++++++-
 arch/arm/mach-socfpga/misc.c                       |  53 +++++++++
 arch/arm/mach-socfpga/reset_manager.c              |  36 +++++-
 configs/socfpga_arria10_defconfig                  |  16 +++
 drivers/mmc/socfpga_dw_mmc.c                       |   5 +-
 include/configs/socfpga_arria10_socdk.h            |  94 +++++++++++++++
 10 files changed, 413 insertions(+), 10 deletions(-)
 create mode 100644 configs/socfpga_arria10_defconfig
 create mode 100644 include/configs/socfpga_arria10_socdk.h

-- 
2.6.2

[U-Boot] [PATCHv3 1/9] arm: socfpga: introduce SOCFPGA_GEN5 config property

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

In order to re-use as much Cyclone5 and Arria5 code as possible to support
the Arria10 platform, we need to wrap some of the code with #ifdef's. By
adding CONFIG_SOCFPGA_GEN5, we can shorten the check by not having to check
for both AV || AV.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
 arch/arm/mach-socfpga/Kconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 0cb9f9e..4ea171a 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -2,9 +2,14 @@ if ARCH_SOCFPGA
 
 config TARGET_SOCFPGA_ARRIA5
 	bool
+	select SOCFPGA_GEN5
 
 config TARGET_SOCFPGA_CYCLONE5
 	bool
+	select SOCFPGA_GEN5
+
+config SOCFPGA_GEN5
+	bool
 
 choice
 	prompt "Altera SOCFPGA board select"
-- 
2.6.2

[U-Boot] [PATCHv3 2/9] arm: socfpga: arria10: add system manager defines

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Add system manager defines for Arria10.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v3: combine system_manager_a10.h into system_manager.h
v2: clean up parenthesis
---
 .../arm/mach-socfpga/include/mach/system_manager.h | 122 +++++++++++++++++++++
 1 file changed, 122 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 8712f8e..cc070dc 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -15,6 +15,7 @@ void sysmgr_config_warmrstcfgio(int enable);
 void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
 #endif
 
+#if defined(CONFIG_SOCFPGA_GEN5)
 struct socfpga_system_manager {
 	/* System Manager Module */
 	u32	siliconid1;			/* 0x00 */
@@ -115,6 +116,77 @@ struct socfpga_system_manager {
 	u32	_pad_0x734;
 	u32	spim0usefpga;			/* 0x738 */
 };
+#else /* Arria10 System Manager */
+struct socfpga_system_manager {
+	u32  siliconid1;
+	u32  siliconid2;
+	u32  wddbg;
+	u32  bootinfo;
+	u32  mpu_ctrl_l2_ecc;
+	u32  _pad_0x14_0x1f[3];
+	u32  dma;
+	u32  dma_periph;
+	u32  sdmmcgrp_ctrl;
+	u32  sdmmc_l3master;
+	u32  nand_bootstrap;
+	u32  nand_l3master;
+	u32  usb0_l3master;
+	u32  usb1_l3master;
+	u32  emac_global;
+	u32  emac0;
+	u32  emac1;
+	u32  emac2;
+	u32  _pad_0x50_0x5f[4];
+	u32  fpgaintf_en_global;
+	u32  fpgaintf_en_0;
+	u32  fpgaintf_en_1;
+	u32  fpgaintf_en_2;
+	u32  fpgaintf_en_3;
+	u32  _pad_0x74_0x7f[3];
+	u32  noc_addr_remap_value;
+	u32  noc_addr_remap_set;
+	u32  noc_addr_remap_clear;
+	u32  _pad_0x8c_0x8f;
+	u32  ecc_intmask_value;
+	u32  ecc_intmask_set;
+	u32  ecc_intmask_clr;
+	u32  ecc_intstatus_serr;
+	u32  ecc_intstatus_derr;
+	u32  mpu_status_l2_ecc;
+	u32  mpu_clear_l2_ecc;
+	u32  mpu_status_l1_parity;
+	u32  mpu_clear_l1_parity;
+	u32  mpu_set_l1_parity;
+	u32  _pad_0xb8_0xbf[2];
+	u32  noc_timeout;
+	u32  noc_idlereq_set;
+	u32  noc_idlereq_clr;
+	u32  noc_idlereq_value;
+	u32  noc_idleack;
+	u32  noc_idlestatus;
+	u32  fpga2soc_ctrl;
+	u32  _pad_0xdc_0xff[9];
+	u32  tsmc_tsel_0;
+	u32  tsmc_tsel_1;
+	u32  tsmc_tsel_2;
+	u32  tsmc_tsel_3;
+	u32  _pad_0x110_0x200[60];
+	u32  romhw_ctrl;
+	u32  romcode_ctrl;
+	u32  romcode_cpu1startaddr;
+	u32  romcode_initswstate;
+	u32  romcode_initswlastld;
+	u32  _pad_0x214_0x217;
+	u32  warmram_enable;
+	u32  warmram_datastart;
+	u32  warmram_length;
+	u32  warmram_execution;
+	u32  warmram_crc;
+	u32  _pad_0x22c_0x22f;
+	u32  isw_handoff[8];
+	u32  romcode_bootromswstate[8];
+};
+#endif
 
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX	(1 << 0)
 #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO	(1 << 1)
@@ -142,4 +214,54 @@ struct socfpga_system_manager {
 #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB			2
 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK			0x3
 
+/* For dedicated IO configuration */
+/* Voltage select enums */
+#define VOLTAGE_SEL_3V		0x0
+#define VOLTAGE_SEL_1P8V	0x1
+#define VOLTAGE_SEL_2P5V	0x2
+
+/* Input buffer enable */
+#define INPUT_BUF_DISABLE	0
+#define INPUT_BUF_1P8V		1
+#define INPUT_BUF_2P5V3V	2
+
+/* Weak pull up enable */
+#define WK_PU_DISABLE		0
+#define WK_PU_ENABLE		1
+
+/* Pull up slew rate control */
+#define PU_SLW_RT_SLOW		0
+#define PU_SLW_RT_FAST		1
+#define PU_SLW_RT_DEFAULT	PU_SLW_RT_SLOW
+
+/* Pull down slew rate control */
+#define PD_SLW_RT_SLOW		0
+#define PD_SLW_RT_FAST		1
+#define PD_SLW_RT_DEFAULT	PD_SLW_RT_SLOW
+
+/* Drive strength control */
+#define PU_DRV_STRG_DEFAULT	0x10
+#define PD_DRV_STRG_DEFAULT	0x10
+
+/* bit position */
+#define PD_DRV_STRG_LSB		0
+#define PD_SLW_RT_LSB		5
+#define PU_DRV_STRG_LSB		8
+#define PU_SLW_RT_LSB		13
+#define WK_PU_LSB		16
+#define INPUT_BUF_LSB		17
+#define BIAS_TRIM_LSB		19
+#define VOLTAGE_SEL_LSB		0
+
+#define ALT_SYSMGR_NOC_H2F_SET_MSK	0x00000001
+#define ALT_SYSMGR_NOC_LWH2F_SET_MSK	0x00000010
+#define ALT_SYSMGR_NOC_F2H_SET_MSK	0x00000100
+#define ALT_SYSMGR_NOC_F2SDR0_SET_MSK	0x00010000
+#define ALT_SYSMGR_NOC_F2SDR1_SET_MSK	0x00100000
+#define ALT_SYSMGR_NOC_F2SDR2_SET_MSK	0x01000000
+#define ALT_SYSMGR_NOC_TMO_EN_SET_MSK	0x00000001
+
+#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK	0x00000002
+#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK	0x00000002
+
 #endif /* _SYSTEM_MANAGER_H_ */
-- 
2.6.2

[U-Boot] [PATCHv3 3/9] arm: socfpga: arria10: add reset manager for Arria10

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Add the defines for the reset manager and some basic reset functionality.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v3: remove duplicate reset function
    use CONFIG_SOCFPGA_GEN5
v2: integrate into a5/c5 reset manager
---
 arch/arm/mach-socfpga/include/mach/reset_manager.h | 65 ++++++++++++++++++++++
 arch/arm/mach-socfpga/reset_manager.c              | 36 +++++++++++-
 2 files changed, 100 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index e50fbd8..e7b814a 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -15,6 +15,7 @@ void socfpga_bridges_reset(int enable);
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
 
+#if defined(CONFIG_SOCFPGA_GEN5)
 struct socfpga_reset_manager {
 	u32	status;
 	u32	ctrl;
@@ -28,6 +29,42 @@ struct socfpga_reset_manager {
 	u32	padding2[12];
 	u32	tstscratch;
 };
+#else
+struct socfpga_reset_manager {
+	u32	stat;
+	u32	ramstat;
+	u32	miscstat;
+	u32	ctrl;
+	u32	hdsken;
+	u32	hdskreq;
+	u32	hdskack;
+	u32	counts;
+	u32	mpu_mod_reset;
+	u32	per0_mod_reset;
+	u32	per1_mod_reset;
+	u32	brg_mod_reset;
+	u32	sys_mod_reset;
+	u32	coldmodrst;
+	u32	nrstmodrst;
+	u32	dbgmodrst;
+	u32	mpuwarmmask;
+	u32	per0warmmask;
+	u32	per1warmmask;
+	u32	brgwarmmask;
+	u32	syswarmmask;
+	u32	nrstwarmmask;
+	u32	l3warmmask;
+	u32	tststa;
+	u32	tstscratch;
+	u32	hdsktimeout;
+	u32	hmcintr;
+	u32	hmcintren;
+	u32	hmcintrens;
+	u32	hmcintrenr;
+	u32	hmcgpout;
+	u32	hmcgpin;
+};
+#endif
 
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
@@ -55,6 +92,7 @@ struct socfpga_reset_manager {
 #define RSTMGR_BANK(_reset)			\
 	(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
 
+#if defined(CONFIG_SOCFPGA_GEN5)
 /*
  * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
  * 0 ... mpumodrst
@@ -74,6 +112,33 @@ struct socfpga_reset_manager {
 #define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 22)
 #define RSTMGR_DMA		RSTMGR_DEFINE(1, 28)
 #define RSTMGR_SDR		RSTMGR_DEFINE(1, 29)
+#else
+/*
+ * SocFPGA Arria10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ * 4 ... sysmodrst
+ */
+#define RSTMGR_EMAC0		RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1		RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2		RSTMGR_DEFINE(1, 2)
+#define RSTMGR_L4WD0		RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1		RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4SYSTIMER0	RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4SYSTIMER1	RSTMGR_DEFINE(2, 3)
+#define RSTMGR_SPTIMER0		RSTMGR_DEFINE(2, 4)
+#define RSTMGR_SPTIMER1		RSTMGR_DEFINE(2, 5)
+#define RSTMGR_UART0		RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1		RSTMGR_DEFINE(2, 17)
+#define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 18)
+#define RSTMGR_QSPI		RSTMGR_DEFINE(1, 6)
+#define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 7)
+#define RSTMGR_DMA		RSTMGR_DEFINE(1, 16)
+#define RSTMGR_DDRSCH		RSTMGR_DEFINE(3, 6)
+#endif
 
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)	RSTMGR_##_name
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index b6beaa2..abcd365 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -18,7 +18,9 @@ static const struct socfpga_reset_manager *reset_manager_base =
 static struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
-/* Assert or de-assert SoCFPGA reset manager reset. */
+/*
+ * Assert or de-assert SoCFPGA reset manager reset.
+ */
 void socfpga_per_reset(u32 reset, int set)
 {
 	const void *reg;
@@ -26,13 +28,25 @@ void socfpga_per_reset(u32 reset, int set)
 	if (RSTMGR_BANK(reset) == 0)
 		reg = &reset_manager_base->mpu_mod_reset;
 	else if (RSTMGR_BANK(reset) == 1)
+#if defined(CONFIG_SOCFPGA_GEN5)
 		reg = &reset_manager_base->per_mod_reset;
+#else
+		reg = &reset_manager_base->per0_mod_reset;
+#endif
 	else if (RSTMGR_BANK(reset) == 2)
+#if defined(CONFIG_SOCFPGA_GEN5)
 		reg = &reset_manager_base->per2_mod_reset;
+#else
+		reg = &reset_manager_base->per1_mod_reset;
+#endif
 	else if (RSTMGR_BANK(reset) == 3)
 		reg = &reset_manager_base->brg_mod_reset;
 	else if (RSTMGR_BANK(reset) == 4)
+#if defined(CONFIG_SOCFPGA_GEN5)
 		reg = &reset_manager_base->misc_mod_reset;
+#else
+		reg = &reset_manager_base->sys_mod_reset;
+#endif
 	else	/* Invalid reset register, do nothing */
 		return;
 
@@ -46,13 +60,29 @@ void socfpga_per_reset(u32 reset, int set)
  * Assert reset on every peripheral but L4WD0.
  * Watchdog must be kept intact to prevent glitches
  * and/or hangs.
+ * For the Arria10, we disable all the peripherals except L4 watchdog0,
+ * L4 Timer 0, and ECC.
  */
 void socfpga_per_reset_all(void)
 {
+#if defined(CONFIG_SOCFPGA_GEN5)
 	const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
 
 	writel(~l4wd0, &reset_manager_base->per_mod_reset);
 	writel(0xffffffff, &reset_manager_base->per2_mod_reset);
+#else
+	const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(WD0)) |
+			(1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
+
+	unsigned mask_ecc_ocp = 0x0000FF00;
+
+	/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
+	writel(~l4wd0, &reset_manager_base->per1_mod_reset);
+	setbits_le32(&reset_manager_base->per0_mod_reset, ~mask_ecc_ocp);
+
+	/* Finally disable the ECC_OCP */
+	setbits_le32(&reset_manager_base->per0_mod_reset, mask_ecc_ocp);
+#endif
 }
 
 /*
@@ -71,6 +101,7 @@ void reset_cpu(ulong addr)
 		;
 }
 
+#if defined(CONFIG_SOCFPGA_GEN5)
 /*
  * Release peripherals from reset based on handoff
  */
@@ -78,6 +109,7 @@ void reset_deassert_peripherals_handoff(void)
 {
 	writel(0, &reset_manager_base->per_mod_reset);
 }
+#endif
 
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 void socfpga_bridges_reset(int enable)
@@ -92,6 +124,7 @@ void socfpga_bridges_reset(int enable)
 
 void socfpga_bridges_reset(int enable)
 {
+#if defined(CONFIG_SOCFPGA_GEN5)
 	const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
 				L3REGS_REMAP_HPS2FPGA_MASK |
 				L3REGS_REMAP_OCRAM_MASK;
@@ -116,5 +149,6 @@ void socfpga_bridges_reset(int enable)
 		/* Remap the bridges into memory map */
 		writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
 	}
+#endif
 }
 #endif
-- 
2.6.2

[U-Boot] [PATCHv3 4/9] arm: socfpga: arria10: add misc functions for Arria10

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinh.linux@gmail.com>

Add arch_early_init_r function. The Arria10 has a firewall protection
around the SDRAM and OCRAM. These firewalls are to be disabled in order
for U-Boot to function.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v3: s/reset_assert_all_peripherals_except_l4wd0_l4timer0/socfpga_per_reset_all
    use CONFIG_SOCFPGA_GEN5
v2: reuse misc functions from a5/c5
---
 arch/arm/mach-socfpga/misc.c | 53 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index b110f5b..16d83d4 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -15,6 +15,7 @@
 #include <watchdog.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/arch/scan_manager.h>
+#include <asm/arch/sdram_a10.h>
 #include <asm/arch/system_manager.h>
 #include <asm/arch/dwmmc.h>
 #include <asm/arch/nic301.h>
@@ -31,11 +32,20 @@ static struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 static struct socfpga_reset_manager *reset_manager_base =
 	(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
+#if defined(CONFIG_SOCFPGA_GEN5)
 static struct nic301_registers *nic301_regs =
 	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
+#endif
 static struct scu_registers *scu_regs =
 	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
+	(void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
+static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
+	(void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
+#endif
+
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
@@ -207,9 +217,14 @@ static int socfpga_fpga_id(const bool print_id)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
+#if defined(CONFIG_SOCFPGA_GEN5)
 	const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
 	puts("CPU:   Altera SoCFPGA Platform\n");
 	socfpga_fpga_id(1);
+#else
+	const u32 bsel = (readl(&sysmgr_regs->bootinfo) >> 12) & 0x7;
+	puts("CPU:   Altera SoCFPGA Arria 10\n");
+#endif
 	printf("BOOT:  %s\n", bsel_str[bsel].name);
 	return 0;
 }
@@ -292,6 +307,7 @@ int arch_cpu_init(void)
 	return 0;
 }
 
+#if defined(CONFIG_SOCFPGA_GEN5)
 /*
  * Convert all NIC-301 AMBA slaves from secure to non-secure
  */
@@ -411,6 +427,43 @@ int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 
 	return 0;
 }
+#else
+/*
++ * This function initializes security policies to be consistent across
++ * all logic units in the Arria 10.
++ *
++ * The idea is to set all security policies to be normal, nonsecure
++ * for all units.
++ */
+static void initialize_security_policies(void)
+{
+	/* Put OCRAM in non-secure */
+	writel(0x003f0000, &noc_fw_ocram_base->region0);
+	writel(0x1, &noc_fw_ocram_base->enable);
+
+	/* Put DDR in non-secure */
+	writel(0xffff0000, &noc_fw_ddr_l3_base->hpsregion0addr);
+	writel(0x1, &noc_fw_ddr_l3_base->enable);
+}
+
+int arch_early_init_r(void)
+{
+	initialize_security_policies();
+
+	/* Configure the L2 controller to make SDRAM start at 0 */
+	writel(0x1, &pl310->pl310_addr_filter_start);
+
+	/* assert reset to all except L4WD0 and L4TIMER0 */
+	socfpga_per_reset_all();
+
+	/* configuring the clock based on handoff */
+	/* TODO: Add call to cm_basic_init() */
+
+	/* Add device descriptor to FPGA device table */
+	socfpga_fpga_add();
+	return 0;
+}
+#endif
 
 U_BOOT_CMD(
 	bridge, 2, 1, do_bridge,
-- 
2.6.2

[U-Boot] [PATCHv3 5/9] arm: socfpga: arria10: add socfpga_arria10_socdk config

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Add config for the Arria10 SoC Development Kit.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v3: further clean up, remove extra defines, keep bare mininum options
v2: clean up socfpga_arria10_socdk.h to use socfpga_common.h
---
 include/configs/socfpga_arria10_socdk.h | 94 +++++++++++++++++++++++++++++++++
 1 file changed, 94 insertions(+)
 create mode 100644 include/configs/socfpga_arria10_socdk.h

diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h
new file mode 100644
index 0000000..577f60f
--- /dev/null
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -0,0 +1,94 @@
+/*
+ *  Copyright (C) 2015 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
+#define __CONFIG_SOCFGPA_ARRIA10_H__
+
+#include <asm/arch/base_addr_a10.h>
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+
+/*
+ * Memory configurations
+ */
+#define PHYS_SDRAM_1_SIZE		0x2000000
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"zImage"
+#define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND      "run mmcload; run mmcboot"
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/*
+ * Display CPU and Board Info
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+
+/* PHY */
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+
+#endif
+
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0/* device 0 */
+#define CONFIG_ENV_OFFSET		512/* just after the MBR */
+
+/*
+ * arguments passed to the bootz command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"verify=n\0" \
+	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"bootimage=zImage\0" \
+	"fdt_addr=100\0" \
+	"fdtimage=socfpga.dtb\0" \
+		"fsloadcmd=ext2load\0" \
+	"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"mmcroot=/dev/mmcblk0p2\0" \
+	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${mmcroot} rw rootwait;" \
+		"bootz ${loadaddr} - ${fdt_addr}\0" \
+	"mmcload=mmc rescan;" \
+		"load mmc 0:1 ${loadaddr} ${bootimage};" \
+		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+	"qspiroot=/dev/mtdblock0\0" \
+	"qspirootfstype=jffs2\0" \
+	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+		"bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+#endif	/* __CONFIG_H */
-- 
2.6.2

[U-Boot] [PATCHv3 6/9] arm: socfpga: arria10: add socfpga_arria10_defconfig

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Add a defconfig file for Arria10, which does not include enabling SPL.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v3: align with u-boot-socfpga/master
v2: none
---
 configs/socfpga_arria10_defconfig | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 configs/socfpga_arria10_defconfig

diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
new file mode 100644
index 0000000..422261b
--- /dev/null
+++ b/configs/socfpga_arria10_defconfig
@@ -0,0 +1,16 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_ARRIA10=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk"
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_DESIGNWARE_SPI=y
+CONFIG_DM_MMC=y
-- 
2.6.2

[U-Boot] [PATCHv3 7/9] arm: socfpga: arria10: add config option build for arria10

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: none
---
 arch/arm/Kconfig              |  4 ++--
 arch/arm/mach-socfpga/Kconfig | 10 ++++++++++
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 408e4ff..c43c8b4 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -500,9 +500,9 @@ config RMOBILE
 config ARCH_SOCFPGA
 	bool "Altera SOCFPGA family"
 	select CPU_V7
-	select SUPPORT_SPL
+	select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
 	select OF_CONTROL
-	select SPL_OF_CONTROL
+	select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
 	select DM
 	select DM_SPI_FLASH
 	select DM_SPI
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 4ea171a..0d2d8d6 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -1,5 +1,8 @@
 if ARCH_SOCFPGA
 
+config TARGET_SOCFPGA_ARRIA10
+	bool
+
 config TARGET_SOCFPGA_ARRIA5
 	bool
 	select SOCFPGA_GEN5
@@ -23,6 +26,10 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
 	bool "Altera SOCFPGA SoCDK (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_ARRIA10_SOCDK
+	bool "Altera SOCFPGA SoCDK (Arria 10)"
+	select TARGET_SOCFPGA_ARRIA10
+
 config TARGET_SOCFPGA_DENX_MCVEVK
 	bool "DENX MCVEVK (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
@@ -47,6 +54,7 @@ endchoice
 
 config SYS_BOARD
 	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
@@ -56,6 +64,7 @@ config SYS_BOARD
 
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
+	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -67,6 +76,7 @@ config SYS_SOC
 
 config SYS_CONFIG_NAME
 	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
 	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
-- 
2.6.2

[U-Boot] [PATCHv3 8/9] arm: socfpga: remove building scan manager

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

The scan manager is not needed for the Arria10. Edit the makefile to
build the scan manager for arria5 and cyclone5 only.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v3: use CONFIG_SOCFPGA_GEN5 option for build
---
 arch/arm/mach-socfpga/Makefile | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 316b326..173ff3e 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -8,11 +8,12 @@
 #
 
 obj-y	+= misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
-	   fpga_manager.o scan_manager.o
+	   fpga_manager.o
+
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
 # QTS-generated config file wrappers
-obj-y	+= wrap_pll_config.o
+obj-$(CONFIG_SOCFPGA_GEN5)	+= scan_manager.o wrap_pll_config.o
 obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o	\
 			   wrap_sdram_config.o
 CFLAGS_wrap_iocsr_config.o	+= -I$(srctree)/board/$(BOARDDIR)
-- 
2.6.2

[U-Boot] [PATCHv3 9/9] arm: socfpga: fix up a questionable macro for SDMMC

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Move the macro into the socfpga_dwmci_clksel().

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
 arch/arm/mach-socfpga/include/mach/system_manager.h | 8 +++++---
 drivers/mmc/socfpga_dw_mmc.c                        | 5 +++--
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h
index cc070dc..f8a9b69 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -201,9 +201,11 @@ struct socfpga_system_manager {
 #define SYSMGR_FPGAINTF_NAND	(1 << 4)
 #define SYSMGR_FPGAINTF_SDMMC	(1 << 5)
 
-/* FIXME: This is questionable macro. */
-#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)	\
-	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
+#if defined(CONFIG_SOCFPGA_GEN5)
+#define SYSMGR_SDMMC_SMPSEL_SHIFT	3
+#else
+#define SYSMGR_SDMMC_SMPSEL_SHIFT	4
+#endif
 
 /* EMAC Group Bit definitions */
 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	0x0
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 5b0c3a8..6a55a6c 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -33,6 +33,8 @@ struct dwmci_socfpga_priv_data {
 static void socfpga_dwmci_clksel(struct dwmci_host *host)
 {
 	struct dwmci_socfpga_priv_data *priv = host->priv;
+	u32 sdmmc_mask = ((((priv->smplsel) & 0x7) << SYSMGR_SDMMC_SMPSEL_SHIFT) |
+			 ((priv->drvsel) & 0x7) << 0);
 
 	/* Disable SDMMC clock. */
 	clrbits_le32(&clock_manager_base->per_pll.en,
@@ -40,8 +42,7 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
 
 	debug("%s: drvsel %d smplsel %d\n", __func__,
 	      priv->drvsel, priv->smplsel);
-	writel(SYSMGR_SDMMC_CTRL_SET(priv->smplsel, priv->drvsel),
-		&system_manager_base->sdmmcgrp_ctrl);
+	writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
 
 	debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
 		readl(&system_manager_base->sdmmcgrp_ctrl));
-- 
2.6.2

[U-Boot] [PATCHv3 1/9] arm: socfpga: introduce SOCFPGA_GEN5 config property

[Marek Vasut]

On Wednesday, December 02, 2015 at 07:12:48 AM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> In order to re-use as much Cyclone5 and Arria5 code as possible to support
> the Arria10 platform, we need to wrap some of the code with #ifdef's. By
> adding CONFIG_SOCFPGA_GEN5, we can shorten the check by not having to check
> for both AV || AV.

CV || AV ;-)

> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> ---
>  arch/arm/mach-socfpga/Kconfig | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index 0cb9f9e..4ea171a 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -2,9 +2,14 @@ if ARCH_SOCFPGA
> 
>  config TARGET_SOCFPGA_ARRIA5
>  	bool
> +	select SOCFPGA_GEN5
> 
>  config TARGET_SOCFPGA_CYCLONE5
>  	bool
> +	select SOCFPGA_GEN5
> +
> +config SOCFPGA_GEN5

Shall this be called SOCFPGA_GEN5 or TARGET_SOCFPGA_GEN5 , what do you think ?

> +	bool
> 
>  choice
>  	prompt "Altera SOCFPGA board select"

Best regards,
Marek Vasut

[U-Boot] [PATCHv3 3/9] arm: socfpga: arria10: add reset manager for Arria10

[Marek Vasut]

On Wednesday, December 02, 2015 at 07:12:50 AM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> Add the defines for the reset manager and some basic reset functionality.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> ---
> v3: remove duplicate reset function
>     use CONFIG_SOCFPGA_GEN5
> v2: integrate into a5/c5 reset manager

[...]

> @@ -26,13 +28,25 @@ void socfpga_per_reset(u32 reset, int set)
>  	if (RSTMGR_BANK(reset) == 0)
>  		reg = &reset_manager_base->mpu_mod_reset;
>  	else if (RSTMGR_BANK(reset) == 1)
> +#if defined(CONFIG_SOCFPGA_GEN5)
>  		reg = &reset_manager_base->per_mod_reset;
> +#else
> +		reg = &reset_manager_base->per0_mod_reset;
> +#endif

The other option would be to just rename these registers for in
struct socfpga_reset_manager {} and you won't need those ifdefs.

>  	else if (RSTMGR_BANK(reset) == 2)
> +#if defined(CONFIG_SOCFPGA_GEN5)
>  		reg = &reset_manager_base->per2_mod_reset;
> +#else
> +		reg = &reset_manager_base->per1_mod_reset;
> +#endif

Same here.

>  	else if (RSTMGR_BANK(reset) == 3)
>  		reg = &reset_manager_base->brg_mod_reset;
>  	else if (RSTMGR_BANK(reset) == 4)
> +#if defined(CONFIG_SOCFPGA_GEN5)
>  		reg = &reset_manager_base->misc_mod_reset;
> +#else
> +		reg = &reset_manager_base->sys_mod_reset;
> +#endif

I'd just add a comment that misc_mod_reset is sys_mod_reset on gen10 and
also rename it.

>  	else	/* Invalid reset register, do nothing */
>  		return;
> 
> @@ -46,13 +60,29 @@ void socfpga_per_reset(u32 reset, int set)
>   * Assert reset on every peripheral but L4WD0.
>   * Watchdog must be kept intact to prevent glitches
>   * and/or hangs.
> + * For the Arria10, we disable all the peripherals except L4 watchdog0,
> + * L4 Timer 0, and ECC.
>   */
>  void socfpga_per_reset_all(void)
>  {
> +#if defined(CONFIG_SOCFPGA_GEN5)
>  	const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
> 
>  	writel(~l4wd0, &reset_manager_base->per_mod_reset);
>  	writel(0xffffffff, &reset_manager_base->per2_mod_reset);
> +#else
> +	const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(WD0)) |
> +			(1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
> +
> +	unsigned mask_ecc_ocp = 0x0000FF00;
> +
> +	/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
> +	writel(~l4wd0, &reset_manager_base->per1_mod_reset);
> +	setbits_le32(&reset_manager_base->per0_mod_reset, ~mask_ecc_ocp);
> +
> +	/* Finally disable the ECC_OCP */
> +	setbits_le32(&reset_manager_base->per0_mod_reset, mask_ecc_ocp);
> +#endif
>  }
> 
>  /*

[...]

[U-Boot] [PATCHv3 4/9] arm: socfpga: arria10: add misc functions for Arria10

[Marek Vasut]

On Wednesday, December 02, 2015 at 07:12:51 AM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinh.linux@gmail.com>
> 
> Add arch_early_init_r function. The Arria10 has a firewall protection
> around the SDRAM and OCRAM. These firewalls are to be disabled in order
> for U-Boot to function.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> ---
> v3:
> s/reset_assert_all_peripherals_except_l4wd0_l4timer0/socfpga_per_reset_all
> use CONFIG_SOCFPGA_GEN5
> v2: reuse misc functions from a5/c5
> ---
>  arch/arm/mach-socfpga/misc.c | 53
> ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53
> insertions(+)
> 
> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> index b110f5b..16d83d4 100644
> --- a/arch/arm/mach-socfpga/misc.c
> +++ b/arch/arm/mach-socfpga/misc.c
> @@ -15,6 +15,7 @@
>  #include <watchdog.h>
>  #include <asm/arch/reset_manager.h>
>  #include <asm/arch/scan_manager.h>
> +#include <asm/arch/sdram_a10.h>
>  #include <asm/arch/system_manager.h>
>  #include <asm/arch/dwmmc.h>
>  #include <asm/arch/nic301.h>
> @@ -31,11 +32,20 @@ static struct socfpga_system_manager *sysmgr_regs =
>  	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>  static struct socfpga_reset_manager *reset_manager_base =
>  	(struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
> +#if defined(CONFIG_SOCFPGA_GEN5)
>  static struct nic301_registers *nic301_regs =
>  	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> +#endif
>  static struct scu_registers *scu_regs =
>  	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
> 
> +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +static const struct socfpga_noc_fw_ocram *noc_fw_ocram_base =
> +	(void *)SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS;
> +static const struct socfpga_noc_fw_ddr_l3 *noc_fw_ddr_l3_base =
> +	(void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
> +#endif

If you're using #ifdef -> #else down below in the code, please use it here as 
well to be consistent.

>  int dram_init(void)
>  {
>  	gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);

[...]

[U-Boot] [PATCHv3 5/9] arm: socfpga: arria10: add socfpga_arria10_socdk config

[Marek Vasut]

On Wednesday, December 02, 2015 at 07:12:52 AM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> Add config for the Arria10 SoC Development Kit.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Acked-by: Marek Vasut <marex@denx.de>

Best regards,
Marek Vasut

[U-Boot] [PATCHv3 6/9] arm: socfpga: arria10: add socfpga_arria10_defconfig

[Marek Vasut]

On Wednesday, December 02, 2015 at 07:12:53 AM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> Add a defconfig file for Arria10, which does not include enabling SPL.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Acked-by: Marek Vasut <marex@denx.de>

Best regards,
Marek Vasut

[U-Boot] [PATCHv3 7/9] arm: socfpga: arria10: add config option build for arria10

[Marek Vasut]

On Wednesday, December 02, 2015 at 07:12:54 AM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> ---
> v2: none
> ---
>  arch/arm/Kconfig              |  4 ++--
>  arch/arm/mach-socfpga/Kconfig | 10 ++++++++++
>  2 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 408e4ff..c43c8b4 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -500,9 +500,9 @@ config RMOBILE
>  config ARCH_SOCFPGA
>  	bool "Altera SOCFPGA family"
>  	select CPU_V7
> -	select SUPPORT_SPL
> +	select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
>  	select OF_CONTROL
> -	select SPL_OF_CONTROL
> +	select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
>  	select DM
>  	select DM_SPI_FLASH
>  	select DM_SPI
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
> index 4ea171a..0d2d8d6 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -1,5 +1,8 @@
>  if ARCH_SOCFPGA
> 
> +config TARGET_SOCFPGA_ARRIA10
> +	bool
> +

This should go below ARRIA5 to keep thing sorted numerically.

>  config TARGET_SOCFPGA_ARRIA5
>  	bool
>  	select SOCFPGA_GEN5
> @@ -23,6 +26,10 @@ config TARGET_SOCFPGA_CYCLONE5_SOCDK
>  	bool "Altera SOCFPGA SoCDK (Cyclone V)"
>  	select TARGET_SOCFPGA_CYCLONE5
> 
> +config TARGET_SOCFPGA_ARRIA10_SOCDK
> +	bool "Altera SOCFPGA SoCDK (Arria 10)"
> +	select TARGET_SOCFPGA_ARRIA10
> +
>  config TARGET_SOCFPGA_DENX_MCVEVK
>  	bool "DENX MCVEVK (Cyclone V)"
>  	select TARGET_SOCFPGA_CYCLONE5
> @@ -47,6 +54,7 @@ endchoice
> 
>  config SYS_BOARD
>  	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
> +	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
>  	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
>  	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
>  	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
> @@ -56,6 +64,7 @@ config SYS_BOARD
> 
>  config SYS_VENDOR
>  	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
> +	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
>  	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
>  	default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
>  	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
> @@ -67,6 +76,7 @@ config SYS_SOC
> 
>  config SYS_CONFIG_NAME
>  	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
> +	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
>  	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
>  	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
>  	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK

[U-Boot] [PATCHv3 8/9] arm: socfpga: remove building scan manager

[Marek Vasut]

On Wednesday, December 02, 2015 at 07:12:55 AM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> The scan manager is not needed for the Arria10. Edit the makefile to
> build the scan manager for arria5 and cyclone5 only.
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Acked-by: Marek Vasut <marex@denx.de>

Best regards,
Marek Vasut

[U-Boot] [PATCHv3 9/9] arm: socfpga: fix up a questionable macro for SDMMC

[Marek Vasut]

On Wednesday, December 02, 2015 at 07:12:56 AM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
> 
> Move the macro into the socfpga_dwmci_clksel().
> 
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
> ---
>  arch/arm/mach-socfpga/include/mach/system_manager.h | 8 +++++---
>  drivers/mmc/socfpga_dw_mmc.c                        | 5 +++--
>  2 files changed, 8 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h
> b/arch/arm/mach-socfpga/include/mach/system_manager.h index
> cc070dc..f8a9b69 100644
> --- a/arch/arm/mach-socfpga/include/mach/system_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
> @@ -201,9 +201,11 @@ struct socfpga_system_manager {
>  #define SYSMGR_FPGAINTF_NAND	(1 << 4)
>  #define SYSMGR_FPGAINTF_SDMMC	(1 << 5)
> 
> -/* FIXME: This is questionable macro. */
> -#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel)	\
> -	((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
> +#if defined(CONFIG_SOCFPGA_GEN5)
> +#define SYSMGR_SDMMC_SMPSEL_SHIFT	3

Should this be SMPSEL or SMPLSEL (the original variable contained 'l') ?

> +#else
> +#define SYSMGR_SDMMC_SMPSEL_SHIFT	4
> +#endif
> 
>  /* EMAC Group Bit definitions */
>  #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII	0x0
> diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
> index 5b0c3a8..6a55a6c 100644
> --- a/drivers/mmc/socfpga_dw_mmc.c
> +++ b/drivers/mmc/socfpga_dw_mmc.c
> @@ -33,6 +33,8 @@ struct dwmci_socfpga_priv_data {
>  static void socfpga_dwmci_clksel(struct dwmci_host *host)
>  {
>  	struct dwmci_socfpga_priv_data *priv = host->priv;
> +	u32 sdmmc_mask = ((((priv->smplsel) & 0x7) << SYSMGR_SDMMC_SMPSEL_SHIFT)
> | +			 ((priv->drvsel) & 0x7) << 0);

I am just waiting for someone smart in the hardware design dept. to move the
drvsel register a bit. You should really define SYSMGR_SDMMC_DRVSEL_SHIFT and
use it here.

>  	/* Disable SDMMC clock. */
>  	clrbits_le32(&clock_manager_base->per_pll.en,
> @@ -40,8 +42,7 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
> 
>  	debug("%s: drvsel %d smplsel %d\n", __func__,
>  	      priv->drvsel, priv->smplsel);
> -	writel(SYSMGR_SDMMC_CTRL_SET(priv->smplsel, priv->drvsel),
> -		&system_manager_base->sdmmcgrp_ctrl);
> +	writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
> 
>  	debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
>  		readl(&system_manager_base->sdmmcgrp_ctrl));

Best regards,
Marek Vasut

[U-Boot] [PATCHv3 1/9] arm: socfpga: introduce SOCFPGA_GEN5 config property

[Dinh Nguyen]

On Wed, Dec 2, 2015 at 8:12 AM, Marek Vasut <marex@denx.de> wrote:
> On Wednesday, December 02, 2015 at 07:12:48 AM, dinguyen at opensource.altera.com
> wrote:
>> From: Dinh Nguyen <dinguyen@opensource.altera.com>
>>
>> In order to re-use as much Cyclone5 and Arria5 code as possible to support
>> the Arria10 platform, we need to wrap some of the code with #ifdef's. By
>> adding CONFIG_SOCFPGA_GEN5, we can shorten the check by not having to check
>> for both AV || AV.
>
> CV || AV ;-)
>
>> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
>> ---
>>  arch/arm/mach-socfpga/Kconfig | 5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
>> index 0cb9f9e..4ea171a 100644
>> --- a/arch/arm/mach-socfpga/Kconfig
>> +++ b/arch/arm/mach-socfpga/Kconfig
>> @@ -2,9 +2,14 @@ if ARCH_SOCFPGA
>>
>>  config TARGET_SOCFPGA_ARRIA5
>>       bool
>> +     select SOCFPGA_GEN5
>>
>>  config TARGET_SOCFPGA_CYCLONE5
>>       bool
>> +     select SOCFPGA_GEN5
>> +
>> +config SOCFPGA_GEN5
>
> Shall this be called SOCFPGA_GEN5 or TARGET_SOCFPGA_GEN5 , what do you think ?
>

Yeah, TARGET_SOCFPGA_GEN5 for consistency.

Dinh