* [U-Boot] [PATCHv5 1/2] arm: socfpga: arria10: add reset manager for Arria10
@ 2015-12-03 20:07 dinguyen at opensource.altera.com
2015-12-03 20:07 ` [U-Boot] [PATCH 2/2] arm: socfpga: add define for bootinfo bsel bit shift dinguyen at opensource.altera.com
0 siblings, 1 reply; 3+ messages in thread
From: dinguyen at opensource.altera.com @ 2015-12-03 20:07 UTC (permalink / raw)
To: u-boot
From: Dinh Nguyen <dinguyen@opensource.altera.com>
Add the defines for the reset manager and some basic reset functionality.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v5: rename the mod_reest on A10 to match those in gen5
v4: rename mod_reset names to be used by both gen5 and a10
v3: remove duplicate reset function
use CONFIG_SOCFPGA_GEN5
v2: integrate into a5/c5 reset manager
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 65 ++++++++++++++++++++++
arch/arm/mach-socfpga/reset_manager.c | 24 +++++++-
2 files changed, 88 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index e50fbd8..6ddba18 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -15,6 +15,7 @@ void socfpga_bridges_reset(int enable);
void socfpga_per_reset(u32 reset, int set);
void socfpga_per_reset_all(void);
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@@ -28,6 +29,42 @@ struct socfpga_reset_manager {
u32 padding2[12];
u32 tstscratch;
};
+#else
+struct socfpga_reset_manager {
+ u32 stat;
+ u32 ramstat;
+ u32 miscstat;
+ u32 ctrl;
+ u32 hdsken;
+ u32 hdskreq;
+ u32 hdskack;
+ u32 counts;
+ u32 mpu_mod_reset;
+ u32 per_mod_reset; /* stated as per0_mod_reset in A10 datasheet */
+ u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */
+ u32 brg_mod_reset;
+ u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */
+ u32 coldmodrst;
+ u32 nrstmodrst;
+ u32 dbgmodrst;
+ u32 mpuwarmmask;
+ u32 per0warmmask;
+ u32 per1warmmask;
+ u32 brgwarmmask;
+ u32 syswarmmask;
+ u32 nrstwarmmask;
+ u32 l3warmmask;
+ u32 tststa;
+ u32 tstscratch;
+ u32 hdsktimeout;
+ u32 hmcintr;
+ u32 hmcintren;
+ u32 hmcintrens;
+ u32 hmcintrenr;
+ u32 hmcgpout;
+ u32 hmcgpin;
+};
+#endif
#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
@@ -55,6 +92,7 @@ struct socfpga_reset_manager {
#define RSTMGR_BANK(_reset) \
(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/*
* SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
* 0 ... mpumodrst
@@ -74,6 +112,33 @@ struct socfpga_reset_manager {
#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22)
#define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
#define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
+#else
+/*
+ * SocFPGA Arria10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ * 4 ... sysmodrst
+ */
+#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2)
+#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
+#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
+#define RSTMGR_SPTIMER0 RSTMGR_DEFINE(2, 4)
+#define RSTMGR_SPTIMER1 RSTMGR_DEFINE(2, 5)
+#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17)
+#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18)
+#define RSTMGR_QSPI RSTMGR_DEFINE(1, 6)
+#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7)
+#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
+#define RSTMGR_DDRSCH RSTMGR_DEFINE(3, 6)
+#endif
/* Create a human-readable reference to SoCFPGA reset. */
#define SOCFPGA_RESET(_name) RSTMGR_##_name
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index b6beaa2..d0ff6c4 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -18,7 +18,9 @@ static const struct socfpga_reset_manager *reset_manager_base =
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-/* Assert or de-assert SoCFPGA reset manager reset. */
+/*
+ * Assert or de-assert SoCFPGA reset manager reset.
+ */
void socfpga_per_reset(u32 reset, int set)
{
const void *reg;
@@ -46,13 +48,29 @@ void socfpga_per_reset(u32 reset, int set)
* Assert reset on every peripheral but L4WD0.
* Watchdog must be kept intact to prevent glitches
* and/or hangs.
+ * For the Arria10, we disable all the peripherals except L4 watchdog0,
+ * L4 Timer 0, and ECC.
*/
void socfpga_per_reset_all(void)
{
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
writel(~l4wd0, &reset_manager_base->per_mod_reset);
writel(0xffffffff, &reset_manager_base->per2_mod_reset);
+#else
+ const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) |
+ (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
+
+ unsigned mask_ecc_ocp = 0x0000FF00;
+
+ /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
+ writel(~l4wd0, &reset_manager_base->per1_mod_reset);
+ setbits_le32(&reset_manager_base->per0_mod_reset, ~mask_ecc_ocp);
+
+ /* Finally disable the ECC_OCP */
+ setbits_le32(&reset_manager_base->per0_mod_reset, mask_ecc_ocp);
+#endif
}
/*
@@ -71,6 +89,7 @@ void reset_cpu(ulong addr)
;
}
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/*
* Release peripherals from reset based on handoff
*/
@@ -78,6 +97,7 @@ void reset_deassert_peripherals_handoff(void)
{
writel(0, &reset_manager_base->per_mod_reset);
}
+#endif
#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
void socfpga_bridges_reset(int enable)
@@ -92,6 +112,7 @@ void socfpga_bridges_reset(int enable)
void socfpga_bridges_reset(int enable)
{
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
L3REGS_REMAP_HPS2FPGA_MASK |
L3REGS_REMAP_OCRAM_MASK;
@@ -116,5 +137,6 @@ void socfpga_bridges_reset(int enable)
/* Remap the bridges into memory map */
writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
}
+#endif
}
#endif
--
2.6.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH 2/2] arm: socfpga: add define for bootinfo bsel bit shift
2015-12-03 20:07 [U-Boot] [PATCHv5 1/2] arm: socfpga: arria10: add reset manager for Arria10 dinguyen at opensource.altera.com
@ 2015-12-03 20:07 ` dinguyen at opensource.altera.com
2015-12-03 23:36 ` Marek Vasut
0 siblings, 1 reply; 3+ messages in thread
From: dinguyen at opensource.altera.com @ 2015-12-03 20:07 UTC (permalink / raw)
To: u-boot
From: Dinh Nguyen <dinguyen@opensource.altera.com>
On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10,
the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so that
the reading the bsel can generic.
Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
arch/arm/mach-socfpga/include/mach/system_manager.h | 2 ++
arch/arm/mach-socfpga/misc.c | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h
index e688c50..9ca889a 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -203,8 +203,10 @@ struct socfpga_system_manager {
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define SYSMGR_SDMMC_SMPLSEL_SHIFT 3
+#define SYSMGR_BOOTINFO_BSEL_SHIFT 0
#else
#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
+#define SYSMGR_BOOTINFO_BSEL_SHIFT 12
#endif
#define SYSMGR_SDMMC_DRVSEL_SHIFT 0
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 78774d5..15c4c2a 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -215,12 +215,12 @@ static int socfpga_fpga_id(const bool print_id)
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
+ const u32 bsel = (readl(&sysmgr_regs->bootinfo) >>
+ SYSMGR_BOOTINFO_BSEL_SHIFT) & 0x7;
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
- const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
puts("CPU: Altera SoCFPGA Platform\n");
socfpga_fpga_id(1);
#else
- const u32 bsel = (readl(&sysmgr_regs->bootinfo) >> 12) & 0x7;
puts("CPU: Altera SoCFPGA Arria 10\n");
#endif
printf("BOOT: %s\n", bsel_str[bsel].name);
--
2.6.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH 2/2] arm: socfpga: add define for bootinfo bsel bit shift
2015-12-03 20:07 ` [U-Boot] [PATCH 2/2] arm: socfpga: add define for bootinfo bsel bit shift dinguyen at opensource.altera.com
@ 2015-12-03 23:36 ` Marek Vasut
0 siblings, 0 replies; 3+ messages in thread
From: Marek Vasut @ 2015-12-03 23:36 UTC (permalink / raw)
To: u-boot
On Thursday, December 03, 2015 at 09:07:18 PM, dinguyen at opensource.altera.com
wrote:
> From: Dinh Nguyen <dinguyen@opensource.altera.com>
>
> On arria5/cyclone5 parts, the bsel bits are at shift 0, while for arria10,
> the bsel bits are at shift 12. Add SYSMGR_BOOTINFO_BSEL_SHIFT define so
> that the reading the bsel can generic.
>
> Suggested-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Applied both, thanks.
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2015-12-03 23:36 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-12-03 20:07 [U-Boot] [PATCHv5 1/2] arm: socfpga: arria10: add reset manager for Arria10 dinguyen at opensource.altera.com
2015-12-03 20:07 ` [U-Boot] [PATCH 2/2] arm: socfpga: add define for bootinfo bsel bit shift dinguyen at opensource.altera.com
2015-12-03 23:36 ` Marek Vasut
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.